[PATCH 0/2] target/riscv: fixup atomic implementation

LIU Zhiwei posted 2 patches 1 week ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/20200629130731.1080-1-zhiwei_liu@c-sky.com
Maintainers: Richard Henderson <rth@twiddle.net>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Palmer Dabbelt <palmer@dabbelt.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
target/riscv/insn_trans/trans_rva.inc.c | 60 +++++++++++++++++++------
tcg/tcg-op.c                            |  4 +-
2 files changed, 49 insertions(+), 15 deletions(-)

[PATCH 0/2] target/riscv: fixup atomic implementation

Posted by LIU Zhiwei 1 week ago
When I tested RVA with RISU, I found there is something wrong.
In particular, amo*.w instructions should only operate the lowerest 32
bits. However, the current implementation uses the whole XLEN bits.

LIU Zhiwei (2):
  tcg/tcg-op: Fix nonatomic_op load with MO_SIGN
  target/riscv: Do amo*.w insns operate with 32 bits

 target/riscv/insn_trans/trans_rva.inc.c | 60 +++++++++++++++++++------
 tcg/tcg-op.c                            |  4 +-
 2 files changed, 49 insertions(+), 15 deletions(-)

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2.23.0