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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5+9scEeG4yNntnWLNUGiOItv0SsM9bx+/uT7ZxipYNE=; b=oWYmYQvMhm/DdnJ0Ol2d5wxfA3yhLgtEhmOHDlWbwyRo0JAB8Ub1wvbxfDVcZfkzVc NTe0IEpwE39PPq7O+SpHXkrmgMycOcUgAiQPkIW94/1BUUZQPRxdNSfJAMyI98W2HUDv CnxkFw3f1jY0z7shh5hcso391TnhRPWzxcId8s84l9EzP1UI8te1RXuAQH3wV8Hilegv oorQS1hO7ODGDvuEcaTum3OTS6bZgIdpWgZM+3vzDfKVaDevItytRiMceFvGq93DUQL0 MdLloETPYFt+2bVFOGIeaLy+yQocva41LebZtoLL+1kYKa6NWwd06baGtKOFefWQa5IL kPug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5+9scEeG4yNntnWLNUGiOItv0SsM9bx+/uT7ZxipYNE=; b=drFi/sTZMbOQ/TslCG/RWukiN+clu8x1I+77DBMuBN+nFitVUCUEJoNlPDCjsVV5sr ymoHRMoKaC1KjHbHhsuKIJuAFHTsma7XdtSa+JlRMmiVBQnF0QddXyY5bbfUkaNGy/0F Vfzuh/ED3oJQNN4U4PedzHq+WBHKw/MLHkksbSGplecHJj2JeIHZUaq1tA97l5I9pt6D MWDK5A9CyqBamrQ0PHbhfeD+yoms7h1W/bN557859HDB1zjYPxFOmmqjjsJEuzSmBgiy /9+a9H0erniJ4V7bY5Ts07154Xft34CpuVgZXOfZtwsj+WbJv5VJmhzG6RVNwnMeeeK/ K3LA== X-Gm-Message-State: AOAM531F2EBsCNz9Z6j8OzzuHWGg27Bm36UgDVSt28fy2pU02DmGlXH5 3EEfhGptCHtMsFzHkfVNeYdk3LPdoGqE2g== X-Google-Smtp-Source: ABdhPJwCkn7IFkjfyT0dQ8MjnRd3/UlSUXokzEMiXwVTmLZaT8JokZ/mqBtOU201t68/F3uFMel7qA== X-Received: by 2002:a1c:4185:: with SMTP id o127mr3931727wma.8.1593184534754; Fri, 26 Jun 2020 08:15:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 56/57] target/arm: Add allocation tag storage for system mode Date: Fri, 26 Jun 2020 16:14:23 +0100 Message-Id: <20200626151424.30117-57-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Look up the physical address for the given virtual address, convert that to a tag physical address, and finally return the host address that backs it. Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-45-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/mte_helper.c | 131 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 4f9bd3add3d..5ea57d487a4 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/ram_addr.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" =20 @@ -74,8 +75,138 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, int ptr_size, MMUAccessType tag_access, int tag_size, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY /* Tag storage not implemented. */ return NULL; +#else + uintptr_t index; + CPUIOTLBEntry *iotlbentry; + int in_page, flags; + ram_addr_t ptr_ra; + hwaddr ptr_paddr, tag_paddr, xlat; + MemoryRegion *mr; + ARMASIdx tag_asi; + AddressSpace *tag_as; + void *host; + + /* + * Probe the first byte of the virtual address. This raises an + * exception for inaccessible pages, and resolves the virtual address + * into the softmmu tlb. + * + * When RA =3D=3D 0, this is for mte_probe1. The page is expected to = be + * valid. Indicate to probe_access_flags no-fault, then assert that + * we received a valid page. + */ + flags =3D probe_access_flags(env, ptr, ptr_access, ptr_mmu_idx, + ra =3D=3D 0, &host, ra); + assert(!(flags & TLB_INVALID_MASK)); + + /* + * Find the iotlbentry for ptr. This *must* be present in the TLB + * because we just found the mapping. + * TODO: Perhaps there should be a cputlb helper that returns a + * matching tlb entry + iotlb entry. + */ + index =3D tlb_index(env, ptr_mmu_idx, ptr); +# ifdef CONFIG_DEBUG_TCG + { + CPUTLBEntry *entry =3D tlb_entry(env, ptr_mmu_idx, ptr); + target_ulong comparator =3D (ptr_access =3D=3D MMU_DATA_LOAD + ? entry->addr_read + : tlb_addr_write(entry)); + g_assert(tlb_hit(comparator, ptr)); + } +# endif + iotlbentry =3D &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; + + /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ + if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) { + return NULL; + } + + /* + * If not backed by host ram, there is no tag storage: access unchecke= d. + * This is probably a guest os bug though, so log it. + */ + if (unlikely(flags & TLB_MMIO)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Page @ 0x%" PRIx64 " indicates Tagged Normal memory= " + "but is not backed by host ram\n", ptr); + return NULL; + } + + /* + * The Normal memory access can extend to the next page. E.g. a single + * 8-byte access to the last byte of a page will check only the last + * tag on the first page. + * Any page access exception has priority over tag check exception. + */ + in_page =3D -(ptr | TARGET_PAGE_MASK); + if (unlikely(ptr_size > in_page)) { + void *ignore; + flags |=3D probe_access_flags(env, ptr + in_page, ptr_access, + ptr_mmu_idx, ra =3D=3D 0, &ignore, ra); + assert(!(flags & TLB_INVALID_MASK)); + } + + /* Any debug exception has priority over a tag check exception. */ + if (unlikely(flags & TLB_WATCHPOINT)) { + int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; + assert(ra !=3D 0); + cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, + iotlbentry->attrs, wp, ra); + } + + /* + * Find the physical address within the normal mem space. + * The memory region lookup must succeed because TLB_MMIO was + * not set in the cputlb lookup above. + */ + mr =3D memory_region_from_host(host, &ptr_ra); + tcg_debug_assert(mr !=3D NULL); + tcg_debug_assert(memory_region_is_ram(mr)); + ptr_paddr =3D ptr_ra; + do { + ptr_paddr +=3D mr->addr; + mr =3D mr->container; + } while (mr); + + /* Convert to the physical address in tag space. */ + tag_paddr =3D ptr_paddr >> (LOG2_TAG_GRANULE + 1); + + /* Look up the address in tag space. */ + tag_asi =3D iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; + tag_as =3D cpu_get_address_space(env_cpu(env), tag_asi); + mr =3D address_space_translate(tag_as, tag_paddr, &xlat, NULL, + tag_access =3D=3D MMU_DATA_STORE, + iotlbentry->attrs); + + /* + * Note that @mr will never be NULL. If there is nothing in the addre= ss + * space at @tag_paddr, the translation will return the unallocated me= mory + * region. For our purposes, the result must be ram. + */ + if (unlikely(!memory_region_is_ram(mr))) { + /* ??? Failure is a board configuration error. */ + qemu_log_mask(LOG_UNIMP, + "Tag Memory @ 0x%" HWADDR_PRIx " not found for " + "Normal Memory @ 0x%" HWADDR_PRIx "\n", + tag_paddr, ptr_paddr); + return NULL; + } + + /* + * Ensure the tag memory is dirty on write, for migration. + * Tag memory can never contain code or display memory (vga). + */ + if (tag_access =3D=3D MMU_DATA_STORE) { + ram_addr_t tag_ra =3D memory_region_get_ram_addr(mr) + xlat; + cpu_physical_memory_set_dirty_flag(tag_ra, DIRTY_MEMORY_MIGRATION); + } + + return memory_region_get_ram_ptr(mr) + xlat; +#endif } =20 uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) --=20 2.20.1