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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0oVfTOhMQ6Tde7hKNa/ourLtYXrK2B3QeNm/nMxWem8=; b=qkqfW5DWWVce1lt2gMkWTq63P2U/IlsJCEsJ+9vfWvJqhzA712wi57+DXM0ky4yZmF k7Rmwj8ojD2TeI0FKBIZJHmroIvyTEJ26BZjETbVSaG8rOFDJltxjbmFQmBeX7cZFG0g LSPUxyrCWag8gN6JqmRjSJEGOep+XQypwyUigkYYuJ9BVryveQHmgnz69Z7lK+Y5bEqn TM69nYosX1he6vXjnp5oH6QRFhcKcmGNqG67gk62nuOBinrWWX+rOUi4g/ToeoD/v7Na pGktQgXe94INIKwcnrWPU8iXmCHe0R0EHIfPwx2YZEU19etkhU0LeZkwTx1JHQlDr4lC fRIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0oVfTOhMQ6Tde7hKNa/ourLtYXrK2B3QeNm/nMxWem8=; b=gRhRB8YxqcJXdB61h64QMwahGkD68YCCkoXfUNBdVgoJkynoUAO7JmCX50S09SUJ8L D2BZ7Utgt2TVj+aRnyDXwDGkP27YlWYp9TY5YetbgAL4I0RIMCmTRZKJ16tR8ltR+qi3 4hbtVQqs2arJ/1/nOSzHWWlnKKK3uwtEiuOLBJGUIQBIos4BfIz+AvkTbmgo4j4fqHlr vsF27Qfyxa+tLD0v4xbjx4FTITX3aAaTOSlSr7DvJCwfpBvFwgipyhvwt7Qp5eaqpLbJ TmgAzhUWvzKXlHO480Lt4j4jVwNpJ+WoJmrhpJvvmUzWFECxDeoEBeYQZlqOry+nGIJ1 afYQ== X-Gm-Message-State: AOAM532NXToViRbBmbFIn6ZHBv02cQMdRE2wn3SOFSVpnYvh5pTSkqlG u8/OTbRR9DIrZENke1w7VsLRPfoOF9J8Yg== X-Google-Smtp-Source: ABdhPJy7U7eIeuCTerVABvOSikTiIMfjD1e/o9NWRGOfceLWauuzsNrozOzyVNCTTq7/26scAircHw== X-Received: by 2002:adf:de01:: with SMTP id b1mr4163979wrm.305.1593184526971; Fri, 26 Jun 2020 08:15:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 50/57] target/arm: Complete TBI clearing for user-only for SVE Date: Fri, 26 Jun 2020 16:14:17 +0100 Message-Id: <20200626151424.30117-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson There are a number of paths by which the TBI is still intact for user-only in the SVE helpers. Because we currently always set TBI for user-only, we do not need to pass down the actual TBI setting from above, and we can remove the top byte in the inner-most primitives, so that none are forgotten. Moreover, this keeps the "dirty" pointer around at the higher levels, where we need it for any MTE checking. Since the normal case, especially for user-only, goes through RAM, this clearing merely adds two insns per page lookup, which will be completely in the noise. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-39-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 3 +++ target/arm/sve_helper.c | 19 +++++++++++++++++-- target/arm/translate-a64.c | 5 +++++ 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d9876337c05..afe81e9b6c0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -203,6 +203,9 @@ static void arm_cpu_reset(DeviceState *dev) * Enable TBI0 and TBI1. While the real kernel only enables TBI0, * turning on both here will produce smaller code and otherwise * make no difference to the user-level emulation. + * + * In sve_probe_page, we assume that this is set. + * Do not modify this without other changes. */ env->cp15.tcr_el[1].raw_tcr =3D (3ULL << 37); #else diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index ad974c2cc57..382fa82bc8a 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -3966,14 +3966,16 @@ static void sve_##NAME##_host(void *vd, intptr_t re= g_off, void *host) \ static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,= \ target_ulong addr, uintptr_t ra) = \ { = \ - *(TYPEE *)(vd + H(reg_off)) =3D (TYPEM)TLB(env, addr, ra); = \ + *(TYPEE *)(vd + H(reg_off)) =3D = \ + (TYPEM)TLB(env, useronly_clean_ptr(addr), ra); = \ } =20 #define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \ static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,= \ target_ulong addr, uintptr_t ra) = \ { = \ - TLB(env, addr, (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); = \ + TLB(env, useronly_clean_ptr(addr), = \ + (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); = \ } =20 #define DO_LD_PRIM_1(NAME, H, TE, TM) \ @@ -4091,6 +4093,19 @@ static bool sve_probe_page(SVEHostPage *info, bool n= ofault, int flags; =20 addr +=3D mem_off; + + /* + * User-only currently always issues with TBI. See the comment + * above useronly_clean_ptr. Usually we clean this top byte away + * during translation, but we can't do that for e.g. vector + imm + * addressing modes. + * + * We currently always enable TBI for user-only, and do not provide + * a way to turn it off. So clean the pointer unconditionally here, + * rather than look it up here, or pass it down from above. + */ + addr =3D useronly_clean_ptr(addr); + flags =3D probe_access_flags(env, addr, access_type, mmu_idx, nofault, &info->host, retaddr); info->flags =3D flags; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e46c4a49e00..c20af6ee9d0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14634,6 +14634,11 @@ static void aarch64_tr_init_disas_context(DisasCon= textBase *dcbase, dc->features =3D env->features; dc->dcz_blocksize =3D arm_cpu->dcz_blocksize; =20 +#ifdef CONFIG_USER_ONLY + /* In sve_probe_page, we assume TBI is enabled. */ + tcg_debug_assert(dc->tbid & 1); +#endif + /* Single step state. The code-generation logic here is: * SS_ACTIVE =3D=3D 0: * generate code with no special handling for single-stepping (except --=20 2.20.1