From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185098; cv=none; d=zohomail.com; s=zohoarc; b=SAOXbzXhY1WX9uayhrdIOf9WAvCpSDHNF5mwuZwmcsMm4v8XTpLHkn/7+eba8tERGtrxFGdsbDLX1alVZbEp+ccEnNuZTVQS9qWZaxJw3uin5+2hOBNKgMldh4CAsgcRm1qRTyMgPRCEO6a8MQTQ6UFvEFvfeLvRiQHNpzPU7WA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185098; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=acP3Sx4OGOgiAbreBwnSKlVu9vGjvqCv6xOFJh6nkmA=; b=FvqmV+puKIKkWWQeYQ7D2TsQWR6OzFXLClwe6CNIjBJDnPWemG10R0FSTvBPuC56GjjA4//8B5gmtYqHU7IveAWRhI/lLAXc0pB8sW7ODP87u6QAcyh0jnsvCOISDmmrmMlgdrso9sAf70WdKCpHOdWGedG0xXnXf9NduY96DXQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185098725848.3372880092713; Fri, 26 Jun 2020 08:24:58 -0700 (PDT) Received: from localhost ([::1]:57588 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqDp-0002Uo-Fg for importer@patchew.org; Fri, 26 Jun 2020 11:24:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35292) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq3j-0001nX-Hg for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:31 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:45067) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq3h-0006Ar-Qu for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:31 -0400 Received: by mail-wr1-x430.google.com with SMTP id s10so9821636wrw.12 for ; Fri, 26 Jun 2020 08:14:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=acP3Sx4OGOgiAbreBwnSKlVu9vGjvqCv6xOFJh6nkmA=; b=DyYW4V0N7Rs19CAsNBze9ru/0AxHimeYSIXEkvBK6WH8PJ/+L1x4b7EPs7NSVGhbNI e+YKG3uNKxLC7ay37ssKVSN62NNq+vyX7aViRjCvuDKCu4Gk5TBuJK9nc7uBBET4PS1E saTNuuKgp/UnVSdLKLQ7HfMYh7z3lxmtV/8cM4d2KxzXw3LHRTxXWtAwcKkcHcmQ9nU2 jN/jPZqXc8VJwVuL5twYIady742o5e7ezQjcm5SRjZszDaaMBwvVu80GzftVXBa60HTj QhVUXbzJAHRLGRG066F4b+usmWUybYW/8QyVjCu9Jb5oNb8Q3nrsWpv5xUewhsSZjOlQ xIrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=acP3Sx4OGOgiAbreBwnSKlVu9vGjvqCv6xOFJh6nkmA=; b=KlJUsr2gM0eLpTDYDbRueUp0puAobuZOLnv4s4rmQFcEj2aowJew4C7MJCMJuvDOYS 6fe6ypdYEAWUkUAzFzIZTnypVM7uJOjVM+3R2bpKhD6zc1Z1aEt1cxDjSiFUieqwgcVj +eohKyArfwhZiBfPg6/VtmVvLy/qQbxQ+FVz+JGy3NggLiyZ0TxkJgrpMpe0ZWhUExoL SPv/vg8cNneI6RPAulxJXgUVIpnTJI6a/5UBwJHcd+40H0KGeROJyBt7P4PPYNcE6OvR b/Bl1XzjGl/pW5iT0sXG4l5ywmQvR1PujsEQFO+cDmTiH152Qu8Z0V/7DvRqYeUxSQhi J1Og== X-Gm-Message-State: AOAM530QQN309Vvs4hX0vUlJjML9GxN8B975ixXV6KZWGlrenxU2tjDL mF3hDr7xCNfF1Qp3FTFY8KIV3vwx2aLBag== X-Google-Smtp-Source: ABdhPJxGXe7yGCiyniGBRQadKbMYMNdWDp2UwCSn5foHC8Xdjj2cL9wklYtDh9DF9mbF2botcCJpcg== X-Received: by 2002:adf:c404:: with SMTP id v4mr4126758wrf.85.1593184468148; Fri, 26 Jun 2020 08:14:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/57] hw/arm/aspeed: Remove extraneous MemoryRegion object owner Date: Fri, 26 Jun 2020 16:13:28 +0100 Message-Id: <20200626151424.30117-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 I'm confused by this code, 'bmc' is created as: bmc =3D g_new0(AspeedBoardState, 1); Then we use it as QOM owner for different MemoryRegion objects. But looking at memory_region_init_ram (similarly for ROM): void memory_region_init_ram(MemoryRegion *mr, struct Object *owner, const char *name, uint64_t size, Error **errp) { DeviceState *owner_dev; Error *err =3D NULL; memory_region_init_ram_nomigrate(mr, owner, name, size, &err); if (err) { error_propagate(errp, err); return; } /* This will assert if owner is neither NULL nor a DeviceState. * We only want the owner here for the purposes of defining a * unique name for migration. TODO: Ideally we should implement * a naming scheme for Objects which are not DeviceStates, in * which case we can relax this restriction. */ owner_dev =3D DEVICE(owner); vmstate_register_ram(mr, owner_dev); } The expected assertion is not triggered ('bmc' is not NULL neither a DeviceState). 'bmc' structure is defined as: struct AspeedBoardState { AspeedSoCState soc; MemoryRegion ram_container; MemoryRegion max_ram; }; What happens is when using 'OBJECT(bmc)', the QOM macros cast the memory pointed by bmc, which first member is 'soc', which is initialized ...: object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); The 'soc' object is indeed a DeviceState, so the assertion passes. Since this is fragile and only happens to work by luck, remove the dangerous OBJECT(bmc) owner argument. Note, this probably breaks migration for this machine. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200623072132.2868-2-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 863757e1f03..167fd5ed1c7 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -329,12 +329,12 @@ static void aspeed_machine_init(MachineState *machine) * needed by the flash modules of the Aspeed machines. */ if (ASPEED_MACHINE(machine)->mmio_exec) { - memory_region_init_alias(boot_rom, OBJECT(bmc), "aspeed.boot_r= om", + memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", &fl->mmio, 0, fl->size); memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, boot_rom); } else { - memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom= ", + memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", fl->size, &error_abort); memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, boot_rom); @@ -345,7 +345,7 @@ static void aspeed_machine_init(MachineState *machine) if (machine->kernel_filename && sc->num_cpus > 1) { /* With no u-boot we must set up a boot stub for the secondary CPU= */ MemoryRegion *smpboot =3D g_new(MemoryRegion, 1); - memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot", + memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 0x80, &error_abort); memory_region_add_subregion(get_system_memory(), AST_SMP_MAILBOX_BASE, smpboot); --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593184564; cv=none; d=zohomail.com; s=zohoarc; b=TfY5ioBZS9Q8UFpy0TkG9F8KH+wwxerb2FDt1J6krxlHINjTAjzBwn0pYRx9Rew4RtufuhnKwwmxEveBEy2yAAyfqXe8CXMaZyec3bKunoBH3VVYNz/InG0dsHvfRFwDogYRsXRTnsPzL2Ro49ty0+hhM3sxHrl7fTNowEEQHu8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593184564; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wHkNxYOciTE2oOBZnE2EDvVEW4h7Fv9ILw3mBQCiruk=; b=KWEu98+JX1JJ2HvfBqngIUtfCDpC0TmdvohoR8hLwBSO5XiYPUrk5OeArcCzGMjEgjcUfB6Haex4XQ7HclnlCRqOCVkNMFkRSKrfgDjBKGXoD8eKncQNHWwJwmUVWqbC00dF9PzXvoYqKFnUCJ/FEVxGRU/89wvsciCc926Eqd4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593184564582906.6640438640017; Fri, 26 Jun 2020 08:16:04 -0700 (PDT) Received: from localhost ([::1]:47926 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joq5C-0003qd-NP for importer@patchew.org; Fri, 26 Jun 2020 11:16:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35308) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq3l-0001pI-1W for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:33 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:46448) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq3j-0006BR-51 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:32 -0400 Received: by mail-wr1-x430.google.com with SMTP id r12so9802804wrj.13 for ; Fri, 26 Jun 2020 08:14:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wHkNxYOciTE2oOBZnE2EDvVEW4h7Fv9ILw3mBQCiruk=; b=sdBPql90cqhGYGENmHlUwo5QO5juetB+MJX9MhPVMD+Bd+fMnFm765MOi2BT05pUQV ywSjgexzturKX7COf3C/Qdk+T52GKzAYwqVnjNCe89ToPJfBXtaEn9NGqcu/Np5Nk48/ nPXRP5t4fuY5tiAoqGveMN2OxgKv0YPhGiACTApDc4KCHVK2QM0lkRt6QTwgppDcSZf8 HvHBZ/3e3Y83CapsW4ekzlKaAoQQE2tB14wy2wAUyfNhcE/8XU47qZB77UKjGTu7xxQo CEsP+osCjpQASS28/8vCbOC9PPH4N7ZGxlbOatzRTSzB7lkuaHMkyWEIR/E2AcdA09bV ojUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wHkNxYOciTE2oOBZnE2EDvVEW4h7Fv9ILw3mBQCiruk=; b=n6jLMHu62Nzw/WV0HXXKa+RBv6Y86pLlOCm4j3vObrwLsAqfyd83MrbMLUSwrweLpc DzsxfiTRO2pDEoYhnY6Hjvy1eVyPDcq3I6w0ArzXfh1hHPe58q8u85pk+IhkotsRwU0p 8HTpb9hLpZJxGGHuCmKLmDjIfdrDPlaltlzx0HkR0/surqiQVSDGEmjm3eCnMxTri5D6 gqiXSZtNhM/z8DT03TbUcmD18gt3hAGomRkVqO/AoE+e1fhWFGu5inYvfR2VboIHT1lI I5ZNR8vbQJs/A7G3cybOPctZrcyshj0yHdW/l8hCNIZVYaEeW53rEAmdm5mxAq1lacZj 4HIw== X-Gm-Message-State: AOAM530SMUNGNotlP0hqCvwZPeQ+DxrAM9Li7ZqVoqFjILv62rW3yB2j aBoBLXSIgZ8hjDUJ9AAPFTvF2oQ/0GU2Ng== X-Google-Smtp-Source: ABdhPJyJ0vc48zedWYxR1Yu3dcPNurfI9wkJ4j5EMND/0MfIH08cQsaAGoukmQ+RwGDWcPZ4eaV7Uw== X-Received: by 2002:a5d:4a01:: with SMTP id m1mr4274396wrq.250.1593184469311; Fri, 26 Jun 2020 08:14:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/57] hw/arm/aspeed: Rename AspeedBoardState as AspeedMachineState Date: Fri, 26 Jun 2020 16:13:29 +0100 Message-Id: <20200626151424.30117-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 To have a more consistent naming, rename AspeedBoardState as AspeedMachineState. Suggested-by: C=C3=A9dric Le Goater Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Message-id: 20200623072132.2868-3-f4bug@amsat.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed.h | 4 ++-- hw/arm/aspeed.c | 20 ++++++++++---------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 95b4daece86..5114ba0bd4f 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -11,7 +11,7 @@ =20 #include "hw/boards.h" =20 -typedef struct AspeedBoardState AspeedBoardState; +typedef struct AspeedMachineState AspeedMachineState; =20 #define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed") #define ASPEED_MACHINE(obj) \ @@ -45,7 +45,7 @@ typedef struct AspeedMachineClass { const char *spi_model; uint32_t num_cs; uint32_t macs_mask; - void (*i2c_init)(AspeedBoardState *bmc); + void (*i2c_init)(AspeedMachineState *bmc); } AspeedMachineClass; =20 =20 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 167fd5ed1c7..a167b736970 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -32,7 +32,7 @@ static struct arm_boot_info aspeed_board_binfo =3D { .board_id =3D -1, /* device-tree-only board */ }; =20 -struct AspeedBoardState { +struct AspeedMachineState { AspeedSoCState soc; MemoryRegion ram_container; MemoryRegion max_ram; @@ -253,7 +253,7 @@ static void sdhci_attach_drive(SDHCIState *sdhci, Drive= Info *dinfo) =20 static void aspeed_machine_init(MachineState *machine) { - AspeedBoardState *bmc; + AspeedMachineState *bmc; AspeedMachineClass *amc =3D ASPEED_MACHINE_GET_CLASS(machine); AspeedSoCClass *sc; DriveInfo *drive0 =3D drive_get(IF_MTD, 0, 0); @@ -261,7 +261,7 @@ static void aspeed_machine_init(MachineState *machine) int i; NICInfo *nd =3D &nd_table[0]; =20 - bmc =3D g_new0(AspeedBoardState, 1); + bmc =3D g_new0(AspeedMachineState, 1); =20 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 4 * GiB); @@ -374,7 +374,7 @@ static void aspeed_machine_init(MachineState *machine) arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); } =20 -static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) +static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D &bmc->soc; DeviceState *dev; @@ -396,7 +396,7 @@ static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_ab= ort); } =20 -static void ast2500_evb_i2c_init(AspeedBoardState *bmc) +static void ast2500_evb_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D &bmc->soc; uint8_t *eeprom_buf =3D g_malloc0(8 * 1024); @@ -413,13 +413,13 @@ static void ast2500_evb_i2c_init(AspeedBoardState *bm= c) i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", = 0x32); } =20 -static void ast2600_evb_i2c_init(AspeedBoardState *bmc) +static void ast2600_evb_i2c_init(AspeedMachineState *bmc) { /* Start with some devices on our I2C busses */ ast2500_evb_i2c_init(bmc); } =20 -static void romulus_bmc_i2c_init(AspeedBoardState *bmc) +static void romulus_bmc_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D &bmc->soc; =20 @@ -428,7 +428,7 @@ static void romulus_bmc_i2c_init(AspeedBoardState *bmc) i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", = 0x32); } =20 -static void swift_bmc_i2c_init(AspeedBoardState *bmc) +static void swift_bmc_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D &bmc->soc; =20 @@ -457,7 +457,7 @@ static void swift_bmc_i2c_init(AspeedBoardState *bmc) i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", = 0x4a); } =20 -static void sonorapass_bmc_i2c_init(AspeedBoardState *bmc) +static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D &bmc->soc; =20 @@ -501,7 +501,7 @@ static void sonorapass_bmc_i2c_init(AspeedBoardState *b= mc) =20 } =20 -static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) +static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D &bmc->soc; uint8_t *eeprom_buf =3D g_malloc0(8 * 1024); --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=gAVU66Bka2C31iTs/7lhQdbitwvERu6cMLvGdW1VOYU=; b=wF3jCnfedOFNoYhYCM+xFBrQXmjhgvuXH3fLFP73VeATuzHsYWSmp46hqIp8dI7bnb BhVGMEOuPf6wfCNnbl+KLNv4BsFYdbEMZdVqUjKnW8LRYRS4LP10agenMVXiENsQyUmO L97mxhhVTlI3R9QmJoxmpLFU9h85Uv010lkDdVc++/2U+pQYFaLaKH4N0+JlOaOVYaBz TWivR9QJ2XBW0lo3aDm7V1Hyb+qm4LggraEg+IN6lDQQ+5v5EGQ+F0u1JK7JRHnFuYP5 Y/tyS/DBIaILTWiAUREORSpd0QbYhCpIp+2p6RqXpzuZNHpZqXc3guZwoBg0f+MQLBT1 oTRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gAVU66Bka2C31iTs/7lhQdbitwvERu6cMLvGdW1VOYU=; b=ffT0LW7X/bY1Q1lgf97wi/94AXgKfqhCzGkSw28iT13EN3BtbCe/cZKztj0zGoBEOE leuRV4FsXtmr8+X5RnpYsNSXPGTGxp7vvnrqFzJrM9GgcuyBxCK+sXU4QOnjQXulKsKC MFCd/P0rKkU5HwXoGaBb8lzVV/wL5/FiE2/WDNgUO6pWs6X1l1D+c66bEVYbBU2nf0mF h67+B3ILA5xrup3bGGz+91bHjeI596Wxl8WRj+z75tr+28PKt4/X5scOSAMed6Hm5rOs UgEHNy3Ju0cLtQmuZaPMAeriMid+/b0T0sizxzoYAKEs+TBdqlrB1gY3CzXfDGFvglpO wt1A== X-Gm-Message-State: AOAM532vi+CzNGkUJ4ifUeENyrhfGQovcoIq6lFTSIiW0wOrRUTuKhjS kbicIvsT5dWQUhnRXwEnGLvfMwG+d2L2cw== X-Google-Smtp-Source: ABdhPJzIZ7vAtohsyjJZ1XmOJJObhrXr4eqSBvVJlgZgBjxCkQ29BVpnPr7UTg6aq8iMRHa+uwG4+A== X-Received: by 2002:a1c:2d54:: with SMTP id t81mr4247277wmt.154.1593184470404; Fri, 26 Jun 2020 08:14:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/57] hw/arm/aspeed: QOM'ify AspeedMachineState Date: Fri, 26 Jun 2020 16:13:30 +0100 Message-Id: <20200626151424.30117-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 AspeedMachineState seems crippled. We use incorrectly 2 different structures to do the same thing. Merge them altogether: - Move AspeedMachine fields to AspeedMachineState - AspeedMachineState is now QOM - Remove unused AspeedMachine structure Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Message-id: 20200623072132.2868-4-f4bug@amsat.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed.h | 8 +------- hw/arm/aspeed.c | 11 +++++++---- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 5114ba0bd4f..09da9d9accf 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -15,13 +15,7 @@ typedef struct AspeedMachineState AspeedMachineState; =20 #define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed") #define ASPEED_MACHINE(obj) \ - OBJECT_CHECK(AspeedMachine, (obj), TYPE_ASPEED_MACHINE) - -typedef struct AspeedMachine { - MachineState parent_obj; - - bool mmio_exec; -} AspeedMachine; + OBJECT_CHECK(AspeedMachineState, (obj), TYPE_ASPEED_MACHINE) =20 #define ASPEED_MAC0_ON (1 << 0) #define ASPEED_MAC1_ON (1 << 1) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a167b736970..665d04fbf68 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -33,9 +33,14 @@ static struct arm_boot_info aspeed_board_binfo =3D { }; =20 struct AspeedMachineState { + /* Private */ + MachineState parent_obj; + /* Public */ + AspeedSoCState soc; MemoryRegion ram_container; MemoryRegion max_ram; + bool mmio_exec; }; =20 /* Palmetto hardware value: 0x120CE416 */ @@ -253,7 +258,7 @@ static void sdhci_attach_drive(SDHCIState *sdhci, Drive= Info *dinfo) =20 static void aspeed_machine_init(MachineState *machine) { - AspeedMachineState *bmc; + AspeedMachineState *bmc =3D ASPEED_MACHINE(machine); AspeedMachineClass *amc =3D ASPEED_MACHINE_GET_CLASS(machine); AspeedSoCClass *sc; DriveInfo *drive0 =3D drive_get(IF_MTD, 0, 0); @@ -261,8 +266,6 @@ static void aspeed_machine_init(MachineState *machine) int i; NICInfo *nd =3D &nd_table[0]; =20 - bmc =3D g_new0(AspeedMachineState, 1); - memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 4 * GiB); memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); @@ -751,7 +754,7 @@ static const TypeInfo aspeed_machine_types[] =3D { }, { .name =3D TYPE_ASPEED_MACHINE, .parent =3D TYPE_MACHINE, - .instance_size =3D sizeof(AspeedMachine), + .instance_size =3D sizeof(AspeedMachineState), .instance_init =3D aspeed_machine_instance_init, .class_size =3D sizeof(AspeedMachineClass), .class_init =3D aspeed_machine_class_init, --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185330; cv=none; d=zohomail.com; s=zohoarc; b=PfdAX4bhJaWwcgsPdXOW7G8oA2GHWHgen1FVPd9Kqw80JOi26brA7fuTORdjR/liMPwefMhRN/x9G3fVFdheH94vD1Y+wBuBoEHkOKfovqXPLPafQ3hizOFi5mSIneDCm9+1Jq4mhVH84e422zU2mp9JPE2awMItmNpS9hDy2iU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185330; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5NNpdAjIha1dM9ij9yn8AmBkK2T4lQIQisubYegz+24=; b=eB/ldMsRY8IHaNKd99OvvW5am9Rn+OwmpfbvJ27/MewD83otAYsk44lQ1WUUBOYoKVKUVDy3+7TQu/XCDRzoiea2lByX2d9K4gP7be00/4GS7bBgWYWi/DuJxgxvNRrWC+BDGSnoR7oBr2REhITBoCrearpQkaB6nxcd9PM/zgs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185330580388.6993337542227; Fri, 26 Jun 2020 08:28:50 -0700 (PDT) Received: from localhost ([::1]:46158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqHZ-0000yJ-5O for importer@patchew.org; Fri, 26 Jun 2020 11:28:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35376) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq3q-0001up-Uz for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:38 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:36083) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq3m-0006Ci-JI for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:38 -0400 Received: by mail-wm1-x343.google.com with SMTP id 17so9709478wmo.1 for ; Fri, 26 Jun 2020 08:14:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5NNpdAjIha1dM9ij9yn8AmBkK2T4lQIQisubYegz+24=; b=z2bc0kBn8qni+TYpmNR47RCxvOKOtjs6XldAc2gchth767mtaVYZxHWTdCRv/CQpJS 99uuZmBzZYEj71m8qr3fCK5tWZqYe5HsDuYIO3I830t4j8iV/z4ztzQFx3vQTYmPhle2 pDOedvlfT8bXDfhEKIDQhLVP7CFuCpuQcuBQ8nztLl7YzML8iiiGMUqPLJItxD41Y0PD 93Fb2r7beiFMuGnmtxyjmLG6wNegtnFT3no66mOB+MFGEHZJ6HrLyhsWK/LNLkLkCEP+ RO4NWCQC9d8p4UA1fsuGxSG5O2M2mZWI8qe9P0668tntzprmbpszZAAKFf9jRkO+lI14 cxoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5NNpdAjIha1dM9ij9yn8AmBkK2T4lQIQisubYegz+24=; b=a/OwhZNWQcH1437kl4J62c3CCRddiP0kTCMxTEhQ1jWv5vPrRJyQ5/3S73fb80c4Q9 lW3xR5NitIWgVIM12a0viGDkdz8CMdMh62mLaWS2F5nB+dAdt1T84J7srFWgq9nj3A95 3EVOAfvlVyYEsV2iYCj9AG9fwNVe96Enzmbc/OY96zxeW+UrDAW5YoOt/C26P40CGVNI ChWketdxL+U6QxAQVYg6abEh42+CXGgskDrBSG9z5JcXsUs1rzm8LrTz0/j5UH7HIP7t uRMVM+jWkxL8Qa3010/O4GEKZsNuULcAv7/NrTYuKcVCp7iPm+idiMpqTY5LWmK+6J0P EL4A== X-Gm-Message-State: AOAM5323xKMWsby/MVR4xup2oP/SsIN6lktgb3BSI9aZVBpY/6yu1zDp yzTsY0E4OBvZQCYoAWasL16fsRef8ZKxpA== X-Google-Smtp-Source: ABdhPJzWjJJZN8A3jeQ/Yhmhn1W6jelt7U5K6bfSV8eggKX0JD1xiocNLROw0Ct4pCTkqSc5wh+k5g== X-Received: by 2002:a7b:ca52:: with SMTP id m18mr3918676wml.92.1593184471473; Fri, 26 Jun 2020 08:14:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/57] hw/i2c/core: Add i2c_try_create_slave() and i2c_realize_and_unref() Date: Fri, 26 Jun 2020 16:13:31 +0100 Message-Id: <20200626151424.30117-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 Extract i2c_try_create_slave() and i2c_realize_and_unref() from i2c_create_slave(). We can now set properties on a I2CSlave before it is realized. This is in line with the recent qdev/QOM changes merged in commit 6675a653d2e. Reviewed-by: Corey Minyard Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Markus Armbruster Tested-by: C=C3=A9dric Le Goater Message-id: 20200623072723.6324-2-f4bug@amsat.org Signed-off-by: Peter Maydell --- include/hw/i2c/i2c.h | 2 ++ hw/i2c/core.c | 18 ++++++++++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h index 41172115652..d6e3d85faf0 100644 --- a/include/hw/i2c/i2c.h +++ b/include/hw/i2c/i2c.h @@ -80,6 +80,8 @@ int i2c_send(I2CBus *bus, uint8_t data); uint8_t i2c_recv(I2CBus *bus); =20 DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr); +DeviceState *i2c_try_create_slave(const char *name, uint8_t addr); +bool i2c_realize_and_unref(DeviceState *dev, I2CBus *bus, Error **errp); =20 /* lm832x.c */ void lm832x_key_event(DeviceState *dev, int key, int state); diff --git a/hw/i2c/core.c b/hw/i2c/core.c index 1aac457a2a0..acf34a12d6d 100644 --- a/hw/i2c/core.c +++ b/hw/i2c/core.c @@ -267,13 +267,27 @@ const VMStateDescription vmstate_i2c_slave =3D { } }; =20 -DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr) +DeviceState *i2c_try_create_slave(const char *name, uint8_t addr) { DeviceState *dev; =20 dev =3D qdev_new(name); qdev_prop_set_uint8(dev, "address", addr); - qdev_realize_and_unref(dev, &bus->qbus, &error_fatal); + return dev; +} + +bool i2c_realize_and_unref(DeviceState *dev, I2CBus *bus, Error **errp) +{ + return qdev_realize_and_unref(dev, &bus->qbus, errp); +} + +DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr) +{ + DeviceState *dev; + + dev =3D i2c_try_create_slave(name, addr); + i2c_realize_and_unref(dev, bus, &error_fatal); + return dev; } =20 --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185201; cv=none; d=zohomail.com; s=zohoarc; b=h0O+ftK5N26cMTHr6w6zXSaw/2Slr8fV4ijFg7HMjGXESDldAyle8Namm+BdYuhKXY0OkC44RLQUum1dd6np+7XWXqF/1LX5v8ZfjqvSAeLONvowZEOdUbauyVq5HZD4hx+L/dh+/0qNnZngNxz+4FsVexK7YBbkG4179sd2cQw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185201; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MGJixcDIgTvYDsTmGzHDvC7oKBPaR9Bngw/q3X8ML5A=; b=RlNVd+Kl2imOmlboJLi+D49c/q0KL6kNT76IuGXrUkvza4hGtKD15mUqbPU0B7cDCgGTazLEWk9ZYSWZCAjxVkUe3d7BfnLGk4yuMPfJL4v3AVmMR5P45X5XnE+dkCmJnwTpY58eZkzkt6jS6ci2nwwBspqj7XM96wDqbZDH7R0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185201126867.1541921084215; Fri, 26 Jun 2020 08:26:41 -0700 (PDT) Received: from localhost ([::1]:37746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqFT-0005w6-Rf for importer@patchew.org; Fri, 26 Jun 2020 11:26:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35348) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq3o-0001s5-9E for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:36 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:53870) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq3m-0006DO-JY for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:35 -0400 Received: by mail-wm1-x32e.google.com with SMTP id j18so9157612wmi.3 for ; Fri, 26 Jun 2020 08:14:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MGJixcDIgTvYDsTmGzHDvC7oKBPaR9Bngw/q3X8ML5A=; b=tRd/GlfSq+fFbMFybYhBW+gWTUwa7fZtEYw8RH1txvzLYUp//sgX0paVD6KfZjCuDx hiWrh2Y3+ImLKyGN7FOKF1RR3uoYA1K+2V0VFI8cmN5z98o5oUYgp8GbGxXBIPYMZ/td YsMSjmJ91ClnAlfANoIwBwb0NGXvaRyUFVvTirpTW1stml92rOWlc4IfJ+iruFlqfHHw 4l7GjpQzqcGdX93aQy/CjieHqTNILb74S08M/80Vm5VoJlfxKaxWknN573Wq7N3A7HqN ND+zD7M9bpkl6o4AOd0kDv0SyTqy5dcpMilNw1BOzTSdnwbJc1MxS72lw+hAPlqBj0iP y6nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MGJixcDIgTvYDsTmGzHDvC7oKBPaR9Bngw/q3X8ML5A=; b=FXrJhIIRpCOibm1lUeVsRgfwdXMKYw53r/2xe5QDmomms272wrwderHvBRZdPP05D2 Z3sf7CZ/YV6MjqQL8gKsv1J6Nx7PTe0BNZJfi0wsa9BYgSl/B4y4OcJlK/HXhFBXj3Kj f/5/mzjykqLWdM9fn0CsJL5NNCdhAfano9IgWKc9XoUk5xZae0PWS1SD1b8s9nYOINvq YLaIKBrTelQSxjEet5FX+ecmh+QVN4W7gA/8UMsD9KqrRPXl0swabYmwKuO2HQ6vi/Qd lTK4UW/yzuLx2rN60AiYoGiKqVWL6bvVBLdh/OYbgVDX/J9dCQTBliy6CL+ifNun7fqw GVhg== X-Gm-Message-State: AOAM533YZylU8bGxtjoa5xcCM6zrlrpHpFAEA7y6zpUVNH1rKVj0gP1W h66KZYyAVBoCqiep3XSYAZODpmLI3a5S7g== X-Google-Smtp-Source: ABdhPJxdphpo27N1fjiYQhmRp9RSl03g7hANtNJC7zjjmv0Ss6DOA1ls0yDnp1L9p5g/Vrl9UEJRaQ== X-Received: by 2002:a7b:cb59:: with SMTP id v25mr3843942wmj.141.1593184472501; Fri, 26 Jun 2020 08:14:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/57] hw/misc/pca9552: Rename 'nr_leds' as 'pin_count' Date: Fri, 26 Jun 2020 16:13:32 +0100 Message-Id: <20200626151424.30117-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 The PCA9552 device does not expose LEDs, but simple pins to connnect LEDs to. To be clearer with the device model, rename 'nr_leds' as 'pin_count'. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: C=C3=A9dric Le Goater Message-id: 20200623072723.6324-3-f4bug@amsat.org Signed-off-by: Peter Maydell --- include/hw/misc/pca9552.h | 2 +- hw/misc/pca9552.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h index ebb43c63fe1..bc5ed310878 100644 --- a/include/hw/misc/pca9552.h +++ b/include/hw/misc/pca9552.h @@ -26,7 +26,7 @@ typedef struct PCA9552State { =20 uint8_t regs[PCA9552_NR_REGS]; uint8_t max_reg; - uint8_t nr_leds; + uint8_t pin_count; } PCA9552State; =20 #endif diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c index cac729e35af..81da757a7ea 100644 --- a/hw/misc/pca9552.c +++ b/hw/misc/pca9552.c @@ -37,7 +37,7 @@ static void pca9552_update_pin_input(PCA9552State *s) { int i; =20 - for (i =3D 0; i < s->nr_leds; i++) { + for (i =3D 0; i < s->pin_count; i++) { uint8_t input_reg =3D PCA9552_INPUT0 + (i / 8); uint8_t input_shift =3D (i % 8); uint8_t config =3D pca9552_pin_get_config(s, i); @@ -185,7 +185,7 @@ static void pca9552_get_led(Object *obj, Visitor *v, co= nst char *name, error_setg(errp, "%s: error reading %s", __func__, name); return; } - if (led < 0 || led > s->nr_leds) { + if (led < 0 || led > s->pin_count) { error_setg(errp, "%s invalid led %s", __func__, name); return; } @@ -228,7 +228,7 @@ static void pca9552_set_led(Object *obj, Visitor *v, co= nst char *name, error_setg(errp, "%s: error reading %s", __func__, name); return; } - if (led < 0 || led > s->nr_leds) { + if (led < 0 || led > s->pin_count) { error_setg(errp, "%s invalid led %s", __func__, name); return; } @@ -291,9 +291,9 @@ static void pca9552_initfn(Object *obj) * PCA955X device */ s->max_reg =3D PCA9552_LS3; - s->nr_leds =3D 16; + s->pin_count =3D 16; =20 - for (led =3D 0; led < s->nr_leds; led++) { + for (led =3D 0; led < s->pin_count; led++) { char *name; =20 name =3D g_strdup_printf("led%d", led); --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593184731; cv=none; d=zohomail.com; s=zohoarc; b=gfzDnRXDkQ0rKz4RkceshPbS7uBryPH8wkWuDvPTh4WuYZoqwOnXYvvaPZjYKtLO1QNx/O7Vu3b4FUsqFTjPwJ7TW9HBC8C5FIpiJjp3Bks0syyhDa47Xo36scweLhlt4I2kdRcanb54yGpITBN8X4V7pqD6IW0DFCP72wGbTnI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593184731; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RSrZKYU6XiD6HydRIvmILFJ3Ak6gyAmjGgVo7fpGeB0=; b=gnhJCybVIJ7kOY7Ly0BRWhMpozAQ7td+R+tMRGywDWKv9R9WJsgFPRfmlkgfL78aDOkHqCF89/MQvj6DdskP5EEyMyhIQ4MHqwbkxvQ4KrPBglrpiXZOiF3BqvTE3rfXARnUQ63G0K2dv+kS3n6uKDJYNAOqLBbFUmTQ6H99Lto= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593184731158655.7257571713834; Fri, 26 Jun 2020 08:18:51 -0700 (PDT) Received: from localhost ([::1]:57894 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joq7t-0007wZ-Rq for importer@patchew.org; Fri, 26 Jun 2020 11:18:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35424) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq3s-0001xu-Dd for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:40 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:50439) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq3o-0006Ea-BS for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:39 -0400 Received: by mail-wm1-x32f.google.com with SMTP id l17so9180221wmj.0 for ; Fri, 26 Jun 2020 08:14:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=RSrZKYU6XiD6HydRIvmILFJ3Ak6gyAmjGgVo7fpGeB0=; b=fjCspdTVMVecu1GggGELeMmg0tDoca/7upHArLWlwjgNucnK7bTFLjHQbzS0hwojQv XFJbN+vdnVa+ex8DPiWTT9KRriJuqMoarnVMcN59pvr97pina4Xo8oJLKppJKb+sOode nOAJXlE4l5//bLDuVZx5/jOWjnyFmd9gk2cD0e9d5Fl6voqqcP+majVi1pijSQDPImE4 IF3gfi8IWAmrTh4HVODIgmPieIIqWMLVcK9Vzm8dLw3BiD/YTmmi2ReDmBLv2HlKodqc ds4NuMAWpTcbUdD9yKphOwGHf0w4o/TNUWv0X8dAaJD+v9InF8eYo4slTAGQJXEH7ZNt Wj3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RSrZKYU6XiD6HydRIvmILFJ3Ak6gyAmjGgVo7fpGeB0=; b=oxKhE+QJMHERQ9VUMhdnOgYZU9lw1usOyXTVtd0s+0hSG9T4P9JazbPvzbrQLIN7mE kP+vB5Z6oyR3g/3s+KCQ8YPP2bBkzUFzGiVISzPg2SAsEcc3VUdcFns5rUP8g94b2Eoc mNx06UyTqPEd2zTqy8crWFhcIosVjZE8IKww14h2okmRTHEX4sNNDjQOZoss3a2HK1xO zqKfTJg5uwitCYIT5O6z1Ubm+B4uRv9KROu72Hf5MBM0IU+9vmMCYI8QOVvATt49UEmL WLkNdzZeXAmksH5FfaZdnAM7y3tILKp0WP2Bue6pDlz5b9oigmdgIuqiV5YiG7xMw207 zX5A== X-Gm-Message-State: AOAM532FXQ9EVVRwnXTXOIl3e6LZidAc7+T5rMUr9zk22ZPmy1C5nkDQ fitH0g+eZ0ExHxylqbzQjkXTrEc1rZJiKQ== X-Google-Smtp-Source: ABdhPJzRyoOSQitlmi9dXEiSBpS0gn/iublkvV5AYfntls0bSheVNQPwijuuOwfpqK4U2MeTPzN1yQ== X-Received: by 2002:a05:600c:2202:: with SMTP id z2mr4154899wml.13.1593184473654; Fri, 26 Jun 2020 08:14:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/57] hw/misc/pca9552: Rename generic code as pca955x Date: Fri, 26 Jun 2020 16:13:33 +0100 Message-Id: <20200626151424.30117-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 Various code from the PCA9552 device model is generic to the PCA955X family. We'll split the generic code in a base class in the next commit. To ease review, first do a dumb renaming. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: C=C3=A9dric Le Goater Message-id: 20200623072723.6324-4-f4bug@amsat.org Signed-off-by: Peter Maydell --- include/hw/misc/pca9552.h | 10 ++--- hw/misc/pca9552.c | 80 +++++++++++++++++++-------------------- 2 files changed, 45 insertions(+), 45 deletions(-) diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h index bc5ed310878..db527595a38 100644 --- a/include/hw/misc/pca9552.h +++ b/include/hw/misc/pca9552.h @@ -12,11 +12,11 @@ #include "hw/i2c/i2c.h" =20 #define TYPE_PCA9552 "pca9552" -#define PCA9552(obj) OBJECT_CHECK(PCA9552State, (obj), TYPE_PCA9552) +#define PCA955X(obj) OBJECT_CHECK(PCA955xState, (obj), TYPE_PCA9552) =20 -#define PCA9552_NR_REGS 10 +#define PCA955X_NR_REGS 10 =20 -typedef struct PCA9552State { +typedef struct PCA955xState { /*< private >*/ I2CSlave i2c; /*< public >*/ @@ -24,9 +24,9 @@ typedef struct PCA9552State { uint8_t len; uint8_t pointer; =20 - uint8_t regs[PCA9552_NR_REGS]; + uint8_t regs[PCA955X_NR_REGS]; uint8_t max_reg; uint8_t pin_count; -} PCA9552State; +} PCA955xState; =20 #endif diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c index 81da757a7ea..5681ff3b22d 100644 --- a/hw/misc/pca9552.c +++ b/hw/misc/pca9552.c @@ -25,7 +25,7 @@ =20 static const char *led_state[] =3D {"on", "off", "pwm0", "pwm1"}; =20 -static uint8_t pca9552_pin_get_config(PCA9552State *s, int pin) +static uint8_t pca955x_pin_get_config(PCA955xState *s, int pin) { uint8_t reg =3D PCA9552_LS0 + (pin / 4); uint8_t shift =3D (pin % 4) << 1; @@ -33,14 +33,14 @@ static uint8_t pca9552_pin_get_config(PCA9552State *s, = int pin) return extract32(s->regs[reg], shift, 2); } =20 -static void pca9552_update_pin_input(PCA9552State *s) +static void pca955x_update_pin_input(PCA955xState *s) { int i; =20 for (i =3D 0; i < s->pin_count; i++) { uint8_t input_reg =3D PCA9552_INPUT0 + (i / 8); uint8_t input_shift =3D (i % 8); - uint8_t config =3D pca9552_pin_get_config(s, i); + uint8_t config =3D pca955x_pin_get_config(s, i); =20 switch (config) { case PCA9552_LED_ON: @@ -58,7 +58,7 @@ static void pca9552_update_pin_input(PCA9552State *s) } } =20 -static uint8_t pca9552_read(PCA9552State *s, uint8_t reg) +static uint8_t pca955x_read(PCA955xState *s, uint8_t reg) { switch (reg) { case PCA9552_INPUT0: @@ -79,7 +79,7 @@ static uint8_t pca9552_read(PCA9552State *s, uint8_t reg) } } =20 -static void pca9552_write(PCA9552State *s, uint8_t reg, uint8_t data) +static void pca955x_write(PCA955xState *s, uint8_t reg, uint8_t data) { switch (reg) { case PCA9552_PSC0: @@ -94,7 +94,7 @@ static void pca9552_write(PCA9552State *s, uint8_t reg, u= int8_t data) case PCA9552_LS2: case PCA9552_LS3: s->regs[reg] =3D data; - pca9552_update_pin_input(s); + pca955x_update_pin_input(s); break; =20 case PCA9552_INPUT0: @@ -110,7 +110,7 @@ static void pca9552_write(PCA9552State *s, uint8_t reg,= uint8_t data) * after each byte is sent to or received by the device. The index * rollovers to 0 when the maximum register address is reached. */ -static void pca9552_autoinc(PCA9552State *s) +static void pca955x_autoinc(PCA955xState *s) { if (s->pointer !=3D 0xFF && s->pointer & PCA9552_AUTOINC) { uint8_t reg =3D s->pointer & 0xf; @@ -120,12 +120,12 @@ static void pca9552_autoinc(PCA9552State *s) } } =20 -static uint8_t pca9552_recv(I2CSlave *i2c) +static uint8_t pca955x_recv(I2CSlave *i2c) { - PCA9552State *s =3D PCA9552(i2c); + PCA955xState *s =3D PCA955X(i2c); uint8_t ret; =20 - ret =3D pca9552_read(s, s->pointer & 0xf); + ret =3D pca955x_read(s, s->pointer & 0xf); =20 /* * From the Specs: @@ -143,40 +143,40 @@ static uint8_t pca9552_recv(I2CSlave *i2c) __func__); } =20 - pca9552_autoinc(s); + pca955x_autoinc(s); =20 return ret; } =20 -static int pca9552_send(I2CSlave *i2c, uint8_t data) +static int pca955x_send(I2CSlave *i2c, uint8_t data) { - PCA9552State *s =3D PCA9552(i2c); + PCA955xState *s =3D PCA955X(i2c); =20 /* First byte sent by is the register address */ if (s->len =3D=3D 0) { s->pointer =3D data; s->len++; } else { - pca9552_write(s, s->pointer & 0xf, data); + pca955x_write(s, s->pointer & 0xf, data); =20 - pca9552_autoinc(s); + pca955x_autoinc(s); } =20 return 0; } =20 -static int pca9552_event(I2CSlave *i2c, enum i2c_event event) +static int pca955x_event(I2CSlave *i2c, enum i2c_event event) { - PCA9552State *s =3D PCA9552(i2c); + PCA955xState *s =3D PCA955X(i2c); =20 s->len =3D 0; return 0; } =20 -static void pca9552_get_led(Object *obj, Visitor *v, const char *name, +static void pca955x_get_led(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - PCA9552State *s =3D PCA9552(obj); + PCA955xState *s =3D PCA955X(obj); int led, rc, reg; uint8_t state; =20 @@ -195,7 +195,7 @@ static void pca9552_get_led(Object *obj, Visitor *v, co= nst char *name, * reading the INPUTx reg */ reg =3D PCA9552_LS0 + led / 4; - state =3D (pca9552_read(s, reg) >> (led % 8)) & 0x3; + state =3D (pca955x_read(s, reg) >> (led % 8)) & 0x3; visit_type_str(v, name, (char **)&led_state[state], errp); } =20 @@ -209,10 +209,10 @@ static inline uint8_t pca955x_ledsel(uint8_t oldval, = int led_num, int state) ((state & 0x3) << (led_num << 1)); } =20 -static void pca9552_set_led(Object *obj, Visitor *v, const char *name, +static void pca955x_set_led(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - PCA9552State *s =3D PCA9552(obj); + PCA955xState *s =3D PCA955X(obj); Error *local_err =3D NULL; int led, rc, reg, val; uint8_t state; @@ -244,9 +244,9 @@ static void pca9552_set_led(Object *obj, Visitor *v, co= nst char *name, } =20 reg =3D PCA9552_LS0 + led / 4; - val =3D pca9552_read(s, reg); + val =3D pca955x_read(s, reg); val =3D pca955x_ledsel(val, led % 4, state); - pca9552_write(s, reg, val); + pca955x_write(s, reg, val); } =20 static const VMStateDescription pca9552_vmstate =3D { @@ -254,17 +254,17 @@ static const VMStateDescription pca9552_vmstate =3D { .version_id =3D 0, .minimum_version_id =3D 0, .fields =3D (VMStateField[]) { - VMSTATE_UINT8(len, PCA9552State), - VMSTATE_UINT8(pointer, PCA9552State), - VMSTATE_UINT8_ARRAY(regs, PCA9552State, PCA9552_NR_REGS), - VMSTATE_I2C_SLAVE(i2c, PCA9552State), + VMSTATE_UINT8(len, PCA955xState), + VMSTATE_UINT8(pointer, PCA955xState), + VMSTATE_UINT8_ARRAY(regs, PCA955xState, PCA955X_NR_REGS), + VMSTATE_I2C_SLAVE(i2c, PCA955xState), VMSTATE_END_OF_LIST() } }; =20 static void pca9552_reset(DeviceState *dev) { - PCA9552State *s =3D PCA9552(dev); + PCA955xState *s =3D PCA955X(dev); =20 s->regs[PCA9552_PSC0] =3D 0xFF; s->regs[PCA9552_PWM0] =3D 0x80; @@ -275,15 +275,15 @@ static void pca9552_reset(DeviceState *dev) s->regs[PCA9552_LS2] =3D 0x55; s->regs[PCA9552_LS3] =3D 0x55; =20 - pca9552_update_pin_input(s); + pca955x_update_pin_input(s); =20 s->pointer =3D 0xFF; s->len =3D 0; } =20 -static void pca9552_initfn(Object *obj) +static void pca955x_initfn(Object *obj) { - PCA9552State *s =3D PCA9552(obj); + PCA955xState *s =3D PCA955X(obj); int led; =20 /* If support for the other PCA955X devices are implemented, these @@ -297,7 +297,7 @@ static void pca9552_initfn(Object *obj) char *name; =20 name =3D g_strdup_printf("led%d", led); - object_property_add(obj, name, "bool", pca9552_get_led, pca9552_se= t_led, + object_property_add(obj, name, "bool", pca955x_get_led, pca955x_se= t_led, NULL, NULL); g_free(name); } @@ -308,9 +308,9 @@ static void pca9552_class_init(ObjectClass *klass, void= *data) DeviceClass *dc =3D DEVICE_CLASS(klass); I2CSlaveClass *k =3D I2C_SLAVE_CLASS(klass); =20 - k->event =3D pca9552_event; - k->recv =3D pca9552_recv; - k->send =3D pca9552_send; + k->event =3D pca955x_event; + k->recv =3D pca955x_recv; + k->send =3D pca955x_send; dc->reset =3D pca9552_reset; dc->vmsd =3D &pca9552_vmstate; } @@ -318,14 +318,14 @@ static void pca9552_class_init(ObjectClass *klass, vo= id *data) static const TypeInfo pca9552_info =3D { .name =3D TYPE_PCA9552, .parent =3D TYPE_I2C_SLAVE, - .instance_init =3D pca9552_initfn, - .instance_size =3D sizeof(PCA9552State), + .instance_init =3D pca955x_initfn, + .instance_size =3D sizeof(PCA955xState), .class_init =3D pca9552_class_init, }; =20 -static void pca9552_register_types(void) +static void pca955x_register_types(void) { type_register_static(&pca9552_info); } =20 -type_init(pca9552_register_types) +type_init(pca955x_register_types) --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1kBX+OtXDHcOxGLHMho84sZlThQbaHQb6QPwO/QBb5Q=; b=w5NTZIdVxQs62effb13gdKhtG4ksaoBsW7gwrS7MZ0IWpeE6N5jgVWQgFNx96Isk+t LNChWO0Y9S12yt44tKEFmmnVIXN6a2WcyDORYhnz0SwuYx3kfopfeniaL+gbjWzJMPrM iyhCpBxgQ0B8y4/ybu++Qdc/aRSNuXcj2Ed2q3BXPL+7nr0SFYoLE5HB4woe9lBeZHo8 L3xrBfcfhj1Q8UNu6wDY1MLcMDUDTyH6InHf2/94LhK7k82e2udvDQY5y96Q0PhizN88 3/81HF3voUthZbEa/HtiXY0TNQxMhItMg4UG/PAANXgQZVw8VlkBaPsR1MKkxxBGpPXx N4Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1kBX+OtXDHcOxGLHMho84sZlThQbaHQb6QPwO/QBb5Q=; b=unusPaPjtV0p/KBf3M/p6JdOIr+7jOCAVYa5bmTVx9Exiihi/owSajHebxULO1fNTp SYwBkuZmaFqQfQk1biWOQwZiR+8YgixhHbg+r5Wrja5frIQt8MYM8tJ53+knxsuIRUwR KCAm0rLnG8WRNDGPWST8l9E7XDx9/csAPvb4Un4BRG5hvLhER828vmV/eRHgDq8cIr8B 32msy4zobBs0JqVkrBfikQRywmPoPaNmR5wZRJfRKDxRnWLRc3xclgLSIPQhXR+fj6vn lFPJocw4TMnKWvpILKXGk7yaeh3RlXVgbCRDtEuxIYBK0/TMViifyHM1OvAKCqB0nJNK P8Ew== X-Gm-Message-State: AOAM530W8LXvwPZLzd8S/rhTscNvsUKOxKhoPb95dkC3fDj1N2K5dtn5 ZrHpT+YKv6qfBvzZeWlaoGQcqN6wTCnndw== X-Google-Smtp-Source: ABdhPJxBEh2TSeJHxYPEYtFnj+F0LAP/9fShjh6LbPZ/3a03V0FNg4PV9qYoyPqYkEBTZXIuZ3C4Qw== X-Received: by 2002:a1c:6887:: with SMTP id d129mr3886228wmc.179.1593184474795; Fri, 26 Jun 2020 08:14:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/57] hw/misc/pca9552: Add generic PCA955xClass, parent of TYPE_PCA9552 Date: Fri, 26 Jun 2020 16:13:34 +0100 Message-Id: <20200626151424.30117-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 Extract the code common to the PCA955x family in PCA955xClass, keeping the PCA9552 specific parts into pca9552_class_init(). Remove the 'TODO' comment added in commit 5141d4158cf. Suggested-by: C=C3=A9dric Le Goater Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: C=C3=A9dric Le Goater Message-id: 20200623072723.6324-5-f4bug@amsat.org Signed-off-by: Peter Maydell --- include/hw/misc/pca9552.h | 6 ++-- hw/misc/pca9552.c | 66 ++++++++++++++++++++++++++++----------- 2 files changed, 51 insertions(+), 21 deletions(-) diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h index db527595a38..90843b03b8a 100644 --- a/include/hw/misc/pca9552.h +++ b/include/hw/misc/pca9552.h @@ -12,9 +12,11 @@ #include "hw/i2c/i2c.h" =20 #define TYPE_PCA9552 "pca9552" -#define PCA955X(obj) OBJECT_CHECK(PCA955xState, (obj), TYPE_PCA9552) +#define TYPE_PCA955X "pca955x" +#define PCA955X(obj) OBJECT_CHECK(PCA955xState, (obj), TYPE_PCA955X) =20 #define PCA955X_NR_REGS 10 +#define PCA955X_PIN_COUNT_MAX 16 =20 typedef struct PCA955xState { /*< private >*/ @@ -25,8 +27,6 @@ typedef struct PCA955xState { uint8_t pointer; =20 uint8_t regs[PCA955X_NR_REGS]; - uint8_t max_reg; - uint8_t pin_count; } PCA955xState; =20 #endif diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c index 5681ff3b22d..4de57dbe2e2 100644 --- a/hw/misc/pca9552.c +++ b/hw/misc/pca9552.c @@ -4,6 +4,7 @@ * https://www.nxp.com/docs/en/application-note/AN264.pdf * * Copyright (c) 2017-2018, IBM Corporation. + * Copyright (c) 2020 Philippe Mathieu-Daud=C3=A9 * * This work is licensed under the terms of the GNU GPL, version 2 or * later. See the COPYING file in the top-level directory. @@ -18,6 +19,20 @@ #include "qapi/error.h" #include "qapi/visitor.h" =20 +typedef struct PCA955xClass { + /*< private >*/ + I2CSlaveClass parent_class; + /*< public >*/ + + uint8_t pin_count; + uint8_t max_reg; +} PCA955xClass; + +#define PCA955X_CLASS(klass) \ + OBJECT_CLASS_CHECK(PCA955xClass, (klass), TYPE_PCA955X) +#define PCA955X_GET_CLASS(obj) \ + OBJECT_GET_CLASS(PCA955xClass, (obj), TYPE_PCA955X) + #define PCA9552_LED_ON 0x0 #define PCA9552_LED_OFF 0x1 #define PCA9552_LED_PWM0 0x2 @@ -35,9 +50,10 @@ static uint8_t pca955x_pin_get_config(PCA955xState *s, i= nt pin) =20 static void pca955x_update_pin_input(PCA955xState *s) { + PCA955xClass *k =3D PCA955X_GET_CLASS(s); int i; =20 - for (i =3D 0; i < s->pin_count; i++) { + for (i =3D 0; i < k->pin_count; i++) { uint8_t input_reg =3D PCA9552_INPUT0 + (i / 8); uint8_t input_shift =3D (i % 8); uint8_t config =3D pca955x_pin_get_config(s, i); @@ -112,10 +128,12 @@ static void pca955x_write(PCA955xState *s, uint8_t re= g, uint8_t data) */ static void pca955x_autoinc(PCA955xState *s) { + PCA955xClass *k =3D PCA955X_GET_CLASS(s); + if (s->pointer !=3D 0xFF && s->pointer & PCA9552_AUTOINC) { uint8_t reg =3D s->pointer & 0xf; =20 - reg =3D (reg + 1) % (s->max_reg + 1); + reg =3D (reg + 1) % (k->max_reg + 1); s->pointer =3D reg | PCA9552_AUTOINC; } } @@ -176,6 +194,7 @@ static int pca955x_event(I2CSlave *i2c, enum i2c_event = event) static void pca955x_get_led(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { + PCA955xClass *k =3D PCA955X_GET_CLASS(obj); PCA955xState *s =3D PCA955X(obj); int led, rc, reg; uint8_t state; @@ -185,7 +204,7 @@ static void pca955x_get_led(Object *obj, Visitor *v, co= nst char *name, error_setg(errp, "%s: error reading %s", __func__, name); return; } - if (led < 0 || led > s->pin_count) { + if (led < 0 || led > k->pin_count) { error_setg(errp, "%s invalid led %s", __func__, name); return; } @@ -212,6 +231,7 @@ static inline uint8_t pca955x_ledsel(uint8_t oldval, in= t led_num, int state) static void pca955x_set_led(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { + PCA955xClass *k =3D PCA955X_GET_CLASS(obj); PCA955xState *s =3D PCA955X(obj); Error *local_err =3D NULL; int led, rc, reg, val; @@ -228,7 +248,7 @@ static void pca955x_set_led(Object *obj, Visitor *v, co= nst char *name, error_setg(errp, "%s: error reading %s", __func__, name); return; } - if (led < 0 || led > s->pin_count) { + if (led < 0 || led > k->pin_count) { error_setg(errp, "%s invalid led %s", __func__, name); return; } @@ -283,17 +303,11 @@ static void pca9552_reset(DeviceState *dev) =20 static void pca955x_initfn(Object *obj) { - PCA955xState *s =3D PCA955X(obj); + PCA955xClass *k =3D PCA955X_GET_CLASS(obj); int led; =20 - /* If support for the other PCA955X devices are implemented, these - * constant values might be part of class structure describing the - * PCA955X device - */ - s->max_reg =3D PCA9552_LS3; - s->pin_count =3D 16; - - for (led =3D 0; led < s->pin_count; led++) { + assert(k->pin_count <=3D PCA955X_PIN_COUNT_MAX); + for (led =3D 0; led < k->pin_count; led++) { char *name; =20 name =3D g_strdup_printf("led%d", led); @@ -303,28 +317,44 @@ static void pca955x_initfn(Object *obj) } } =20 -static void pca9552_class_init(ObjectClass *klass, void *data) +static void pca955x_class_init(ObjectClass *klass, void *data) { - DeviceClass *dc =3D DEVICE_CLASS(klass); I2CSlaveClass *k =3D I2C_SLAVE_CLASS(klass); =20 k->event =3D pca955x_event; k->recv =3D pca955x_recv; k->send =3D pca955x_send; +} + +static const TypeInfo pca955x_info =3D { + .name =3D TYPE_PCA955X, + .parent =3D TYPE_I2C_SLAVE, + .instance_init =3D pca955x_initfn, + .instance_size =3D sizeof(PCA955xState), + .class_init =3D pca955x_class_init, + .abstract =3D true, +}; + +static void pca9552_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PCA955xClass *pc =3D PCA955X_CLASS(oc); + dc->reset =3D pca9552_reset; dc->vmsd =3D &pca9552_vmstate; + pc->max_reg =3D PCA9552_LS3; + pc->pin_count =3D 16; } =20 static const TypeInfo pca9552_info =3D { .name =3D TYPE_PCA9552, - .parent =3D TYPE_I2C_SLAVE, - .instance_init =3D pca955x_initfn, - .instance_size =3D sizeof(PCA955xState), + .parent =3D TYPE_PCA955X, .class_init =3D pca9552_class_init, }; =20 static void pca955x_register_types(void) { + type_register_static(&pca955x_info); type_register_static(&pca9552_info); } =20 --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593184787; cv=none; d=zohomail.com; s=zohoarc; b=FVBr5HTXbscaaAqn0P/L4HjCZrSMwPWRJ0qdnfd/fEWewqqjTHtl66aSyxh2twiZ4JXMvvQVFXLBHUuuEAiUE94FT5f2bHeRoL2eWTbUARg5EM5dnZ5rbhMNvm3/iGnvUt+Kb72HFg/6y+F1Rfzeawk5LkuBao7dWHSdLv106E4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593184787; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Q8Ef3HWA8rNM9aTbA2EQAMf+hEg1mxxGyImAVLJmAIk=; b=sZg3zG2ErKaNOpVPZrMhqJcUjKJC77ZU+jmPSW2KgjOQ4tOEnJiT2Zu5jnQ+SIjjW7 H2JFwjL2MiAKYKjDHw/gMuB96cmNceiWZGZ3co6eNvyocEDXmIUheXwvbMnpry9fkDZc dYQrJsJSNjoGQR7diwv1p1/EjzI2mVFfM7PzajphkljC8tqRII6gw6dT4YB0TpsbeV7s AmU92bfkBF0OOw7GIi4w9Qb6V5xLhgDgPYZKLQHUIOoKr0g6NvOrVgBu6DaW9onGGvQ4 hZGVT1yXmNQqVNAHSz/DUz7Ky3ZN3l2LbnrYPJhcSmZaz951elvakB0ckgBNFcJDV5l9 NyMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q8Ef3HWA8rNM9aTbA2EQAMf+hEg1mxxGyImAVLJmAIk=; b=PxFx8+t6V+lANn9EI9YByLsXPQUyDhWFSWK+n47m2EFO53F+Ax1weE6TcSf009VaJl 31yd7iS+sHLQnHGV9NmhBd+LS3VLlY688wmNfI2a0yvBh5Hd40NDwEO/0Xnto5iT3bPP 4XrIGkY0cvGsWHC9zTclkUehnVLMGNH/XvbId+JmUnPO3UqUwaqhllGuhwDypSGwb4kR 9Hmi/hv9oy51ijgdrD+kfEkF87A1Abq+H3QvCM+aYHd3BkbJgHrJWDlxJzKv/M8Lxyhg 9i70jG3vqlD4mWxvvjIoAFA4auGgs3s5LEFlACY3jCKdswwanww5+KCoyjsuXTUMVGH3 FZVQ== X-Gm-Message-State: AOAM530YS2yCnuIn9VxIQS5/TD8xFDJtYNMR+e1HQS4uBKR+Ou9BqqCX lKVhGcq19fFbyyTcL1lmOVL68ntteTUX0Q== X-Google-Smtp-Source: ABdhPJwRYMVOauEYyWDMd6dL1z0UwW/sprD3rPfVgbjzawwk/whZ6CliGGJWD6V6RadziUekliIc2w== X-Received: by 2002:a1c:e143:: with SMTP id y64mr3910481wmg.90.1593184475946; Fri, 26 Jun 2020 08:14:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/57] hw/misc/pca9552: Add a 'description' property for debugging purpose Date: Fri, 26 Jun 2020 16:13:35 +0100 Message-Id: <20200626151424.30117-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 Add a description field to distinguish between multiple devices. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: C=C3=A9dric Le Goater Message-id: 20200623072723.6324-6-f4bug@amsat.org Signed-off-by: Peter Maydell --- include/hw/misc/pca9552.h | 1 + hw/misc/pca9552.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h index 90843b03b8a..bf1a5891378 100644 --- a/include/hw/misc/pca9552.h +++ b/include/hw/misc/pca9552.h @@ -27,6 +27,7 @@ typedef struct PCA955xState { uint8_t pointer; =20 uint8_t regs[PCA955X_NR_REGS]; + char *description; /* For debugging purpose only */ } PCA955xState; =20 #endif diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c index 4de57dbe2e2..2cc52b02057 100644 --- a/hw/misc/pca9552.c +++ b/hw/misc/pca9552.c @@ -13,6 +13,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/module.h" +#include "hw/qdev-properties.h" #include "hw/misc/pca9552.h" #include "hw/misc/pca9552_regs.h" #include "migration/vmstate.h" @@ -317,13 +318,30 @@ static void pca955x_initfn(Object *obj) } } =20 +static void pca955x_realize(DeviceState *dev, Error **errp) +{ + PCA955xState *s =3D PCA955X(dev); + + if (!s->description) { + s->description =3D g_strdup("pca-unspecified"); + } +} + +static Property pca955x_properties[] =3D { + DEFINE_PROP_STRING("description", PCA955xState, description), + DEFINE_PROP_END_OF_LIST(), +}; + static void pca955x_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc =3D DEVICE_CLASS(klass); I2CSlaveClass *k =3D I2C_SLAVE_CLASS(klass); =20 k->event =3D pca955x_event; k->recv =3D pca955x_recv; k->send =3D pca955x_send; + dc->realize =3D pca955x_realize; + device_class_set_props(dc, pca955x_properties); } =20 static const TypeInfo pca955x_info =3D { --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593184821; cv=none; d=zohomail.com; s=zohoarc; b=TrnuqheOt/Xev/HQAEX95fOzvIU4m2wh2pnlr2OkN+jF1oxM/Eqc+CubwsXQ9gQgOvCjOEtnLIjB3Pi5nocDCj9dr1pIHbQpcl1aC5UQ5rypDhNQL5W6yGJOBNVtN7lFgMk6gtqlzy79a6dH50Dxwm6R9pOBTJCAGHxCwfETK5s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593184821; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NAVH5y7iWpRw66JxeAnEE7mguU/FzOf8PzQCxUY5S0o=; b=HSc3DXXtEWO0JZ1WfXsFakGw0pa8ZBYtAUQvJB5cHr1Cz2zZPbyfVsFV2F8kjzhlK2Ubx4Yv7Yf0GSUn48gQwIlP6N9YDvtz1OR7uBKzGoOLEWKjjGjYzIrc3DZ30Ez6hzxKJalqzZwgVf+f/gUBjzdOUdgP6ZIhB135Q/plVRU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593184821075272.66569604462416; Fri, 26 Jun 2020 08:20:21 -0700 (PDT) Received: from localhost ([::1]:36944 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joq9L-0002Tz-Il for importer@patchew.org; Fri, 26 Jun 2020 11:20:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35468) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq3x-00021f-N7 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:45 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:44776) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq3q-0006GO-LV for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:45 -0400 Received: by mail-wr1-x444.google.com with SMTP id b6so9837189wrs.11 for ; Fri, 26 Jun 2020 08:14:38 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NAVH5y7iWpRw66JxeAnEE7mguU/FzOf8PzQCxUY5S0o=; b=iryO9eF9WC5BuHf5JIEB980xDud3lSmurQ/PHj4rSK+1R4O/rf4aQNogVcIKF5QYq0 0MQNcxmMSTsAl1c5DcYPn5BwaoNxnvRQrVBh2FfKJwfz0RE4EVoETX0Cgox6/d5Ulaqq GP4oEyT+WfvjHYcmJufkpRRv63gCY1f7m5UJqBMC2Zl3zy2rfiChL1fL47f1/BTZDp1F M27fu5lCXbp9f9fPrkoopRFKPFA0z9vmyiFzRM0OQzQ8znMoDojL5Xv4xshLvPQ6NMv+ MtGtS4TyUE8O8LmS1NthGf9ybUAiSsRyBUruHxeT0RifO2RD5caIKXwEPDZAu2zIsS3P 9OYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NAVH5y7iWpRw66JxeAnEE7mguU/FzOf8PzQCxUY5S0o=; b=CBDiDlkyxXM1s8rt4wbBMIIJWrEBG2CUv/C8ifbN/nUAP3tHWy7GPszGA8NXYDAF2E rdBVWkrrs9gcXVGFAypjv5gIDbLVCdMLm16wuGnO7xVPpR79mQCRvieV1GS5S/oamZfn 7U6nYXRBxi/rhMfTncEsNg088xISQhC/WLyWUbRhandIlOkm3rER19X2k/nHTOJUtla/ 4A/TOOR/cXB+uHApj66ZjKG72YlDyixkmmfC4Wmz338G8HtEi3cVxnYXgKzwB/HR/RRy SCDBRaRkLP5aT1x3FQ2VTtFVRKA78d3hFjbmoVbsexxmK7D56J8c3OK8pzZuI0OTFmDL 5nzg== X-Gm-Message-State: AOAM530q+4aGrDQFwQaAp9c54IM5VoP3gc6tvYZyuMBGtDylkbbPbNhs 9uwQpm5iWLErpzofjhairI5ZbOmp/tiZEg== X-Google-Smtp-Source: ABdhPJxd/4VmNXEoVwl8m/RpvpfsYOMzhSl7JqCitiaMNRCpBmeKKpgZC3YTcc8k8uVd4jFtla3pBg== X-Received: by 2002:a5d:4a45:: with SMTP id v5mr4309953wrs.228.1593184476975; Fri, 26 Jun 2020 08:14:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/57] hw/misc/pca9552: Trace GPIO High/Low events Date: Fri, 26 Jun 2020 16:13:36 +0100 Message-Id: <20200626151424.30117-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 Add a trivial representation of the PCA9552 GPIOs. Example booting obmc-phosphor-image: $ qemu-system-arm -M witherspoon-bmc -trace pca955x_gpio_status 1592689902.327837:pca955x_gpio_status pca-unspecified GPIOs 0-15 [*......= .........] 1592689902.329934:pca955x_gpio_status pca-unspecified GPIOs 0-15 [**.....= .........] 1592689902.330717:pca955x_gpio_status pca-unspecified GPIOs 0-15 [***....= .........] 1592689902.331431:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****...= .........] 1592689902.332163:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****...= ......*..] 1592689902.332888:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****...= ......**.] 1592689902.333629:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****...= ......***] 1592690032.793289:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****...= ......*.*] 1592690033.303163:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****...= ......***] 1592690033.812962:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****...= ......*.*] 1592690034.323234:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****...= ......***] 1592690034.832922:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****...= ......*.*] We notice the GPIO #14 (front-power LED) starts to blink. This LED is described in the witherspoon device-tree [*]: front-power { retain-state-shutdown; default-state =3D "keep"; gpios =3D <&pca0 14 GPIO_ACTIVE_LOW>; }; [*] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts?id=3Db1f9be9392f0#n140 Suggested-by: C=C3=A9dric Le Goater Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: C=C3=A9dric Le Goater Message-id: 20200623072723.6324-7-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/misc/pca9552.c | 39 +++++++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 3 +++ 2 files changed, 42 insertions(+) diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c index 2cc52b02057..41f8ad213dd 100644 --- a/hw/misc/pca9552.c +++ b/hw/misc/pca9552.c @@ -13,12 +13,14 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/module.h" +#include "qemu/bitops.h" #include "hw/qdev-properties.h" #include "hw/misc/pca9552.h" #include "hw/misc/pca9552_regs.h" #include "migration/vmstate.h" #include "qapi/error.h" #include "qapi/visitor.h" +#include "trace.h" =20 typedef struct PCA955xClass { /*< private >*/ @@ -49,6 +51,39 @@ static uint8_t pca955x_pin_get_config(PCA955xState *s, i= nt pin) return extract32(s->regs[reg], shift, 2); } =20 +/* Return INPUT status (bit #N belongs to GPIO #N) */ +static uint16_t pca955x_pins_get_status(PCA955xState *s) +{ + return (s->regs[PCA9552_INPUT1] << 8) | s->regs[PCA9552_INPUT0]; +} + +static void pca955x_display_pins_status(PCA955xState *s, + uint16_t previous_pins_status) +{ + PCA955xClass *k =3D PCA955X_GET_CLASS(s); + uint16_t pins_status, pins_changed; + int i; + + pins_status =3D pca955x_pins_get_status(s); + pins_changed =3D previous_pins_status ^ pins_status; + if (!pins_changed) { + return; + } + if (trace_event_get_state_backends(TRACE_PCA955X_GPIO_STATUS)) { + char *buf =3D g_newa(char, k->pin_count + 1); + + for (i =3D 0; i < k->pin_count; i++) { + if (extract32(pins_status, i, 1)) { + buf[i] =3D '*'; + } else { + buf[i] =3D '.'; + } + } + buf[i] =3D '\0'; + trace_pca955x_gpio_status(s->description, buf); + } +} + static void pca955x_update_pin_input(PCA955xState *s) { PCA955xClass *k =3D PCA955X_GET_CLASS(s); @@ -98,6 +133,8 @@ static uint8_t pca955x_read(PCA955xState *s, uint8_t reg) =20 static void pca955x_write(PCA955xState *s, uint8_t reg, uint8_t data) { + uint16_t pins_status; + switch (reg) { case PCA9552_PSC0: case PCA9552_PWM0: @@ -110,8 +147,10 @@ static void pca955x_write(PCA955xState *s, uint8_t reg= , uint8_t data) case PCA9552_LS1: case PCA9552_LS2: case PCA9552_LS3: + pins_status =3D pca955x_pins_get_status(s); s->regs[reg] =3D data; pca955x_update_pin_input(s); + pca955x_display_pins_status(s, pins_status); break; =20 case PCA9552_INPUT0: diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 68a6d9f2ab8..bd7bd37ea8d 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -209,3 +209,6 @@ via1_adb_poll(uint8_t data, const char *vadbint, int st= atus, int index, int size # grlib_ahb_apb_pnp.c grlib_ahb_pnp_read(uint64_t addr, uint32_t value) "AHB PnP read addr:0x%03= "PRIx64" data:0x%08x" grlib_apb_pnp_read(uint64_t addr, uint32_t value) "APB PnP read addr:0x%03= "PRIx64" data:0x%08x" + +# pca9552.c +pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-= 15 [%s]" --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=amm+Xwelw2VlS16IoGViV05sMwQyqKglsr1nUDeUMzc=; b=L9I6MPnBMynVstZHCNTeCqW3qUr/7ccQdoU+qM9PT+EOsSfQEMVYOtBa1kp4ryCFLu 0y2fEm1SMmXZScba85AQpTJEhoc1sh18GdaKSj49LMrta6nr9Mux/iDOWfeg8rhixGdh gCgQJv84HoSSZhza/IdEjKbesTLa3e03sj5WrMiSQzi7t/322MYfsvcBTMWF307mB+GU 6oSauxf8PvUiGpLWit25+78+c/6WT+a7QfuTyePF3SU23ky9uH3UVikK0AVsRBWJV0uC 39XPBpbNYY2LYL4Rhwz6jWWBYGxwoHi8MRKyGAReQGRT1SgrAUmDN/i9m8BcITjbCu45 F+PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=amm+Xwelw2VlS16IoGViV05sMwQyqKglsr1nUDeUMzc=; b=W6RfdsFx9wK4v9z0biiVDB2yfmGLkcEARrwgtTG4W/JYM5ZouL64fn3aL3keV64RKk 4eN99gXfewx2nj+tfPj5lVULOLi991Pw+QLsi+tLX3Jw3szMqttPnZG7HHZ5xwWhYLwq ns7PCYhDk2AqpYliWs3p11LPhmdBtXsEORyzt0RQ1rIPbZi9E2gnLYSFjxTJi0VwXclU IVjmSgXw9vj3oMqzFXAy/raSGhdzqoP4vuBakBr2Wdebfe4oDrWNtz6jLF4dbFb0tMgj iea7LzcUT79lQvqUyq895XczBPLBvrZKL8/RlEsmuvkm4ar16nRKpvepS+CM4CrYNwsz ZASg== X-Gm-Message-State: AOAM5323Ll4PWEofJVOEKA9MK9Pk/SImE4FlrERTgwzHBz4LUE/FnbZs eZskKkTgyba4Yc1uKWa02PxKDcD9YXIA6A== X-Google-Smtp-Source: ABdhPJxhCc25FxQW1bYV1tSWDd0I0659PEMnjTzbnTzZvBK9qBw0ArGLuChi5oSOU9tGC17mazsqZw== X-Received: by 2002:a1c:2d83:: with SMTP id t125mr4026270wmt.187.1593184477864; Fri, 26 Jun 2020 08:14:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/57] hw/arm/aspeed: Describe each PCA9552 device Date: Fri, 26 Jun 2020 16:13:37 +0100 Message-Id: <20200626151424.30117-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 We have 2 distinct PCA9552 devices. Set their description to distinguish them when looking at the trace events. Description name taken from: https://github.com/open-power/witherspoon-xml/blob/master/witherspoon.xml Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Corey Minyard Reviewed-by: Markus Armbruster Tested-by: C=C3=A9dric Le Goater Message-id: 20200623072723.6324-8-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 665d04fbf68..379f9672a56 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -508,12 +508,15 @@ static void witherspoon_bmc_i2c_init(AspeedMachineSta= te *bmc) { AspeedSoCState *soc =3D &bmc->soc; uint8_t *eeprom_buf =3D g_malloc0(8 * 1024); + DeviceState *dev; =20 /* Bus 3: TODO bmp280@77 */ /* Bus 3: TODO max31785@52 */ /* Bus 3: TODO dps310@76 */ - i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA955= 2, - 0x60); + dev =3D i2c_try_create_slave(TYPE_PCA9552, 0x60); + qdev_prop_set_string(dev, "description", "pca1"); + i2c_realize_and_unref(dev, aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), + &error_fatal); =20 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0= x4c); i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0= x4c); @@ -528,8 +531,10 @@ static void witherspoon_bmc_i2c_init(AspeedMachineStat= e *bmc) =20 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51, eeprom_buf); - i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA95= 52, - 0x60); + dev =3D i2c_try_create_slave(TYPE_PCA9552, 0x60); + qdev_prop_set_string(dev, "description", "pca0"); + i2c_realize_and_unref(dev, aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), + &error_fatal); /* Bus 11: TODO ucd90160@64 */ } =20 --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593184701; cv=none; d=zohomail.com; s=zohoarc; b=lI3C7j70YEA4JsjFLDxq21+1WFFQ6NltFk2Zs+Ws04uXKCSpsby0jvBEPCfMtQNal6PxpT9QE71xcmuA1G6ouupASdwhql7oQ+YgbqCrjgY+B1pIUoqx66uK/cvDy5GIa6EjJMFkR6DrcgKUGDUz3fgPGCkXyssIlMq04Q1fa2M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593184701; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RX+/KL2V5N56qsvGdealctYk7vBUGmzE5uNTGiV8fFk=; b=T8yNhBly8Euc1uRUYTf97muxPRVkSZIP4m3aDVgBxvN0Jit2F2olPDdWnRNnuixYVGopcZQ9xkeztcoZq37uKpB8R3o+yRytF8hcYP8sI/rwlaveQDbylBubRBlSvUeYQCdAgmHR0OrX2It33iMDFwvNBsMFYegIqtoC7Uf9+AA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593184701483686.5453091830777; Fri, 26 Jun 2020 08:18:21 -0700 (PDT) Received: from localhost ([::1]:55756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joq7Q-00071E-14 for importer@patchew.org; Fri, 26 Jun 2020 11:18:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq40-00027V-Cy for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:48 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:34837) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq3w-0006I1-Pv for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:48 -0400 Received: by mail-wr1-x42b.google.com with SMTP id g18so9900907wrm.2 for ; Fri, 26 Jun 2020 08:14:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=RX+/KL2V5N56qsvGdealctYk7vBUGmzE5uNTGiV8fFk=; b=UPfqbBg6Plf49zdwp7xWUDjXIB2z+dfIP4BQftCMCYq8IKwFEerltLx5GeUDX/hAkJ nV/CP/+CQM60BL+QIXHfVtTQrMjDqL39nVg/stduAa4Zc1eGuODLCJHANW0WKFCTj/am P+o3Pp17M3K/0cRge9gBCBfkWTQLoTQFpgMDJpa+HFufJ0ylde8r6HbzHHCNq+qqhMXl ygQLtWHfGHS73RNBMLpBtV0npSg3u0zAvY+JaGI52b93H6U9aWE6Wx707JP3UjK5ERyo gieBKBbmvu81XdJ9m2UVm+jtAoqr1eF0JnwrkFfHF/CKANFNYh664vv+94Ip7NdzhW9v y8AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RX+/KL2V5N56qsvGdealctYk7vBUGmzE5uNTGiV8fFk=; b=pKUywJpaqsgUE3jvsCdYVagV5znja4wU+ezINasnkyOqItNH2vgqmga1IqLNF2k4Kp auizKDyyhKugjZfnBCI15pID6kq2vpB9LZewcbQ7NMIxkp6DITSyp/afJNo986P3Jizi jNOugHVTzicFNq6c1wbBmh6Iv4owZFeJpTIC/ukLWkursPkydNsxxYE5m4UI8k7V66rs GofnghgG4vKANyky9TVsy42Sq0xVCHtp9EnZYcrSfuyCZbbkegUqdxF47ZkLq4indh4S wUs2JFKOc9yayyI5MLKGjRXmBtDaUjjckbSWSLHmMX0YNAsbtfZzGD1DstOw3B+IxRjg 2TRQ== X-Gm-Message-State: AOAM531cKrehAH3jrlQp4Lz3OLPTwRNQOfZ0D9Bh/RIZ7USZHiPXTLjP pcFhg7tumYdta1X8nh4fwyT8iqRCFmGPFg== X-Google-Smtp-Source: ABdhPJzIT3HXS6wf54XZdzojf+5Yu+3JGXH+xEiZ6wWlzzZl4BzFfSOsaZYGHDmfvFxyOYwTGCF7gg== X-Received: by 2002:adf:dc90:: with SMTP id r16mr4360107wrj.264.1593184478890; Fri, 26 Jun 2020 08:14:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/57] hw/misc/pca9552: Trace GPIO change events Date: Fri, 26 Jun 2020 16:13:38 +0100 Message-Id: <20200626151424.30117-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 Emit a trace event when a GPIO change its state. Example booting obmc-phosphor-image: $ qemu-system-arm -M witherspoon-bmc -trace pca955x_gpio_change 1592690552.687372:pca955x_gpio_change pca1 GPIO id:0 status: 0 -> 1 1592690552.690169:pca955x_gpio_change pca1 GPIO id:1 status: 0 -> 1 1592690552.691673:pca955x_gpio_change pca1 GPIO id:2 status: 0 -> 1 1592690552.696886:pca955x_gpio_change pca1 GPIO id:3 status: 0 -> 1 1592690552.698614:pca955x_gpio_change pca1 GPIO id:13 status: 0 -> 1 1592690552.699833:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1 1592690552.700842:pca955x_gpio_change pca1 GPIO id:15 status: 0 -> 1 1592690683.841921:pca955x_gpio_change pca1 GPIO id:14 status: 1 -> 0 1592690683.861660:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1 1592690684.371460:pca955x_gpio_change pca1 GPIO id:14 status: 1 -> 0 1592690684.882115:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1 1592690685.391411:pca955x_gpio_change pca1 GPIO id:14 status: 1 -> 0 1592690685.901391:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1 1592690686.411678:pca955x_gpio_change pca1 GPIO id:14 status: 1 -> 0 1592690686.921279:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1 We notice the GPIO #14 (front-power LED) starts to blink. This LED is described in the witherspoon device-tree [*]: front-power { retain-state-shutdown; default-state =3D "keep"; gpios =3D <&pca0 14 GPIO_ACTIVE_LOW>; }; [*] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts?id=3Db1f9be9392f0#n140 Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: C=C3=A9dric Le Goater Message-id: 20200623072723.6324-9-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/misc/pca9552.c | 15 +++++++++++++++ hw/misc/trace-events | 1 + 2 files changed, 16 insertions(+) diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c index 41f8ad213dd..1c3ad57432a 100644 --- a/hw/misc/pca9552.c +++ b/hw/misc/pca9552.c @@ -82,6 +82,21 @@ static void pca955x_display_pins_status(PCA955xState *s, buf[i] =3D '\0'; trace_pca955x_gpio_status(s->description, buf); } + if (trace_event_get_state_backends(TRACE_PCA955X_GPIO_CHANGE)) { + for (i =3D 0; i < k->pin_count; i++) { + if (extract32(pins_changed, i, 1)) { + unsigned new_state =3D extract32(pins_status, i, 1); + + /* + * We display the state using the PCA logic ("active-high"= ). + * This is not the state of the LED, which signal might be + * wired "active-low" on the board. + */ + trace_pca955x_gpio_change(s->description, i, + !new_state, new_state); + } + } + } } =20 static void pca955x_update_pin_input(PCA955xState *s) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index bd7bd37ea8d..ebea53735c4 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -212,3 +212,4 @@ grlib_apb_pnp_read(uint64_t addr, uint32_t value) "APB = PnP read addr:0x%03"PRIx6 =20 # pca9552.c pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-= 15 [%s]" +pca955x_gpio_change(const char *description, unsigned id, unsigned prev_st= ate, unsigned current_state) "%s GPIO id:%u status: %u -> %u" --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593184571; cv=none; d=zohomail.com; s=zohoarc; b=lMwUgCIzinrOAF0582a+ihr8v7+vMvFafoGDXoOUVfo7mvFnazbDNs6WOOTZMFwnH2PTycTy++A3hcTrAHrnMH083PGshrV23Y3t3Z9hVfCa22IMEZTx7OYNHuCAi0tW14E7Upwtwz0+hiWlHrGePBPoCez/w9AMj5KtkAZNpc0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593184571; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KiwKMAfLqBpV0Mc8jDI36+MCGtlMsxICaCbL8Ck1LtA=; b=QRTX6WdfNjdlh8gLfMBXil6sBXqg2euZWZDQtD1DyJXIYxguqO4CL2rtsaXoriXVTVS3v+zvggTJd2vXjDgrsdYxdGcRfPyCt334LjYpy1oCYBW+IjPzCW/kZSJ3tgAz4QeCwOvvp1anhuIX6PraSRoGJGLYpteaY2KYCCczSkE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159318457113260.45056787900512; Fri, 26 Jun 2020 08:16:11 -0700 (PDT) Received: from localhost ([::1]:48608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joq5J-00047R-RF for importer@patchew.org; Fri, 26 Jun 2020 11:16:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35540) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq3z-00026R-Ue for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:47 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:37170) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq3w-0006IN-Pi for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:47 -0400 Received: by mail-wr1-x42e.google.com with SMTP id a6so9868289wrm.4 for ; Fri, 26 Jun 2020 08:14:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KiwKMAfLqBpV0Mc8jDI36+MCGtlMsxICaCbL8Ck1LtA=; b=viX4ROki9khXvURFoFHvwAW4qmRvNI1j3aTat0WLzRFeDUVmfut10SBSAlLI6Y5YgO YeTzj71kRWt6VRRCf1nAdSfa9+3qve8wb4BJfW64q7nXtMf0ekGQvBhlVwCiih6+nfOo UTl33igRbfRbct1kvr2rKLlgE0Ndnh2DC3zQ3JNCIxweioR4ftvns6Y0GIV0GD+J4Bmc gAXYYD0lgvp0Ex7HIVrFV8b1Tr2FFe5+nDFeQCPTU3IAiwL3upKxJiPTX+SeMmjazYD8 eIEPGd8Bw5ClPhPf9V3x1ROldFy0mxAJ0JR1KWh9/VIb1TQuuUubucLqcpDxz5KymI/Q Jk6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KiwKMAfLqBpV0Mc8jDI36+MCGtlMsxICaCbL8Ck1LtA=; b=PbizvoJqeZm1c/Gp97Lu/6IdioZSHQRHFdCTCD/bw7h3/brDxsJE1gKDJOFhaxg9Fe WHZojbpOVCEkZI7TDiPIwcLnANgfrBkgrAmS8xorKh7hQhDTzx4rm62KHAHHfQc/wKeB h3UY//avu8haoYAGmD2fffKJTBu3006Saj7P30SYSYFtFTqfoI6EkTXv1GZuHC6b58uc k4kJAQPXpl5uBCMU/hPJQrt0qBhct+buYNAog+aubiIYG9P2zY2DbC11BKzVyeOcAL+n MHRrOL4LjaKSrR81h5LdB0hgJbfpnCsNdyahItWm51xfvmruhDPdxN2MFYaSdmC4/Nzv tyow== X-Gm-Message-State: AOAM531sPnNUL/U38BgX6aULOQzVA9ggmI/FnkAIOdb1ZIv1AivBh7dT WlRSheMhrxAL3JV630TKMhNEW2balTeI+w== X-Google-Smtp-Source: ABdhPJwbpdXvjx3kn9wB+AxaIeKP6qi5gG0T0KAzQvBznRZ3fFEVjzKaKColgahPcVH6h1u3UcJAwQ== X-Received: by 2002:adf:de01:: with SMTP id b1mr4160836wrm.305.1593184480108; Fri, 26 Jun 2020 08:14:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/57] hw/misc/pca9552: Model qdev output GPIOs Date: Fri, 26 Jun 2020 16:13:39 +0100 Message-Id: <20200626151424.30117-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 The PCA9552 has 16 GPIOs which can be used as input, output or PWM mode. QEMU models the output GPIO with the qemu_irq type. Let the device expose the 16 GPIOs to allow us to later connect LEDs to these outputs. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: C=C3=A9dric Le Goater Message-id: 20200623072723.6324-10-f4bug@amsat.org Signed-off-by: Peter Maydell --- include/hw/misc/pca9552.h | 1 + hw/misc/pca9552.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h index bf1a5891378..600356fbf90 100644 --- a/include/hw/misc/pca9552.h +++ b/include/hw/misc/pca9552.h @@ -27,6 +27,7 @@ typedef struct PCA955xState { uint8_t pointer; =20 uint8_t regs[PCA955X_NR_REGS]; + qemu_irq gpio[PCA955X_PIN_COUNT_MAX]; char *description; /* For debugging purpose only */ } PCA955xState; =20 diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c index 1c3ad57432a..80caa9ec8fc 100644 --- a/hw/misc/pca9552.c +++ b/hw/misc/pca9552.c @@ -17,6 +17,7 @@ #include "hw/qdev-properties.h" #include "hw/misc/pca9552.h" #include "hw/misc/pca9552_regs.h" +#include "hw/irq.h" #include "migration/vmstate.h" #include "qapi/error.h" #include "qapi/visitor.h" @@ -111,9 +112,11 @@ static void pca955x_update_pin_input(PCA955xState *s) =20 switch (config) { case PCA9552_LED_ON: + qemu_set_irq(s->gpio[i], 1); s->regs[input_reg] |=3D 1 << input_shift; break; case PCA9552_LED_OFF: + qemu_set_irq(s->gpio[i], 0); s->regs[input_reg] &=3D ~(1 << input_shift); break; case PCA9552_LED_PWM0: @@ -374,11 +377,14 @@ static void pca955x_initfn(Object *obj) =20 static void pca955x_realize(DeviceState *dev, Error **errp) { + PCA955xClass *k =3D PCA955X_GET_CLASS(dev); PCA955xState *s =3D PCA955X(dev); =20 if (!s->description) { s->description =3D g_strdup("pca-unspecified"); } + + qdev_init_gpio_out(dev, s->gpio, k->pin_count); } =20 static Property pca955x_properties[] =3D { --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185552; cv=none; d=zohomail.com; s=zohoarc; b=R3zzFUS3RBczjbC4n/e15ysTAfelBVZy0D+S1DO3erKKxEzDzptZbmQXPGRPDWvEXPNOOoEMfCsPbf2gZDydiNi3CGesmhdPlVxlAVEM8UKYk7z70vw3zfEwamtuNJa7DfLvBCR0rcg0sw/lP95WrXjFnBbSyd737+B0ip7jjGs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185552; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0jclhN1iI8Ils0M7tH4L8prj0mKxUP8gosaZhHheF7I=; b=e/vVJ3cQ1MZzV93fjiFNUC9hLQsno80BRihPmATZteza11fqNlpiMb5XOWkBWEIsYYer047GHRI5zSF6Dqqx1NyeSGoLrKC04K9ixua5vGBZ+4a/H3m8rjoyVxP3XZ/8+SUfkQyJPrb64HFAoeXkupYO7vDz8Gu/g1GS7k459Ng= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159318555201276.01336209724673; Fri, 26 Jun 2020 08:32:32 -0700 (PDT) Received: from localhost ([::1]:34630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqL8-00081Q-Eo for importer@patchew.org; Fri, 26 Jun 2020 11:32:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35600) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq42-0002CQ-Cm for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:50 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:33991) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq3x-0006JC-99 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:50 -0400 Received: by mail-wm1-x32d.google.com with SMTP id u26so9095741wmn.1 for ; Fri, 26 Jun 2020 08:14:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0jclhN1iI8Ils0M7tH4L8prj0mKxUP8gosaZhHheF7I=; b=HASE1GBTZmsW0//eemhsZdvHpYvDq7eTQhv0Pxnxuz2yMkdcE7TajImcK5b5ng01ZY 858zW3VEdnaz/iWkxeRKTYN617GAYSeTfGbUPTYFpCOh7wwlnUPLJQTtdA4djQbj4zoY JvMbpELmCVw7N2jLYuY+RzJfZ394ig41hNSYLWexSu1lVtBg2BjYQ03vXXONGs6TAZCu qZ/57pvNSFy+AKMdi/im9DFMQrBc2gx2aLPHY4YYkqWfsziLTkedKAIba1icFRL4AxTH Ww/8cVNRPMBceS7nhhDAsRVsC8u1+35p6jBtExMtgyMZxUZvdNOTj51//AWvQKjyOKE4 z3jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0jclhN1iI8Ils0M7tH4L8prj0mKxUP8gosaZhHheF7I=; b=gP4s8PuQ2YEoc6A5ibUsBPoFtwEtKN4TJ6v3gIh3wp9oYBekDt6GVbVakhLbkQGHSv Vtpno3xtjcYZOD8v5w18u/QlkEHf5bN/fYvUtNwbkF7zt16xzZzajxesDg47C6LTsstT fRuFRR0Tz53ZEfyry/S7/0bM5vDwGG4YZvurJr1x+HMdIMfYhBZ0kYKSe1qOsqU1Zwfz tzq6ah98t7UIgzYty4AZetAWsd/ntSn+5HqKqtLXvkf1dSZV4krcpLovb8buMHCrwkwK FC2HTLuC/RR1ZIYmoKd8CO0XSrBRo5rGZ5wP8btItp0EA7k+s/vPCc+LkXXYoP1f1pT0 7XEQ== X-Gm-Message-State: AOAM530xNf+gyxk2RUSCLygzeNqE5mPlaAl0KC4FkUP4+Hv+dpPmWh6k B8OSk4A83ET/tQzDKolFRntrfHjJ5e/1Dw== X-Google-Smtp-Source: ABdhPJwT97GDmfQwclQl0bbdVr5si7nN4+0sRWTxSvxHzuQEEE0J7YWNIEQNhVMabh2l7Dmn9HIPbA== X-Received: by 2002:a7b:ca52:: with SMTP id m18mr3919302wml.92.1593184481073; Fri, 26 Jun 2020 08:14:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/57] target/arm: Add isar tests for mte Date: Fri, 26 Jun 2020 16:13:40 +0100 Message-Id: <20200626151424.30117-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cf66b8c7fb0..ff70115801f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3814,6 +3814,16 @@ static inline bool isar_feature_aa64_bti(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; } =20 +static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *i= d) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) !=3D 0; +} + +static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >=3D 2; +} + static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 4 && --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185001; cv=none; d=zohomail.com; s=zohoarc; b=ewRX28CwF3B4e47Unqyhs1XobqZK+C9JWO1F3vYwPoRe/Ik41YXqPkXak/oU168fGWH0me+pGfUsRS1itNFNa47Ld7Wn7o9l4OBxPiC3P/VOMT7TMxUtIu3lS6IJaxF+HhXfYqQDR35HWq9SEXFnUrGnK6lLfUQLw4KL8og6ReQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185001; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rjuUJVD20e+gziaQHiWZSwoTVScu50+CWJVxi25EUi0=; b=aKgGL0ql/2wAwpiquVbwA39sax0lnKqjtVTMjKXY4PgCpvpkx1Vwpbyvqt/5fwkWNW/y9zNTmWx08OUSy4gIo3w/SHRo0AaDyNjNtxQ2uFKq7brAkG+tAz5mdrlExLzoX3N8O6yDYw3lEkwiGjV9TeWO8zwFQwA+AFI8achIS6A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185001088133.92405982329524; Fri, 26 Jun 2020 08:23:21 -0700 (PDT) Received: from localhost ([::1]:49496 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqCF-0007fQ-Or for importer@patchew.org; Fri, 26 Jun 2020 11:23:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35574) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq41-00029R-6I for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:49 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:33414) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq3x-0006Jb-E7 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:48 -0400 Received: by mail-wm1-x344.google.com with SMTP id a6so9087934wmm.0 for ; Fri, 26 Jun 2020 08:14:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rjuUJVD20e+gziaQHiWZSwoTVScu50+CWJVxi25EUi0=; b=hxWb1ZbI7ZjxzlwUEX7AYsgh6PXtnVBPZa+B6C9LsN7/huzG2Gc5/cmHG+55HpHIwW /gctvslhWJmMukLwbTgA0zcXgRuYSk6HV+Ls7cvoskNh7HKAeXBSRbta3lwttzVeLG9l gnyWBEbUGNMsKBdjNbTvnbzQLw0ccDO/cVIVWflM5xVHbK9cjwCaFVj3i0KXRpgUsYT9 skxM1b/1hmlmagNNhHjae8RiiIf8TEKtb9Vl6fXdhc7BpvAuAMbvDzXLfFF4kMx/UsCF vLtRi3CkNQWfhdyFYqL2di9gmKw6a+GHO4qC0R7VzR/7p2zXXxRl0JZsMC9lJh6qlgsx DN7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rjuUJVD20e+gziaQHiWZSwoTVScu50+CWJVxi25EUi0=; b=CGF9VqnZHWxno71fIZ0beitCpZqTBtdGtfsmiKw7mnUrYwl6ojC9z1cBLWsplSnGy/ /lsCrkfOOjfTv7ARRE3NoBujAgWHZ4++9RAO9TsXV2W8y5Ab9lktxPQF4OthCaaK0j03 4QRYrqAP4dZZVpCu9WrKpbYrzwJHtpuMjASBp5jR69VI8no+BuEicZIV1du90iFzy/21 hIbuM+xdJcCAC9VCq/DAtKbrVydgkBiSlho0HJhsAFor8XhoEQ2MW/BRhflD7oLFnSf4 dE5GWMyZhI1nYGbLHINaBb4eBtdxiM7NINb+0/qhog6dt6Ni1UG3hqQ7ag1dE8YtVbg9 zSyQ== X-Gm-Message-State: AOAM530uEEGPITJuUSBfeoLI/WOcsPSTq6hZT1P8UJcZVoQrz5bwbteG PquRDMXQk8WzR4UYQno0W3v8dWPNWYPUnQ== X-Google-Smtp-Source: ABdhPJzaZ/1zxa6AwmD2hIDklCxxKpTIGVpqazaCIC4JEK4/CSFvK4ActxUvKXcFtlfUckoMc1Wk+w== X-Received: by 2002:a1c:6354:: with SMTP id x81mr3823816wmb.98.1593184482122; Fri, 26 Jun 2020 08:14:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/57] target/arm: Improve masking of SCR RES0 bits Date: Fri, 26 Jun 2020 16:13:41 +0100 Message-Id: <20200626151424.30117-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Protect reads of aa64 id registers with ARM_CP_STATE_AA64. Use this as a simpler test than arm_el_is_aa64, since EL3 cannot change mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 972a7667309..a29f0a28d84 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2011,9 +2011,16 @@ static void scr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) uint32_t valid_mask =3D 0x3fff; ARMCPU *cpu =3D env_archcpu(env); =20 - if (arm_el_is_aa64(env, 3)) { + if (ri->state =3D=3D ARM_CP_STATE_AA64) { value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. */ valid_mask &=3D ~SCR_NET; + + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |=3D SCR_TLOR; + } + if (cpu_isar_feature(aa64_pauth, cpu)) { + valid_mask |=3D SCR_API | SCR_APK; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); } @@ -2032,12 +2039,6 @@ static void scr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) valid_mask &=3D ~SCR_SMD; } } - if (cpu_isar_feature(aa64_lor, cpu)) { - valid_mask |=3D SCR_TLOR; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - valid_mask |=3D SCR_API | SCR_APK; - } =20 /* Clear all-context RES0 bits. */ value &=3D valid_mask; --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593184905; cv=none; d=zohomail.com; s=zohoarc; b=FJOq711sPC2iSxcEgJxRpy/J0CAhLwj6Rid7+KfgxVxujztZUx0taj460ZyLxkGrhmwWWsSstsdu8U60QoZGeOM+jBvGckcqG1oEcMExa/zwtwqkKxICRo3zsilnaZPRZf6yjA+zv4xcpa+YM9NlBOX4IJor5gB8ZzP3eaDwD1k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593184905; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OiVkZdXmMFp02tYSp5OVNi5864zwIsR2HUEVngWMuuQ=; b=Oz9tSH6VTN34R0wLqUdQyUvPu8QqEjV49FoBc475eh0+j65VGMJdmvyAAmdKJa/AM9vncvPUKv8cCIdJkqSG+bDhtMgAKvSYTI9qQr99ZpkP2reCBUtlXoXmP4+prFYAWSQInaCu/iPgC4mYOgomVGs6mJsQfIdlmsCPb9U/w/w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593184905632480.0533691473454; Fri, 26 Jun 2020 08:21:45 -0700 (PDT) Received: from localhost ([::1]:41672 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqAi-0004Ua-CO for importer@patchew.org; Fri, 26 Jun 2020 11:21:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq41-000298-1q for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:49 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:50978) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq3x-0006Jq-9c for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:48 -0400 Received: by mail-wm1-x341.google.com with SMTP id l17so9180574wmj.0 for ; Fri, 26 Jun 2020 08:14:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OiVkZdXmMFp02tYSp5OVNi5864zwIsR2HUEVngWMuuQ=; b=j8eXAvb5sSuAv0/OJvaqL2818q0DSyGaB/EjOLiSAvSZahnFjCa7BQSfioYUjAFnaB YfLxc9Jx1K4uLXWneasunP5PgdkFj2MufzSIIzp4ooyrG5sA0wTiz1K+N4RofsuwPd29 lmyvpm9PKaxla9v20ejK8YE0U5hbEku4w+bM73/dkRl+cAP3A2PpMmdLsSFwaQvkvxGD nTeXwMQMwzDnzuZm1tUEyJBMO1e4j/3iv8TJ0Hja/Hr467Mow/bdwdLJ9QS50ysCQPbs TlF7YigOGEa8/VuAsI6JujW+Mb5onrSIB/3gp3HkQ8C+ILj1VTJ/9v14bjK7lfNHB4W2 Z+4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OiVkZdXmMFp02tYSp5OVNi5864zwIsR2HUEVngWMuuQ=; b=eRDG8/8DmKx/vqJkNyYUgiingRNnVaKo4ONaJk7YPIts+850VWEaSZQZ0lWielUyYe 8odqa9ufNA2n7fcp0/VfNV7CQE8H2cqGOgcUwuJgM5+NNW429CIVuXPxYu0Rvzy9mB0C a8R0hmzk1oqwsim0pIJv2nCmlM8a58L/tecrkGwCi71HL5sYptxVMRE91zZpcsu2D23F Zi4wyGh5Wfq6A4BGKGYpJqzZ02ljN/AiPu0dzaVFBJqUIa0WtTsFucFh2n0o+TrbsMmd c3fFbrukDhXB3DmvwA+vNxgeNwl7LxQWIiqqGoMZk8CSGkT8MlbVUTXvLmaabYczzrwU tb8A== X-Gm-Message-State: AOAM5316xaYedoqksxHYfydbPEdbKWBNyQ3TV6UqqMZgHvaX6NN8sPXN GpDhHXvVxTV7Bv8oRoERb1ssMeH3VfrtMQ== X-Google-Smtp-Source: ABdhPJz1RGpx7xdbVYjD1UWsjr95CkTv1/FVN+8rx/wUQd8ZqPzutn+TtBvi25S0iRerQAsOk0pZCw== X-Received: by 2002:a1c:a949:: with SMTP id s70mr4314261wme.137.1593184483183; Fri, 26 Jun 2020 08:14:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/57] target/arm: Add support for MTE to SCTLR_ELx Date: Fri, 26 Jun 2020 16:13:42 +0100 Message-Id: <20200626151424.30117-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This does not attempt to rectify all of the res0 bits, but does clear the mte bits when not enabled. Since there is no high-part mapping of SCTLR, aa32 mode cannot write to these bits. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a29f0a28d84..8a0fb015819 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4698,6 +4698,22 @@ static void sctlr_write(CPUARMState *env, const ARMC= PRegInfo *ri, { ARMCPU *cpu =3D env_archcpu(env); =20 + if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { + /* M bit is RAZ/WI for PMSA with no MPU implemented */ + value &=3D ~SCTLR_M; + } + + /* ??? Lots of these bits are not implemented. */ + + if (ri->state =3D=3D ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, = cpu)) { + if (ri->opc1 =3D=3D 6) { /* SCTLR_EL3 */ + value &=3D ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); + } else { + value &=3D ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | + SCTLR_ATA0 | SCTLR_ATA); + } + } + if (raw_read(env, ri) =3D=3D value) { /* Skip the TLB flush if nothing actually changed; Linux likes * to do a lot of pointless SCTLR writes. @@ -4705,13 +4721,8 @@ static void sctlr_write(CPUARMState *env, const ARMC= PRegInfo *ri, return; } =20 - if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { - /* M bit is RAZ/WI for PMSA with no MPU implemented */ - value &=3D ~SCTLR_M; - } - raw_write(env, ri, value); - /* ??? Lots of these bits are not implemented. */ + /* This may enable/disable the MMU, so do a TLB flush. */ tlb_flush(CPU(cpu)); =20 --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593184791; cv=none; d=zohomail.com; s=zohoarc; b=fLCy94sBJQmab9oMNeAZbSzeMuIiwfXiE0/CHO1H9zYThOmD92vLSSVdqk5qt5NzL9KdKTburVL9LrX0kDyTk09VmxzWeOecA5jUoNJ/FzMDadPMarW0bchTBZTKphgGhbfX+NRJTdsCCHuEz/EoQiIR32SW/vj1zgWY4Ze6RdI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593184791; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9pMs3LEbOiq50D52Qgdo7AAYpmJBtOiQsJyttNTt1Gw=; b=Ck16XpSF0fijepO2fs/qJHGVGgEooIyhngDZeQLF/CNooLFYsvH+Vb7B6wn7xBbNhk2G8zfOyBWVaCG2N+RNfMKWYIvi2LjXqEpoGDsdvErQt957l1rKCY7KXfYXmWeUw7YIb5Rqe/h/gFueE6f9rIDnjAmERgMv+b57l5+m6Qk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159318479131134.92865003546967; Fri, 26 Jun 2020 08:19:51 -0700 (PDT) Received: from localhost ([::1]:34656 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joq8s-0001Vq-1j for importer@patchew.org; Fri, 26 Jun 2020 11:19:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35592) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq41-0002Au-T8 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:49 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:43778) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq3y-0006KP-3o for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:49 -0400 Received: by mail-wr1-x442.google.com with SMTP id j4so7404011wrp.10 for ; Fri, 26 Jun 2020 08:14:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9pMs3LEbOiq50D52Qgdo7AAYpmJBtOiQsJyttNTt1Gw=; b=nMaaip0NLvOoecvmqwY1FB62j5Q2DqpLUIUcrnibC9h2ZynG7JK1QfJBsc2HiLOJEB 4A2NOBDxA7HsZ2NO2RfoMMLjMU/rGlI/PRJRbiGS+VqCOzMDBQuK0W3xAzAjj0imrMz4 2b1ysRQnzDgAT3TZM9FfYK3a5Ti9VPRlMbp32d+HW36fDIG79V9rpqSdnEwkQztTLDty Z2FETzqFOoIyCh1LaR5Cnbim0c2oiCOSf2Vf4Ck1v3n97GqpSExqsNw8gSD1VLvt+nqH 606qlBMac8FZOkCe4U5wtTtFS8LGZFuBXirDvLbQi1l3O8TG1lS6QImUXDJuAwbfzVKh jwlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9pMs3LEbOiq50D52Qgdo7AAYpmJBtOiQsJyttNTt1Gw=; b=NpvVfxMmXtSXswX8qCsHIAiUyZNg9M8GU5OA+9XfxgmUmzDbJp84/AhR6BZEkhq4gW w81eLzG2EuyoUkfrYtZ5LZVn/pn1if8QOvcWnOwOdidL+/iOyNVlMkPifAyRAclb8LWr z02Be7f25P7/f/uE5Q19sbBELgxAKFlqknmDaZ6BejUSqmBb0FeNnyBtwOQWmUQkf0zw mKNd8XARfXYAJnXSi1ppOa6a0jem328GB2Q8qvaQ2DDT/V3F6vFFBJ6pn8j/CISl2g1u AK9GDWQQ7zogIq8Vba1X0+dwleMwfTu1nj/ngLNxnbBRT/paXocPMzSzdWlCIdqHeV9S zvlw== X-Gm-Message-State: AOAM531ZaxT6eDYeHjF7lvSf9aDoCwNuAyp/07Hpl5UwdB6xOSfa6U5j gzSq2+mRtc8p35D45s8hb+BSR/pmL2PF5A== X-Google-Smtp-Source: ABdhPJxMNd8uNVQ7P5xw0ouvPSOT7C3sYY6kPzEX6rP3EzyyBlER2nPlCEBgv9w+O+UqFk0bZb+7Pg== X-Received: by 2002:a5d:6a04:: with SMTP id m4mr4216479wru.418.1593184484148; Fri, 26 Jun 2020 08:14:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/57] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3 Date: Fri, 26 Jun 2020 16:13:43 +0100 Message-Id: <20200626151424.30117-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8a0fb015819..d6c326b58e8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2021,6 +2021,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |=3D SCR_API | SCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |=3D SCR_ATA; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); } @@ -5248,17 +5251,22 @@ static void do_hcr_write(CPUARMState *env, uint64_t= value, uint64_t valid_mask) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |=3D HCR_API | HCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |=3D HCR_ATA | HCR_DCT | HCR_TID5; + } } =20 /* Clear RES0 bits. */ value &=3D valid_mask; =20 - /* These bits change the MMU setup: + /* + * These bits change the MMU setup: * HCR_VM enables stage 2 translation * HCR_PTW forbids certain page-table setups - * HCR_DC Disables stage1 and enables stage2 translation + * HCR_DC disables stage1 and enables stage2 translation + * HCR_DCT enables tagging on (disabled) stage1 translation */ - if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { + if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT= )) { tlb_flush(CPU(cpu)); } env->cp15.hcr_el2 =3D value; --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593184908; cv=none; d=zohomail.com; s=zohoarc; b=md2Q3yGac/PAifc60WbIIKqKiFRP3fkMhdTj4sXURq+UK+ztPScG2u3Vfa2eHuS8ZZKe5wJBgTumYesFpnbrZ2RVOuYvGt+jmCbBCzB4WTAzScQxJcNRu5Fd8/Rc0s1kLXWV81xL5RKOGSiWEjfkkhpDWyE1LudIHtCklCZC39I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593184908; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aWyt2cysYoyz/Pja0/FYad6jYHqTEkVsxAonTLdhkWs=; b=D16X3DWFfMqOeb7MVXkVYnpX9FBqp3+Gb6g47Q5eqi1NWMI4rXblxRas19qUepk/Qtdg7gs5GZLSSfIIuEXSAJWU9VVxaN7yByMgiUCgxD/Hi6ieEXYYANvGXxP+pC19GZOYMh0IUVZXYqnAjLpGcJXb/rrYcej4tfhSINKlD+g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593184908273833.6942863933098; Fri, 26 Jun 2020 08:21:48 -0700 (PDT) Received: from localhost ([::1]:41932 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqAk-0004ar-WB for importer@patchew.org; Fri, 26 Jun 2020 11:21:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35638) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq43-0002Fp-J3 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:51 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:34836) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq3z-0006LE-2V for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:51 -0400 Received: by mail-wr1-x429.google.com with SMTP id g18so9901223wrm.2 for ; Fri, 26 Jun 2020 08:14:46 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aWyt2cysYoyz/Pja0/FYad6jYHqTEkVsxAonTLdhkWs=; b=O7kd4ngpgu/XuXsazTZP+VFT3/vqRpsgnmP/p7RwNPzKgmiwc2nxKIns7kFWvYJbOa b6FeksKAPlOugRq4Fciwy4bkwCyRFafxdMam3H97c5L0z8g8X/CgX/xH/If8gABqC+2X NMJO71IT7070+Z4NZai3cGcOYVlbcICFgIcizYwKT96gKUsNjGmmmp6+WHiDnnIRKgpg 2TriMCjVeaxhELVd1J3ODkiz7f+1M2eLnaoHKILcS+LBOt0Thcgo/gQCxwcz8UVh1z3L bJGraVHVp2bP03EtoDmsVhhb+FZ//FGFbDb2+zHtq0L9+SP7xthjY+UBg0C1ivy89vM6 zmuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aWyt2cysYoyz/Pja0/FYad6jYHqTEkVsxAonTLdhkWs=; b=msCcRSekkA/xiZjGX/XIeHCaWgYUpIzxkY7wvijX8TZjuYCqj+0iuLh3GckNV3d/3v M6vqrqM16WYBc6dCISZ96Rxze7c/KuOuLi3l1EXoIy51v2m9Q3FZ+quaryi67zzmm+Gl N902TtHTgUBTg9RTjnN9/Dgr0TYkbzwdHprxkIJghovRx25hEZLUJENZnO6lziRVZo5x snPzLBdgtKA8Bj0Z9u3df34tVeNRLzyRcy9WnD0FFsnY+e3QP1nKJlZbsVLBEzfGT50Q qfTH1LzprWA459/ar5ryACrPT042LG/IeDl1JrVC74zeGmXWddIQ9mTLN+HW11SVlWA2 xaHA== X-Gm-Message-State: AOAM532fmTpdyy0pLmhx6ps0BvoImlcpMtasc5NY1uRkQVjVDh5zSM7t 213EtwEffbRRFaBBRvKPTMDJbtlOSQhYYg== X-Google-Smtp-Source: ABdhPJwEZ48teg3dScasUTwsjvRay9ErvU9QmWvU0gg4Df9RMpzpOqynOTJsLrBbqoSvjZgJLy5uNg== X-Received: by 2002:adf:c404:: with SMTP id v4mr4127858wrf.85.1593184485264; Fri, 26 Jun 2020 08:14:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/57] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT Date: Fri, 26 Jun 2020 16:13:44 +0100 Message-Id: <20200626151424.30117-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Emphasize that the is_jmp option exits to the main loop. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.h | 14 ++++++++------ target/arm/translate-a64.c | 8 ++++---- target/arm/translate-vfp.inc.c | 4 ++-- target/arm/translate.c | 12 ++++++------ 4 files changed, 20 insertions(+), 18 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 19650a9e2d7..d5edef2943f 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -148,7 +148,8 @@ static inline void disas_set_insn_syndrome(DisasContext= *s, uint32_t syn) =20 /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically= */ -#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamical= ly */ +/* CPU state was modified dynamically; exit to main loop for interrupts. */ +#define DISAS_UPDATE_EXIT DISAS_TARGET_1 /* These instructions trap after executing, so the A32/T32 decoder must * defer them until after the conditional execution state has been updated. * WFI also needs special handling when single-stepping. @@ -164,11 +165,12 @@ static inline void disas_set_insn_syndrome(DisasConte= xt *s, uint32_t syn) * custom end-of-TB code) */ #define DISAS_BX_EXCRET DISAS_TARGET_8 -/* For instructions which want an immediate exit to the main loop, - * as opposed to attempting to use lookup_and_goto_ptr. Unlike - * DISAS_UPDATE this doesn't write the PC on exiting the translation - * loop so you need to ensure something (gen_a64_set_pc_im or runtime - * helper) has done so before we reach return from cpu_tb_exec. +/* + * For instructions which want an immediate exit to the main loop, as oppo= sed + * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, th= is + * doesn't write the PC on exiting the translation loop so you need to ens= ure + * something (gen_a64_set_pc_im or runtime helper) has done so before we r= each + * return from cpu_tb_exec. */ #define DISAS_EXIT DISAS_TARGET_9 =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4cef862c415..e4795ae100c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1616,7 +1616,7 @@ static void handle_msr_i(DisasContext *s, uint32_t in= sn, gen_helper_msr_i_daifclear(cpu_env, t1); tcg_temp_free_i32(t1); /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ - s->base.is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE_EXIT; break; =20 default: @@ -1795,7 +1795,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, =20 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { /* I/O operations must end the TB here (whether read or write) */ - s->base.is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE_EXIT; } if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* @@ -1810,7 +1810,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ - s->base.is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE_EXIT; } } =20 @@ -14292,7 +14292,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) gen_goto_tb(dc, 1, dc->base.pc_next); break; default: - case DISAS_UPDATE: + case DISAS_UPDATE_EXIT: gen_a64_set_pc_im(dc->base.pc_next); /* fall through */ case DISAS_EXIT: diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index bf31b186578..afa8a5f8885 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -123,7 +123,7 @@ static bool full_vfp_access_check(DisasContext *s, bool= ignore_vfp_enabled) * this to be the last insn in the TB). */ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - s->base.is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE_EXIT; gen_io_start(); } gen_helper_v7m_preserve_fp_state(cpu_env); @@ -2860,6 +2860,6 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VL= LDM_VLSTM *a) tcg_temp_free_i32(fptr); =20 /* End the TB, because we have updated FP control bits */ - s->base.is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE_EXIT; return true; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 795964da1f1..146ff5ddc24 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2775,7 +2775,7 @@ static void gen_msr_banked(DisasContext *s, int r, in= t sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); tcg_temp_free_i32(tcg_reg); - s->base.is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE_EXIT; } =20 static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) @@ -2797,7 +2797,7 @@ static void gen_mrs_banked(DisasContext *s, int r, in= t sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); store_reg(s, rn, tcg_reg); - s->base.is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE_EXIT; } =20 /* Store value to PC as for an exception return (ie don't @@ -5114,7 +5114,7 @@ static void gen_srs(DisasContext *s, tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); - s->base.is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE_EXIT; } =20 /* Generate a label used for skipping this instruction */ @@ -8160,7 +8160,7 @@ static bool trans_SETEND(DisasContext *s, arg_SETEND = *a) } if (a->E !=3D (s->be_data =3D=3D MO_BE)) { gen_helper_setend(cpu_env); - s->base.is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE_EXIT; } return true; } @@ -8873,7 +8873,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) break; case DISAS_NEXT: case DISAS_TOO_MANY: - case DISAS_UPDATE: + case DISAS_UPDATE_EXIT: gen_set_pc_im(dc, dc->base.pc_next); /* fall through */ default: @@ -8900,7 +8900,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) case DISAS_JUMP: gen_goto_ptr(); break; - case DISAS_UPDATE: + case DISAS_UPDATE_EXIT: gen_set_pc_im(dc, dc->base.pc_next); /* fall through */ default: --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185013; cv=none; d=zohomail.com; s=zohoarc; b=g2BuSHRfI30RpscEzXYxndcl42XxR2B/x5sdrEnT5nWLSFb3sAZFweraPpMtHsjrlzFqfgwA9fA71fxKc5WrUZgibVhyn4gwfGiHWdzuVivteIPUfGhoCQookQpIvK3c2D6lnq3PdvJ6we6fjxVuhF1fc2m5ZpDgAUbhdWfT6+A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185013; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lxJLokSSwLrc0Y70TKAH3hjExPU/swMhK4k3zquMN7k=; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Add an option that writes back the PC, like DISAS_UPDATE_EXIT, but does not exit back to the main loop. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.h | 2 ++ target/arm/translate-a64.c | 3 +++ target/arm/translate.c | 4 ++++ 3 files changed, 9 insertions(+) diff --git a/target/arm/translate.h b/target/arm/translate.h index d5edef2943f..6dfe24cedc0 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -173,6 +173,8 @@ static inline void disas_set_insn_syndrome(DisasContext= *s, uint32_t syn) * return from cpu_tb_exec. */ #define DISAS_EXIT DISAS_TARGET_9 +/* CPU state was modified dynamically; no need to exit, but do not chain. = */ +#define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10 =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e4795ae100c..027be7d8c29 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14298,6 +14298,9 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) case DISAS_EXIT: tcg_gen_exit_tb(NULL, 0); break; + case DISAS_UPDATE_NOCHAIN: + gen_a64_set_pc_im(dc->base.pc_next); + /* fall through */ case DISAS_JUMP: tcg_gen_lookup_and_goto_ptr(); break; diff --git a/target/arm/translate.c b/target/arm/translate.c index 146ff5ddc24..c39a929b938 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8874,6 +8874,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) case DISAS_NEXT: case DISAS_TOO_MANY: case DISAS_UPDATE_EXIT: + case DISAS_UPDATE_NOCHAIN: gen_set_pc_im(dc, dc->base.pc_next); /* fall through */ default: @@ -8897,6 +8898,9 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->base.pc_next); break; + case DISAS_UPDATE_NOCHAIN: + gen_set_pc_im(dc, dc->base.pc_next); + /* fall through */ case DISAS_JUMP: gen_goto_ptr(); break; --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185111; cv=none; d=zohomail.com; s=zohoarc; b=KS02k0esoWUw5OwWp1bYj/UefRiwg6Oerjnmqxpr0HoAC/LXIS8ZWyrbxlKYtRJ8Lk7V5dj0KlGlHotDx5P3/eRHvhihzz+JT3tBJZF2uWHZNQvxfeBNfV8aRSX0He2gy4b+HPNZC2Zd9zgsnL2Ljsx1OkvWDW+17XHsCAdM86U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185111; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3JhZ3wDYLmG32gJ9N1aTvgQgu0hTvog32hizBZWQ+I4=; b=HCTQLIsvy1pFAy+aBDdm+eVxwCOOYNDc/E+BgHPN07YL+hH250M8RMEwPtedd9SGdQuIhFVMu3S7kFIBWGBdAHyY5wRfDuSV9fphYv+sFOkYU1jlEV8qQud8UTVx3RtJPGgPHG98LE2oFPY1G7gXVPVBPglZSbE3chcXrjIBHCY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185111202497.735984254605; Fri, 26 Jun 2020 08:25:11 -0700 (PDT) Received: from localhost ([::1]:58478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqE1-0002rT-Pe for importer@patchew.org; Fri, 26 Jun 2020 11:25:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq44-0002IY-GC for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:52 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:54959) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq41-0006N6-KH for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:52 -0400 Received: by mail-wm1-x342.google.com with SMTP id o8so9155768wmh.4 for ; Fri, 26 Jun 2020 08:14:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=3JhZ3wDYLmG32gJ9N1aTvgQgu0hTvog32hizBZWQ+I4=; b=lk7yOhD1x7iMf50nPEYIQ5fkX9qzBLdPGrdHYzFL2tIXgHua3CXBAmxIF+4IFzYnMX vA8GcAqQVy8h/Aarw26/bDljpolz1IxsOEleECgq7CJUzTGftXUdRigxjxAn+tj8ICrN pHHl/rtVLePWuoIeXqQf6sVGFfUWe1meKXykV3pdpU2ikQIEWsEQW/+2MDbdKJzsWiEG 6sfPXKFJNQDNffifLJ8yMtu52B1kds5TV0VCiKN7vLZPCNYfS1MSCvUQweToYamxMX9Z 9pNecootrdBkbh4bASCq3GZTv+XGcIQDOLDPe0aclymxOZTdP/nsnAyRE2Sd1u3aXvIq tb5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3JhZ3wDYLmG32gJ9N1aTvgQgu0hTvog32hizBZWQ+I4=; b=ny/GzjfePJeWJsK1XuZ/AB84F7p8excZmahN5R+EhnFsMfF9o+BNX6tMaKRxRzUlhz z9q6Bh4Q08jP7Bl+3UCmU+xrtyznczunYVin9gfcTaDJO83hArtCINRFet9YxKOM4j7H 45Dv99wCiJXrFgTAF6TIuWBR0pnk5vyNDTLBe7IVhBFx+m6DGuib0iJvpo9oez5rC8P7 bxzqAtLcDtDSVvexci6SayT8Z8vZ7dQwoB5pUzhfUCt3+zKNwcw9wHHO2hV7etG8q2E9 ypmexq6H2UaK+ZwjB0i2YuvttUT4T+vdAZI7x45MJhbO7AabtSp0ewi74o4Mo4Av6AqA ZodA== X-Gm-Message-State: AOAM532SbH6GSKW9wE2JBA1vx10oiBa81CxpuNTuFl+t6Sv7begYQKdV 53Ej/YrwYYjpyMishobYBLQUTZY+ti1VyA== X-Google-Smtp-Source: ABdhPJygOJ856Fk1SJi2LlmchHz+HiUalg9XUJqVpmTOGK8fh6ObHUSls0IJNnTIbyr1O3L7xDjGXA== X-Received: by 2002:a05:600c:2202:: with SMTP id z2mr4155883wml.13.1593184487789; Fri, 26 Jun 2020 08:14:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/57] target/arm: Add MTE system registers Date: Fri, 26 Jun 2020 16:13:46 +0100 Message-Id: <20200626151424.30117-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 ++ target/arm/internals.h | 9 ++++ target/arm/helper.c | 94 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 21 +++++++++ 4 files changed, 128 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ff70115801f..0a98b6a06d6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -502,6 +502,9 @@ typedef struct CPUARMState { uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register = */ + uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ + uint64_t gcr_el1; + uint64_t rgsr_el1; } cp15; =20 struct { @@ -1282,6 +1285,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) #define PSTATE_UAO (1U << 23) +#define PSTATE_TCO (1U << 25) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4bdbc3a8ace..56b46726857 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1159,6 +1159,9 @@ static inline uint32_t aarch64_pstate_valid_mask(cons= t ARMISARegisters *id) if (isar_feature_aa64_uao(id)) { valid |=3D PSTATE_UAO; } + if (isar_feature_aa64_mte(id)) { + valid |=3D PSTATE_TCO; + } =20 return valid; } @@ -1234,4 +1237,10 @@ void arm_log_exception(int idx); =20 #endif /* !CONFIG_USER_ONLY */ =20 +/* + * The log2 of the words in the tag block, for GMID_EL1.BS. + * The is the maximum, 256 bytes, which manipulates 64-bits of tags. + */ +#define GMID_EL1_BS 6 + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index d6c326b58e8..b4842ea23eb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5881,6 +5881,9 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, =20 + { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), + "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ }; @@ -6855,6 +6858,86 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { }; #endif /*CONFIG_USER_ONLY*/ =20 +static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + +static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && + arm_feature(env, ARM_FEATURE_EL2) && + !(arm_hcr_el2_eff(env) & HCR_ATA)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && + arm_feature(env, ARM_FEATURE_EL3) && + !(env->cp15.scr_el3 & SCR_ATA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_TCO; +} + +static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= al) +{ + env->pstate =3D (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); +} + +static const ARMCPRegInfo mte_reginfo[] =3D { + { .name =3D "TFSRE0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 6, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_mte, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[0]) }, + { .name =3D "TFSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_mte, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[1]) }, + { .name =3D "TFSR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D access_mte, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[2]) }, + { .name =3D "TFSR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[3]) }, + { .name =3D "RGSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 5, + .access =3D PL1_RW, .accessfn =3D access_mte, + .fieldoffset =3D offsetof(CPUARMState, cp15.rgsr_el1) }, + { .name =3D "GCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 6, + .access =3D PL1_RW, .accessfn =3D access_mte, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcr_el1) }, + { .name =3D "GMID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 4, + .access =3D PL1_R, .accessfn =3D access_aa64_tid5, + .type =3D ARM_CP_CONST, .resetvalue =3D GMID_EL1_BS }, + { .name =3D "TCO", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, + .type =3D ARM_CP_NO_RAW, + .access =3D PL0_RW, .readfn =3D tco_read, .writefn =3D tco_write }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo mte_tco_ro_reginfo[] =3D { + { .name =3D "TCO", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, + .type =3D ARM_CP_CONST, .access =3D PL0_RW, }, + REGINFO_SENTINEL +}; #endif =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -7980,6 +8063,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } #endif /*CONFIG_USER_ONLY*/ + + /* + * If full MTE is enabled, add all of the system registers. + * If only "instructions available at EL0" are enabled, + * then define only a RAZ/WI version of PSTATE.TCO. + */ + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, mte_reginfo); + } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { + define_arm_cp_regs(cpu, mte_tco_ro_reginfo); + } #endif =20 if (cpu_isar_feature(any_predinv, cpu)) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 027be7d8c29..d4793dd8fea 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1619,6 +1619,27 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_UPDATE_EXIT; break; =20 + case 0x1c: /* TCO */ + if (dc_isar_feature(aa64_mte, s)) { + /* Full MTE is enabled -- set the TCO bit as directed. */ + if (crm & 1) { + set_pstate_bits(PSTATE_TCO); + } else { + clear_pstate_bits(PSTATE_TCO); + } + t1 =3D tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, t1); + tcg_temp_free_i32(t1); + /* Many factors, including TCO, go into MTE_ACTIVE. */ + s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; + } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { + /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. = */ + s->base.is_jmp =3D DISAS_NEXT; + } else { + goto do_unallocated; + } + break; + default: do_unallocated: unallocated_encoding(s); --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Cache the composite ATA setting. Cache when MTE is fully enabled, i.e. access to tags are enabled and tag checks affect the PE. Do this for both the normal context and the UNPRIV context. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 12 ++++++++---- target/arm/internals.h | 18 +++++++++++++++++ target/arm/translate.h | 5 +++++ target/arm/helper.c | 40 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 4 ++++ 5 files changed, 75 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0a98b6a06d6..cb4f6ba69f2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3187,10 +3187,10 @@ typedef ARMCPU ArchCPU; * | | | TBFLAG_A32 | | * | | +-----+----------+ TBFLAG_AM32 | * | TBFLAG_ANY | |TBFLAG_M32| | - * | | +-+----------+--------------| - * | | | TBFLAG_A64 | - * +--------------+---------+---------------------------+ - * 31 20 15 0 + * | +-----------+----------+--------------| + * | | TBFLAG_A64 | + * +--------------+-------------------------------------+ + * 31 20 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ @@ -3257,6 +3257,10 @@ FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) FIELD(TBFLAG_A64, UNPRIV, 14, 1) +FIELD(TBFLAG_A64, ATA, 15, 1) +FIELD(TBFLAG_A64, TCMA, 16, 2) +FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) +FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) =20 /** * cpu_mmu_index: diff --git a/target/arm/internals.h b/target/arm/internals.h index 56b46726857..53e249687ba 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1198,6 +1198,24 @@ static inline int exception_target_el(CPUARMState *e= nv) return target_el; } =20 +/* Determine if allocation tags are available. */ +static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, + uint64_t sctlr) +{ + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ATA)) { + return false; + } + if (el < 2 + && arm_feature(env, ARM_FEATURE_EL2) + && !(arm_hcr_el2_eff(env) & HCR_ATA)) { + return false; + } + sctlr &=3D (el =3D=3D 0 ? SCTLR_ATA0 : SCTLR_ATA); + return sctlr !=3D 0; +} + #ifndef CONFIG_USER_ONLY =20 /* Security attributes for an address, as returned by v8m_security_lookup.= */ diff --git a/target/arm/translate.h b/target/arm/translate.h index 6dfe24cedc0..98bcc37c479 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -30,6 +30,7 @@ typedef struct DisasContext { ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ uint8_t tbii; /* TBI1|TBI0 for insns */ uint8_t tbid; /* TBI1|TBI0 for data */ + uint8_t tcma; /* TCMA1|TCMA0 for MTE */ bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ @@ -77,6 +78,10 @@ typedef struct DisasContext { bool unpriv; /* True if v8.3-PAuth is active. */ bool pauth_active; + /* True if v8.5-MTE access to tags is enabled. */ + bool ata; + /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */ + bool mte_active[2]; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ bool bt; /* True if any CP15 access is trapped by HSTR_EL2 */ diff --git a/target/arm/helper.c b/target/arm/helper.c index b4842ea23eb..2c6ec244af8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10655,6 +10655,16 @@ static int aa64_va_parameter_tbid(uint64_t tcr, AR= MMMUIdx mmu_idx) } } =20 +static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) +{ + if (regime_has_2_ranges(mmu_idx)) { + return extract64(tcr, 57, 2); + } else { + /* Replicate the single TCMA bit so we always have 2 bits. */ + return extract32(tcr, 30, 1) * 3; + } +} + ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { @@ -12679,6 +12689,36 @@ static uint32_t rebuild_hflags_a64(CPUARMState *en= v, int el, int fp_el, } } =20 + if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { + /* + * Set MTE_ACTIVE if any access may be Checked, and leave clear + * if all accesses must be Unchecked: + * 1) If no TBI, then there are no tags in the address to check, + * 2) If Tag Check Override, then all accesses are Unchecked, + * 3) If Tag Check Fail =3D=3D 0, then Checked access have no effe= ct, + * 4) If no Allocation Tag Access, then all accesses are Unchecked. + */ + if (allocation_tag_access_enabled(env, el, sctlr)) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, ATA, 1); + if (tbid + && !(env->pstate & PSTATE_TCO) + && (sctlr & (el =3D=3D 0 ? SCTLR_TCF0 : SCTLR_TCF))) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1); + } + } + /* And again for unprivileged accesses, if required. */ + if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV) + && tbid + && !(env->pstate & PSTATE_TCO) + && (sctlr & SCTLR_TCF0) + && allocation_tag_access_enabled(env, 0, sctlr)) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1); + } + /* Cache TCMA as well as TBI. */ + flags =3D FIELD_DP32(flags, TBFLAG_A64, TCMA, + aa64_va_parameter_tcma(tcr, mmu_idx)); + } + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d4793dd8fea..55f49585be4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14171,6 +14171,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->mmu_idx =3D core_to_aa64_mmu_idx(core_mmu_idx); dc->tbii =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBII); dc->tbid =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBID); + dc->tcma =3D FIELD_EX32(tb_flags, TBFLAG_A64, TCMA); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); @@ -14182,6 +14183,9 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->bt =3D FIELD_EX32(tb_flags, TBFLAG_A64, BT); dc->btype =3D FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); dc->unpriv =3D FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV); + dc->ata =3D FIELD_EX32(tb_flags, TBFLAG_A64, ATA); + dc->mte_active[0] =3D FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); + dc->mte_active[1] =3D FIELD_EX32(tb_flags, TBFLAG_A64, MTE0_ACTIVE); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185209; cv=none; d=zohomail.com; s=zohoarc; b=e+MQmpf1xstj9Ouf7+5YQ/aPNiptQyJauWd7rCSNJVdnTFo38I4XzpOwrikn4RWbGN4LMS6M+6x/wF807r/gyBM8EaPCc1ie9pPdMdjJuBnkSlKiPXB7OZq+nSqdpdJPpknOPgpn+2y+DVjCER/S7s7WXQ9eseRHKoqnNNWuw5w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185209; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/G8k8+jbJUrLWrICrwU7nxlVad0l1SACguDlrS0IJC8=; b=EZ8P4O9CMZDw67H3Hvg1aGrdOLw3EbYE2lIIphjKu+/is05HfegyvylzU0bSdl5v5uYSEJer9uUU+FBa1XGtxoxTtL4lh3VgHq65GLL8qXDCpgfGFHzoE1hEOnEht+QOhvUpfHXEaYbhcgJnfIrIIH1k8mAeNCBF7dteKAp2k0Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185209768312.30739750492296; Fri, 26 Jun 2020 08:26:49 -0700 (PDT) Received: from localhost ([::1]:38774 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqFc-0006Ns-Fj for importer@patchew.org; Fri, 26 Jun 2020 11:26:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35724) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq46-0002MR-2P for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:54 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:35857) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq43-0006OW-Rl for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:53 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 17so9710434wmo.1 for ; Fri, 26 Jun 2020 08:14:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 5 +++ target/arm/mte_helper.c | 72 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 18 ++++++++++ target/arm/Makefile.objs | 1 + 5 files changed, 98 insertions(+) create mode 100644 target/arm/mte_helper.c diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 3df7c185aa1..587ccbe42ff 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -103,3 +103,5 @@ DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64= , i64) DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) + +DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) diff --git a/target/arm/internals.h b/target/arm/internals.h index 53e249687ba..ae611a6ff5d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1261,4 +1261,9 @@ void arm_log_exception(int idx); */ #define GMID_EL1_BS 6 =20 +static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) +{ + return deposit64(ptr, 56, 4, rtag); +} + #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c new file mode 100644 index 00000000000..539a04de84b --- /dev/null +++ b/target/arm/mte_helper.c @@ -0,0 +1,72 @@ +/* + * ARM v8.5-MemTag Operations + * + * Copyright (c) 2020 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" + + +static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) +{ + if (exclude =3D=3D 0xffff) { + return 0; + } + if (offset =3D=3D 0) { + while (exclude & (1 << tag)) { + tag =3D (tag + 1) & 15; + } + } else { + do { + do { + tag =3D (tag + 1) & 15; + } while (exclude & (1 << tag)); + } while (--offset > 0); + } + return tag; +} + +uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) +{ + int rtag; + + /* + * Our IMPDEF choice for GCR_EL1.RRND=3D=3D1 is to behave as if + * GCR_EL1.RRND=3D=3D0, always producing deterministic results. + */ + uint16_t exclude =3D extract32(rm | env->cp15.gcr_el1, 0, 16); + int start =3D extract32(env->cp15.rgsr_el1, 0, 4); + int seed =3D extract32(env->cp15.rgsr_el1, 8, 16); + int offset, i; + + /* RandomTag */ + for (i =3D offset =3D 0; i < 4; ++i) { + /* NextRandomTagBit */ + int top =3D (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^ + extract32(seed, 2, 1) ^ extract32(seed, 0, 1)); + seed =3D (top << 15) | (seed >> 1); + offset |=3D top << i; + } + rtag =3D choose_nonexcluded_tag(start, offset, exclude); + env->cp15.rgsr_el1 =3D rtag | (seed << 8); + + return address_with_allocation_tag(rn, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 55f49585be4..30683061f94 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -226,6 +226,12 @@ static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i= 64 addr) return clean; } =20 +/* Insert a zero tag into src, with the result at dst. */ +static void gen_address_with_allocation_tag0(TCGv_i64 dst, TCGv_i64 src) +{ + tcg_gen_andi_i64(dst, src, ~MAKE_64BIT_MASK(56, 4)); +} + typedef struct DisasCompare64 { TCGCond cond; TCGv_i64 value; @@ -5284,6 +5290,18 @@ static void disas_data_proc_2src(DisasContext *s, ui= nt32_t insn) case 3: /* SDIV */ handle_div(s, true, sf, rm, rn, rd); break; + case 4: /* IRG */ + if (sf =3D=3D 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + if (s->ata) { + gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, + cpu_reg_sp(s, rn), cpu_reg(s, rm)); + } else { + gen_address_with_allocation_tag0(cpu_reg_sp(s, rd), + cpu_reg_sp(s, rn)); + } + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 83febd232c8..fa39fd7c831 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -86,3 +86,4 @@ obj-$(CONFIG_SOFTMMU) +=3D psci.o obj-$(TARGET_AARCH64) +=3D translate-a64.o helper-a64.o obj-$(TARGET_AARCH64) +=3D translate-sve.o sve_helper.o obj-$(TARGET_AARCH64) +=3D pauth_helper.o +obj-$(TARGET_AARCH64) +=3D mte_helper.o --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson The current Arm ARM has adjusted the official decode of "Add/subtract (immediate)" so that the shift field is only bit 22, and bit 23 is part of the op1 field of the parent category "Data processing - immediate". Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-11-richard.henderson@linaro.org Suggested-by: Peter Maydell Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 30683061f94..03aa0925983 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3754,22 +3754,22 @@ static void disas_pc_rel_adr(DisasContext *s, uint3= 2_t insn) /* * Add/subtract (immediate) * - * 31 30 29 28 24 23 22 21 10 9 5 4 0 - * +--+--+--+-----------+-----+-------------+-----+-----+ - * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd | - * +--+--+--+-----------+-----+-------------+-----+-----+ + * 31 30 29 28 23 22 21 10 9 5 4 0 + * +--+--+--+-------------+--+-------------+-----+-----+ + * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd | + * +--+--+--+-------------+--+-------------+-----+-----+ * * sf: 0 -> 32bit, 1 -> 64bit * op: 0 -> add , 1 -> sub * S: 1 -> set flags - * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 + * sh: 1 -> LSL imm by 12 */ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) { int rd =3D extract32(insn, 0, 5); int rn =3D extract32(insn, 5, 5); uint64_t imm =3D extract32(insn, 10, 12); - int shift =3D extract32(insn, 22, 2); + bool shift =3D extract32(insn, 22, 1); bool setflags =3D extract32(insn, 29, 1); bool sub_op =3D extract32(insn, 30, 1); bool is_64bit =3D extract32(insn, 31, 1); @@ -3778,15 +3778,8 @@ static void disas_add_sub_imm(DisasContext *s, uint3= 2_t insn) TCGv_i64 tcg_rd =3D setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); TCGv_i64 tcg_result; =20 - switch (shift) { - case 0x0: - break; - case 0x1: + if (shift) { imm <<=3D 12; - break; - default: - unallocated_encoding(s); - return; } =20 tcg_result =3D tcg_temp_new_i64(); @@ -4174,7 +4167,7 @@ static void disas_data_proc_imm(DisasContext *s, uint= 32_t insn) case 0x20: case 0x21: /* PC-rel. addressing */ disas_pc_rel_adr(s, insn); break; - case 0x22: case 0x23: /* Add/subtract (immediate) */ + case 0x22: /* Add/subtract (immediate) */ disas_add_sub_imm(s, insn); break; case 0x24: /* Logical (immediate) */ --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185039; cv=none; d=zohomail.com; s=zohoarc; b=NO3+t8cVkqriEOk33EGioULjiESpznWJxQJ0Hh3p7SVIPz1okaz7J0zq7wDKvvzKxujbrjHNQnI9+LdVg9d8yGsSKPuzR1kOycOGLJqADI7zVuLsl0Ozj3afcqjiCqKG7vaFlTFl3K3qxAkbNTxdyZZVBHrDdHLDaRuGTDrnc9E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185039; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8VSF8mtn2rKIPWEKD7pM39hWrvESRKdjWGtuiRVbIO0=; b=KuCCLO87Bz12jXmuehk07nSx38J4wzgD0MVSLC9BXFce82xGvWmQhjXC1av3C821Sg5fFuoiy1Er5OBKzc/qKgc44/cWNFVPsfupuqw04a/J7TnKH5WLQ8iumHCORqTnzsLY5kaRUxbYD5tkz/BAkDLWAXiDVWFQ6H85RFbwCls= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185039698266.6712830463458; Fri, 26 Jun 2020 08:23:59 -0700 (PDT) Received: from localhost ([::1]:52588 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqCs-0000Tz-Az for importer@patchew.org; Fri, 26 Jun 2020 11:23:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35760) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq48-0002Sx-AT for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:56 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:33570) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq46-0006QF-HJ for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:56 -0400 Received: by mail-wr1-x42c.google.com with SMTP id f18so1796338wrs.0 for ; Fri, 26 Jun 2020 08:14:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-a64.h | 1 + target/arm/internals.h | 9 +++++++ target/arm/mte_helper.c | 10 ++++++++ target/arm/translate-a64.c | 51 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 71 insertions(+) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 587ccbe42ff..6c116481e8f 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -105,3 +105,4 @@ DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env,= i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) =20 DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index ae611a6ff5d..5c69d4e5a56 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1261,6 +1261,15 @@ void arm_log_exception(int idx); */ #define GMID_EL1_BS 6 =20 +/* We associate one allocation tag per 16 bytes, the minimum. */ +#define LOG2_TAG_GRANULE 4 +#define TAG_GRANULE (1 << LOG2_TAG_GRANULE) + +static inline int allocation_tag_from_addr(uint64_t ptr) +{ + return extract64(ptr, 56, 4); +} + static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) { return deposit64(ptr, 56, 4, rtag); diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 539a04de84b..9ab9ed749d8 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -70,3 +70,13 @@ uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint= 64_t rm) =20 return address_with_allocation_tag(rn, rtag); } + +uint64_t HELPER(addsubg)(CPUARMState *env, uint64_t ptr, + int32_t offset, uint32_t tag_offset) +{ + int start_tag =3D allocation_tag_from_addr(ptr); + uint16_t exclude =3D extract32(env->cp15.gcr_el1, 0, 16); + int rtag =3D choose_nonexcluded_tag(start_tag, tag_offset, exclude); + + return address_with_allocation_tag(ptr + offset, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 03aa0925983..2ec02c8a5f3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3808,6 +3808,54 @@ static void disas_add_sub_imm(DisasContext *s, uint3= 2_t insn) tcg_temp_free_i64(tcg_result); } =20 +/* + * Add/subtract (immediate, with tags) + * + * 31 30 29 28 23 22 21 16 14 10 9 5 4 0 + * +--+--+--+-------------+--+---------+--+-------+-----+-----+ + * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd | + * +--+--+--+-------------+--+---------+--+-------+-----+-----+ + * + * op: 0 -> add, 1 -> sub + */ +static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn) +{ + int rd =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + int uimm4 =3D extract32(insn, 10, 4); + int uimm6 =3D extract32(insn, 16, 6); + bool sub_op =3D extract32(insn, 30, 1); + TCGv_i64 tcg_rn, tcg_rd; + int imm; + + /* Test all of sf=3D1, S=3D0, o2=3D0, o3=3D0. */ + if ((insn & 0xa040c000u) !=3D 0x80000000u || + !dc_isar_feature(aa64_mte_insn_reg, s)) { + unallocated_encoding(s); + return; + } + + imm =3D uimm6 << LOG2_TAG_GRANULE; + if (sub_op) { + imm =3D -imm; + } + + tcg_rn =3D cpu_reg_sp(s, rn); + tcg_rd =3D cpu_reg_sp(s, rd); + + if (s->ata) { + TCGv_i32 offset =3D tcg_const_i32(imm); + TCGv_i32 tag_offset =3D tcg_const_i32(uimm4); + + gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + tcg_temp_free_i32(tag_offset); + tcg_temp_free_i32(offset); + } else { + tcg_gen_addi_i64(tcg_rd, tcg_rn, imm); + gen_address_with_allocation_tag0(tcg_rd, tcg_rd); + } +} + /* The input should be a value in the bottom e bits (with higher * bits zero); returns that value replicated into every element * of size e in a 64 bit integer. @@ -4170,6 +4218,9 @@ static void disas_data_proc_imm(DisasContext *s, uint= 32_t insn) case 0x22: /* Add/subtract (immediate) */ disas_add_sub_imm(s, insn); break; + case 0x23: /* Add/subtract (immediate, with tags) */ + disas_add_sub_imm_with_tags(s, insn); + break; case 0x24: /* Logical (immediate) */ disas_logic_imm(s, insn); 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2ec02c8a5f3..ee9dfa8e439 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5346,6 +5346,21 @@ static void disas_data_proc_2src(DisasContext *s, ui= nt32_t insn) cpu_reg_sp(s, rn)); } break; + case 5: /* GMI */ + if (sf =3D=3D 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } else { + TCGv_i64 t1 =3D tcg_const_i64(1); + TCGv_i64 t2 =3D tcg_temp_new_i64(); + + tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4); + tcg_gen_shl_i64(t1, t1, t2); + tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1); + + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + } + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185498; cv=none; d=zohomail.com; s=zohoarc; b=LilvYBSf8k9IEtYucmRYh7tqNDOmsEsWUHbBNzLAkzU52IKhrajJTuXolsFyTozIPUSISmGA95Rqn3ewYdr2aCd59yT102ABzqtFdULVyHRDyE1KA4KNdrK63dHZhD7d5xMQ/5F9DZ0pbCkIYX9J0QIK1JWzTHSj8H7JHMcAEzQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185498; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a0syJ1sIv8i3fVj+GdrHNB0e6D/PFUBhQOSTOV0RdwE=; b=ZzvwN6XowMBc02f9SSgEQeXa6OCKaNLW5HU9AzFycuobsksHuDrN/HHlF7tTjGZ4nmNUDJeIWahyWzGtvPot9oTTgHQx1JZtDVFY4qZSdSEd61pHlo30Ok+oZKbud+CJSz8Vaaza+l97ExEG0OO4OIqcby2MQXlBcowuhLJkCo4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185498100724.876074239529; Fri, 26 Jun 2020 08:31:38 -0700 (PDT) Received: from localhost ([::1]:58566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqKG-0006DW-S2 for importer@patchew.org; Fri, 26 Jun 2020 11:31:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35784) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4A-0002Yx-Jl for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:58 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:45068) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq48-0006S9-Rr for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:58 -0400 Received: by mail-wr1-x42d.google.com with SMTP id s10so9823089wrw.12 for ; Fri, 26 Jun 2020 08:14:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=a0syJ1sIv8i3fVj+GdrHNB0e6D/PFUBhQOSTOV0RdwE=; b=b/5+kgSzMRMIlYczvyM8xG6L84sLT371oYCvxYNunM+65D4D+aP4hwdF99kU9oTyMK n19roWgs/G5K53rDjtMELB4VzTonGYCCyzjYLyCcCPfhcQQqFjBmo9iaIkNzxQQ4hrXP xw1nht7obIj44bCV1EIPj68uVZqg2RYQMbWthKw96WICATxh24k3MMrxUFJI3+yd6P2V x6ygnz8JcA7/0pMDu14W3a770VTl7ASC50vqjKS1RvZ1C0ouQvdelpZn8PRNwHmfkIQU /LlM6RGYAFd9L+9dvsKWmDoWK7lYBAXnvsJF5UFmBtACuzYyyrkbIwgyb9oXfejQbHSt ve7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a0syJ1sIv8i3fVj+GdrHNB0e6D/PFUBhQOSTOV0RdwE=; b=jAFHBX9CLY1e3LVwgEHx7ENun8FJy5tTxIWnYYBM/PiLe+VRzO/x5wykzyWJJ0S/yc VztJZyhzbp9HBfIm04VmXnN9iLJHWD7xQxpUdRsGnyW252JKV7im+4amd5TpUX33TL/t SycXfFvrRlOoVWcG93qVwPdZnO/NugFgItLgeM2nfGR/P27Z1uc5CauIXjPv7PhDYhoX ooZ7KTA7N5DTMQ7M0TrXn7tyc6CYXJfe7EFKlSw7n8FytZu1m7DLvp8E9nhTmbhnFYTh vH4P5Ot4xPruHwkSvXQkOpXUaOIltk9VZvPx4PLR70h2rrsPm1cAOIZNBc3wRCMFxZBO Nr2Q== X-Gm-Message-State: AOAM530qV4wEqFse+HEVTJpBmvj8AnRNnFpbsBF659SmXhHoWMnsEWHI UZGru24xFgOwU+jMFRrr36AJJI8TfcSRTQ== X-Google-Smtp-Source: ABdhPJwp/l7QtIW51GzCO2pFfqC8U3YlCZwoadq8RwduGWXvcyn53F9LxzBLaf9Zq+dekFsnhid7Cg== X-Received: by 2002:a5d:670d:: with SMTP id o13mr921948wru.307.1593184494956; Fri, 26 Jun 2020 08:14:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/57] target/arm: Implement the SUBP instruction Date: Fri, 26 Jun 2020 16:13:52 +0100 Message-Id: <20200626151424.30117-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ee9dfa8e439..abbcdbb53ae 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5315,19 +5315,39 @@ static void handle_crc32(DisasContext *s, */ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) { - unsigned int sf, rm, opcode, rn, rd; + unsigned int sf, rm, opcode, rn, rd, setflag; sf =3D extract32(insn, 31, 1); + setflag =3D extract32(insn, 29, 1); rm =3D extract32(insn, 16, 5); opcode =3D extract32(insn, 10, 6); rn =3D extract32(insn, 5, 5); rd =3D extract32(insn, 0, 5); =20 - if (extract32(insn, 29, 1)) { + if (setflag && opcode !=3D 0) { unallocated_encoding(s); return; } =20 switch (opcode) { + case 0: /* SUBP(S) */ + if (sf =3D=3D 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } else { + TCGv_i64 tcg_n, tcg_m, tcg_d; + + tcg_n =3D read_cpu_reg_sp(s, rn, true); + tcg_m =3D read_cpu_reg_sp(s, rm, true); + tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56); + tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56); + tcg_d =3D cpu_reg(s, rd); + + if (setflag) { + gen_sub_CC(true, tcg_d, tcg_n, tcg_m); + } else { + tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m); + } + } + break; case 2: /* UDIV */ handle_div(s, false, sf, rm, rn, rd); break; --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185800; cv=none; d=zohomail.com; s=zohoarc; b=ZyE4r6KYTUSChPj9qwfi/oA4yHogGLNO39so9QHfCF3QZFPZAsoqYMhyxwCeujIgNERBqsrVo6xrGfIiMviOfE84/HCLCjOYX32x7nG5cZGmrvIHgxAoW6QONr+kI6OjZ+0OfR6ECZOrkKboKng48gp5k+FSkfsz0FvjWMkQrfU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185800; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Z3WhPCSbc/ErEx8VXjma/l1Goh9ApGA8m0ZTZ011C2o=; b=SeTQhJO5/N1ryPVyp16NpK1oypmIHX9Jizp3Z/Ot5NwSESF0Q0TRrAVJO1WvPvd7R4J1gojMkCrzXnuqieFW1G8uOImyHIB4d4lKxnQ6NCsBWWHJmeauTdKjaDC3BvFcuAL2iLB5KT1l29HxgdRu16qXX/75fLN3KdBH12IEAZA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185800649438.8970159582035; Fri, 26 Jun 2020 08:36:40 -0700 (PDT) Received: from localhost ([::1]:51268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqP9-0006YO-Db for importer@patchew.org; Fri, 26 Jun 2020 11:36:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4C-0002dD-19 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:00 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:41706) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4A-0006Tr-8j for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:14:59 -0400 Received: by mail-wr1-x430.google.com with SMTP id h15so9845550wrq.8 for ; Fri, 26 Jun 2020 08:14:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Z3WhPCSbc/ErEx8VXjma/l1Goh9ApGA8m0ZTZ011C2o=; b=W68PDnB8XVh76ZTvt739lPw4floRS3q6OJisncP8jyctXY8j8DFijsJZuIiTlbedwZ IyPr/HH6x+ndy2jJanf+Vzc1opzPW9N6bDN3STJvHyzAXkQo6IlnQk3anHLY+Bet8g4s FvrR6UFUE3yVwBBlZILutSXrL8uUBkZ5o6Mhe5+/5V+d+Oa3h9R5MjS+nzVysBQoxWI4 zpS9LYnxgv2OdYBXirx3CVf3S+xArStEL+fdnDem01su/JQZzLpkfD5E4MMCIMQm8k90 k9LKbU1wBYcm53sIYcqD2YZAZ+IW5VtIeuvzQ41U3HEisUbjZH59ukY1m31ht2m1D+h7 +UPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z3WhPCSbc/ErEx8VXjma/l1Goh9ApGA8m0ZTZ011C2o=; b=QlZsNAIfJ+9TJ+sEfyYG8O+ZlF2Zxgovj+/M8LJwKnvO8XgILEp3uVMXSIHBTqNnx5 3dESgnYEp3NX5LmCcJdBOTOHBlsOurXjs358TfFUbfhL7oMguVFI89Sem4Bx6rdlnDiI L99mfb9qziRhzgLebH8MHq3xJbslzH5jE65pUoOgFRGZA2jX1XTVdRSeroTL3m16xbau gFIGHXoOdSrSyv5eNde1qug/KpukUC1eh3a/wVeAxYnP6OD1Nu/9CR36oztE/5mczbVl cVSjq0374BrHCu6wouLy+IJoBPGf9HHu3Rx3jqYRhNuH+pMo8J98nWP510HJLGCzQGEZ VOEQ== X-Gm-Message-State: AOAM533WXmLZROOrT9i5/1QX+25UN1VosuEv3MUjgbr+hqLR7JUnm00x IWiA2RgMplvCgPqSwS8PUoWxpyE/lNL1yA== X-Google-Smtp-Source: ABdhPJyCfH1h7MiNl3v11mrX2M1bI4MnFYhs6eC+lnpBwBflCA9qUclwaKOqLL8MQfZhtSL6C8YV0A== X-Received: by 2002:adf:8067:: with SMTP id 94mr4093422wrk.427.1593184496559; Fri, 26 Jun 2020 08:14:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/57] target/arm: Define arm_cpu_do_unaligned_access for user-only Date: Fri, 26 Jun 2020 16:13:53 +0100 Message-Id: <20200626151424.30117-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use the same code as system mode, so that we generate the same exception + syndrome for the unaligned access. For the moment, if MTE is enabled so that this path is reachable, this would generate a SIGSEGV in the user-only cpu_loop. Decoding the syndrome to produce the proper SIGBUS will be done later. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 2 +- target/arm/tlb_helper.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e44e18062cf..d9b8ec791ed 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2169,8 +2169,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->tlb_fill =3D arm_cpu_tlb_fill; cc->debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; -#if !defined(CONFIG_USER_ONLY) cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; +#if !defined(CONFIG_USER_ONLY) cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; cc->adjust_watchpoint_address =3D arm_adjust_watchpoint_address; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 7388494a554..522a6442a48 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -10,8 +10,6 @@ #include "internals.h" #include "exec/exec-all.h" =20 -#if !defined(CONFIG_USER_ONLY) - static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, bool same_el, bool ea, @@ -122,6 +120,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr va= ddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } =20 +#if !defined(CONFIG_USER_ONLY) + /* * arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185118; cv=none; d=zohomail.com; s=zohoarc; b=mZtvbWA9hCXFa25MGPGE9+k7ffSD0A/aewaneiUwqtYQ6A8gnEje1Ppz0imuC7ZtNUuw0APUsOhbvm74aRDYN1gtyc4M0cwtnaeFNae3KzfqQyXrOO1NiwbY+IvJ3XJ7Zz5d90vYZ+0BkQGEE++s6n58fslZDhi5zXdUK/6YUDA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185118; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YLzrdkPLvWXYAAoJJii7JD1emWuYVWVKUKC3VjS9b5A=; b=CwvkwV1qttXHhHr4gVNxJsHa6AVvSiRHp1Jns4gJfh8hNYKNd3jzI4ZftiUqoizfQcmYuCXal8oOLmkhB6B7/zWXwOF/5pLkr/JnJeajgo6MY8SXdRlwFUnO0QvRShhir+Ne4YY7SN1Vmgf8wEx78CipjXYD2PB0rZgPOgSydDs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185118979679.6263394785649; Fri, 26 Jun 2020 08:25:18 -0700 (PDT) Received: from localhost ([::1]:59214 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqE9-00039K-KX for importer@patchew.org; Fri, 26 Jun 2020 11:25:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35874) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4G-0002mO-2X for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:04 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:34312) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4B-0006Vf-US for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:03 -0400 Received: by mail-wr1-x431.google.com with SMTP id f7so6867004wrw.1 for ; Fri, 26 Jun 2020 08:14:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YLzrdkPLvWXYAAoJJii7JD1emWuYVWVKUKC3VjS9b5A=; b=syNyzMcAmB6QIXsbtytVWCznBCeUfaSMgeCE37MiP27fB9KXNCM8HTLFXr77zZbInR yOGEc1Pczi3j0KxZmYJCjyk1ykEC9/3apU3pKf5ASX+nVkQIyLWaRtguJYG+9zu2sjoS s1Mlar7qIxvwwlHrGjV+dt1Q2BUbwrODu3naukCbwl/yA92cEtcH2KnwlfmUSHB2npFT RgTtNdSc4jdl8WY6UlU6I/uSM3/HrP4ipcZV3fJ+miylWnTYEVSnuWMPqQ/M4IWsMLos e/DPpHEuUIs9WpA/VVQ1t/ycil8X545n/Oe3rJEn1BZvtqYN7OK3UrXYz09aMAsmUUsG tacw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YLzrdkPLvWXYAAoJJii7JD1emWuYVWVKUKC3VjS9b5A=; b=opJsapmsFEigd1RddrDqC72WCuRHBhCXoZqGn3qwqzlh7NYMkOMHpyIbiTx3E8nvV4 0txXIXJVToI8gR2/WcfszvxaxHl/MFafs6sqd60V8aIryp0qx0rCt+zYyEPLwZeaCfxx ZEKE24JSaQVgFxpXbrXJgqTRRWqHo67GHSRnQRjHrVDZ9PtZvP/wMS/cdZpdUYF/1vLo ly+lpvhQ3/BegbCeRkvBP1phz/Hwy2YQEicRJXxh7Oupg55tnsh6ZwAzMWy0eUO90AYp EeAADOgN5w7xEQOnkwsOjnANSWXrt2hSEFVG9UdjV97hBWcvNkU3Xx+jTYGf/Qcdr5Kq 1gAA== X-Gm-Message-State: AOAM530ZTfJFDmLmzYcPyN45ora9eh7spv5N0OiGQKzuGhUQsKhqk6c2 2u47vgSLPkgRY08uMbLATpOQyS17QGCGuw== X-Google-Smtp-Source: ABdhPJzKtIIVikVErkX/Q1rGCBID3wu+MZmgbSPmL6HED4Uc8DMP63sie8paDW+jV3NPS7e6bZVC1g== X-Received: by 2002:adf:f3cf:: with SMTP id g15mr3937733wrp.388.1593184497847; Fri, 26 Jun 2020 08:14:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/57] target/arm: Implement LDG, STG, ST2G instructions Date: Fri, 26 Jun 2020 16:13:54 +0100 Message-Id: <20200626151424.30117-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-a64.h | 7 ++ target/arm/helper.h | 2 + target/arm/mte_helper.c | 194 +++++++++++++++++++++++++++++++++++++ target/arm/op_helper.c | 16 +++ target/arm/translate-a64.c | 172 +++++++++++++++++++++++++++++++- 5 files changed, 386 insertions(+), 5 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 6c116481e8f..2fa61b86fa7 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -106,3 +106,10 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env= , i64) =20 DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) +DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_2(stg_stub, TCG_CALL_NO_WG, void, env, i64) +DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_2(st2g_stub, TCG_CALL_NO_WG, void, env, i64) diff --git a/target/arm/helper.h b/target/arm/helper.h index 2a20c8174cf..759639a63a2 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -96,6 +96,8 @@ DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_= RWG, void, env) DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) =20 +DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, = i32) + DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_2(vfp_set_fpscr, void, env, i32) =20 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 9ab9ed749d8..7ec7930dfc8 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -44,6 +44,40 @@ static int choose_nonexcluded_tag(int tag, int offset, u= int16_t exclude) return tag; } =20 +/** + * allocation_tag_mem: + * @env: the cpu environment + * @ptr_mmu_idx: the addressing regime to use for the virtual address + * @ptr: the virtual address for which to look up tag memory + * @ptr_access: the access to use for the virtual address + * @ptr_size: the number of bytes in the normal memory access + * @tag_access: the access to use for the tag memory + * @tag_size: the number of bytes in the tag memory access + * @ra: the return address for exception handling + * + * Our tag memory is formatted as a sequence of little-endian nibbles. + * That is, the byte at (addr >> (LOG2_TAG_GRANULE + 1)) contains two + * tags, with the tag at [3:0] for the lower addr and the tag at [7:4] + * for the higher addr. + * + * Here, resolve the physical address from the virtual address, and return + * a pointer to the corresponding tag byte. Exit with exception if the + * virtual address is not accessible for @ptr_access. + * + * The @ptr_size and @tag_size values may not have an obvious relation + * due to the alignment of @ptr, and the number of tag checks required. + * + * If there is no tag storage corresponding to @ptr, return NULL. + */ +static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, + uint64_t ptr, MMUAccessType ptr_access, + int ptr_size, MMUAccessType tag_access, + int tag_size, uintptr_t ra) +{ + /* Tag storage not implemented. */ + return NULL; +} + uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) { int rtag; @@ -80,3 +114,163 @@ uint64_t HELPER(addsubg)(CPUARMState *env, uint64_t pt= r, =20 return address_with_allocation_tag(ptr + offset, rtag); } + +static int load_tag1(uint64_t ptr, uint8_t *mem) +{ + int ofs =3D extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + return extract32(*mem, ofs, 4); +} + +uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + int mmu_idx =3D cpu_mmu_index(env, false); + uint8_t *mem; + int rtag =3D 0; + + /* Trap if accessing an invalid page. */ + mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, 1, + MMU_DATA_LOAD, 1, GETPC()); + + /* Load if page supports tags. */ + if (mem) { + rtag =3D load_tag1(ptr, mem); + } + + return address_with_allocation_tag(xt, rtag); +} + +static void check_tag_aligned(CPUARMState *env, uint64_t ptr, uintptr_t ra) +{ + if (unlikely(!QEMU_IS_ALIGNED(ptr, TAG_GRANULE))) { + arm_cpu_do_unaligned_access(env_cpu(env), ptr, MMU_DATA_STORE, + cpu_mmu_index(env, false), ra); + g_assert_not_reached(); + } +} + +/* For use in a non-parallel context, store to the given nibble. */ +static void store_tag1(uint64_t ptr, uint8_t *mem, int tag) +{ + int ofs =3D extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + *mem =3D deposit32(*mem, ofs, 4, tag); +} + +/* For use in a parallel context, atomically store to the given nibble. */ +static void store_tag1_parallel(uint64_t ptr, uint8_t *mem, int tag) +{ + int ofs =3D extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + uint8_t old =3D atomic_read(mem); + + while (1) { + uint8_t new =3D deposit32(old, ofs, 4, tag); + uint8_t cmp =3D atomic_cmpxchg(mem, old, new); + if (likely(cmp =3D=3D old)) { + return; + } + old =3D cmp; + } +} + +typedef void stg_store1(uint64_t, uint8_t *, int); + +static inline void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt, + uintptr_t ra, stg_store1 store1) +{ + int mmu_idx =3D cpu_mmu_index(env, false); + uint8_t *mem; + + check_tag_aligned(env, ptr, ra); + + /* Trap if accessing an invalid page. */ + mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, TAG_GRAN= ULE, + MMU_DATA_STORE, 1, ra); + + /* Store if page supports tags. */ + if (mem) { + store1(ptr, mem, allocation_tag_from_addr(xt)); + } +} + +void HELPER(stg)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_stg(env, ptr, xt, GETPC(), store_tag1); +} + +void HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_stg(env, ptr, xt, GETPC(), store_tag1_parallel); +} + +void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr) +{ + int mmu_idx =3D cpu_mmu_index(env, false); + uintptr_t ra =3D GETPC(); + + check_tag_aligned(env, ptr, ra); + probe_write(env, ptr, TAG_GRANULE, mmu_idx, ra); +} + +static inline void do_st2g(CPUARMState *env, uint64_t ptr, uint64_t xt, + uintptr_t ra, stg_store1 store1) +{ + int mmu_idx =3D cpu_mmu_index(env, false); + int tag =3D allocation_tag_from_addr(xt); + uint8_t *mem1, *mem2; + + check_tag_aligned(env, ptr, ra); + + /* + * Trap if accessing an invalid page(s). + * This takes priority over !allocation_tag_access_enabled. + */ + if (ptr & TAG_GRANULE) { + /* Two stores unaligned mod TAG_GRANULE*2 -- modify two bytes. */ + mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, + TAG_GRANULE, MMU_DATA_STORE, 1, ra); + mem2 =3D allocation_tag_mem(env, mmu_idx, ptr + TAG_GRANULE, + MMU_DATA_STORE, TAG_GRANULE, + MMU_DATA_STORE, 1, ra); + + /* Store if page(s) support tags. */ + if (mem1) { + store1(TAG_GRANULE, mem1, tag); + } + if (mem2) { + store1(0, mem2, tag); + } + } else { + /* Two stores aligned mod TAG_GRANULE*2 -- modify one byte. */ + mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, + 2 * TAG_GRANULE, MMU_DATA_STORE, 1, ra); + if (mem1) { + tag |=3D tag << 4; + atomic_set(mem1, tag); + } + } +} + +void HELPER(st2g)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_st2g(env, ptr, xt, GETPC(), store_tag1); +} + +void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_st2g(env, ptr, xt, GETPC(), store_tag1_parallel); +} + +void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) +{ + int mmu_idx =3D cpu_mmu_index(env, false); + uintptr_t ra =3D GETPC(); + int in_page =3D -(ptr | TARGET_PAGE_MASK); + + check_tag_aligned(env, ptr, ra); + + if (likely(in_page >=3D 2 * TAG_GRANULE)) { + probe_write(env, ptr, 2 * TAG_GRANULE, mmu_idx, ra); + } else { + probe_write(env, ptr, TAG_GRANULE, mmu_idx, ra); + probe_write(env, ptr + TAG_GRANULE, TAG_GRANULE, mmu_idx, ra); + } +} diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index eb0de080f11..b1065216b2d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -935,3 +935,19 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, = uint32_t i) return ((uint32_t)x >> shift) | (x << (32 - shift)); } } + +void HELPER(probe_access)(CPUARMState *env, target_ulong ptr, + uint32_t access_type, uint32_t mmu_idx, + uint32_t size) +{ + uint32_t in_page =3D -((uint32_t)ptr | TARGET_PAGE_SIZE); + uintptr_t ra =3D GETPC(); + + if (likely(size <=3D in_page)) { + probe_access(env, ptr, size, access_type, mmu_idx, ra); + } else { + probe_access(env, ptr, in_page, access_type, mmu_idx, ra); + probe_access(env, ptr + in_page, size - in_page, + access_type, mmu_idx, ra); + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index abbcdbb53ae..436191c15cf 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -232,6 +232,19 @@ static void gen_address_with_allocation_tag0(TCGv_i64 = dst, TCGv_i64 src) tcg_gen_andi_i64(dst, src, ~MAKE_64BIT_MASK(56, 4)); } =20 +static void gen_probe_access(DisasContext *s, TCGv_i64 ptr, + MMUAccessType acc, int log2_size) +{ + TCGv_i32 t_acc =3D tcg_const_i32(acc); + TCGv_i32 t_idx =3D tcg_const_i32(get_mem_index(s)); + TCGv_i32 t_size =3D tcg_const_i32(1 << log2_size); + + gen_helper_probe_access(cpu_env, ptr, t_acc, t_idx, t_size); + tcg_temp_free_i32(t_acc); + tcg_temp_free_i32(t_idx); + tcg_temp_free_i32(t_size); +} + typedef struct DisasCompare64 { TCGCond cond; TCGv_i64 value; @@ -3685,6 +3698,154 @@ static void disas_ldst_single_struct(DisasContext *= s, uint32_t insn) } } =20 +/* + * Load/Store memory tags + * + * 31 30 29 24 22 21 12 10 5 0 + * +-----+-------------+-----+---+------+-----+------+------+ + * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | + * +-----+-------------+-----+---+------+-----+------+------+ + */ +static void disas_ldst_tag(DisasContext *s, uint32_t insn) +{ + int rt =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + uint64_t offset =3D sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; + int op2 =3D extract32(insn, 10, 2); + int op1 =3D extract32(insn, 22, 2); + bool is_load =3D false, is_pair =3D false, is_zero =3D false; + int index =3D 0; + TCGv_i64 addr, clean_addr, tcg_rt; + + /* We checked insn bits [29:24,21] in the caller. */ + if (extract32(insn, 30, 2) !=3D 3) { + goto do_unallocated; + } + + /* + * @index is a tri-state variable which has 3 states: + * < 0 : post-index, writeback + * =3D 0 : signed offset + * > 0 : pre-index, writeback + */ + switch (op1) { + case 0: + if (op2 !=3D 0) { + /* STG */ + index =3D op2 - 2; + break; + } + goto do_unallocated; + case 1: + if (op2 !=3D 0) { + /* STZG */ + is_zero =3D true; + index =3D op2 - 2; + } else { + /* LDG */ + is_load =3D true; + } + break; + case 2: + if (op2 !=3D 0) { + /* ST2G */ + is_pair =3D true; + index =3D op2 - 2; + break; + } + goto do_unallocated; + case 3: + if (op2 !=3D 0) { + /* STZ2G */ + is_pair =3D is_zero =3D true; + index =3D op2 - 2; + break; + } + goto do_unallocated; + + default: + do_unallocated: + unallocated_encoding(s); + return; + } + + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + + if (rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + addr =3D read_cpu_reg_sp(s, rn, true); + if (index >=3D 0) { + /* pre-index or signed offset */ + tcg_gen_addi_i64(addr, addr, offset); + } + + if (is_load) { + tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); + tcg_rt =3D cpu_reg(s, rt); + if (s->ata) { + gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); + } else { + clean_addr =3D clean_data_tbi(s, addr); + gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); + gen_address_with_allocation_tag0(tcg_rt, addr); + } + } else { + tcg_rt =3D cpu_reg_sp(s, rt); + if (!s->ata) { + /* + * For STG and ST2G, we need to check alignment and probe memo= ry. + * TODO: For STZG and STZ2G, we could rely on the stores below, + * at least for system mode; user-only won't enforce alignment. + */ + if (is_pair) { + gen_helper_st2g_stub(cpu_env, addr); + } else { + gen_helper_stg_stub(cpu_env, addr); + } + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (is_pair) { + gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); + } else { + gen_helper_stg_parallel(cpu_env, addr, tcg_rt); + } + } else { + if (is_pair) { + gen_helper_st2g(cpu_env, addr, tcg_rt); + } else { + gen_helper_stg(cpu_env, addr, tcg_rt); + } + } + } + + if (is_zero) { + TCGv_i64 clean_addr =3D clean_data_tbi(s, addr); + TCGv_i64 tcg_zero =3D tcg_const_i64(0); + int mem_index =3D get_mem_index(s); + int i, n =3D (1 + is_pair) << LOG2_TAG_GRANULE; + + tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, + MO_Q | MO_ALIGN_16); + for (i =3D 8; i < n; i +=3D 8) { + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q); + } + tcg_temp_free_i64(tcg_zero); + } + + if (index !=3D 0) { + /* pre-index or post-index */ + if (index < 0) { + /* post-index */ + tcg_gen_addi_i64(addr, addr, offset); + } + tcg_gen_mov_i64(cpu_reg_sp(s, rn), addr); + } +} + /* Loads and stores */ static void disas_ldst(DisasContext *s, uint32_t insn) { @@ -3709,13 +3870,14 @@ static void disas_ldst(DisasContext *s, uint32_t in= sn) case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; - case 0x19: /* LDAPR/STLR (unscaled immediate) */ - if (extract32(insn, 10, 2) !=3D 0 || - extract32(insn, 21, 1) !=3D 0) { + case 0x19: + if (extract32(insn, 21, 1) !=3D 0) { + disas_ldst_tag(s, insn); + } else if (extract32(insn, 10, 2) =3D=3D 0) { + disas_ldst_ldapr_stlr(s, insn); + } else { unallocated_encoding(s); - break; } - disas_ldst_ldapr_stlr(s, insn); break; default: unallocated_encoding(s); --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185238; cv=none; d=zohomail.com; s=zohoarc; b=Ig0cByFQ6Thy+46cdH8GoApW1D/IHq8pu9XUdGkj5IULca3ngxuR5zAxe6TYDhhYTYCF1KixmwL2ZYHzAS28xFxHZyzRFSW7P2kuA43DauqxaMDCcocq6iER9uFwEi6rWy/TtE9y6OpcqwACfkv8rgFSZ321ghPgHcGsUTIKwxs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185238; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 436191c15cf..e2295a371b2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2690,7 +2690,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) * +-----+-------+---+---+-------+---+-------+-------+------+------+ * * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit - * LDPSW 01 + * LDPSW/STGP 01 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit * V: 0 -> GPR, 1 -> Vector * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, @@ -2715,6 +2715,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t= insn) bool is_signed =3D false; bool postindex =3D false; bool wback =3D false; + bool set_tag =3D false; =20 TCGv_i64 clean_addr, dirty_addr; =20 @@ -2727,6 +2728,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_= t insn) =20 if (is_vector) { size =3D 2 + opc; + } else if (opc =3D=3D 1 && !is_load) { + /* STGP */ + if (!dc_isar_feature(aa64_mte_insn_reg, s) || index =3D=3D 0) { + unallocated_encoding(s); + return; + } + size =3D 3; + set_tag =3D true; } else { size =3D 2 + extract32(opc, 1, 1); is_signed =3D extract32(opc, 0, 1); @@ -2767,7 +2776,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t= insn) return; } =20 - offset <<=3D size; + offset <<=3D (set_tag ? LOG2_TAG_GRANULE : size); =20 if (rn =3D=3D 31) { gen_check_sp_alignment(s); @@ -2777,8 +2786,22 @@ static void disas_ldst_pair(DisasContext *s, uint32_= t insn) if (!postindex) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - clean_addr =3D clean_data_tbi(s, dirty_addr); =20 + if (set_tag) { + if (!s->ata) { + /* + * TODO: We could rely on the stores below, at least for + * system mode, if we arrange to add MO_ALIGN_16. + */ + gen_helper_stg_stub(cpu_env, dirty_addr); + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); + } else { + gen_helper_stg(cpu_env, dirty_addr, dirty_addr); + } + } + + clean_addr =3D clean_data_tbi(s, dirty_addr); if (is_vector) { if (is_load) { do_fp_ld(s, rt, clean_addr, size); --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185614; cv=none; d=zohomail.com; s=zohoarc; b=V2WUre4g+++86Z2GyLRdrkbmmSwKvNMHHERfWJkyjpX6Q0shr/VbM2cvB502ak0xbNCsihIP41Mn1fMwybaVdDAzEITM3w/InAHjDS6BsP2r02nG2KRXborzoRXWymGVWK3E+ZojNSQPbj++E0qiv/Dn/AC7NwMiZWdP5i+DgnI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185614; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qsOodnm1qeB+KB+yqVxO1rsPzGD5oxJ366HcOjFmYxY=; b=fG3PdKxhgjqLjVEM7nfzOUnsZOUVYn9eqvBPeDhHCne1dpUYZcgP4Wl+G16ZIVxKn6joRCGkkMJ3aDXMrscs0AtWC7YgGMbQ53C5VSAj6xk5DJGnXg1Td5TV8IoD4UOxy2jANUuncZ3BSq9fnzMVHZkVZRxbWtlihAM2Z7Knl0A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185614058499.6865970633763; Fri, 26 Jun 2020 08:33:34 -0700 (PDT) Received: from localhost ([::1]:38662 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqM8-0001Ec-Od for importer@patchew.org; Fri, 26 Jun 2020 11:33:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35856) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4F-0002kY-5X for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:03 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:52629) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4D-0006Wj-Bh for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:02 -0400 Received: by mail-wm1-x344.google.com with SMTP id q15so9160623wmj.2 for ; Fri, 26 Jun 2020 08:15:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:14:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qsOodnm1qeB+KB+yqVxO1rsPzGD5oxJ366HcOjFmYxY=; b=bThhGxWpM5LrXTuqeCmS/UersBa4sqSxfaHVpgv6LfMWv8X51cQy+5JXnCW1BhMKo3 ueToEZ5USep9XA9lei5pn83/l1D7nCjiMRyFF0Baz6W1WP9bptMjvhqO59T772F49qMl vearV8hib7mmCRPsBK5SFnJROWCwqoiWBGaZyMuQE7x5e4ZQwsCCAXEHVoSbawzBi7o1 vheRdiUx73rdLlRHjvAT2gG+UTg+Mj+yI1hpzWS2Y4x7p4AgJFFv5k3eN8v72Fv0RNpw xQrbFg1u/3SmMNa5clfEb6WF6HcHZutLxXWx9TzK3PV3I7sHWNGfLdJfoqPlgYsdF+N8 KZlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qsOodnm1qeB+KB+yqVxO1rsPzGD5oxJ366HcOjFmYxY=; b=amp5d0z7HDZDH/yNO+V+rv7HTGG4zaXIIT+kB8/Qt0LnImJYbp2SQeVrDCSEknOiVn hI9J40DkZ7G7k6CHX4X/gRGoliXmrFJWaCLkkth4P4i3EmH809waUesW7Cks9UnCLuGF qjUKFFU77M9LmQFcWLi+COjl6vVJkF8hdq6e49RY2XINDe85Xah4osFBZqCxkt1WPs1b 60ZjPCQ89irm39oR8GE+vsuw7PBbxJJ19c5oPl5omj3MYtssO7UDmNaz6cFSk6m84nnF 0c8FjHej8b0gKf/ySajAPfcFrPRfTLXgBDRQcAvd9z+YFJEJw/VW+xT51wZuoeIad67P 134g== X-Gm-Message-State: AOAM532N2dGYOLTSloXYvg+L9ipBw8s6jJMOzsrxkR5E8kAgtoqGn6fS db6v7UDAtzi4yWocIVe6vahJ6eWnsQ1zrA== X-Google-Smtp-Source: ABdhPJxukKEVUD5jKt18MHY9Xel6dYaVewsO36brKK7DNB8WNcQLbzRg9tqWkun7l16BKOvdxuikpA== X-Received: by 2002:a1c:2d54:: with SMTP id t81mr4249439wmt.154.1593184499755; Fri, 26 Jun 2020 08:14:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/57] target/arm: Restrict the values of DCZID.BS under TCG Date: Fri, 26 Jun 2020 16:13:56 +0100 Message-Id: <20200626151424.30117-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We can simplify our DC_ZVA if we recognize that the largest BS that we actually use in system mode is 64. Let us just assert that it fits within TARGET_PAGE_SIZE. For DC_GVA and STZGM, we want to be able to write whole bytes of tag memory, so assert that BS is >=3D 2 * TAG_GRANULE, or 32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d9b8ec791ed..d9876337c05 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1758,6 +1758,30 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) } #endif =20 + if (tcg_enabled()) { + int dcz_blocklen =3D 4 << cpu->dcz_blocksize; + + /* + * We only support DCZ blocklen that fits on one page. + * + * Architectually this is always true. However TARGET_PAGE_SIZE + * is variable and, for compatibility with -machine virt-2.7, + * is only 1KiB, as an artifact of legacy ARMv5 subpage support. + * But even then, while the largest architectural DCZ blocklen + * is 2KiB, no cpu actually uses such a large blocklen. + */ + assert(dcz_blocklen <=3D TARGET_PAGE_SIZE); + + /* + * We only support DCZ blocksize >=3D 2*TAG_GRANULE, which is to s= ay + * both nibbles of each byte storing tag data may be written at on= ce. + * Since TAG_GRANULE is 16, this means that blocklen must be >=3D = 32. + */ + if (cpu_isar_feature(aa64_mte, cpu)) { + assert(dcz_blocklen >=3D 2 * TAG_GRANULE); + } + } + qemu_init_vcpu(cs); cpu_reset(cs); =20 --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185218; cv=none; d=zohomail.com; s=zohoarc; b=DNTilqekHT7i63ZYkszk+WhNeRN6y/u3zaUHEG7HquI/gSHUWDfzU78/dXbxtAbHqlrhp+mqoqmKBxbdESeYEs+ii1WZfec3+bUGEsf/XfuWPI9DBbpwY77WUQ7gZYnm+bUKL4qE5LEm/1EaXwdgdQQ9uinI0gIpart2kCknEl8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185218; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kErye9eNnDjstzH+b9YxgalNIVLgWMD+e3T4oMN/njw=; b=MIJbVLZ7om323kjrBJFaba9+rs73WxYHYEIvzUJifGN2RuC9FZFFi+qEataqT+Vp9F+p1wOMkccoK0lpP1U8qG/k2muStoeI9TJYXdtUov87W/BKWWYeGGIAYWji6+4c/6cDJ5pzpzyq7NFJJMRXW1joEReZ2/UlL0U304m2k6A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159318521828798.75066581277758; Fri, 26 Jun 2020 08:26:58 -0700 (PDT) Received: from localhost ([::1]:39610 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqFk-0006iO-SF for importer@patchew.org; Fri, 26 Jun 2020 11:26:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35880) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4G-0002nT-KO for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:04 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:36933) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4E-0006YN-Lf for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:04 -0400 Received: by mail-wm1-x344.google.com with SMTP id o2so9723983wmh.2 for ; Fri, 26 Jun 2020 08:15:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.14.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kErye9eNnDjstzH+b9YxgalNIVLgWMD+e3T4oMN/njw=; b=qAWak+eV11R9viLF53UGkq2Gcrob3Vnb9jXyQwLw9aT5IPNSOPI6AIisqRounN5vmn vRLbQU71r5VcFYYv54mmrUBrNprPkvfcra6BYglJrzoUZFAcE3jCyscvL2ZFE5PhJwfe QGE9cOovv0Ht2GyKsd30qATrnFhZo/eyeLYTr6uSPuks5vjihbNHKwD/2aqJagCybPeH YakvGp1Ph5DVYTenvmNWp5DNIGHl9z8hqKdDTV1p1p9W+1r5KaPXupvdyLOteXkq2DVO 6rY9IvgfqnmkXzOg5wnWcQkVqA9+WjTW2Mz5MfSjK1bAL2uU6CmCIhU8wTtWJ6KPKfR/ m+xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kErye9eNnDjstzH+b9YxgalNIVLgWMD+e3T4oMN/njw=; b=VqARpkMh2N/FzyvPuo/GFlnaPblDWlXYJpkkijRXrnXekkSHPvs4mmDNG7ZgPSxCeV 4MRARe3JIUrQy0Kv3MWnuO1oG2fwxRt6bjq7tsp+EjPPQiYthmItGZwGs8tovFGhlXOI jClJW9l2fPtG4m4hFvSBYiFNtpWF0qHvUcV56uZuqCBsIeBAY0O0294akDNaIPf/IVsB vfT3zMlTQ1IVIkC9PnQFet0MSEuPusoetjr6bzcBJJCWHb2erTYFyxpaaVeIxofFSfst 9TAk0U5ooblpdrgVccy8jmQWTEOE63qBE0mbnDWaOhZ06Taf4dxQPE+f6xgiuzFrm9e2 JQKQ== X-Gm-Message-State: AOAM530YDuZPeD20E7ewJViQ9CDMuqrzTQ5iy+mYRyTCTJfacI5sTR+I zqGaD2fPcRyUB4zw/bddaaDVZn2lMpHh7g== X-Google-Smtp-Source: ABdhPJy4FRYW/3V3x2IpHIaF+mYv/+Ozhq0LPcNg7eBPaK5hCEiROGXXmPS8bOzts7ZPp0Zdsy91/w== X-Received: by 2002:a7b:ca52:: with SMTP id m18mr3920667wml.92.1593184500902; Fri, 26 Jun 2020 08:15:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/57] target/arm: Simplify DC_ZVA Date: Fri, 26 Jun 2020 16:13:57 +0100 Message-Id: <20200626151424.30117-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Now that we know that the operation is on a single page, we need not loop over pages while probing. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-a64.c | 94 +++++++++++------------------------------ 1 file changed, 25 insertions(+), 69 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index bc0649a44aa..8682630ff6c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1119,85 +1119,41 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vadd= r_in) * (which matches the usual QEMU behaviour of not implementing either * alignment faults or any memory attribute handling). */ - - ARMCPU *cpu =3D env_archcpu(env); - uint64_t blocklen =3D 4 << cpu->dcz_blocksize; + int blocklen =3D 4 << env_archcpu(env)->dcz_blocksize; uint64_t vaddr =3D vaddr_in & ~(blocklen - 1); + int mmu_idx =3D cpu_mmu_index(env, false); + void *mem; + + /* + * Trapless lookup. In addition to actual invalid page, may + * return NULL for I/O, watchpoints, clean pages, etc. + */ + mem =3D tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx); =20 #ifndef CONFIG_USER_ONLY - { + if (unlikely(!mem)) { + uintptr_t ra =3D GETPC(); + /* - * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than - * the block size so we might have to do more than one TLB lookup. - * We know that in fact for any v8 CPU the page size is at least 4K - * and the block size must be 2K or less, but TARGET_PAGE_SIZE is = only - * 1K as an artefact of legacy v5 subpage support being present in= the - * same QEMU executable. So in practice the hostaddr[] array has - * two entries, given the current setting of TARGET_PAGE_BITS_MIN. + * Trap if accessing an invalid page. DC_ZVA requires that we sup= ply + * the original pointer for an invalid page. But watchpoints requ= ire + * that we probe the actual space. So do both. */ - int maxidx =3D DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); - void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)]; - int try, i; - unsigned mmu_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + (void) probe_write(env, vaddr_in, 1, mmu_idx, ra); + mem =3D probe_write(env, vaddr, blocklen, mmu_idx, ra); =20 - assert(maxidx <=3D ARRAY_SIZE(hostaddr)); - - for (try =3D 0; try < 2; try++) { - - for (i =3D 0; i < maxidx; i++) { - hostaddr[i] =3D tlb_vaddr_to_host(env, - vaddr + TARGET_PAGE_SIZE *= i, - 1, mmu_idx); - if (!hostaddr[i]) { - break; - } - } - if (i =3D=3D maxidx) { - /* - * If it's all in the TLB it's fair game for just writing = to; - * we know we don't need to update dirty status, etc. - */ - for (i =3D 0; i < maxidx - 1; i++) { - memset(hostaddr[i], 0, TARGET_PAGE_SIZE); - } - memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); - return; - } + if (unlikely(!mem)) { /* - * OK, try a store and see if we can populate the tlb. This - * might cause an exception if the memory isn't writable, - * in which case we will longjmp out of here. We must for - * this purpose use the actual register value passed to us - * so that we get the fault address right. + * The only remaining reason for mem =3D=3D NULL is I/O. + * Just do a series of byte writes as the architecture demands. */ - helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); - /* Now we can populate the other TLB entries, if any */ - for (i =3D 0; i < maxidx; i++) { - uint64_t va =3D vaddr + TARGET_PAGE_SIZE * i; - if (va !=3D (vaddr_in & TARGET_PAGE_MASK)) { - helper_ret_stb_mmu(env, va, 0, oi, GETPC()); - } + for (int i =3D 0; i < blocklen; i++) { + cpu_stb_mmuidx_ra(env, vaddr + i, 0, mmu_idx, ra); } - } - - /* - * Slow path (probably attempt to do this to an I/O device or - * similar, or clearing of a block of code we have translations - * cached for). Just do a series of byte writes as the architecture - * demands. It's not worth trying to use a cpu_physical_memory_map= (), - * memset(), unmap() sequence here because: - * + we'd need to account for the blocksize being larger than a p= age - * + the direct-RAM access case is almost always going to be dealt - * with in the fastpath code above, so there's no speed benefit - * + we would have to deal with the map returning NULL because the - * bounce buffer was in use - */ - for (i =3D 0; i < blocklen; i++) { - helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); + return; } } -#else - memset(g2h(vaddr), 0, blocklen); #endif + + memset(mem, 0, blocklen); } --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185349; cv=none; d=zohomail.com; s=zohoarc; b=l/8Q8jsSWE3lcx5Sfs67dtrpn99fe3IPj7jynNFsbAg6uDhaFWGZPJPTx5xNOHPEXix+lpCjKhBCZM+oy175VqylzNfMyqP+v1GAU2M8Gs87Wq2VrDsROGLJbQEOesThLWhZK+THtwKujoZtuTTn+x3CpW0LTOIDWc5L2VEUC28= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185349; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=e7FbhF1Dy3EaqHLB3F1GgTrSdqI07DdpzshNwR1uJmk=; b=M+x1TjNGzo/FVA5s/qRZ0HtVFbAYsJHDxi4vVl/rfsBiiMiFaRtfcmNX081ogz6TV8aiIKEzl2hOsyNLkD++9MJyOgMAce5O+NbVkuom3eVjpGFY1bYxgmPh8RV9BOtqkT95g3BELeUG7zwasYYNeRK4gUaMxdyGEI6IFUHcjIg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185349611637.9226251363183; Fri, 26 Jun 2020 08:29:09 -0700 (PDT) Received: from localhost ([::1]:48044 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqHs-0001lc-2r for importer@patchew.org; Fri, 26 Jun 2020 11:29:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4I-0002rk-D9 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:06 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:51270) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4G-0006a0-4U for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:06 -0400 Received: by mail-wm1-x333.google.com with SMTP id 22so9168816wmg.1 for ; Fri, 26 Jun 2020 08:15:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-a64.h | 3 ++ target/arm/translate.h | 2 + target/arm/mte_helper.c | 84 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 72 ++++++++++++++++++++++++++++---- 4 files changed, 153 insertions(+), 8 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 2fa61b86fa7..7b628d100e0 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -113,3 +113,6 @@ DEF_HELPER_FLAGS_2(stg_stub, TCG_CALL_NO_WG, void, env,= i64) DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_2(st2g_stub, TCG_CALL_NO_WG, void, env, i64) +DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(stzgm_tags, TCG_CALL_NO_WG, void, env, i64, i64) diff --git a/target/arm/translate.h b/target/arm/translate.h index 98bcc37c479..16f2699ad72 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -91,6 +91,8 @@ typedef struct DisasContext { * < 0, set by the current instruction. */ int8_t btype; + /* A copy of cpu->dcz_blocksize. */ + uint8_t dcz_blocksize; /* True if this page is guarded. */ bool guarded_page; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 7ec7930dfc8..27d4b4536c0 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -274,3 +274,87 @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) probe_write(env, ptr + TAG_GRANULE, TAG_GRANULE, mmu_idx, ra); } } + +#define LDGM_STGM_SIZE (4 << GMID_EL1_BS) + +uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) +{ + int mmu_idx =3D cpu_mmu_index(env, false); + uintptr_t ra =3D GETPC(); + void *tag_mem; + + ptr =3D QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); + + /* Trap if accessing an invalid page. */ + tag_mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, + LDGM_STGM_SIZE, MMU_DATA_LOAD, + LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); + + /* The tag is squashed to zero if the page does not support tags. */ + if (!tag_mem) { + return 0; + } + + QEMU_BUILD_BUG_ON(GMID_EL1_BS !=3D 6); + /* + * We are loading 64-bits worth of tags. The ordering of elements + * within the word corresponds to a 64-bit little-endian operation. + */ + return ldq_le_p(tag_mem); +} + +void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) +{ + int mmu_idx =3D cpu_mmu_index(env, false); + uintptr_t ra =3D GETPC(); + void *tag_mem; + + ptr =3D QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); + + /* Trap if accessing an invalid page. */ + tag_mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, + LDGM_STGM_SIZE, MMU_DATA_LOAD, + LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); + + /* + * Tag store only happens if the page support tags, + * and if the OS has enabled access to the tags. + */ + if (!tag_mem) { + return; + } + + QEMU_BUILD_BUG_ON(GMID_EL1_BS !=3D 6); + /* + * We are storing 64-bits worth of tags. The ordering of elements + * within the word corresponds to a 64-bit little-endian operation. + */ + stq_le_p(tag_mem, val); +} + +void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D cpu_mmu_index(env, false); + int log2_dcz_bytes, log2_tag_bytes; + intptr_t dcz_bytes, tag_bytes; + uint8_t *mem; + + /* + * In arm_cpu_realizefn, we assert that dcz > LOG2_TAG_GRANULE+1, + * i.e. 32 bytes, which is an unreasonably small dcz anyway, + * to make sure that we can access one complete tag byte here. + */ + log2_dcz_bytes =3D env_archcpu(env)->dcz_blocksize + 2; + log2_tag_bytes =3D log2_dcz_bytes - (LOG2_TAG_GRANULE + 1); + dcz_bytes =3D (intptr_t)1 << log2_dcz_bytes; + tag_bytes =3D (intptr_t)1 << log2_tag_bytes; + ptr &=3D -dcz_bytes; + + mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, dcz_byte= s, + MMU_DATA_STORE, tag_bytes, ra); + if (mem) { + int tag_pair =3D (val & 0xf) * 0x11; + memset(mem, tag_pair, tag_bytes); + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e2295a371b2..7dc493774ec 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3736,7 +3736,7 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) uint64_t offset =3D sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; int op2 =3D extract32(insn, 10, 2); int op1 =3D extract32(insn, 22, 2); - bool is_load =3D false, is_pair =3D false, is_zero =3D false; + bool is_load =3D false, is_pair =3D false, is_zero =3D false, is_mult = =3D false; int index =3D 0; TCGv_i64 addr, clean_addr, tcg_rt; =20 @@ -3756,9 +3756,14 @@ static void disas_ldst_tag(DisasContext *s, uint32_t= insn) if (op2 !=3D 0) { /* STG */ index =3D op2 - 2; - break; + } else { + /* STZGM */ + if (s->current_el =3D=3D 0 || offset !=3D 0) { + goto do_unallocated; + } + is_mult =3D is_zero =3D true; } - goto do_unallocated; + break; case 1: if (op2 !=3D 0) { /* STZG */ @@ -3774,17 +3779,27 @@ static void disas_ldst_tag(DisasContext *s, uint32_= t insn) /* ST2G */ is_pair =3D true; index =3D op2 - 2; - break; + } else { + /* STGM */ + if (s->current_el =3D=3D 0 || offset !=3D 0) { + goto do_unallocated; + } + is_mult =3D true; } - goto do_unallocated; + break; case 3: if (op2 !=3D 0) { /* STZ2G */ is_pair =3D is_zero =3D true; index =3D op2 - 2; - break; + } else { + /* LDGM */ + if (s->current_el =3D=3D 0 || offset !=3D 0) { + goto do_unallocated; + } + is_mult =3D is_load =3D true; } - goto do_unallocated; + break; =20 default: do_unallocated: @@ -3792,7 +3807,9 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) return; } =20 - if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + if (is_mult + ? !dc_isar_feature(aa64_mte, s) + : !dc_isar_feature(aa64_mte_insn_reg, s)) { goto do_unallocated; } =20 @@ -3806,6 +3823,44 @@ static void disas_ldst_tag(DisasContext *s, uint32_t= insn) tcg_gen_addi_i64(addr, addr, offset); } =20 + if (is_mult) { + tcg_rt =3D cpu_reg(s, rt); + + if (is_zero) { + int size =3D 4 << s->dcz_blocksize; + + if (s->ata) { + gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); + } + /* + * The non-tags portion of STZGM is mostly like DC_ZVA, + * except the alignment happens before the access. + */ + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_helper_dc_zva(cpu_env, clean_addr); + } else if (s->ata) { + if (is_load) { + gen_helper_ldgm(tcg_rt, cpu_env, addr); + } else { + gen_helper_stgm(cpu_env, addr, tcg_rt); + } + } else { + MMUAccessType acc =3D is_load ? MMU_DATA_LOAD : MMU_DATA_STORE; + int size =3D 4 << GMID_EL1_BS; + + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_probe_access(s, clean_addr, acc, size); + + if (is_load) { + /* The result tags are zeros. */ + tcg_gen_movi_i64(tcg_rt, 0); + } + } + return; + } + if (is_load) { tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); tcg_rt =3D cpu_reg(s, rt); @@ -14472,6 +14527,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; dc->features =3D env->features; + dc->dcz_blocksize =3D arm_cpu->dcz_blocksize; =20 /* Single step state. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Like the regular data cache flushes, these are nops within qemu. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 65 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2c6ec244af8..d8c31d03dad 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6929,6 +6929,32 @@ static const ARMCPRegInfo mte_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, .type =3D ARM_CP_NO_RAW, .access =3D PL0_RW, .readfn =3D tco_read, .writefn =3D tco_write }, + { .name =3D "DC_IGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL1_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_IGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_IGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL1_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_IGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CIGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CIGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, REGINFO_SENTINEL }; =20 @@ -6938,6 +6964,43 @@ static const ARMCPRegInfo mte_tco_ro_reginfo[] =3D { .type =3D ARM_CP_CONST, .access =3D PL0_RW, }, REGINFO_SENTINEL }; + +static const ARMCPRegInfo mte_el0_cacheop_reginfo[] =3D { + { .name =3D "DC_CGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGVAP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGDVAP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGVADP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGDVADP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CIGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CIGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + REGINFO_SENTINEL +}; + #endif =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -8071,8 +8134,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) */ if (cpu_isar_feature(aa64_mte, cpu)) { define_arm_cp_regs(cpu, mte_reginfo); + define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { define_arm_cp_regs(cpu, mte_tco_ro_reginfo); + define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } #endif =20 --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185369; cv=none; d=zohomail.com; s=zohoarc; b=Aq5j1JPjK05tOrAazxmkOQFAPKEM4JbFbtcaFP1eAngHRqBTa2WMX27xLRGWmWNpfuqaMvh+Xwb0G0rMWlaNCTJ6q671MpA3F6yi+hpWVjUnL402Yw1iHyZ10G/Ci2Fs5kNQEHqYInPTiv+GnTR1PL6i3v00EQ4ZHtljig2KlG4= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4niuaNLMyHoiI7IBJkW4eFNXSPAaql3UxQ8+CmFrSD4=; b=FUtsWH9XeaIaSpYAIGbzeeIhRVzgFR2S5orqMEBXz73Qr3Y4haB+LxAhT/It29SO2i HSXZAu3ZGkYQwpD71P6eR41ap+2zGQZrOePSMjo+u1xyoH2rHp4eCkdrvgIohaGB+/kq Fys6WZGARiYFfE205/r4lQk1vJoLAI/P8oWqi+cVeK73FZ7Gqwx7eabtKrz3KxfyCEt5 /ec/56UCj4/twsiyasEEl9+koNrXEkzW7GPSR6lKtx5MblM9I4ODLymSaf7aOhtkdzG9 3HxoVQyupCY7vjyQpWGrdop01PblJYUEaykobO+M7YK3ERjfUVKCGZKKeUpTIbqnH8gt jobQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4niuaNLMyHoiI7IBJkW4eFNXSPAaql3UxQ8+CmFrSD4=; b=lMQJZhIGNYFK+Zi389LWlA2vWk1RQ6zLGVYaVLSsHtyIVIYiSbUhMDKBLymmDeo72V 0tDc+Xax261NUABpsa8nOTml52+lkb6eXc7gRueZJxd26S8INlOoRYtY/KRCOoMEi8ip FqOkf//SWQjY73f8+wearGE5PVPS6i4K13IHl8+b0frkPqa+MXgpFibajhsoCfKT2OBg XYMGIr3INmEFmMAsnkyVoZk9ah+IUIwx8fpfxBkMW+3uJ+QcLwju+4PUYTAKdrmYjd51 7FffGXa7/UWHWFf2LiGS9kEksq7Fwy+n4VhrFT91rS/RqAXnarhS+j7lwWIhW2O96lPe syDQ== X-Gm-Message-State: AOAM530aEkHV13LSYmcpuHHbC7EzIRk5Xdo4iV3N/ijuxcJEvznrpIg/ 5137a61LrVbSuaiy+vnMSRj2edxsVjY//g== X-Google-Smtp-Source: ABdhPJx5lJbau7IuhvNtK81XTa0QDkb8Wg7yzYv/QoSugT5Pt5xVKmrORLfMS3vLSQfDkPXAt7rEkg== X-Received: by 2002:a05:600c:2202:: with SMTP id z2mr4157128wml.13.1593184505008; Fri, 26 Jun 2020 08:15:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/57] target/arm: Move regime_el to internals.h Date: Fri, 26 Jun 2020 16:14:00 +0100 Message-Id: <20200626151424.30117-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We will shortly need this in mte_helper.c as well. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 36 ++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 36 ------------------------------------ 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5c69d4e5a56..c36fcb151b7 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -913,6 +913,42 @@ static inline bool regime_is_pan(CPUARMState *env, ARM= MMUIdx mmu_idx) } } =20 +/* Return the exception level which controls this address translation regi= me */ +static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_Stage2: + case ARMMMUIdx_E2: + return 2; + case ARMMMUIdx_SE3: + return 3; + case ARMMMUIdx_SE10_0: + return arm_el_is_aa64(env, 3) ? 1 : 3; + case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_MPrivNegPri: + case ARMMMUIdx_MUserNegPri: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MUser: + case ARMMMUIdx_MSPrivNegPri: + case ARMMMUIdx_MSUserNegPri: + case ARMMMUIdx_MSPriv: + case ARMMMUIdx_MSUser: + return 1; + default: + g_assert_not_reached(); + } +} + /* Return the FSR value for a debug exception (watchpoint, hardware * breakpoint or BKPT insn) targeting the specified exception level. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index d8c31d03dad..d14313de664 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9793,42 +9793,6 @@ void arm_cpu_do_interrupt(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -/* Return the exception level which controls this address translation regi= me */ -static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_Stage2: - case ARMMMUIdx_E2: - return 2; - case ARMMMUIdx_SE3: - return 3; - case ARMMMUIdx_SE10_0: - return arm_el_is_aa64(env, 3) ? 1 : 3; - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_MPrivNegPri: - case ARMMMUIdx_MUserNegPri: - case ARMMMUIdx_MPriv: - case ARMMMUIdx_MUser: - case ARMMMUIdx_MSPrivNegPri: - case ARMMMUIdx_MSUserNegPri: - case ARMMMUIdx_MSPriv: - case ARMMMUIdx_MSUser: - return 1; - default: - g_assert_not_reached(); - } -} - uint64_t arm_sctlr(CPUARMState *env, int el) { /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185890; cv=none; d=zohomail.com; s=zohoarc; b=SVK8OKOIOM/cR5ufBi5yMP4vq0I2gao0im8CZAE2GxR/DK5w3UEU30qY55BQrE2Ja8h85XjW4JG5wqsCDZMdGsHigcbg+9fSjJURM+nIQfzglXk4NgldKst7inspuysfx5vxQGtUUfHsF6PsEuM3YD1oK0J9YGDs0gImtkUGHJA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185890; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3Yoep4sdiJr6Nl07VaQfGsAhmJmgCfg3E/7/P1j/4h8=; b=GYBnO47np2H0d8E1EddbcbdZ7aNe6hy7dEu/ZhovJbiM8g1iv3HaW8a+jml7ielmc2yDx3PoDX6W4+BSq1Q62sFCOaj2A+p72e3IZBeXU2HQJInnNZNzJqiLGDcYMXBP+PSWqjpJ3NAwGSIsBERDmkOxwSevmc64dz97FFpMzqE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185890610518.3787179246217; Fri, 26 Jun 2020 08:38:10 -0700 (PDT) Received: from localhost ([::1]:59566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqQb-0001XM-EK for importer@patchew.org; Fri, 26 Jun 2020 11:38:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4L-0002zC-SL for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:09 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:38034) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4J-0006bk-MO for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:09 -0400 Received: by mail-wm1-x32b.google.com with SMTP id f18so9720091wml.3 for ; Fri, 26 Jun 2020 08:15:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=3Yoep4sdiJr6Nl07VaQfGsAhmJmgCfg3E/7/P1j/4h8=; b=O9EnPJpuPv1ODtmZb5lDJ9cM5r9m6Kombq1UsiSPGWyZ0Ap7FBokFEOHIlsPtlBZWR 26EAtO90P9sqCKl4f91lLjipjPPXbWKYz2qK+/iHQZWRF/g0fS2qhoSVvHsCm4FonWnr p/HsKbf+eaOpoJtrw3TDpufRdusXtVxJczZIer+3/mkbSWDb0stGsyMiYFWNnbvvMuH/ Qfb/Bw+/ag2nS+5gn4Pi4iwiuSh95eWVpF40rPrOzFGrsMuy5CjsAO35uM54ga3WeHQb Lefb+C2I65KaHSPEr0DhBJMJpJeQC/gB9FIBZ0IwKCcNbuWoebLryUliO1ye6eFSeKnu OSKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3Yoep4sdiJr6Nl07VaQfGsAhmJmgCfg3E/7/P1j/4h8=; b=cwT36uM4bgUYdjlJO2xeTzAJDGPofHVBlqD3yxWVDF+4pMnHXMEUj32ewyknQzsnjy eAeH8M7Gz43zgv5ySHh2UYE6px6i0INSsBUODMxBTZU+Tu46GWudAA7jezOnuEih2q5L dTxYHP/fGHp3Ct1o6MVNqJZzIZrRVbSYS1HXK0iw1VNVHLScyWowxN7lPozFn2KTB6bS setcvOV14r4FC0mGGX8rZGz4IIZv0bOjp3dpw7zUPCx8S81RmpuddWogDn+t+GjHqfi0 XMHXQmO3RH/XlfXqGrBqMR8wB+wlelYozb7kX+BGCT4hb1RvUsBd0qGLSaBqg6SZrghu MwWA== X-Gm-Message-State: AOAM533pg/yvgPMVjiA+TCuNFfyki8K4mho4tlpanD1/8tPOW5BvB6b2 /ZYn9ZjptcCiT0GAZcsbEfVG513fVKUctQ== X-Google-Smtp-Source: ABdhPJyUF8NUz4b4PDFU3qPHnUlbSZ4jxhdvhPZtLw7S7oGFr1q+YBT+i1oe4VVnfmPSlZzgx/jCGA== X-Received: by 2002:a1c:6887:: with SMTP id d129mr3888353wmc.179.1593184505993; Fri, 26 Jun 2020 08:15:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/57] target/arm: Move regime_tcr to internals.h Date: Fri, 26 Jun 2020 16:14:01 +0100 Message-Id: <20200626151424.30117-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We will shortly need this in mte_helper.c as well. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 9 +++++++++ target/arm/helper.c | 9 --------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index c36fcb151b7..7c9abbabc9a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -949,6 +949,15 @@ static inline uint32_t regime_el(CPUARMState *env, ARM= MMUIdx mmu_idx) } } =20 +/* Return the TCR controlling this translation regime */ +static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + return &env->cp15.vtcr_el2; + } + return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; +} + /* Return the FSR value for a debug exception (watchpoint, hardware * breakpoint or BKPT insn) targeting the specified exception level. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index d14313de664..33f902387b4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9875,15 +9875,6 @@ static inline uint64_t regime_ttbr(CPUARMState *env,= ARMMMUIdx mmu_idx, =20 #endif /* !CONFIG_USER_ONLY */ =20 -/* Return the TCR controlling this translation regime */ -static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { - return &env->cp15.vtcr_el2; - } - return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; -} - /* Convert a possible stage1+2 MMU index into the appropriate * stage 1 MMU index */ --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185492; cv=none; d=zohomail.com; s=zohoarc; b=bsIufhjPrsuC6tEEjJBl6ZqEb2XcA8OcaQSxsVHGpCG2HDxRaNn7M8B1LTD38c6rWlbwq4R/pr5E9Awct7ZU6laXA1G6ZOWHS5THlLVPm7RA9mTt5v9EHApOBQgFglzhwlP0PnkRPVtLC6aCEe+phfnDl7Gyjh1zK0KkTl1rg88= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185492; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/eAAFosRGRJgv69Ri2fpL1KyoB3EcB8x/VAhiKbENhM=; b=l3UP4PP/3+L2kSThN+ID7RsFRR6llSIhfCzzUKA7WIaP2OLBrMGgCuI2oC1z2XXKoPXr5YV+AXSgKIyzpWxbo4MdFL4KtodUMrXhqG4WTWurFJnVeeugOPn3Wz3nN1W9p5BekNrmLEhHAYam8gnZYk0u8ECFozKP+fd/ebBf0G8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185492858529.2391445729028; Fri, 26 Jun 2020 08:31:32 -0700 (PDT) Received: from localhost ([::1]:58052 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqKB-000603-GJ for importer@patchew.org; Fri, 26 Jun 2020 11:31:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35992) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4O-00032T-WC for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:14 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:56276) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4L-0006c1-4X for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:12 -0400 Received: by mail-wm1-x330.google.com with SMTP id g75so9145590wme.5 for ; Fri, 26 Jun 2020 08:15:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/eAAFosRGRJgv69Ri2fpL1KyoB3EcB8x/VAhiKbENhM=; b=waVUE6KdRQtwT71HY2AIXFLpvtpxQkbgmFN9cOdjXNKuPWnZV6Ez63WBYfzZbMg/sg bZ17v2O/eQn5C1RslVVPYewEtLJHZHQ5gXYjWYKyt3/G8rstg0kh89HdPqEXDDDZeAdZ GHO149iSSjCvP9leJd3GOSDEGETALkFz9odDisDSoXeulGGuSlL7b1Fzh7ixuGwCUQpv 7qgOWg/SlVil+ZNbrrfQ3oQ+vgBORp1a707yxw5a8j9UqhgsEorPFYeEwVGTE/f2eB4p Pq+umOAVAfgBZScSG3MFtqNxRl7iM9oNvAw+9I/ZPzIyPlU+9zeF+B5PJx0VM+TrMdfr MkyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/eAAFosRGRJgv69Ri2fpL1KyoB3EcB8x/VAhiKbENhM=; b=gBRQsNy2dkasUe9hi4t4vciyVm6W3nt5s/ELZxaOBVteYSbt5YJcg3K821TfGy+Xsr XsRwmqMVcQknSENk/ygTDDhhLV8wcK1OL/yTsBpF+sthmEsgwPCXY2TH8Tz8ceqieyhM m5VXZQUi5dOvNUpfL8zxF+JG6pK+cqUpix+NbvaUWJnmROcd1sJhStaE3fx40jASALfr lp+Rq3lgNt9393SkWHs7Fy/bjBUA/2REu5ob0M/jTYZ1zr7wY6IXiryh8ZF4oF1uj1bc nfmJceWmZfuHE2p2PI+i+CT+GieG0OXCORhsyK+5verRSF+U6nvQtUD/wcgNVzA9vYW5 MUeg== X-Gm-Message-State: AOAM531tHPMXbCOm4N1aaMVrFItxLSSDWrmPiOmKGeeWr4khN9CAfBLP ZBxstjHp6DGjdKutVKMnp+Vu7dzkUVDLPQ== X-Google-Smtp-Source: ABdhPJyei/Rbh0uyCJ78an3Qm4VGERpbrO/+6F1US2MAZzYfTc2oNB802ONqwkz+jkHWfULUkZQn3w== X-Received: by 2002:a1c:2d83:: with SMTP id t125mr4028438wmt.187.1593184507169; Fri, 26 Jun 2020 08:15:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/57] target/arm: Add gen_mte_check1 Date: Fri, 26 Jun 2020 16:14:02 +0100 Message-Id: <20200626151424.30117-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Replace existing uses of check_data_tbi in translate-a64.c that perform a single logical memory access. Leave the helper blank for now to reduce the patch size. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-a64.h | 1 + target/arm/internals.h | 8 +++ target/arm/translate-a64.h | 2 + target/arm/mte_helper.c | 8 +++ target/arm/translate-a64.c | 100 ++++++++++++++++++++++++++++--------- 5 files changed, 95 insertions(+), 24 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 7b628d100e0..2faa49d0a33 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -104,6 +104,7 @@ DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64= , i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) =20 +DEF_HELPER_FLAGS_3(mte_check1, TCG_CALL_NO_WG, i64, env, i32, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/internals.h b/target/arm/internals.h index 7c9abbabc9a..fb92ef6b840 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1310,6 +1310,14 @@ void arm_log_exception(int idx); #define LOG2_TAG_GRANULE 4 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) =20 +/* Bits within a descriptor passed to the helper_mte_check* functions. */ +FIELD(MTEDESC, MIDX, 0, 4) +FIELD(MTEDESC, TBI, 4, 2) +FIELD(MTEDESC, TCMA, 6, 2) +FIELD(MTEDESC, WRITE, 8, 1) +FIELD(MTEDESC, ESIZE, 9, 5) +FIELD(MTEDESC, TSIZE, 14, 10) /* mte_checkN only */ + static inline int allocation_tag_from_addr(uint64_t ptr) { return extract64(ptr, 56, 4); diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index da0f59a2cee..daab6a96665 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -40,6 +40,8 @@ TCGv_ptr get_fpstatus_ptr(bool); bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); bool sve_access_check(DisasContext *s); +TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, + bool tag_checked, int log2_size); =20 /* We should have at some point before trying to access an FP register * done the necessary access check, so assert that diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 27d4b4536c0..ec12768dfc3 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -358,3 +358,11 @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr= , uint64_t val) memset(mem, tag_pair, tag_bytes); } } + +/* + * Perform an MTE checked access for a single logical or atomic access. + */ +uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) +{ + return ptr; +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7dc493774ec..4d0453c8956 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -204,20 +204,20 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 = src) } =20 /* - * Return a "clean" address for ADDR according to TBID. - * This is always a fresh temporary, as we need to be able to - * increment this independently of a dirty write-back address. + * Handle MTE and/or TBI. + * + * For TBI, ideally, we would do nothing. Proper behaviour on fault is + * for the tag to be present in the FAR_ELx register. But for user-only + * mode we do not have a TLB with which to implement this, so we must + * remove the top byte now. + * + * Always return a fresh temporary that we can increment independently + * of the write-back address. */ + static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { TCGv_i64 clean =3D new_tmp_a64(s); - /* - * In order to get the correct value in the FAR_ELx register, - * we must present the memory subsystem with the "dirty" address - * including the TBI. In system mode we can make this work via - * the TLB, dropping the TBI during translation. But for user-only - * mode we don't have that option, and must remove the top byte now. - */ #ifdef CONFIG_USER_ONLY gen_top_byte_ignore(s, clean, addr, s->tbid); #else @@ -245,6 +245,45 @@ static void gen_probe_access(DisasContext *s, TCGv_i64= ptr, tcg_temp_free_i32(t_size); } =20 +/* + * For MTE, check a single logical or atomic access. This probes a single + * address, the exact one specified. The size and alignment of the access + * is not relevant to MTE, per se, but watchpoints do require the size, + * and we want to recognize those before making any other changes to state. + */ +static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, + bool is_write, bool tag_checked, + int log2_size, bool is_unpriv, + int core_idx) +{ + if (tag_checked && s->mte_active[is_unpriv]) { + TCGv_i32 tcg_desc; + TCGv_i64 ret; + int desc =3D 0; + + desc =3D FIELD_DP32(desc, MTEDESC, MIDX, core_idx); + desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); + desc =3D FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_size); + tcg_desc =3D tcg_const_i32(desc); + + ret =3D new_tmp_a64(s); + gen_helper_mte_check1(ret, cpu_env, tcg_desc, addr); + tcg_temp_free_i32(tcg_desc); + + return ret; + } + return clean_data_tbi(s, addr); +} + +TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, + bool tag_checked, int log2_size) +{ + return gen_mte_check1_mmuidx(s, addr, is_write, tag_checked, log2_size, + false, get_mem_index(s)); +} + typedef struct DisasCompare64 { TCGCond cond; TCGv_i64 value; @@ -2367,7 +2406,7 @@ static void gen_compare_and_swap(DisasContext *s, int= rs, int rt, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = size); tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, size | MO_ALIGN | s->be_data); } @@ -2385,7 +2424,9 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + + /* This is a single atomic access, despite the "pair". */ + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = size + 1); =20 if (size =3D=3D 2) { TCGv_i64 cmp =3D tcg_temp_new_i64(); @@ -2510,7 +2551,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), + true, rn !=3D 31, size); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); return; =20 @@ -2519,7 +2561,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), + false, rn !=3D 31, size); s->is_ldex =3D true; gen_load_exclusive(s, rt, rt2, clean_addr, size, false); if (is_lasr) { @@ -2539,7 +2582,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), + true, rn !=3D 31, size); do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; @@ -2555,7 +2599,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), + false, rn !=3D 31, size); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true,= rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -2569,7 +2614,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), + true, rn !=3D 31, size); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); return; } @@ -2587,7 +2633,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), + false, rn !=3D 31, size); s->is_ldex =3D true; gen_load_exclusive(s, rt, rt2, clean_addr, size, true); if (is_lasr) { @@ -2881,6 +2928,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, bool iss_valid =3D !is_vector; bool post_index; bool writeback; + int memidx; =20 TCGv_i64 clean_addr, dirty_addr; =20 @@ -2938,7 +2986,11 @@ static void disas_ldst_reg_imm9(DisasContext *s, uin= t32_t insn, if (!post_index) { tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); } - clean_addr =3D clean_data_tbi(s, dirty_addr); + + memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); + clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, + writeback || rn !=3D 31, + size, is_unpriv, memidx); =20 if (is_vector) { if (is_store) { @@ -2948,7 +3000,6 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - int memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_ind= ex(s); bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); =20 if (is_store) { @@ -3045,7 +3096,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); =20 tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, size); =20 if (is_vector) { if (is_store) { @@ -3130,7 +3181,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, dirty_addr =3D read_cpu_reg_sp(s, rn, 1); offset =3D imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, siz= e); =20 if (is_vector) { if (is_store) { @@ -3223,7 +3274,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31,= size); =20 if (o3_opc =3D=3D 014) { /* @@ -3300,7 +3351,8 @@ static void disas_ldst_pac(DisasContext *s, uint32_t = insn, tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); =20 /* Note that "clean" and "dirty" here refer to TBI not PAC. */ - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D gen_mte_check1(s, dirty_addr, false, + is_wback || rn !=3D 31, size); =20 tcg_rt =3D cpu_reg(s, rt); do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185980; cv=none; d=zohomail.com; s=zohoarc; b=LnWJfPj3mnKLMbdEahWt3z9CpYC8J5lQxbsiHR7X75mFQjHEPOxIe23+qYKE9KTZEN11ykKccLndZbcl+cw+ZnzRMj2/3RIJd/f9LLIo141NTBmGqqjEWR1kjNPYE6pXH2363iL4voqhXm0Y+77FCHEVlEW3Eu3jU89qjUl62y0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185980; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kqEQTPMX1WDm8juPE7RyO8nKWSk963nCrcoT+M4LVSk=; b=a99eQvKir2qJ8275w77czSCjKhGnmXIkuFp1lcF3YbKr8TzsIIY71ewD6Gsk6rWsxxnWdGKYUYfw1PnszrRUAT+9KF84rh+H4EzJG/pgc+qPn3PmJPV8wvlIc3R/3SUoGAbYyd+CQ9DOrES3zJ9rCTeMZOzAalLIpVS+bOYCymc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185980972525.7292973877659; Fri, 26 Jun 2020 08:39:40 -0700 (PDT) Received: from localhost ([::1]:39406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqS3-0004t6-F4 for importer@patchew.org; Fri, 26 Jun 2020 11:39:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36020) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4Q-00032x-N5 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:15 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:34915) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4M-0006cs-Sv for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:14 -0400 Received: by mail-wm1-x32f.google.com with SMTP id l2so8227649wmf.0 for ; Fri, 26 Jun 2020 08:15:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Replace existing uses of check_data_tbi in translate-a64.c that perform multiple logical memory access. Leave the helper blank for now to reduce the patch size. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-a64.h | 1 + target/arm/translate-a64.h | 2 ++ target/arm/mte_helper.c | 8 +++++ target/arm/translate-a64.c | 71 +++++++++++++++++++++++++++++--------- 4 files changed, 66 insertions(+), 16 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 2faa49d0a33..005af678c77 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -105,6 +105,7 @@ DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env,= i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) =20 DEF_HELPER_FLAGS_3(mte_check1, TCG_CALL_NO_WG, i64, env, i32, i64) +DEF_HELPER_FLAGS_3(mte_checkN, TCG_CALL_NO_WG, i64, env, i32, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index daab6a96665..781c4413999 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -42,6 +42,8 @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned in= t immn, bool sve_access_check(DisasContext *s); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); +TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, + bool tag_checked, int count, int log2_esize); =20 /* We should have at some point before trying to access an FP register * done the necessary access check, so assert that diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index ec12768dfc3..907a12b3664 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -366,3 +366,11 @@ uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t= desc, uint64_t ptr) { return ptr; } + +/* + * Perform an MTE checked access for multiple logical accesses. + */ +uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_t desc, uint64_t ptr) +{ + return ptr; +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4d0453c8956..52be0400d75 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -284,6 +284,34 @@ TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr= , bool is_write, false, get_mem_index(s)); } =20 +/* + * For MTE, check multiple logical sequential accesses. + */ +TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, + bool tag_checked, int log2_esize, int total_size) +{ + if (tag_checked && s->mte_active[0] && total_size !=3D (1 << log2_esiz= e)) { + TCGv_i32 tcg_desc; + TCGv_i64 ret; + int desc =3D 0; + + desc =3D FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); + desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); + desc =3D FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_esize); + desc =3D FIELD_DP32(desc, MTEDESC, TSIZE, total_size); + tcg_desc =3D tcg_const_i32(desc); + + ret =3D new_tmp_a64(s); + gen_helper_mte_checkN(ret, cpu_env, tcg_desc, addr); + tcg_temp_free_i32(tcg_desc); + + return ret; + } + return gen_mte_check1(s, addr, is_write, tag_checked, log2_esize); +} + typedef struct DisasCompare64 { TCGCond cond; TCGv_i64 value; @@ -2848,7 +2876,10 @@ static void disas_ldst_pair(DisasContext *s, uint32_= t insn) } } =20 - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D gen_mte_checkN(s, dirty_addr, !is_load, + (wback || rn !=3D 31) && !set_tag, + size, 2 << size); + if (is_vector) { if (is_load) { do_fp_ld(s, rt, clean_addr, size); @@ -3514,7 +3545,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; MemOp endian =3D s->be_data; =20 - int ebytes; /* bytes per element */ + int total; /* total bytes */ int elements; /* elements per vector */ int rpt; /* num iterations */ int selem; /* structure elements */ @@ -3584,19 +3615,26 @@ static void disas_ldst_multiple_struct(DisasContext= *s, uint32_t insn) endian =3D MO_LE; } =20 - /* Consecutive little-endian elements from a single register + total =3D rpt * selem * (is_q ? 16 : 8); + tcg_rn =3D cpu_reg_sp(s, rn); + + /* + * Issue the MTE check vs the logical repeat count, before we + * promote consecutive little-endian elements below. + */ + clean_addr =3D gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != =3D 31, + size, total); + + /* + * Consecutive little-endian elements from a single register * can be promoted to a larger little-endian operation. */ if (selem =3D=3D 1 && endian =3D=3D MO_LE) { size =3D 3; } - ebytes =3D 1 << size; - elements =3D (is_q ? 16 : 8) / ebytes; - - tcg_rn =3D cpu_reg_sp(s, rn); - clean_addr =3D clean_data_tbi(s, tcg_rn); - tcg_ebytes =3D tcg_const_i64(ebytes); + elements =3D (is_q ? 16 : 8) >> size; =20 + tcg_ebytes =3D tcg_const_i64(1 << size); for (r =3D 0; r < rpt; r++) { int e; for (e =3D 0; e < elements; e++) { @@ -3630,7 +3668,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) =20 if (is_postidx) { if (rm =3D=3D 31) { - tcg_gen_addi_i64(tcg_rn, tcg_rn, rpt * elements * selem * ebyt= es); + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); } else { tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); } @@ -3676,7 +3714,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) int selem =3D (extract32(opc, 0, 1) << 1 | R) + 1; bool replicate =3D false; int index =3D is_q << 3 | S << 2 | size; - int ebytes, xs; + int xs, total; TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; =20 if (extract32(insn, 31, 1)) { @@ -3730,16 +3768,17 @@ static void disas_ldst_single_struct(DisasContext *= s, uint32_t insn) return; } =20 - ebytes =3D 1 << scale; - if (rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 + total =3D selem << scale; tcg_rn =3D cpu_reg_sp(s, rn); - clean_addr =3D clean_data_tbi(s, tcg_rn); - tcg_ebytes =3D tcg_const_i64(ebytes); =20 + clean_addr =3D gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != =3D 31, + scale, total); + + tcg_ebytes =3D tcg_const_i64(1 << scale); for (xs =3D 0; xs < selem; xs++) { if (replicate) { /* Load and replicate to all elements */ @@ -3766,7 +3805,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) =20 if (is_postidx) { if (rm =3D=3D 31) { - tcg_gen_addi_i64(tcg_rn, tcg_rn, selem * ebytes); + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); } else { tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); } --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185593; cv=none; d=zohomail.com; s=zohoarc; b=FygJvvlNM/bbBaaIcA/8uaOlqdCKddk9mdFt3zVptv6oqvhc55Z4LjC1nhdksomWYclPm/SGzAspyKEYLHWOCjgXMHVJsVQ1vYghh/lf6v2/tkNq0CtKrS8pwndAndzmgPFpPdB+aI52EytaRGT6BO1PvMq5ARe5Qk8torThmlw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185593; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DW69FT0TKjdcN1PDGM+IN2DdN9Pu11pDMtHQlg2vqlE=; b=DKgSVnftNhKGMByploTHyY0zLWS2D6jVqoquErLCJO1Gc1hDjbhwJnRpvY5pBiad3Em+f+OzpoiB6Dflh3UbDXLq4J2JDi8CTQXioQPpU77J3XTLhos6GhQIqxh/dQz8+iGnrbkuNQDEPM23DXkBzfkiR2XelzjLyEJSGhSyv8s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185593503178.7245311653677; Fri, 26 Jun 2020 08:33:13 -0700 (PDT) Received: from localhost ([::1]:36714 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqLn-0000Q4-S7 for importer@patchew.org; Fri, 26 Jun 2020 11:33:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36050) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4S-00033Z-DF for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:16 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:39511) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4O-0006d9-Kp for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:16 -0400 Received: by mail-wm1-x32a.google.com with SMTP id t194so9709888wmt.4 for ; Fri, 26 Jun 2020 08:15:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Fill out the stub that was added earlier. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 48 +++++++++++++++ target/arm/mte_helper.c | 132 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 179 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fb92ef6b840..807830cc400 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1318,6 +1318,10 @@ FIELD(MTEDESC, WRITE, 8, 1) FIELD(MTEDESC, ESIZE, 9, 5) FIELD(MTEDESC, TSIZE, 14, 10) /* mte_checkN only */ =20 +bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr); +uint64_t mte_check1(CPUARMState *env, uint32_t desc, + uint64_t ptr, uintptr_t ra); + static inline int allocation_tag_from_addr(uint64_t ptr) { return extract64(ptr, 56, 4); @@ -1328,4 +1332,48 @@ static inline uint64_t address_with_allocation_tag(u= int64_t ptr, int rtag) return deposit64(ptr, 56, 4, rtag); } =20 +/* Return true if tbi bits mean that the access is checked. */ +static inline bool tbi_check(uint32_t desc, int bit55) +{ + return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1; +} + +/* Return true if tcma bits mean that the access is unchecked. */ +static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag) +{ + /* + * We had extracted bit55 and ptr_tag for other reasons, so fold + * (ptr<59:55> =3D=3D 00000 || ptr<59:55> =3D=3D 11111) into a single = test. + */ + bool match =3D ((ptr_tag + bit55) & 0xf) =3D=3D 0; + bool tcma =3D (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1; + return tcma && match; +} + +/* + * For TBI, ideally, we would do nothing. Proper behaviour on fault is + * for the tag to be present in the FAR_ELx register. But for user-only + * mode, we do not have a TLB with which to implement this, so we must + * remove the top byte. + */ +static inline uint64_t useronly_clean_ptr(uint64_t ptr) +{ + /* TBI is known to be enabled. */ +#ifdef CONFIG_USER_ONLY + ptr =3D sextract64(ptr, 0, 56); +#endif + return ptr; +} + +static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t pt= r) +{ +#ifdef CONFIG_USER_ONLY + int64_t clean_ptr =3D sextract64(ptr, 0, 56); + if (tbi_check(desc, clean_ptr < 0)) { + ptr =3D clean_ptr; + } +#endif + return ptr; +} + #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 907a12b3664..c8a5e7c0edd 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -359,12 +359,142 @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t p= tr, uint64_t val) } } =20 +/* Record a tag check failure. */ +static void mte_check_fail(CPUARMState *env, int mmu_idx, + uint64_t dirty_ptr, uintptr_t ra) +{ + ARMMMUIdx arm_mmu_idx =3D core_to_aa64_mmu_idx(mmu_idx); + int el, reg_el, tcf, select; + uint64_t sctlr; + + reg_el =3D regime_el(env, arm_mmu_idx); + sctlr =3D env->cp15.sctlr_el[reg_el]; + + switch (arm_mmu_idx) { + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E20_0: + el =3D 0; + tcf =3D extract64(sctlr, 38, 2); + break; + default: + el =3D reg_el; + tcf =3D extract64(sctlr, 40, 2); + } + + switch (tcf) { + case 1: + /* + * Tag check fail causes a synchronous exception. + * + * In restore_state_to_opc, we set the exception syndrome + * for the load or store operation. Unwind first so we + * may overwrite that with the syndrome for the tag check. + */ + cpu_restore_state(env_cpu(env), ra, true); + env->exception.vaddress =3D dirty_ptr; + raise_exception(env, EXCP_DATA_ABORT, + syn_data_abort_no_iss(el !=3D 0, 0, 0, 0, 0, 0, 0x= 11), + exception_target_el(env)); + /* noreturn, but fall through to the assert anyway */ + + case 0: + /* + * Tag check fail does not affect the PE. + * We eliminate this case by not setting MTE_ACTIVE + * in tb_flags, so that we never make this runtime call. + */ + g_assert_not_reached(); + + case 2: + /* Tag check fail causes asynchronous flag set. */ + mmu_idx =3D arm_mmu_idx_el(env, el); + if (regime_has_2_ranges(mmu_idx)) { + select =3D extract64(dirty_ptr, 55, 1); + } else { + select =3D 0; + } + env->cp15.tfsr_el[el] |=3D 1 << select; + break; + + default: + /* Case 3: Reserved. */ + qemu_log_mask(LOG_GUEST_ERROR, + "Tag check failure with SCTLR_EL%d.TCF%s " + "set to reserved value %d\n", + reg_el, el ? "" : "0", tcf); + break; + } +} + /* * Perform an MTE checked access for a single logical or atomic access. */ +static bool mte_probe1_int(CPUARMState *env, uint32_t desc, uint64_t ptr, + uintptr_t ra, int bit55) +{ + int mem_tag, mmu_idx, ptr_tag, size; + MMUAccessType type; + uint8_t *mem; + + ptr_tag =3D allocation_tag_from_addr(ptr); + + if (tcma_check(desc, bit55, ptr_tag)) { + return true; + } + + mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); + type =3D FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_= LOAD; + size =3D FIELD_EX32(desc, MTEDESC, ESIZE); + + mem =3D allocation_tag_mem(env, mmu_idx, ptr, type, size, + MMU_DATA_LOAD, 1, ra); + if (!mem) { + return true; + } + + mem_tag =3D load_tag1(ptr, mem); + return ptr_tag =3D=3D mem_tag; +} + +/* + * No-fault version of mte_check1, to be used by SVE for MemSingleNF. + * Returns false if the access is Checked and the check failed. This + * is only intended to probe the tag -- the validity of the page must + * be checked beforehand. + */ +bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr) +{ + int bit55 =3D extract64(ptr, 55, 1); + + /* If TBI is disabled, the access is unchecked. */ + if (unlikely(!tbi_check(desc, bit55))) { + return true; + } + + return mte_probe1_int(env, desc, ptr, 0, bit55); +} + +uint64_t mte_check1(CPUARMState *env, uint32_t desc, + uint64_t ptr, uintptr_t ra) +{ + int bit55 =3D extract64(ptr, 55, 1); + + /* If TBI is disabled, the access is unchecked, and ptr is not dirty. = */ + if (unlikely(!tbi_check(desc, bit55))) { + return ptr; + } + + if (unlikely(!mte_probe1_int(env, desc, ptr, ra, bit55))) { + int mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); + mte_check_fail(env, mmu_idx, ptr, ra); + } + + return useronly_clean_ptr(ptr); +} + uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) { - return ptr; + return mte_check1(env, desc, ptr, GETPC()); } =20 /* --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185789; cv=none; d=zohomail.com; s=zohoarc; b=KxhrYZdh9dhP5AxxvGnYM4BrlCGXiKDTsr9TwxKFbQdblUz0UhFx2TfRMSkvVe+aw/LjVbWQnJzl+TXhK12+Ctw+c0oBOjAosISEN8LHGxAuDUG/Em3BmFFXgYgCBGvD3lfnzOLdyuMq+TokQ3NIxQblBudgLllB3mxIFjFmVE8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185789; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1+yw7gLXFotUGKxyde64a0l3p9IplpBYXObf7vT1zi4=; b=lElq57E5SoiGLeL2lcYQfUF7BwgEYAjSs5kMICHUm/igcoDmno92Gn0eSUmoyKNg9bYkjcR8EYUL7IzGY/0g7XvLGf2570qygz37XM6eFSDHHvFbRbjahqe94jqh80nfk/mML8d6xQu+/QY8VXILdJoAaR7wLSM9yraCQJ88j4o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185789443336.47263957595646; Fri, 26 Jun 2020 08:36:29 -0700 (PDT) Received: from localhost ([::1]:50162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqOy-00066d-6m for importer@patchew.org; Fri, 26 Jun 2020 11:36:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36060) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4T-00034p-2H for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:17 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:43493) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4Q-0006dk-CI for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:16 -0400 Received: by mail-wr1-x430.google.com with SMTP id j4so7405633wrp.10 for ; Fri, 26 Jun 2020 08:15:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1+yw7gLXFotUGKxyde64a0l3p9IplpBYXObf7vT1zi4=; b=tKorKVU83T6sHgD7Hh3Bn3J5ucrGIcFELiwZ+k9Ll40i0AtZs61S57T4/lme+F6ciJ GA3+1zKMtgrs4ZLBAlgVdZypxodEUDtEUPGEYRZ47TPFlCUIle1IQq8EKlH9gXrgoB4r /CEJsXzK5zQA9rlDYbiaoTNWw9L4XqPmJRATRQcn6D+Sjv9+X4di6AYKiqw8CkKQSxKU KLIE4PbXYCSMyObb59VS0ltav7jvCO9BA/vaBXcopu6cD/ypeha49fRdnEApM5EMW2aq W2cQ5+bj4r471Did5A4lJ7puwYgslgoGgSjcqmdmztx4BpAy3viH6jeHolqZimsK4Qno Yi4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1+yw7gLXFotUGKxyde64a0l3p9IplpBYXObf7vT1zi4=; b=T0jlw/Eykj9oUFkifZANbtbvvdP4P6vXeCVMKNKhirp211FIedkYOZWsBeqGk4qTTh ttfxaQmNDMBJufewWoVafOo02XZP0LXBKO5EjKLyeE0rU9VoKetABGBVkb2xV/+/4JON E5yUtFm+R9WJmVXI4o7iF/ld7TbLmoLFylrDEMMeaRUrvR4CmTrrH+36LHDB+3/jx5IH q27itPDVOM+tqAaXVTpALkPJ3whHj20j2NzrGlTGilcgDGyNDAiSZVO4+K7PcqD4faWi Mjjm1+r/eIedoi21dLjRrgwSm5p3OMIE4LAoUJVTYsS+DW/cPjFKUqZz0kc/NoKz4qXP J9wQ== X-Gm-Message-State: AOAM533POeIxzjGSDMLTKbdNKfGqKl9hWX+wYDyQnBZQcB2bN/Bk+lk2 ntdg5UtY7K8JWNUD0vLXAvC9ZqEe66pKZQ== X-Google-Smtp-Source: ABdhPJxcJUdKApYurMW05vGnvoGRNQxmBR5dKSkKZ7XtZuiWIqsxrFz1I6L3sRJwNr3+/GuYYNspVA== X-Received: by 2002:adf:de01:: with SMTP id b1mr4162914wrm.305.1593184511540; Fri, 26 Jun 2020 08:15:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/57] target/arm: Implement helper_mte_checkN Date: Fri, 26 Jun 2020 16:14:05 +0100 Message-Id: <20200626151424.30117-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Fill out the stub that was added earlier. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 2 + target/arm/mte_helper.c | 165 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 166 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 807830cc400..c763a23dfba 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1321,6 +1321,8 @@ FIELD(MTEDESC, TSIZE, 14, 10) /* mte_checkN only */ bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr); uint64_t mte_check1(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra); +uint64_t mte_checkN(CPUARMState *env, uint32_t desc, + uint64_t ptr, uintptr_t ra); =20 static inline int allocation_tag_from_addr(uint64_t ptr) { diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index c8a5e7c0edd..abe6af6b795 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -500,7 +500,170 @@ uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_= t desc, uint64_t ptr) /* * Perform an MTE checked access for multiple logical accesses. */ + +/** + * checkN: + * @tag: tag memory to test + * @odd: true to begin testing at tags at odd nibble + * @cmp: the tag to compare against + * @count: number of tags to test + * + * Return the number of successful tests. + * Thus a return value < @count indicates a failure. + * + * A note about sizes: count is expected to be small. + * + * The most common use will be LDP/STP of two integer registers, + * which means 16 bytes of memory touching at most 2 tags, but + * often the access is aligned and thus just 1 tag. + * + * Using AdvSIMD LD/ST (multiple), one can access 64 bytes of memory, + * touching at most 5 tags. SVE LDR/STR (vector) with the default + * vector length is also 64 bytes; the maximum architectural length + * is 256 bytes touching at most 9 tags. + * + * The loop below uses 7 logical operations and 1 memory operation + * per tag pair. An implementation that loads an aligned word and + * uses masking to ignore adjacent tags requires 18 logical operations + * and thus does not begin to pay off until 6 tags. + * Which, according to the survey above, is unlikely to be common. + */ +static int checkN(uint8_t *mem, int odd, int cmp, int count) +{ + int n =3D 0, diff; + + /* Replicate the test tag and compare. */ + cmp *=3D 0x11; + diff =3D *mem++ ^ cmp; + + if (odd) { + goto start_odd; + } + + while (1) { + /* Test even tag. */ + if (unlikely((diff) & 0x0f)) { + break; + } + if (++n =3D=3D count) { + break; + } + + start_odd: + /* Test odd tag. */ + if (unlikely((diff) & 0xf0)) { + break; + } + if (++n =3D=3D count) { + break; + } + + diff =3D *mem++ ^ cmp; + } + return n; +} + +uint64_t mte_checkN(CPUARMState *env, uint32_t desc, + uint64_t ptr, uintptr_t ra) +{ + int mmu_idx, ptr_tag, bit55; + uint64_t ptr_last, ptr_end, prev_page, next_page; + uint64_t tag_first, tag_end; + uint64_t tag_byte_first, tag_byte_end; + uint32_t esize, total, tag_count, tag_size, n, c; + uint8_t *mem1, *mem2; + MMUAccessType type; + + bit55 =3D extract64(ptr, 55, 1); + + /* If TBI is disabled, the access is unchecked, and ptr is not dirty. = */ + if (unlikely(!tbi_check(desc, bit55))) { + return ptr; + } + + ptr_tag =3D allocation_tag_from_addr(ptr); + + if (tcma_check(desc, bit55, ptr_tag)) { + goto done; + } + + mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); + type =3D FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_= LOAD; + esize =3D FIELD_EX32(desc, MTEDESC, ESIZE); + total =3D FIELD_EX32(desc, MTEDESC, TSIZE); + + /* Find the addr of the end of the access, and of the last element. */ + ptr_end =3D ptr + total; + ptr_last =3D ptr_end - esize; + + /* Round the bounds to the tag granule, and compute the number of tags= . */ + tag_first =3D QEMU_ALIGN_DOWN(ptr, TAG_GRANULE); + tag_end =3D QEMU_ALIGN_UP(ptr_last, TAG_GRANULE); + tag_count =3D (tag_end - tag_first) / TAG_GRANULE; + + /* Round the bounds to twice the tag granule, and compute the bytes. */ + tag_byte_first =3D QEMU_ALIGN_DOWN(ptr, 2 * TAG_GRANULE); + tag_byte_end =3D QEMU_ALIGN_UP(ptr_last, 2 * TAG_GRANULE); + + /* Locate the page boundaries. */ + prev_page =3D ptr & TARGET_PAGE_MASK; + next_page =3D prev_page + TARGET_PAGE_SIZE; + + if (likely(tag_end - prev_page <=3D TARGET_PAGE_SIZE)) { + /* Memory access stays on one page. */ + tag_size =3D (tag_byte_end - tag_byte_first) / (2 * TAG_GRANULE); + mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, type, total, + MMU_DATA_LOAD, tag_size, ra); + if (!mem1) { + goto done; + } + /* Perform all of the comparisons. */ + n =3D checkN(mem1, ptr & TAG_GRANULE, ptr_tag, tag_count); + } else { + /* Memory access crosses to next page. */ + tag_size =3D (next_page - tag_byte_first) / (2 * TAG_GRANULE); + mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, type, next_page - p= tr, + MMU_DATA_LOAD, tag_size, ra); + + tag_size =3D (tag_byte_end - next_page) / (2 * TAG_GRANULE); + mem2 =3D allocation_tag_mem(env, mmu_idx, next_page, type, + ptr_end - next_page, + MMU_DATA_LOAD, tag_size, ra); + + /* + * Perform all of the comparisons. + * Note the possible but unlikely case of the operation spanning + * two pages that do not both have tagging enabled. + */ + n =3D c =3D (next_page - tag_first) / TAG_GRANULE; + if (mem1) { + n =3D checkN(mem1, ptr & TAG_GRANULE, ptr_tag, c); + } + if (n =3D=3D c) { + if (!mem2) { + goto done; + } + n +=3D checkN(mem2, 0, ptr_tag, tag_count - c); + } + } + + /* + * If we failed, we know which granule. Compute the element that + * is first in that granule, and signal failure on that element. + */ + if (unlikely(n < tag_count)) { + uint64_t fail_ofs; + + fail_ofs =3D tag_first + n * TAG_GRANULE - ptr; + fail_ofs =3D ROUND_UP(fail_ofs, esize); + mte_check_fail(env, mmu_idx, ptr + fail_ofs, ra); + } + + done: + return useronly_clean_ptr(ptr); +} + uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_t desc, uint64_t ptr) { - return ptr; + return mte_checkN(env, desc, ptr, GETPC()); } --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185612; cv=none; d=zohomail.com; s=zohoarc; b=lio9H9oAfO8f9FQiSva3jQZ5QwbxLMQjNEcUrOOCLi+AR3t+9OHgVnazeGSt+1yssc/HwCciosawsFpiJTp28ijH3MHyGUo4MAVytlDpowDoL93O9YV6hYSLWRtVVMTdVydPk4hkLBkvs4KfNFnIxXW1Jtg1JDIZwFjzRDCFBE0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185612; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pMVJnmZK4yJTlpuUPHr9ORI4dS+//9tAbhfR111TvGw=; b=Fil34REStHhR72Vx7Tyo9ZyWEi8xXhZvsAnCz7mqndnEJVfvjCPflGxlPldeCtI85RIjnVd4ce7F3D0c7Oidy12fHt2nR3nHFrwvxD7Zgd5CBHPRtSY9hW4z6LHVt9ddi0x8KLLs1oFTl6kPAmuaTiAd3hS1GeXYIVVBkgxMwjk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185612455614.1276977472409; Fri, 26 Jun 2020 08:33:32 -0700 (PDT) Received: from localhost ([::1]:38452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqM7-00019Q-2x for importer@patchew.org; Fri, 26 Jun 2020 11:33:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36070) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4T-00035b-FW for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:18 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:34308) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4Q-0006dr-Cs for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:17 -0400 Received: by mail-wr1-x42a.google.com with SMTP id f7so6867859wrw.1 for ; Fri, 26 Jun 2020 08:15:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pMVJnmZK4yJTlpuUPHr9ORI4dS+//9tAbhfR111TvGw=; b=H163vCbQTuW3DqRQPTkaZ7F9/RxznEXfYt1Av5D45qJGpI2lBNsdZSHYDsDzs9asjc J2qi70HpRHX1EimiV4q2LeyWPiVMjx8SMw6z0yEq5Dueoq+X5VEShH3Nsyqgo1IuaEj6 HS+HGZbGLjYGa1d0Q1Y5sCkk5GBwlcjUfEyEMSVuset9ofv2YricnA51YTf6wO4vnr29 fYuL4vhmYvppQWpZcQ6KBJb/bWRqRZHFAz42zf+KsyUf3MU76ZJjwZXCQrcgW+IiApOl Ym+48rqDAPJj2rMXy4zYPj8Fm92xcVtWXK/3l6KwrshtkdgUQH5sPiOFDBVarX3GmG9A KdKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pMVJnmZK4yJTlpuUPHr9ORI4dS+//9tAbhfR111TvGw=; b=dnspIJmG6C3eWRSZS7jBK1thg9MNREzcCmcZdwjzcc6WU7Oe3K+BoBex4L+2TxrNBa 5gOn+41uU45i+LAkioRA/uaPk6Sf+XQ/jlALdL7mbpQB+ojg2UcR5coCVhCL5VTtxLr4 R9TlgUFr12mKfMEz8/HpFzvhlMZab8OTA6Q1wrO4knoIZymVg+qaBUGEF9LEYrwNcAAM qzUVtUucWX+eFWEVjhCuExBq/RU7Lfdk/S16xZN5SkNmS2O26n82iu2T2rlwyyYtBJTW j8V7/at1kZ5a3GCeFtARYUWp27qWFtBRCZ8WOSv2Bvot+fKxZQA9bxeHPvA3e1QKxMx1 R57w== X-Gm-Message-State: AOAM532mTQYZ12Nn9oUXykBuKNBB0U72G+RUEp5o8yEBzc/1PMFWH865 MoHdHErt+kB2ms5ji9Gcy7d5CJNqYtsWYA== X-Google-Smtp-Source: ABdhPJyoZ4l/M0NTgOdbovRA1Ds05uq6bQ3ybK5Idg1K5ejD0qp2+HBGMY7qQ+ArIT1ibguOQO9+5g== X-Received: by 2002:adf:aad8:: with SMTP id i24mr4276983wrc.102.1593184512621; Fri, 26 Jun 2020 08:15:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/57] target/arm: Add helper_mte_check_zva Date: Fri, 26 Jun 2020 16:14:06 +0100 Message-Id: <20200626151424.30117-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use a special helper for DC_ZVA, rather than the more general mte_checkN. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 106 +++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 16 +++++- 3 files changed, 122 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 005af678c77..5b0b699a50a 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -106,6 +106,7 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env,= i64) =20 DEF_HELPER_FLAGS_3(mte_check1, TCG_CALL_NO_WG, i64, env, i32, i64) DEF_HELPER_FLAGS_3(mte_checkN, TCG_CALL_NO_WG, i64, env, i32, i64) +DEF_HELPER_FLAGS_3(mte_check_zva, TCG_CALL_NO_WG, i64, env, i32, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index abe6af6b795..4f9bd3add3d 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -667,3 +667,109 @@ uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_= t desc, uint64_t ptr) { return mte_checkN(env, desc, ptr, GETPC()); } + +/* + * Perform an MTE checked access for DC_ZVA. + */ +uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32_t desc, uint64_t p= tr) +{ + uintptr_t ra =3D GETPC(); + int log2_dcz_bytes, log2_tag_bytes; + int mmu_idx, bit55; + intptr_t dcz_bytes, tag_bytes, i; + void *mem; + uint64_t ptr_tag, mem_tag, align_ptr; + + bit55 =3D extract64(ptr, 55, 1); + + /* If TBI is disabled, the access is unchecked, and ptr is not dirty. = */ + if (unlikely(!tbi_check(desc, bit55))) { + return ptr; + } + + ptr_tag =3D allocation_tag_from_addr(ptr); + + if (tcma_check(desc, bit55, ptr_tag)) { + goto done; + } + + /* + * In arm_cpu_realizefn, we asserted that dcz > LOG2_TAG_GRANULE+1, + * i.e. 32 bytes, which is an unreasonably small dcz anyway, to make + * sure that we can access one complete tag byte here. + */ + log2_dcz_bytes =3D env_archcpu(env)->dcz_blocksize + 2; + log2_tag_bytes =3D log2_dcz_bytes - (LOG2_TAG_GRANULE + 1); + dcz_bytes =3D (intptr_t)1 << log2_dcz_bytes; + tag_bytes =3D (intptr_t)1 << log2_tag_bytes; + align_ptr =3D ptr & -dcz_bytes; + + /* + * Trap if accessing an invalid page. DC_ZVA requires that we supply + * the original pointer for an invalid page. But watchpoints require + * that we probe the actual space. So do both. + */ + mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); + (void) probe_write(env, ptr, 1, mmu_idx, ra); + mem =3D allocation_tag_mem(env, mmu_idx, align_ptr, MMU_DATA_STORE, + dcz_bytes, MMU_DATA_LOAD, tag_bytes, ra); + if (!mem) { + goto done; + } + + /* + * Unlike the reasoning for checkN, DC_ZVA is always aligned, and thus + * it is quite easy to perform all of the comparisons at once without + * any extra masking. + * + * The most common zva block size is 64; some of the thunderx cpus use + * a block size of 128. For user-only, aarch64_max_initfn will set the + * block size to 512. Fill out the other cases for future-proofing. + * + * In order to be able to find the first miscompare later, we want the + * tag bytes to be in little-endian order. + */ + switch (log2_tag_bytes) { + case 0: /* zva_blocksize 32 */ + mem_tag =3D *(uint8_t *)mem; + ptr_tag *=3D 0x11u; + break; + case 1: /* zva_blocksize 64 */ + mem_tag =3D cpu_to_le16(*(uint16_t *)mem); + ptr_tag *=3D 0x1111u; + break; + case 2: /* zva_blocksize 128 */ + mem_tag =3D cpu_to_le32(*(uint32_t *)mem); + ptr_tag *=3D 0x11111111u; + break; + case 3: /* zva_blocksize 256 */ + mem_tag =3D cpu_to_le64(*(uint64_t *)mem); + ptr_tag *=3D 0x1111111111111111ull; + break; + + default: /* zva_blocksize 512, 1024, 2048 */ + ptr_tag *=3D 0x1111111111111111ull; + i =3D 0; + do { + mem_tag =3D cpu_to_le64(*(uint64_t *)(mem + i)); + if (unlikely(mem_tag !=3D ptr_tag)) { + goto fail; + } + i +=3D 8; + align_ptr +=3D 16 * TAG_GRANULE; + } while (i < tag_bytes); + goto done; + } + + if (likely(mem_tag =3D=3D ptr_tag)) { + goto done; + } + + fail: + /* Locate the first nibble that differs. */ + i =3D ctz64(mem_tag ^ ptr_tag) >> 4; + mte_check_fail(env, mmu_idx, align_ptr + i * TAG_GRANULE, ra); + + done: + return useronly_clean_ptr(ptr); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 52be0400d75..a2a82800102 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1857,7 +1857,21 @@ static void handle_sys(DisasContext *s, uint32_t ins= n, bool isread, return; case ARM_CP_DC_ZVA: /* Writes clear the aligned block of memory which rt points into. = */ - tcg_rt =3D clean_data_tbi(s, cpu_reg(s, rt)); + if (s->mte_active[0]) { + TCGv_i32 t_desc; + int desc =3D 0; + + desc =3D FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); + desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + t_desc =3D tcg_const_i32(desc); + + tcg_rt =3D new_tmp_a64(s); + gen_helper_mte_check_zva(tcg_rt, cpu_env, t_desc, cpu_reg(s, r= t)); + tcg_temp_free_i32(t_desc); + } else { + tcg_rt =3D clean_data_tbi(s, cpu_reg(s, rt)); + } gen_helper_dc_zva(cpu_env, tcg_rt); return; default: --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593186127; cv=none; d=zohomail.com; s=zohoarc; b=lpXW291A9dIF0oM2J1eBD/79FAiXM+ZECppf7aoER4bq3FRGyu7O0nHDAE4bTUKM/0hp+nMfV3HJW8gmSkC0qYIw6jzdPTit90tRUzchfEEeBr3S3TU0XLW9Btv/37RRtdTkAuf8cxYyCup7MmOC64IPZ0Dn0SSXdOVdihtlcWE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593186127; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=U8ufgvqYK3hpRYE+4k7AYm9MeUEmx7S8bSgnZErBoqM=; b=FoTeFEJtEeXX8RQrCJB8yyQ18wkR8K2J2KZGOVC1tzQ+o4jvb10cJmUB63FfD1E4ClyuR1QOF1+0cv9wzwiGoLH1OiMPnnMTNdlmYXmS6voRkcjTJ8Gy9TLEGAJPLsGMqdfLhrF4v1JfOxN4o3GnFwn0b+hYbBDAQ4rZsWAR4Qw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159318612740872.73634709998043; Fri, 26 Jun 2020 08:42:07 -0700 (PDT) Received: from localhost ([::1]:47758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqUQ-00009V-6Z for importer@patchew.org; Fri, 26 Jun 2020 11:42:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36090) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4U-00035i-F6 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:18 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:42026) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4S-0006e7-2P for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:18 -0400 Received: by mail-wr1-x443.google.com with SMTP id o11so9850422wrv.9 for ; Fri, 26 Jun 2020 08:15:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=U8ufgvqYK3hpRYE+4k7AYm9MeUEmx7S8bSgnZErBoqM=; b=hKWu5Ci7gMmoPRowGDelLy+TaMhDgiRlZDIfA//8f87Nqk9SWXp847zZYPOgB4C6bS 1ATjY8w9o7jSXa2P5KwxRTQNjAYjinSu/+5jmYYTGQSw7GRioFkAjP9BucQoQ1WBg9II ZDZuoVl2ktMq91wTpnlBcuLR236Vs21ziqHoSOWLLxVDNqaFjaJkSmpSBkzUNN0jpjMV XnDU/HsOCem0LgiP66xL7pEmL3eHeU70T0X+9sqhmaF4aU02nVQJqO+ejpMdEerly0gj AksyZXR1bgGuY+QNIR/MwjDZe9DcquuBKRDwgTJ0iMRmGLyKrlLkHr99ZHEhEcaiQOUz dBTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U8ufgvqYK3hpRYE+4k7AYm9MeUEmx7S8bSgnZErBoqM=; b=eIk25b5mVxVeeevyzxkxJGXiVBDZqBB7a7uS4vAdDFXVo5BBnHknBxQTAd8c66VFoZ ERa1yCWLa+yBw9scLhx93t2PO/ncAQGZpE0yq7pYugL2+ldNqKW8CIAj+30eDSikDZ77 bfu3PQLs6HWGBuLbVfkAuseBhs2flofOGmX04rSVjryExhiFBTiX/0mkzOvE6o1U8/Am giOwFidsFfO9zSlYutIPX/NbYClQ1z60NVhBeFiISLxCuD8Nv8CGGUua4LFmc0BcGdWR BHPjn+aQIljkGBy+WVjtE98kvJw4+8IgxITEVshnaaS7P25WgbfCG2FNlTY/AvNOq8nh TD8A== X-Gm-Message-State: AOAM533u1uNmL5nXG2WzLTbsZCSVIXb8pRROwR0KiK3hufyxPIgyz4mb K9x5XQAXFTnDsN+pk0zUhXd6Wqen9/E4lA== X-Google-Smtp-Source: ABdhPJyiOnmOObK63ekVL7Duruni++2EWE+P/tIgH73CcqPpv0DVGMJ0jAsglDLrmM1gDFKQ3RQPMg== X-Received: by 2002:a5d:6a04:: with SMTP id m4mr4218476wru.418.1593184513698; Fri, 26 Jun 2020 08:15:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/57] target/arm: Use mte_checkN for sve unpredicated loads Date: Fri, 26 Jun 2020 16:14:07 +0100 Message-Id: <20200626151424.30117-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 61 +++++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 28 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index ac7b3119e5f..11e0dfc2100 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4342,71 +4342,76 @@ static void do_ldr(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) int len_remain =3D len % 8; int nparts =3D len / 8 + ctpop8(len_remain); int midx =3D get_mem_index(s); - TCGv_i64 addr, t0, t1; + TCGv_i64 dirty_addr, clean_addr, t0, t1; =20 - addr =3D tcg_temp_new_i64(); - t0 =3D tcg_temp_new_i64(); + dirty_addr =3D tcg_temp_new_i64(); + tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); + clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len, M= O_8); + tcg_temp_free_i64(dirty_addr); =20 - /* Note that unpredicated load/store of vector/predicate registers + /* + * Note that unpredicated load/store of vector/predicate registers * are defined as a stream of bytes, which equates to little-endian - * operations on larger quantities. There is no nice way to force - * a little-endian load for aarch64_be-linux-user out of line. - * + * operations on larger quantities. * Attempt to keep code expansion to a minimum by limiting the * amount of unrolling done. */ if (nparts <=3D 4) { int i; =20 + t0 =3D tcg_temp_new_i64(); for (i =3D 0; i < len_align; i +=3D 8) { - tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + i); - tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEQ); + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ); tcg_gen_st_i64(t0, cpu_env, vofs + i); + tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8); } + tcg_temp_free_i64(t0); } else { TCGLabel *loop =3D gen_new_label(); TCGv_ptr tp, i =3D tcg_const_local_ptr(0); =20 + /* Copy the clean address into a local temp, live across the loop.= */ + t0 =3D clean_addr; + clean_addr =3D tcg_temp_local_new_i64(); + tcg_gen_mov_i64(clean_addr, t0); + tcg_temp_free_i64(t0); + gen_set_label(loop); =20 - /* Minimize the number of local temps that must be re-read from - * the stack each iteration. Instead, re-compute values other - * than the loop counter. - */ + t0 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ); + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + tp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tp, i, imm); - tcg_gen_extu_ptr_i64(addr, tp); - tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, rn)); - - tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEQ); - tcg_gen_add_ptr(tp, cpu_env, i); tcg_gen_addi_ptr(i, i, 8); tcg_gen_st_i64(t0, tp, vofs); tcg_temp_free_ptr(tp); + tcg_temp_free_i64(t0); =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); } =20 - /* Predicate register loads can be any multiple of 2. + /* + * Predicate register loads can be any multiple of 2. * Note that we still store the entire 64-bit unit into cpu_env. */ if (len_remain) { - tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + len_align); - + t0 =3D tcg_temp_new_i64(); switch (len_remain) { case 2: case 4: case 8: - tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LE | ctz32(len_remain)); + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, + MO_LE | ctz32(len_remain)); break; =20 case 6: t1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEUL); - tcg_gen_addi_i64(addr, addr, 4); - tcg_gen_qemu_ld_i64(t1, addr, midx, MO_LEUW); + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUL); + tcg_gen_addi_i64(clean_addr, clean_addr, 4); + tcg_gen_qemu_ld_i64(t1, clean_addr, midx, MO_LEUW); tcg_gen_deposit_i64(t0, t0, t1, 32, 32); tcg_temp_free_i64(t1); break; @@ -4415,9 +4420,9 @@ static void do_ldr(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) g_assert_not_reached(); } tcg_gen_st_i64(t0, cpu_env, vofs + len_align); + tcg_temp_free_i64(t0); } - tcg_temp_free_i64(addr); - tcg_temp_free_i64(t0); + tcg_temp_free_i64(clean_addr); } =20 /* Similarly for stores. */ --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185755; cv=none; d=zohomail.com; s=zohoarc; b=gzb1RvDjvkbsWvYIAn3o2c095KczYpkFjNkurXDFX06B/4io/3j1RlEcp8e89be0mplDJE8BvkijOkmc8WHPs/Cw5LeuEvjwcc5qd/VmeJcQn/Y+7AkbSKEL9rAzJkOTNs4G+FWkibjE2k4K03PdXtwyvxsIRFW6AZlkl1346vk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185755; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IZ1By0aBWZl6mdMkdU84BXCqvgEwyk0TS8TpL6POa6w=; b=e1cvWWfIJ9BieraS0A2/fGc0FvASsMxpb6xYQZnfqkrH7eZpjRGye3KykcY+lTe2FTfPRy5xT1bt3y9T2lZzPgs1ODEhpwwiBJOgcl2toSJVrrtiJolte2mD3cDE+7lN3CCGQanF2DP8HrFnY32ZKJT5Ql3F71lYZY54k4HYVD8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185755275551.0687553393404; Fri, 26 Jun 2020 08:35:55 -0700 (PDT) Received: from localhost ([::1]:46718 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqOP-0004bd-8J for importer@patchew.org; Fri, 26 Jun 2020 11:35:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4X-00037b-CI for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:21 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:34848) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4S-0006eN-L4 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:21 -0400 Received: by mail-wr1-x432.google.com with SMTP id g18so9902872wrm.2 for ; Fri, 26 Jun 2020 08:15:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=IZ1By0aBWZl6mdMkdU84BXCqvgEwyk0TS8TpL6POa6w=; b=qeEqBQEaXQBJ2uZjZ1xPkSsqE/CVTnYaX8o7FpaRzPxLacqSwKV53LTa2pi2Uzu3RD jwalYsgLz8uS5tdaCcGNdhopvtyQvbtNJ7H6bz1/OEz9XoswKOujmfTJAJK5ErR1FUCM AHZgg8/jP2oz4M5nAdIfpGM579HC5QBQg8dIBpNaaVNv1WGowckfRQcZVTHxESlDYHY1 4U34fyNTbU62tGOT7/OJwd//ZUSROawCnTVF/EX8k0LpGHJqe/Iz/LBmI6/WMT/eR13l s9Nt3i1TxdDp68jP5uTOzLJPtC7GhmyYP1wFLGmuNYrcdEfOIV5V5+XOHIZVlHV8alUU cweA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IZ1By0aBWZl6mdMkdU84BXCqvgEwyk0TS8TpL6POa6w=; b=izpezek9lMDW1Uz4ra4QWUXQtqF6dY0GHK40oXbb4TeDcjw7PRd4TinxBMoZgdzZa1 Pq3M/SzNO7wNigj5BGc8vK3Q3rXug6V/B5tqxe4f5mFif1V5ZuXKfdCHIXpNixCHVcG/ 7Fw8APtk+7tVGnAlWLQ0wD/1fWByx95fzivyJxUnmfoYJzRvi6uHKVf5KbdPvUj8MCRi u0ouensEyuejDWVsaVav2vx5yk9tH6rMUO3BIq+i1jztT637gvLARO9+dv9vd9LLF8b6 CuWMc9/ApJKd7WWQdBpx/tTWkFR4X9CeEDnH+cZVUIWGyj8xWDI4jnquP73qXPhLS98h mYqg== X-Gm-Message-State: AOAM532P1IoDEa9s2J9NvHnFbPbAjxLFNWxdxHclG9KI920mLYaVDSXP oRuVWN8bt2m5nDIVpNmvqz9bDp+ZrLpJnw== X-Google-Smtp-Source: ABdhPJwjilBQ4+F4fbEB31VUQN6nXi4M+jq8PjqmdyaXQSrkjHqg3WDObPt//GYuikDrDnw1grfQTg== X-Received: by 2002:a5d:4687:: with SMTP id u7mr4493321wrq.357.1593184514848; Fri, 26 Jun 2020 08:15:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/57] target/arm: Use mte_checkN for sve unpredicated stores Date: Fri, 26 Jun 2020 16:14:08 +0100 Message-Id: <20200626151424.30117-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 61 +++++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 28 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 11e0dfc2100..4a613ca6892 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4432,10 +4432,12 @@ static void do_str(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) int len_remain =3D len % 8; int nparts =3D len / 8 + ctpop8(len_remain); int midx =3D get_mem_index(s); - TCGv_i64 addr, t0; + TCGv_i64 dirty_addr, clean_addr, t0; =20 - addr =3D tcg_temp_new_i64(); - t0 =3D tcg_temp_new_i64(); + dirty_addr =3D tcg_temp_new_i64(); + tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); + clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len, M= O_8); + tcg_temp_free_i64(dirty_addr); =20 /* Note that unpredicated load/store of vector/predicate registers * are defined as a stream of bytes, which equates to little-endian @@ -4448,33 +4450,35 @@ static void do_str(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) if (nparts <=3D 4) { int i; =20 + t0 =3D tcg_temp_new_i64(); for (i =3D 0; i < len_align; i +=3D 8) { tcg_gen_ld_i64(t0, cpu_env, vofs + i); - tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + i); - tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEQ); + tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEQ); + tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8); } + tcg_temp_free_i64(t0); } else { TCGLabel *loop =3D gen_new_label(); - TCGv_ptr t2, i =3D tcg_const_local_ptr(0); + TCGv_ptr tp, i =3D tcg_const_local_ptr(0); + + /* Copy the clean address into a local temp, live across the loop.= */ + t0 =3D clean_addr; + clean_addr =3D tcg_temp_local_new_i64(); + tcg_gen_mov_i64(clean_addr, t0); + tcg_temp_free_i64(t0); =20 gen_set_label(loop); =20 - t2 =3D tcg_temp_new_ptr(); - tcg_gen_add_ptr(t2, cpu_env, i); - tcg_gen_ld_i64(t0, t2, vofs); - - /* Minimize the number of local temps that must be re-read from - * the stack each iteration. Instead, re-compute values other - * than the loop counter. - */ - tcg_gen_addi_ptr(t2, i, imm); - tcg_gen_extu_ptr_i64(addr, t2); - tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, rn)); - tcg_temp_free_ptr(t2); - - tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEQ); - + t0 =3D tcg_temp_new_i64(); + tp =3D tcg_temp_new_ptr(); + tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_ld_i64(t0, tp, vofs); tcg_gen_addi_ptr(i, i, 8); + tcg_temp_free_ptr(tp); + + tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEQ); + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + tcg_temp_free_i64(t0); =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); @@ -4482,29 +4486,30 @@ static void do_str(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) =20 /* Predicate register stores can be any multiple of 2. */ if (len_remain) { + t0 =3D tcg_temp_new_i64(); tcg_gen_ld_i64(t0, cpu_env, vofs + len_align); - tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + len_align); =20 switch (len_remain) { case 2: case 4: case 8: - tcg_gen_qemu_st_i64(t0, addr, midx, MO_LE | ctz32(len_remain)); + tcg_gen_qemu_st_i64(t0, clean_addr, midx, + MO_LE | ctz32(len_remain)); break; =20 case 6: - tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEUL); - tcg_gen_addi_i64(addr, addr, 4); + tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUL); + tcg_gen_addi_i64(clean_addr, clean_addr, 4); tcg_gen_shri_i64(t0, t0, 32); - tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEUW); + tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUW); break; =20 default: g_assert_not_reached(); } + tcg_temp_free_i64(t0); } - tcg_temp_free_i64(addr); - tcg_temp_free_i64(t0); + tcg_temp_free_i64(clean_addr); } =20 static bool trans_LDR_zri(DisasContext *s, arg_rri *a) --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185880; cv=none; d=zohomail.com; s=zohoarc; b=VovJhZDAD6xpQGXx+2UBo1O+h2xClD5o612XJUrgP96egQTrYYCih/UzK2C4rQlveuEFDtkG+rutkrVWCrbu5T+z4l14EO/mf5nTWUh7roUEreEnA4k6/DELMCxv2THTsHZZ7X6jRR8Rcf8xHTnHr48slAzDDpx3TNSlqDsG9wY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185880; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cRLle7QXbXZMLIYjz446cs4YjOdvOo9M3dbhN/BEdfk=; b=W6/XK5qVRP7C9DYWLUbBz0/Jmr3gTpzY7TRc7G8THNDEoTGetcjNoCINywChjLQa3Ux1cmvR85FxGGYbSaApsy9ye6hH++mkOduRS8v4hu0uCKCDVwW2liAbHYWopjpeRTIASXBK6hh0tpvDDhzC1noDfWFy+5efzTI89lOATaQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185880124532.732491378584; Fri, 26 Jun 2020 08:38:00 -0700 (PDT) Received: from localhost ([::1]:58472 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqQQ-00014I-SU for importer@patchew.org; Fri, 26 Jun 2020 11:37:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36104) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4V-00036p-Gk for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:21 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:39870) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4U-0006eY-06 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:19 -0400 Received: by mail-wr1-x442.google.com with SMTP id q5so9851234wru.6 for ; Fri, 26 Jun 2020 08:15:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cRLle7QXbXZMLIYjz446cs4YjOdvOo9M3dbhN/BEdfk=; b=pP7FzMupdSLPzn0fYRHFicdfG5GQGFo7PselHzcYNAAueM7GhFqjUpDpuafy001MwJ X1QluxFo5pGLwd8HNRJa5WZJJgC/jVPLYAGPxA01XpVHAh4OkbfUvJlO2R5a+8nGB1Bk vaxoIkxEYeBYdTwu/Lau+31hgGDnX5TNzrCn80FnLnDmH+zPonCe08qEE93lLPvOp/Qf HZChrfgbULq3qZsZQWlY66h83k0sigB314Vd2NV5vK8hFVunXvXDgIXf23oD8fjRDEyq 9LKHjLFw67RSjO24LaKiBn3/gwqYwewUFmbIHU4sDtXxuot824QDTv3qRGebvvWmq4NE bX9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cRLle7QXbXZMLIYjz446cs4YjOdvOo9M3dbhN/BEdfk=; b=S8E8IcFZC+8oHux4Jq4q10shDY/WlsRcOKv1HjsvMCOn8BJ9pCjTJVXAGartXzgc97 qOEr5zmAKtQnclx7cJMHprnrYk2ocmf9Y5g/D5bWLRaCXYs/oawfe6rkFYKHRz7kHK1Z Z3/aL/qq5qGti6w1bnik5KTcurdcE4fqtZ7JifEjFDGpNbsShdM6eOIYUscW5O+OUiVa H+KjG12lnk2Nnu77xMJptRDcFIVhiwo8D6e+y98rfqwilE3NPw9Rc7N2zTcdRUbliLWw 63bcvGmKwkyqyp4TTfO7yg/cgGJq7k6tnqgtvkPILic3kX7kRjP9fqhLqTXkLmMEKPMk 1gDQ== X-Gm-Message-State: AOAM533Hjgshva1qoAcfRIElGgJRGCc8x5gorkvX4LwpiSppQaQujoO9 13P41P0gevnebXAKBFBxbpCXnSKOCWl/Nw== X-Google-Smtp-Source: ABdhPJzW5JOSVkFxtPvFyxdgY7Ek5BuSIFAI20qsXqLoQfF+leGtAHVVN2kx0FKXIPy8yuMVWI/SKw== X-Received: by 2002:adf:fe0b:: with SMTP id n11mr4246827wrr.245.1593184515866; Fri, 26 Jun 2020 08:15:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/57] target/arm: Use mte_check1 for sve LD1R Date: Fri, 26 Jun 2020 16:14:09 +0100 Message-Id: <20200626151424.30117-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. 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X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 4a613ca6892..4fa521989de 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4892,7 +4892,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri= _load *a) unsigned esz =3D dtype_esz[a->dtype]; unsigned msz =3D dtype_msz(a->dtype); TCGLabel *over =3D gen_new_label(); - TCGv_i64 temp; + TCGv_i64 temp, clean_addr; =20 /* If the guarding predicate has no bits set, no load occurs. */ if (psz <=3D 8) { @@ -4915,7 +4915,9 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri= _load *a) /* Load the data. */ temp =3D tcg_temp_new_i64(); tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz); - tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s), + clean_addr =3D gen_mte_check1(s, temp, false, true, msz); + + tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), s->be_data | dtype_mop[a->dtype]); =20 /* Broadcast to *all* elements. */ --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185969; cv=none; d=zohomail.com; s=zohoarc; b=YkcGo37ftOM8mKHGgr/B9z0fLR/ISrxg6GxFXjmBiMMBnjFkLhJEBssfj6YhTjeV0H7mqo7wy3BXl+qYTmiDmi6rl1WWX5cGLJba7I1X6tsyhp0NzECDR1YyhEoD8ZzD571s02ORotaldpUkYRiGWIFgc+o6iXq5h5LLIWy+aFw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185969; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bILgS802kOP5gR7fj6y5gd5HeqbKcxvhIhwFysJcVM8=; b=KicxDSe5cxc0kennMcRXn8ffEzl08Hx52/rjcI4MqjUKIMttkxD3J0o8ENtl7aKPd0ntnSTb5xoyUsKJZrVa0Vykpkqzwh+prMl6g29JOle9cpoJNwGSc/RggoinfYIOaK4ndDiNiFuZ2MuRenAR1/bZN9mZukPeLrfGWAvh7iU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159318596982592.420808335566; Fri, 26 Jun 2020 08:39:29 -0700 (PDT) Received: from localhost ([::1]:38340 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqRs-0004RK-Hj for importer@patchew.org; Fri, 26 Jun 2020 11:39:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36128) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4Y-00037z-0w for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:22 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:38619) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4V-0006fL-1F for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:21 -0400 Received: by mail-wr1-x432.google.com with SMTP id z13so9869972wrw.5 for ; Fri, 26 Jun 2020 08:15:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bILgS802kOP5gR7fj6y5gd5HeqbKcxvhIhwFysJcVM8=; b=ikc5jYjQ856AR7oU5l2lo7qkhL6Lc7bpeAg9nDivQwnfosozM7k6Mx9I4AGgQmQ7tT lqYEth884Iw8y0c63t62p9OXgOESc0qXCCSRyOQ+UMPT/DAA6YopSzu/AlUuc52Fq1Ea ogtEol7VGp+sHAVsVejuWEDmwfrB/SvJ9jKVMd5yeLZEjweqClFoRDOaFyDWlU6RhxkD 65zjEEtulgaTS9ivpCmeHourc3PkENWyE3mYSEqM/8PNdhgLyetIVwfn+Efp1XFRHvWl yLfs9PHC75+JyLtPOMDRitHptRM/0emewHXOTRtpieZl8Ay/QrR1BjVMD0rGNtygt4Wj 3ZKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bILgS802kOP5gR7fj6y5gd5HeqbKcxvhIhwFysJcVM8=; b=NX+e3+rk2b3tjTpGg3ScXB7g8xAGDiFk5v3mmPR9+J8PG6r1aIXOnaTtu4AfwEHK2r K2xusyG/uMbIS/202/pnc7MifKwUHmeeGl61Rnpwz/voI5CPGssc5zlzZraSai/rWhFC eCWv7mSOXeIdegIzLqDvaSU81jEsOOUJw5LCK3f93jSsv88/33rpnSdV6yI91Gu1598T N3IawwuhZvaDdqkT1J58Us1MLb3y/kggPCmVWj+cxmpgt0oQp3ai5bdMV9HPfRNHZtUA YgsfSZoz8Ow8W+KwKvAOCaoHICHvDcLeqsg6xj1kCitxXaJ8J3DnEGBrkGJCxdE9oY76 +rZw== X-Gm-Message-State: AOAM530Y+86BmwUYWtPGfOquMyYPGNtT9pAIjfIue4Tn3YGmXeBsVej1 SZ9f+rIM43XxakhOD3qyd6qdrZuXT5Nkkg== X-Google-Smtp-Source: ABdhPJzOd2b6ueRduEQL9wrC4g7qII6iCD7N2FP/XeEceYc1YnnqiwZuMJQcm7ELMswGsBePDcPdOw== X-Received: by 2002:a5d:4f0e:: with SMTP id c14mr4574072wru.410.1593184517379; Fri, 26 Jun 2020 08:15:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/57] target/arm: Tidy trans_LD1R_zpri Date: Fri, 26 Jun 2020 16:14:10 +0100 Message-Id: <20200626151424.30117-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Move the variable declarations to the top of the function, but do not create a new label before sve_access_check. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 4fa521989de..a3a0b98fbc5 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4883,17 +4883,19 @@ static bool trans_LD1RQ_zpri(DisasContext *s, arg_r= pri_load *a) /* Load and broadcast element. */ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) { - if (!sve_access_check(s)) { - return true; - } - unsigned vsz =3D vec_full_reg_size(s); unsigned psz =3D pred_full_reg_size(s); unsigned esz =3D dtype_esz[a->dtype]; unsigned msz =3D dtype_msz(a->dtype); - TCGLabel *over =3D gen_new_label(); + TCGLabel *over; TCGv_i64 temp, clean_addr; =20 + if (!sve_access_check(s)) { + return true; + } + + over =3D gen_new_label(); + /* If the guarding predicate has no bits set, no load occurs. */ if (psz <=3D 8) { /* Reduce the pred_esz_masks value simply to reduce the --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185836; cv=none; d=zohomail.com; s=zohoarc; b=SS7VLqnxBCqlItCmw0WaTuQaXIQuPS94c0DWc9o55qqVRf05b71+qbTkfXtSmE3aUjXT5x8gCnYQB4+KB01xbuZXA2hJBKVJ3j63GJbtFsFKRdSM6lsp9azz0XPO/WNnqXlPjlSo1Rk2CM6USo+0dINzNkv237aLHYAStqF+uww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185836; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8K/dkwNIkhX7mCrarFQM1tsE89/FiAwHTCjUY5kBac8=; b=nWbdLdS7csgpg6+4e1V7QtnsaqVx+YKylqai62v0c+kVRV0AZb/ImOXjmSsnGcS1hMgQ1IXaHUewV/ZAlJRRs0BcLRhYd0p8ejxgIAmOqqjIECbvoV+uhCgTWHlBerZJ8kDW00A1Rmxo6yOPeekb3X3f1VJiND5yUzdhV8Gw38s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185836356220.04188769665848; Fri, 26 Jun 2020 08:37:16 -0700 (PDT) Received: from localhost ([::1]:55108 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqPj-00087y-5j for importer@patchew.org; Fri, 26 Jun 2020 11:37:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36134) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4Y-00038j-RB for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:22 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:39840) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4X-0006fb-2a for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:22 -0400 Received: by mail-wr1-x430.google.com with SMTP id q5so9851399wru.6 for ; Fri, 26 Jun 2020 08:15:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8K/dkwNIkhX7mCrarFQM1tsE89/FiAwHTCjUY5kBac8=; b=lPfBjQBP6rdHkmcKg23Fd+H1zA2Oxfps+2kjceJHaKfD322UYEs5sSRTJpD71tipdd xLHxcPRQ7bJoM2lOwE80i08zP5yMleJXUqhsouvq5/lXgzkIPn9X4a7+XpFLzi2cXJG6 FyrZAYW7sKAHZZrKc03BZ/18H0TU/40WtlkE+vZUv5pxo33vNYh91fn5jBSBhFe0TQUs Z/XQZjXQu9ixDfsSZs4wV7FhIJ0AZG2NxvqI+9N3JvRls//DpPGneZL3Q8uU01LUqzPE 6bWNZ0+Teoh1rJEKrHy1zGwkYMfsoV1WvFFGinLxNBdx6JxnR2x+jJNdsnwZYVwdHnqQ Mn5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8K/dkwNIkhX7mCrarFQM1tsE89/FiAwHTCjUY5kBac8=; b=e+SynhbWm6Kj7l4F0FiWAlcwGIkDVULFRxdbMI7rWPL3c9/n0BmjcAE/ccdbDkeWLs +t5feYDS74RI9ACf3MeEnbZcNjnoqvTLZKAAOA5p0pTOPmqne3j5pIa2TnJm+LLO6JA3 2T8RuReUsCqmx3dpwNyEPxc8bw55AYqYGgo4brZ6QoFb4HJxGOGk6rFv2xUxcfyDwnJG G+MTDRlrEL+GwkgfrfMg6AhAcLdDjMGu/Z9gUbi8wsG8OoUbNY9EQoviJKA+4tplRBBR 0B45UHLI5KfME0n/xX37LQoK3gIgcbCEEwl4Wc9nEmp5ZmZO5BuhPBBmcThIqQBgbyMP v3Vg== X-Gm-Message-State: AOAM530ta6nX/OT7k/0RMmz7K45n/ZBTj72JgVageM4RnrCvODVRwTkM jl7gIr8DjdaIVsKP5xc78wu1xmGWyylHuA== X-Google-Smtp-Source: ABdhPJy/+tX7XIuEwF8sT3Af/mBb4CFJgHV8+u6LX4H6yhVlOmeGB47YXroFDe1bH9AUHFe91rdDXQ== X-Received: by 2002:adf:e908:: with SMTP id f8mr4219043wrm.3.1593184518367; Fri, 26 Jun 2020 08:15:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 44/57] target/arm: Add arm_tlb_bti_gp Date: Fri, 26 Jun 2020 16:14:11 +0100 Message-Id: <20200626151424.30117-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Introduce an lvalue macro to wrap target_tlb_bit0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-33-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 13 +++++++++++++ target/arm/helper.c | 2 +- target/arm/translate-a64.c | 2 +- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cb4f6ba69f2..c54f0ab18a1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3393,6 +3393,19 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *e= nv, unsigned regno) /* Shared between translate-sve.c and sve_helper.c. */ extern const uint64_t pred_esz_masks[4]; =20 +/* Helper for the macros below, validating the argument type. */ +static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) +{ + return x; +} + +/* + * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. + * Using these should be a bit more self-documenting than using the + * generic target bits directly. + */ +#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) + /* * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in diff --git a/target/arm/helper.c b/target/arm/helper.c index 33f902387b4..44a3f9fb480 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11079,7 +11079,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, } /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.= */ if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { - txattrs->target_tlb_bit0 =3D true; + arm_tlb_bti_gp(txattrs) =3D true; } =20 if (cacheattrs !=3D NULL) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a2a82800102..7a3774bfda7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14434,7 +14434,7 @@ static bool is_guarded_page(CPUARMState *env, Disas= Context *s) * table entry even for that case. */ return (tlb_hit(entry->addr_code, addr) && - env_tlb(env)->d[mmu_idx].iotlb[index].attrs.target_tlb_bit0); + arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs)); #endif } =20 --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593186217; cv=none; d=zohomail.com; s=zohoarc; b=GspTBLuChRfWbN+m9Xu3vikDdt9WjTWuQV8QlqXTvGsl8kCnV+ByTRAMi9YF+99gh60BqBlHafMuXKOyvnxEf+iTGgNQn8RxZdGTMc6rseZbVuMOk2qxjgdbcNgKsVftEVNQ49Xxg4HB3LeNFmokXHnCiV0syX/sl5qHOHc13xQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593186217; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eRtALTCNeV1oJ7NKSoS1dyXGzifFBv6RUUWOD8ZwZTc=; b=SgO8cC/gnvNy4a78FHPKfW3hUFHHHQ1qMCbL10Y1I6ONN/NtLosv6SuTXchMCzlwsdgA63ccOTRMcTLw74w8sFvubfThNt6AZqoAQUlFbTDqs63wlDY5X0jOXdnP543070GL5OjQ19JZThR8s7nVDK6DemNhEfa/XI2M5j47tOI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593186217666610.6561680582118; Fri, 26 Jun 2020 08:43:37 -0700 (PDT) Received: from localhost ([::1]:55314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqVs-0003Dm-8T for importer@patchew.org; Fri, 26 Jun 2020 11:43:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36176) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4c-0003B8-DX for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:26 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:56277) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4Y-0006h2-GJ for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:26 -0400 Received: by mail-wm1-x32f.google.com with SMTP id g75so9146342wme.5 for ; Fri, 26 Jun 2020 08:15:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eRtALTCNeV1oJ7NKSoS1dyXGzifFBv6RUUWOD8ZwZTc=; b=pssOm2SIN8MFDQcKYrld+8sBpqU+dINevjlm85L8EaLqyKQkphW8X41ZV0Q527W3SA tYLI2SVY5D0FJhDLMt1ZfveJ+h2vv0fOxHWRDOgLCnzu0wYeI9PHLxcd+ErpSA+YlfSF bO/MO8LuPhlw5sqs8GJ8dwD+XhhmWvKqiR9/LcTmosSDyn6Y6as9Eq+ztAWZTS5zKKu6 /W338u4PnfSG/AwLQnUmPW4az8R7nGKNDwtFEt3vrGSOWrXHzGrthQ/1KICZqMEOfkCO rbg/DZ8d9Zn8r7YPlzqxEbQoZLKfpkgNaNuO6wJ4Wydki2wa4KaEf4mFIk7migMAnDnR UJ8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eRtALTCNeV1oJ7NKSoS1dyXGzifFBv6RUUWOD8ZwZTc=; b=Bs/ft1LWVhbEz2vKX0BKSMPUjKB4nSfTM/l+zGn//kmMFlGeP0nJaqKQmotZ2B7F9C CUx2ldd19IFGAVSHNYcHoYiI+ZNXb2VYgsn6qqNfaZc/naSJ7jcb9qj0EeHO2i2RSwKH 5fwoeM5jzPK87zYD0j825zfl99EBiMwiNl5hW0hfyhHUi4FOLtCHgafcK63K9541nB30 Kj1kc0ZYfbb5dNuIi4Ytj7OV2YF35sjOhjpaxO2C9OnT0BN6n7gEih5nn/7VKABt1LM/ tMlnqgZ+iHDxh+2lWNQeHsIHh/Yh2DCs0NivElpDAPR3SIk/iCzD91xEMBB/wUyJCkkd GsnA== X-Gm-Message-State: AOAM5322GD2EOTyV9eBo4yWseyMntFTKQprAmRabqQptq+ySuq/caOQ+ uHWZJt3KhBQ+0LjxHSi2QAlkT9nria6opQ== X-Google-Smtp-Source: ABdhPJxu/MMmn4BhwOeCWIg1i1m0tQq9Pld993aASeEnobH+5NOLhHbkWAPRZ4EdioV4EjhiOBUBPw== X-Received: by 2002:a1c:a949:: with SMTP id s70mr4317263wme.137.1593184520184; Fri, 26 Jun 2020 08:15:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 45/57] target/arm: Add mte helpers for sve scalar + int loads Date: Fri, 26 Jun 2020 16:14:12 +0100 Message-Id: <20200626151424.30117-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Because the elements are sequential, we can eliminate many tests all at once when the tag hits TCMA, or if the page(s) are not Tagged. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/helper-sve.h | 58 ++++++++++ target/arm/internals.h | 6 + target/arm/sve_helper.c | 218 ++++++++++++++++++++++++++++++------- target/arm/translate-sve.c | 186 ++++++++++++++++++++++--------- 5 files changed, 378 insertions(+), 91 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c54f0ab18a1..3bf0518ca49 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3405,6 +3405,7 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxA= ttrs *x) * generic target bits directly. */ #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) +#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) =20 /* * Naming convention for isar_feature functions: diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 7a200755ace..1bc1974fc26 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -1196,6 +1196,64 @@ DEF_HELPER_FLAGS_4(sve_ld1sds_le_r, TCG_CALL_NO_WG, = void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ld1sdu_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i3= 2) DEF_HELPER_FLAGS_4(sve_ld1sds_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i3= 2) =20 +DEF_HELPER_FLAGS_4(sve_ld1bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_4(sve_ld2bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_4(sve_ld3bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_4(sve_ld4bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i3= 2) + +DEF_HELPER_FLAGS_4(sve_ld1hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld2hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld3hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld4hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_ld1hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld2hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld3hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld4hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_ld1ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld2ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld3ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld4ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_ld1ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld2ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld3ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld4ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_ld1dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld2dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld3dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld4dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_ld1dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld2dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld3dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ld4dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_ld1bhu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i= 32) +DEF_HELPER_FLAGS_4(sve_ld1bsu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i= 32) +DEF_HELPER_FLAGS_4(sve_ld1bdu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i= 32) +DEF_HELPER_FLAGS_4(sve_ld1bhs_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i= 32) +DEF_HELPER_FLAGS_4(sve_ld1bss_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i= 32) +DEF_HELPER_FLAGS_4(sve_ld1bds_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i= 32) + +DEF_HELPER_FLAGS_4(sve_ld1hsu_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl= , i32) +DEF_HELPER_FLAGS_4(sve_ld1hdu_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl= , i32) +DEF_HELPER_FLAGS_4(sve_ld1hss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl= , i32) +DEF_HELPER_FLAGS_4(sve_ld1hds_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl= , i32) + +DEF_HELPER_FLAGS_4(sve_ld1hsu_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl= , i32) +DEF_HELPER_FLAGS_4(sve_ld1hdu_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl= , i32) +DEF_HELPER_FLAGS_4(sve_ld1hss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl= , i32) +DEF_HELPER_FLAGS_4(sve_ld1hds_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl= , i32) + +DEF_HELPER_FLAGS_4(sve_ld1sdu_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl= , i32) +DEF_HELPER_FLAGS_4(sve_ld1sds_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl= , i32) + +DEF_HELPER_FLAGS_4(sve_ld1sdu_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl= , i32) +DEF_HELPER_FLAGS_4(sve_ld1sds_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl= , i32) + DEF_HELPER_FLAGS_4(sve_ldff1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ldff1bhu_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ldff1bsu_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index c763a23dfba..3306c4f8292 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1310,6 +1310,12 @@ void arm_log_exception(int idx); #define LOG2_TAG_GRANULE 4 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) =20 +/* + * The SVE simd_data field, for memory ops, contains either + * rd (5 bits) or a shift count (2 bits). + */ +#define SVE_MTEDESC_SHIFT 5 + /* Bits within a descriptor passed to the helper_mte_check* functions. */ FIELD(MTEDESC, MIDX, 0, 4) FIELD(MTEDESC, TBI, 4, 2) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index e590db66375..767ecb399f9 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4393,15 +4393,89 @@ static void sve_cont_ldst_watchpoints(SVEContLdSt *= info, CPUARMState *env, #endif } =20 +typedef uint64_t mte_check_fn(CPUARMState *, uint32_t, uint64_t, uintptr_t= ); + +static inline QEMU_ALWAYS_INLINE +void sve_cont_ldst_mte_check_int(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, int esiz= e, + int msize, uint32_t mtedesc, uintptr_t ra, + mte_check_fn *check) +{ + intptr_t mem_off, reg_off, reg_last; + + /* Process the page only if MemAttr =3D=3D Tagged. */ + if (arm_tlb_mte_tagged(&info->page[0].attrs)) { + mem_off =3D info->mem_off_first[0]; + reg_off =3D info->reg_off_first[0]; + reg_last =3D info->reg_off_split; + if (reg_last < 0) { + reg_last =3D info->reg_off_last[0]; + } + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + check(env, mtedesc, addr, ra); + } + reg_off +=3D esize; + mem_off +=3D msize; + } while (reg_off <=3D reg_last && (reg_off & 63)); + } while (reg_off <=3D reg_last); + } + + mem_off =3D info->mem_off_first[1]; + if (mem_off >=3D 0 && arm_tlb_mte_tagged(&info->page[1].attrs)) { + reg_off =3D info->reg_off_first[1]; + reg_last =3D info->reg_off_last[1]; + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + check(env, mtedesc, addr, ra); + } + reg_off +=3D esize; + mem_off +=3D msize; + } while (reg_off & 63); + } while (reg_off <=3D reg_last); + } +} + +typedef void sve_cont_ldst_mte_check_fn(SVEContLdSt *info, CPUARMState *en= v, + uint64_t *vg, target_ulong addr, + int esize, int msize, uint32_t mte= desc, + uintptr_t ra); + +static void sve_cont_ldst_mte_check1(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, + int esize, int msize, uint32_t mtedes= c, + uintptr_t ra) +{ + sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize, + mtedesc, ra, mte_check1); +} + +static void sve_cont_ldst_mte_checkN(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, + int esize, int msize, uint32_t mtedes= c, + uintptr_t ra) +{ + sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize, + mtedesc, ra, mte_checkN); +} + + /* * Common helper for all contiguous 1,2,3,4-register predicated stores. */ static inline QEMU_ALWAYS_INLINE void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr, uint32_t desc, const uintptr_t retaddr, - const int esz, const int msz, const int N, + const int esz, const int msz, const int N, uint32_t mtedesc, sve_ldst1_host_fn *host_fn, - sve_ldst1_tlb_fn *tlb_fn) + sve_ldst1_tlb_fn *tlb_fn, + sve_cont_ldst_mte_check_fn *mte_check_fn) { const unsigned rd =3D simd_data(desc); const intptr_t reg_max =3D simd_oprsz(desc); @@ -4426,7 +4500,14 @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const= target_ulong addr, sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz, BP_MEM_READ, retaddr); =20 - /* TODO: MTE check. */ + /* + * Handle mte checks for all active elements. + * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. + */ + if (mte_check_fn && mtedesc) { + mte_check_fn(&info, env, vg, addr, 1 << esz, N << msz, + mtedesc, retaddr); + } =20 flags =3D info.page[0].flags | info.page[1].flags; if (unlikely(flags !=3D 0)) { @@ -4532,26 +4613,67 @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, cons= t target_ulong addr, } } =20 -#define DO_LD1_1(NAME, ESZ) \ -void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \ - target_ulong addr, uint32_t desc) \ -{ \ - sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, \ - sve_##NAME##_host, sve_##NAME##_tlb); \ +static inline QEMU_ALWAYS_INLINE +void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr, + uint32_t desc, const uintptr_t ra, + const int esz, const int msz, const int N, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + int bit55 =3D extract64(addr, 55, 1); + + /* Remove mtedesc from the normal sve descriptor. */ + desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(desc, bit55) || + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { + mtedesc =3D 0; + } + + sve_ldN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_= fn, + N =3D=3D 1 ? sve_cont_ldst_mte_check1 : sve_cont_ldst_mte_ch= eckN); } =20 -#define DO_LD1_2(NAME, ESZ, MSZ) \ -void HELPER(sve_##NAME##_le_r)(CPUARMState *env, void *vg, \ - target_ulong addr, uint32_t desc) \ -{ \ - sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \ - sve_##NAME##_le_host, sve_##NAME##_le_tlb); \ -} \ -void HELPER(sve_##NAME##_be_r)(CPUARMState *env, void *vg, \ - target_ulong addr, uint32_t desc) \ -{ \ - sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \ - sve_##NAME##_be_host, sve_##NAME##_be_tlb); \ +#define DO_LD1_1(NAME, ESZ) \ +void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, 0, \ + sve_##NAME##_host, sve_##NAME##_tlb, NULL); \ +} \ +void HELPER(sve_##NAME##_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, \ + sve_##NAME##_host, sve_##NAME##_tlb); \ +} + +#define DO_LD1_2(NAME, ESZ, MSZ) \ +void HELPER(sve_##NAME##_le_r)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, 0, \ + sve_##NAME##_le_host, sve_##NAME##_le_tlb, NULL); \ +} \ +void HELPER(sve_##NAME##_be_r)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, 0, \ + sve_##NAME##_be_host, sve_##NAME##_be_tlb, NULL); \ +} \ +void HELPER(sve_##NAME##_le_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \ + sve_##NAME##_le_host, sve_##NAME##_le_tlb); \ +} \ +void HELPER(sve_##NAME##_be_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \ + sve_##NAME##_be_host, sve_##NAME##_be_tlb); \ } =20 DO_LD1_1(ld1bb, MO_8) @@ -4577,26 +4699,44 @@ DO_LD1_2(ld1dd, MO_64, MO_64) #undef DO_LD1_1 #undef DO_LD1_2 =20 -#define DO_LDN_1(N) \ -void HELPER(sve_ld##N##bb_r)(CPUARMState *env, void *vg, \ - target_ulong addr, uint32_t desc) \ -{ \ - sve_ldN_r(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, \ - sve_ld1bb_host, sve_ld1bb_tlb); \ +#define DO_LDN_1(N) \ +void HELPER(sve_ld##N##bb_r)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldN_r(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, 0, \ + sve_ld1bb_host, sve_ld1bb_tlb, NULL); \ +} \ +void HELPER(sve_ld##N##bb_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldN_r_mte(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, \ + sve_ld1bb_host, sve_ld1bb_tlb); \ } =20 -#define DO_LDN_2(N, SUFF, ESZ) \ -void HELPER(sve_ld##N##SUFF##_le_r)(CPUARMState *env, void *vg, \ - target_ulong addr, uint32_t desc) \ -{ \ - sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \ - sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb); \ -} \ -void HELPER(sve_ld##N##SUFF##_be_r)(CPUARMState *env, void *vg, \ - target_ulong addr, uint32_t desc) \ -{ \ - sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \ - sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb); \ +#define DO_LDN_2(N, SUFF, ESZ) \ +void HELPER(sve_ld##N##SUFF##_le_r)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, 0, \ + sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb, NULL); \ +} \ +void HELPER(sve_ld##N##SUFF##_be_r)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, 0, \ + sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb, NULL); \ +} \ +void HELPER(sve_ld##N##SUFF##_le_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \ + sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb); \ +} \ +void HELPER(sve_ld##N##SUFF##_be_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \ + sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb); \ } =20 DO_LDN_1(2) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index a3a0b98fbc5..2620c965f04 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4575,18 +4575,32 @@ static const uint8_t dtype_esz[16] =3D { }; =20 static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, - int dtype, gen_helper_gvec_mem *fn) + int dtype, uint32_t mte_n, bool is_write, + gen_helper_gvec_mem *fn) { unsigned vsz =3D vec_full_reg_size(s); TCGv_ptr t_pg; TCGv_i32 t_desc; - int desc; + int desc =3D 0; =20 - /* For e.g. LD4, there are not enough arguments to pass all 4 + /* + * For e.g. LD4, there are not enough arguments to pass all 4 * registers as pointers, so encode the regno into the data field. * For consistency, do this even for LD1. + * TODO: mte_n check here while callers are updated. */ - desc =3D simd_desc(vsz, vsz, zt); + if (mte_n && s->mte_active[0]) { + int msz =3D dtype_msz(dtype); + + desc =3D FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); + desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); + desc =3D FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz); + desc =3D FIELD_DP32(desc, MTEDESC, TSIZE, mte_n << msz); + desc <<=3D SVE_MTEDESC_SHIFT; + } + desc =3D simd_desc(vsz, vsz, zt | desc); t_desc =3D tcg_const_i32(desc); t_pg =3D tcg_temp_new_ptr(); =20 @@ -4600,64 +4614,132 @@ static void do_mem_zpa(DisasContext *s, int zt, in= t pg, TCGv_i64 addr, static void do_ld_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype, int nreg) { - static gen_helper_gvec_mem * const fns[2][16][4] =3D { - /* Little-endian */ - { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, + static gen_helper_gvec_mem * const fns[2][2][16][4] =3D { + { /* mte inactive, little-endian */ + { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r }, - { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, =20 - { gen_helper_sve_ld1sds_le_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1hh_le_r, gen_helper_sve_ld2hh_le_r, - gen_helper_sve_ld3hh_le_r, gen_helper_sve_ld4hh_le_r }, - { gen_helper_sve_ld1hsu_le_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1hdu_le_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1sds_le_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1hh_le_r, gen_helper_sve_ld2hh_le_r, + gen_helper_sve_ld3hh_le_r, gen_helper_sve_ld4hh_le_r }, + { gen_helper_sve_ld1hsu_le_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1hdu_le_r, NULL, NULL, NULL }, =20 - { gen_helper_sve_ld1hds_le_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1hss_le_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld2ss_le_r, - gen_helper_sve_ld3ss_le_r, gen_helper_sve_ld4ss_le_r }, - { gen_helper_sve_ld1sdu_le_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1hds_le_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1hss_le_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld2ss_le_r, + gen_helper_sve_ld3ss_le_r, gen_helper_sve_ld4ss_le_r }, + { gen_helper_sve_ld1sdu_le_r, NULL, NULL, NULL }, =20 - { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1dd_le_r, gen_helper_sve_ld2dd_le_r, - gen_helper_sve_ld3dd_le_r, gen_helper_sve_ld4dd_le_r } }, + { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1dd_le_r, gen_helper_sve_ld2dd_le_r, + gen_helper_sve_ld3dd_le_r, gen_helper_sve_ld4dd_le_r } }, =20 - /* Big-endian */ - { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, - gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r }, - { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, + /* mte inactive, big-endian */ + { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, + gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r }, + { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, =20 - { gen_helper_sve_ld1sds_be_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1hh_be_r, gen_helper_sve_ld2hh_be_r, - gen_helper_sve_ld3hh_be_r, gen_helper_sve_ld4hh_be_r }, - { gen_helper_sve_ld1hsu_be_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1hdu_be_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1sds_be_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1hh_be_r, gen_helper_sve_ld2hh_be_r, + gen_helper_sve_ld3hh_be_r, gen_helper_sve_ld4hh_be_r }, + { gen_helper_sve_ld1hsu_be_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1hdu_be_r, NULL, NULL, NULL }, =20 - { gen_helper_sve_ld1hds_be_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1hss_be_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld2ss_be_r, - gen_helper_sve_ld3ss_be_r, gen_helper_sve_ld4ss_be_r }, - { gen_helper_sve_ld1sdu_be_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1hds_be_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1hss_be_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld2ss_be_r, + gen_helper_sve_ld3ss_be_r, gen_helper_sve_ld4ss_be_r }, + { gen_helper_sve_ld1sdu_be_r, NULL, NULL, NULL }, =20 - { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, - { gen_helper_sve_ld1dd_be_r, gen_helper_sve_ld2dd_be_r, - gen_helper_sve_ld3dd_be_r, gen_helper_sve_ld4dd_be_r } } + { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, + { gen_helper_sve_ld1dd_be_r, gen_helper_sve_ld2dd_be_r, + gen_helper_sve_ld3dd_be_r, gen_helper_sve_ld4dd_be_r } } }, + + { /* mte active, little-endian */ + { { gen_helper_sve_ld1bb_r_mte, + gen_helper_sve_ld2bb_r_mte, + gen_helper_sve_ld3bb_r_mte, + gen_helper_sve_ld4bb_r_mte }, + { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL }, + + { gen_helper_sve_ld1sds_le_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1hh_le_r_mte, + gen_helper_sve_ld2hh_le_r_mte, + gen_helper_sve_ld3hh_le_r_mte, + gen_helper_sve_ld4hh_le_r_mte }, + { gen_helper_sve_ld1hsu_le_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1hdu_le_r_mte, NULL, NULL, NULL }, + + { gen_helper_sve_ld1hds_le_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1hss_le_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1ss_le_r_mte, + gen_helper_sve_ld2ss_le_r_mte, + gen_helper_sve_ld3ss_le_r_mte, + gen_helper_sve_ld4ss_le_r_mte }, + { gen_helper_sve_ld1sdu_le_r_mte, NULL, NULL, NULL }, + + { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1dd_le_r_mte, + gen_helper_sve_ld2dd_le_r_mte, + gen_helper_sve_ld3dd_le_r_mte, + gen_helper_sve_ld4dd_le_r_mte } }, + + /* mte active, big-endian */ + { { gen_helper_sve_ld1bb_r_mte, + gen_helper_sve_ld2bb_r_mte, + gen_helper_sve_ld3bb_r_mte, + gen_helper_sve_ld4bb_r_mte }, + { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL }, + + { gen_helper_sve_ld1sds_be_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1hh_be_r_mte, + gen_helper_sve_ld2hh_be_r_mte, + gen_helper_sve_ld3hh_be_r_mte, + gen_helper_sve_ld4hh_be_r_mte }, + { gen_helper_sve_ld1hsu_be_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1hdu_be_r_mte, NULL, NULL, NULL }, + + { gen_helper_sve_ld1hds_be_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1hss_be_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1ss_be_r_mte, + gen_helper_sve_ld2ss_be_r_mte, + gen_helper_sve_ld3ss_be_r_mte, + gen_helper_sve_ld4ss_be_r_mte }, + { gen_helper_sve_ld1sdu_be_r_mte, NULL, NULL, NULL }, + + { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL }, + { gen_helper_sve_ld1dd_be_r_mte, + gen_helper_sve_ld2dd_be_r_mte, + gen_helper_sve_ld3dd_be_r_mte, + gen_helper_sve_ld4dd_be_r_mte } } }, }; - gen_helper_gvec_mem *fn =3D fns[s->be_data =3D=3D MO_BE][dtype][nreg]; + gen_helper_gvec_mem *fn + =3D fns[s->mte_active[0]][s->be_data =3D=3D MO_BE][dtype][nreg]; =20 - /* While there are holes in the table, they are not + /* + * While there are holes in the table, they are not * accessible via the instruction encoding. */ assert(fn !=3D NULL); - do_mem_zpa(s, zt, pg, addr, dtype, fn); + do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn); } =20 static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a) @@ -4739,7 +4821,7 @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rpr= r_load *a) TCGv_i64 addr =3D new_tmp_a64(s); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); - do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, + do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 0, false, fns[s->be_data =3D=3D MO_BE][a->dtype]); } return true; @@ -4798,7 +4880,7 @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpr= i_load *a) TCGv_i64 addr =3D new_tmp_a64(s); =20 tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), off); - do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, + do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 0, false, fns[s->be_data =3D=3D MO_BE][a->dtype]); } return true; @@ -5002,7 +5084,7 @@ static void do_st_zpa(DisasContext *s, int zt, int pg= , TCGv_i64 addr, fn =3D fn_multiple[be][nreg - 1][msz]; } assert(fn !=3D NULL); - do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), fn); + do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), 0, true, fn); } =20 static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a) --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Because the elements are sequential, we can eliminate many tests all at once when the tag hits TCMA, or if the page(s) are not Tagged. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-35-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-sve.h | 47 +++++++++++ target/arm/sve_helper.c | 95 ++++++++++++++++------ target/arm/translate-sve.c | 162 ++++++++++++++++++++++++------------- 3 files changed, 226 insertions(+), 78 deletions(-) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 1bc1974fc26..1425f33c927 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -1363,6 +1363,53 @@ DEF_HELPER_FLAGS_4(sve_st1hd_be_r, TCG_CALL_NO_WG, v= oid, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_st1sd_le_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_st1sd_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) =20 +DEF_HELPER_FLAGS_4(sve_st1bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_4(sve_st2bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_4(sve_st3bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_4(sve_st4bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i3= 2) + +DEF_HELPER_FLAGS_4(sve_st1hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st2hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st3hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st4hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_st1hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st2hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st3hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st4hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_st1ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st2ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st3ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st4ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_st1ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st2ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st3ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st4ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_st1dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st2dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st3dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st4dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_st1dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st2dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st3dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st4dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_st1bh_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_4(sve_st1bs_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_4(sve_st1bd_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i3= 2) + +DEF_HELPER_FLAGS_4(sve_st1hs_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st1hd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st1hs_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st1hd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_st1sd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_st1sd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + DEF_HELPER_FLAGS_6(sve_ldbsu_zsu, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr, tl, i32) DEF_HELPER_FLAGS_6(sve_ldhsu_le_zsu, TCG_CALL_NO_WG, diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 767ecb399f9..ded9cedd18d 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5022,11 +5022,12 @@ DO_LDFF1_LDNF1_2(dd, MO_64, MO_64) */ =20 static inline QEMU_ALWAYS_INLINE -void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t= desc, - const uintptr_t retaddr, const int esz, - const int msz, const int N, +void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, + uint32_t desc, const uintptr_t retaddr, + const int esz, const int msz, const int N, uint32_t mtedesc, sve_ldst1_host_fn *host_fn, - sve_ldst1_tlb_fn *tlb_fn) + sve_ldst1_tlb_fn *tlb_fn, + sve_cont_ldst_mte_check_fn *mte_check_fn) { const unsigned rd =3D simd_data(desc); const intptr_t reg_max =3D simd_oprsz(desc); @@ -5048,7 +5049,14 @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, targe= t_ulong addr, uint32_t desc, sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz, BP_MEM_WRITE, retaddr); =20 - /* TODO: MTE check. */ + /* + * Handle mte checks for all active elements. + * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. + */ + if (mte_check_fn && mtedesc) { + mte_check_fn(&info, env, vg, addr, 1 << esz, N << msz, + mtedesc, retaddr); + } =20 flags =3D info.page[0].flags | info.page[1].flags; if (unlikely(flags !=3D 0)) { @@ -5142,26 +5150,67 @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, targ= et_ulong addr, uint32_t desc, } } =20 -#define DO_STN_1(N, NAME, ESZ) \ -void HELPER(sve_st##N##NAME##_r)(CPUARMState *env, void *vg, \ - target_ulong addr, uint32_t desc) \ -{ \ - sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, N, \ - sve_st1##NAME##_host, sve_st1##NAME##_tlb); \ +static inline QEMU_ALWAYS_INLINE +void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr, + uint32_t desc, const uintptr_t ra, + const int esz, const int msz, const int N, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + int bit55 =3D extract64(addr, 55, 1); + + /* Remove mtedesc from the normal sve descriptor. */ + desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(desc, bit55) || + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { + mtedesc =3D 0; + } + + sve_stN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_= fn, + N =3D=3D 1 ? sve_cont_ldst_mte_check1 : sve_cont_ldst_mte_ch= eckN); } =20 -#define DO_STN_2(N, NAME, ESZ, MSZ) \ -void HELPER(sve_st##N##NAME##_le_r)(CPUARMState *env, void *vg, \ - target_ulong addr, uint32_t desc) \ -{ \ - sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \ - sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb); \ -} \ -void HELPER(sve_st##N##NAME##_be_r)(CPUARMState *env, void *vg, \ - target_ulong addr, uint32_t desc) \ -{ \ - sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \ - sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb); \ +#define DO_STN_1(N, NAME, ESZ) \ +void HELPER(sve_st##N##NAME##_r)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, N, 0, \ + sve_st1##NAME##_host, sve_st1##NAME##_tlb, NULL); \ +} \ +void HELPER(sve_st##N##NAME##_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_stN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MO_8, N, \ + sve_st1##NAME##_host, sve_st1##NAME##_tlb); \ +} + +#define DO_STN_2(N, NAME, ESZ, MSZ) \ +void HELPER(sve_st##N##NAME##_le_r)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, 0, \ + sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb, NULL); \ +} \ +void HELPER(sve_st##N##NAME##_be_r)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, 0, \ + sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb, NULL); \ +} \ +void HELPER(sve_st##N##NAME##_le_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_stN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \ + sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb); \ +} \ +void HELPER(sve_st##N##NAME##_be_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_stN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \ + sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb); \ } =20 DO_STN_1(1, bb, MO_8) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 2620c965f04..daac8589f33 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5018,73 +5018,125 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_r= pri_load *a) static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz, int esz, int nreg) { - static gen_helper_gvec_mem * const fn_single[2][4][4] =3D { - { { gen_helper_sve_st1bb_r, - gen_helper_sve_st1bh_r, - gen_helper_sve_st1bs_r, - gen_helper_sve_st1bd_r }, - { NULL, - gen_helper_sve_st1hh_le_r, - gen_helper_sve_st1hs_le_r, - gen_helper_sve_st1hd_le_r }, - { NULL, NULL, - gen_helper_sve_st1ss_le_r, - gen_helper_sve_st1sd_le_r }, - { NULL, NULL, NULL, - gen_helper_sve_st1dd_le_r } }, - { { gen_helper_sve_st1bb_r, - gen_helper_sve_st1bh_r, - gen_helper_sve_st1bs_r, - gen_helper_sve_st1bd_r }, - { NULL, - gen_helper_sve_st1hh_be_r, - gen_helper_sve_st1hs_be_r, - gen_helper_sve_st1hd_be_r }, - { NULL, NULL, - gen_helper_sve_st1ss_be_r, - gen_helper_sve_st1sd_be_r }, - { NULL, NULL, NULL, - gen_helper_sve_st1dd_be_r } }, + static gen_helper_gvec_mem * const fn_single[2][2][4][4] =3D { + { { { gen_helper_sve_st1bb_r, + gen_helper_sve_st1bh_r, + gen_helper_sve_st1bs_r, + gen_helper_sve_st1bd_r }, + { NULL, + gen_helper_sve_st1hh_le_r, + gen_helper_sve_st1hs_le_r, + gen_helper_sve_st1hd_le_r }, + { NULL, NULL, + gen_helper_sve_st1ss_le_r, + gen_helper_sve_st1sd_le_r }, + { NULL, NULL, NULL, + gen_helper_sve_st1dd_le_r } }, + { { gen_helper_sve_st1bb_r, + gen_helper_sve_st1bh_r, + gen_helper_sve_st1bs_r, + gen_helper_sve_st1bd_r }, + { NULL, + gen_helper_sve_st1hh_be_r, + gen_helper_sve_st1hs_be_r, + gen_helper_sve_st1hd_be_r }, + { NULL, NULL, + gen_helper_sve_st1ss_be_r, + gen_helper_sve_st1sd_be_r }, + { NULL, NULL, NULL, + gen_helper_sve_st1dd_be_r } } }, + + { { { gen_helper_sve_st1bb_r_mte, + gen_helper_sve_st1bh_r_mte, + gen_helper_sve_st1bs_r_mte, + gen_helper_sve_st1bd_r_mte }, + { NULL, + gen_helper_sve_st1hh_le_r_mte, + gen_helper_sve_st1hs_le_r_mte, + gen_helper_sve_st1hd_le_r_mte }, + { NULL, NULL, + gen_helper_sve_st1ss_le_r_mte, + gen_helper_sve_st1sd_le_r_mte }, + { NULL, NULL, NULL, + gen_helper_sve_st1dd_le_r_mte } }, + { { gen_helper_sve_st1bb_r_mte, + gen_helper_sve_st1bh_r_mte, + gen_helper_sve_st1bs_r_mte, + gen_helper_sve_st1bd_r_mte }, + { NULL, + gen_helper_sve_st1hh_be_r_mte, + gen_helper_sve_st1hs_be_r_mte, + gen_helper_sve_st1hd_be_r_mte }, + { NULL, NULL, + gen_helper_sve_st1ss_be_r_mte, + gen_helper_sve_st1sd_be_r_mte }, + { NULL, NULL, NULL, + gen_helper_sve_st1dd_be_r_mte } } }, }; - static gen_helper_gvec_mem * const fn_multiple[2][3][4] =3D { - { { gen_helper_sve_st2bb_r, - gen_helper_sve_st2hh_le_r, - gen_helper_sve_st2ss_le_r, - gen_helper_sve_st2dd_le_r }, - { gen_helper_sve_st3bb_r, - gen_helper_sve_st3hh_le_r, - gen_helper_sve_st3ss_le_r, - gen_helper_sve_st3dd_le_r }, - { gen_helper_sve_st4bb_r, - gen_helper_sve_st4hh_le_r, - gen_helper_sve_st4ss_le_r, - gen_helper_sve_st4dd_le_r } }, - { { gen_helper_sve_st2bb_r, - gen_helper_sve_st2hh_be_r, - gen_helper_sve_st2ss_be_r, - gen_helper_sve_st2dd_be_r }, - { gen_helper_sve_st3bb_r, - gen_helper_sve_st3hh_be_r, - gen_helper_sve_st3ss_be_r, - gen_helper_sve_st3dd_be_r }, - { gen_helper_sve_st4bb_r, - gen_helper_sve_st4hh_be_r, - gen_helper_sve_st4ss_be_r, - gen_helper_sve_st4dd_be_r } }, + static gen_helper_gvec_mem * const fn_multiple[2][2][3][4] =3D { + { { { gen_helper_sve_st2bb_r, + gen_helper_sve_st2hh_le_r, + gen_helper_sve_st2ss_le_r, + gen_helper_sve_st2dd_le_r }, + { gen_helper_sve_st3bb_r, + gen_helper_sve_st3hh_le_r, + gen_helper_sve_st3ss_le_r, + gen_helper_sve_st3dd_le_r }, + { gen_helper_sve_st4bb_r, + gen_helper_sve_st4hh_le_r, + gen_helper_sve_st4ss_le_r, + gen_helper_sve_st4dd_le_r } }, + { { gen_helper_sve_st2bb_r, + gen_helper_sve_st2hh_be_r, + gen_helper_sve_st2ss_be_r, + gen_helper_sve_st2dd_be_r }, + { gen_helper_sve_st3bb_r, + gen_helper_sve_st3hh_be_r, + gen_helper_sve_st3ss_be_r, + gen_helper_sve_st3dd_be_r }, + { gen_helper_sve_st4bb_r, + gen_helper_sve_st4hh_be_r, + gen_helper_sve_st4ss_be_r, + gen_helper_sve_st4dd_be_r } } }, + { { { gen_helper_sve_st2bb_r_mte, + gen_helper_sve_st2hh_le_r_mte, + gen_helper_sve_st2ss_le_r_mte, + gen_helper_sve_st2dd_le_r_mte }, + { gen_helper_sve_st3bb_r_mte, + gen_helper_sve_st3hh_le_r_mte, + gen_helper_sve_st3ss_le_r_mte, + gen_helper_sve_st3dd_le_r_mte }, + { gen_helper_sve_st4bb_r_mte, + gen_helper_sve_st4hh_le_r_mte, + gen_helper_sve_st4ss_le_r_mte, + gen_helper_sve_st4dd_le_r_mte } }, + { { gen_helper_sve_st2bb_r_mte, + gen_helper_sve_st2hh_be_r_mte, + gen_helper_sve_st2ss_be_r_mte, + gen_helper_sve_st2dd_be_r_mte }, + { gen_helper_sve_st3bb_r_mte, + gen_helper_sve_st3hh_be_r_mte, + gen_helper_sve_st3ss_be_r_mte, + gen_helper_sve_st3dd_be_r_mte }, + { gen_helper_sve_st4bb_r_mte, + gen_helper_sve_st4hh_be_r_mte, + gen_helper_sve_st4ss_be_r_mte, + gen_helper_sve_st4dd_be_r_mte } } }, }; gen_helper_gvec_mem *fn; int be =3D s->be_data =3D=3D MO_BE; =20 if (nreg =3D=3D 0) { /* ST1 */ - fn =3D fn_single[be][msz][esz]; + fn =3D fn_single[s->mte_active[0]][be][msz][esz]; + nreg =3D 1; } else { /* ST2, ST3, ST4 -- msz =3D=3D esz, enforced by encoding */ assert(msz =3D=3D esz); - fn =3D fn_multiple[be][nreg - 1][msz]; + fn =3D fn_multiple[s->mte_active[0]][be][nreg - 1][msz]; } assert(fn !=3D NULL); - do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), 0, true, fn); + do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn); } =20 static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a) --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185826; cv=none; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Because the elements are sequential, we can eliminate many tests all at once when the tag hits TCMA, or if the page(s) are not Tagged. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-36-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-sve.h | 98 ++++++++++++++++ target/arm/sve_helper.c | 99 ++++++++++++++-- target/arm/translate-sve.c | 232 +++++++++++++++++++++++++------------ 3 files changed, 343 insertions(+), 86 deletions(-) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 1425f33c927..f48752eb421 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -1285,6 +1285,55 @@ DEF_HELPER_FLAGS_4(sve_ldff1sds_be_r, TCG_CALL_NO_WG= , void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ldff1dd_le_r, TCG_CALL_NO_WG, void, env, ptr, tl, i= 32) DEF_HELPER_FLAGS_4(sve_ldff1dd_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i= 32) =20 +DEF_HELPER_FLAGS_4(sve_ldff1bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, = i32) +DEF_HELPER_FLAGS_4(sve_ldff1bhu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ldff1bsu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ldff1bdu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ldff1bhs_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ldff1bss_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ldff1bds_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_ldff1hh_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldff1hsu_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldff1hdu_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldff1hss_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldff1hds_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) + +DEF_HELPER_FLAGS_4(sve_ldff1hh_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldff1hsu_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldff1hdu_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldff1hss_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldff1hds_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) + +DEF_HELPER_FLAGS_4(sve_ldff1ss_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldff1sdu_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldff1sds_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) + +DEF_HELPER_FLAGS_4(sve_ldff1ss_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldff1sdu_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldff1sds_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) + +DEF_HELPER_FLAGS_4(sve_ldff1dd_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldff1dd_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) + DEF_HELPER_FLAGS_4(sve_ldnf1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ldnf1bhu_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ldnf1bsu_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) @@ -1316,6 +1365,55 @@ DEF_HELPER_FLAGS_4(sve_ldnf1sds_be_r, TCG_CALL_NO_WG= , void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ldnf1dd_le_r, TCG_CALL_NO_WG, void, env, ptr, tl, i= 32) DEF_HELPER_FLAGS_4(sve_ldnf1dd_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i= 32) =20 +DEF_HELPER_FLAGS_4(sve_ldnf1bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, = i32) +DEF_HELPER_FLAGS_4(sve_ldnf1bhu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ldnf1bsu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ldnf1bdu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ldnf1bhs_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ldnf1bss_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) +DEF_HELPER_FLAGS_4(sve_ldnf1bds_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl,= i32) + +DEF_HELPER_FLAGS_4(sve_ldnf1hh_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldnf1hsu_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldnf1hdu_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldnf1hss_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldnf1hds_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) + +DEF_HELPER_FLAGS_4(sve_ldnf1hh_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldnf1hsu_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldnf1hdu_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldnf1hss_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldnf1hds_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) + +DEF_HELPER_FLAGS_4(sve_ldnf1ss_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldnf1sdu_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldnf1sds_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) + +DEF_HELPER_FLAGS_4(sve_ldnf1ss_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldnf1sdu_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldnf1sds_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) + +DEF_HELPER_FLAGS_4(sve_ldnf1dd_le_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve_ldnf1dd_be_r_mte, TCG_CALL_NO_WG, + void, env, ptr, tl, i32) + DEF_HELPER_FLAGS_4(sve_st1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_st2bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_st3bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index ded9cedd18d..7aca4ad3840 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4794,7 +4794,7 @@ static void record_fault(CPUARMState *env, uintptr_t = i, uintptr_t oprsz) */ static inline QEMU_ALWAYS_INLINE void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr, - uint32_t desc, const uintptr_t retaddr, + uint32_t desc, const uintptr_t retaddr, uint32_t mtedes= c, const int esz, const int msz, const SVEContFault fault, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) @@ -4826,13 +4826,25 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, cons= t target_ulong addr, mem_off =3D info.mem_off_first[0]; flags =3D info.page[0].flags; =20 + /* + * Disable MTE checking if the Tagged bit is not set. Since TBI must + * be set within MTEDESC for MTE, !mtedesc =3D> !mte_active. + */ + if (arm_tlb_mte_tagged(&info.page[0].attrs)) { + mtedesc =3D 0; + } + if (fault =3D=3D FAULT_FIRST) { + /* Trapping mte check for the first-fault element. */ + if (mtedesc) { + mte_check1(env, mtedesc, addr + mem_off, retaddr); + } + /* * Special handling of the first active element, * if it crosses a page boundary or is MMIO. */ bool is_split =3D mem_off =3D=3D info.mem_off_split; - /* TODO: MTE check. */ if (unlikely(flags !=3D 0) || unlikely(is_split)) { /* * Use the slow path for cross-page handling. @@ -4868,7 +4880,9 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const = target_ulong addr, /* Watchpoint hit, see below. */ goto do_fault; } - /* TODO: MTE check. */ + if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) { + goto do_fault; + } /* * Use the slow path for cross-page handling. * This is RAM, without a watchpoint, and will not trap. @@ -4916,7 +4930,9 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const = target_ulong addr, & BP_MEM_READ)) { goto do_fault; } - /* TODO: MTE check. */ + if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) { + goto do_fault; + } host_fn(vd, reg_off, host + mem_off); } reg_off +=3D 1 << esz; @@ -4954,44 +4970,103 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, con= st target_ulong addr, record_fault(env, reg_off, reg_max); } =20 -#define DO_LDFF1_LDNF1_1(PART, ESZ) \ +static inline QEMU_ALWAYS_INLINE +void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr, + uint32_t desc, const uintptr_t retaddr, + const int esz, const int msz, const SVEContFault fa= ult, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + int bit55 =3D extract64(addr, 55, 1); + + /* Remove mtedesc from the normal sve descriptor. */ + desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(desc, bit55) || + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { + mtedesc =3D 0; + } + + sve_ldnfff1_r(env, vg, addr, desc, retaddr, mtedesc, + esz, msz, fault, host_fn, tlb_fn); +} + +#define DO_LDFF1_LDNF1_1(PART, ESZ) \ void HELPER(sve_ldff1##PART##_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ - sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_FIRST, \ + sve_ldnfff1_r(env, vg, addr, desc, GETPC(), 0, ESZ, MO_8, FAULT_FIRST,= \ sve_ld1##PART##_host, sve_ld1##PART##_tlb); \ } \ void HELPER(sve_ldnf1##PART##_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ - sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_NO, \ + sve_ldnfff1_r(env, vg, addr, desc, GETPC(), 0, ESZ, MO_8, FAULT_NO, \ + sve_ld1##PART##_host, sve_ld1##PART##_tlb); \ +} \ +void HELPER(sve_ldff1##PART##_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldnfff1_r_mte(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_FIRST= , \ + sve_ld1##PART##_host, sve_ld1##PART##_tlb); \ +} \ +void HELPER(sve_ldnf1##PART##_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldnfff1_r_mte(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_NO, \ sve_ld1##PART##_host, sve_ld1##PART##_tlb); \ } =20 -#define DO_LDFF1_LDNF1_2(PART, ESZ, MSZ) \ +#define DO_LDFF1_LDNF1_2(PART, ESZ, MSZ) \ void HELPER(sve_ldff1##PART##_le_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ - sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \ + sve_ldnfff1_r(env, vg, addr, desc, GETPC(), 0, ESZ, MSZ, FAULT_FIRST, \ sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \ } \ void HELPER(sve_ldnf1##PART##_le_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ - sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \ + sve_ldnfff1_r(env, vg, addr, desc, GETPC(), 0, ESZ, MSZ, FAULT_NO, \ sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \ } \ void HELPER(sve_ldff1##PART##_be_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ - sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \ + sve_ldnfff1_r(env, vg, addr, desc, GETPC(), 0, ESZ, MSZ, FAULT_FIRST, \ sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \ } \ void HELPER(sve_ldnf1##PART##_be_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ - sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \ + sve_ldnfff1_r(env, vg, addr, desc, GETPC(), 0, ESZ, MSZ, FAULT_NO, \ sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \ +} \ +void HELPER(sve_ldff1##PART##_le_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldnfff1_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST,= \ + sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \ +} \ +void HELPER(sve_ldnf1##PART##_le_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldnfff1_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \ + sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \ +} \ +void HELPER(sve_ldff1##PART##_be_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldnfff1_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST,= \ + sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \ +} \ +void HELPER(sve_ldnf1##PART##_be_r_mte)(CPUARMState *env, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sve_ldnfff1_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \ + sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \ } =20 DO_LDFF1_LDNF1_1(bb, MO_8) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index daac8589f33..e4fbe484930 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4773,104 +4773,188 @@ static bool trans_LD_zpri(DisasContext *s, arg_rp= ri_load *a) =20 static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a) { - static gen_helper_gvec_mem * const fns[2][16] =3D { - /* Little-endian */ - { gen_helper_sve_ldff1bb_r, - gen_helper_sve_ldff1bhu_r, - gen_helper_sve_ldff1bsu_r, - gen_helper_sve_ldff1bdu_r, + static gen_helper_gvec_mem * const fns[2][2][16] =3D { + { /* mte inactive, little-endian */ + { gen_helper_sve_ldff1bb_r, + gen_helper_sve_ldff1bhu_r, + gen_helper_sve_ldff1bsu_r, + gen_helper_sve_ldff1bdu_r, =20 - gen_helper_sve_ldff1sds_le_r, - gen_helper_sve_ldff1hh_le_r, - gen_helper_sve_ldff1hsu_le_r, - gen_helper_sve_ldff1hdu_le_r, + gen_helper_sve_ldff1sds_le_r, + gen_helper_sve_ldff1hh_le_r, + gen_helper_sve_ldff1hsu_le_r, + gen_helper_sve_ldff1hdu_le_r, =20 - gen_helper_sve_ldff1hds_le_r, - gen_helper_sve_ldff1hss_le_r, - gen_helper_sve_ldff1ss_le_r, - gen_helper_sve_ldff1sdu_le_r, + gen_helper_sve_ldff1hds_le_r, + gen_helper_sve_ldff1hss_le_r, + gen_helper_sve_ldff1ss_le_r, + gen_helper_sve_ldff1sdu_le_r, =20 - gen_helper_sve_ldff1bds_r, - gen_helper_sve_ldff1bss_r, - gen_helper_sve_ldff1bhs_r, - gen_helper_sve_ldff1dd_le_r }, + gen_helper_sve_ldff1bds_r, + gen_helper_sve_ldff1bss_r, + gen_helper_sve_ldff1bhs_r, + gen_helper_sve_ldff1dd_le_r }, =20 - /* Big-endian */ - { gen_helper_sve_ldff1bb_r, - gen_helper_sve_ldff1bhu_r, - gen_helper_sve_ldff1bsu_r, - gen_helper_sve_ldff1bdu_r, + /* mte inactive, big-endian */ + { gen_helper_sve_ldff1bb_r, + gen_helper_sve_ldff1bhu_r, + gen_helper_sve_ldff1bsu_r, + gen_helper_sve_ldff1bdu_r, =20 - gen_helper_sve_ldff1sds_be_r, - gen_helper_sve_ldff1hh_be_r, - gen_helper_sve_ldff1hsu_be_r, - gen_helper_sve_ldff1hdu_be_r, + gen_helper_sve_ldff1sds_be_r, + gen_helper_sve_ldff1hh_be_r, + gen_helper_sve_ldff1hsu_be_r, + gen_helper_sve_ldff1hdu_be_r, =20 - gen_helper_sve_ldff1hds_be_r, - gen_helper_sve_ldff1hss_be_r, - gen_helper_sve_ldff1ss_be_r, - gen_helper_sve_ldff1sdu_be_r, + gen_helper_sve_ldff1hds_be_r, + gen_helper_sve_ldff1hss_be_r, + gen_helper_sve_ldff1ss_be_r, + gen_helper_sve_ldff1sdu_be_r, =20 - gen_helper_sve_ldff1bds_r, - gen_helper_sve_ldff1bss_r, - gen_helper_sve_ldff1bhs_r, - gen_helper_sve_ldff1dd_be_r }, + gen_helper_sve_ldff1bds_r, + gen_helper_sve_ldff1bss_r, + gen_helper_sve_ldff1bhs_r, + gen_helper_sve_ldff1dd_be_r } }, + + { /* mte active, little-endian */ + { gen_helper_sve_ldff1bb_r_mte, + gen_helper_sve_ldff1bhu_r_mte, + gen_helper_sve_ldff1bsu_r_mte, + gen_helper_sve_ldff1bdu_r_mte, + + gen_helper_sve_ldff1sds_le_r_mte, + gen_helper_sve_ldff1hh_le_r_mte, + gen_helper_sve_ldff1hsu_le_r_mte, + gen_helper_sve_ldff1hdu_le_r_mte, + + gen_helper_sve_ldff1hds_le_r_mte, + gen_helper_sve_ldff1hss_le_r_mte, + gen_helper_sve_ldff1ss_le_r_mte, + gen_helper_sve_ldff1sdu_le_r_mte, + + gen_helper_sve_ldff1bds_r_mte, + gen_helper_sve_ldff1bss_r_mte, + gen_helper_sve_ldff1bhs_r_mte, + gen_helper_sve_ldff1dd_le_r_mte }, + + /* mte active, big-endian */ + { gen_helper_sve_ldff1bb_r_mte, + gen_helper_sve_ldff1bhu_r_mte, + gen_helper_sve_ldff1bsu_r_mte, + gen_helper_sve_ldff1bdu_r_mte, + + gen_helper_sve_ldff1sds_be_r_mte, + gen_helper_sve_ldff1hh_be_r_mte, + gen_helper_sve_ldff1hsu_be_r_mte, + gen_helper_sve_ldff1hdu_be_r_mte, + + gen_helper_sve_ldff1hds_be_r_mte, + gen_helper_sve_ldff1hss_be_r_mte, + gen_helper_sve_ldff1ss_be_r_mte, + gen_helper_sve_ldff1sdu_be_r_mte, + + gen_helper_sve_ldff1bds_r_mte, + gen_helper_sve_ldff1bss_r_mte, + gen_helper_sve_ldff1bhs_r_mte, + gen_helper_sve_ldff1dd_be_r_mte } }, }; =20 if (sve_access_check(s)) { TCGv_i64 addr =3D new_tmp_a64(s); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); - do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 0, false, - fns[s->be_data =3D=3D MO_BE][a->dtype]); + do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false, + fns[s->mte_active[0]][s->be_data =3D=3D MO_BE][a->dtype= ]); } return true; } =20 static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a) { - static gen_helper_gvec_mem * const fns[2][16] =3D { - /* Little-endian */ - { gen_helper_sve_ldnf1bb_r, - gen_helper_sve_ldnf1bhu_r, - gen_helper_sve_ldnf1bsu_r, - gen_helper_sve_ldnf1bdu_r, + static gen_helper_gvec_mem * const fns[2][2][16] =3D { + { /* mte inactive, little-endian */ + { gen_helper_sve_ldnf1bb_r, + gen_helper_sve_ldnf1bhu_r, + gen_helper_sve_ldnf1bsu_r, + gen_helper_sve_ldnf1bdu_r, =20 - gen_helper_sve_ldnf1sds_le_r, - gen_helper_sve_ldnf1hh_le_r, - gen_helper_sve_ldnf1hsu_le_r, - gen_helper_sve_ldnf1hdu_le_r, + gen_helper_sve_ldnf1sds_le_r, + gen_helper_sve_ldnf1hh_le_r, + gen_helper_sve_ldnf1hsu_le_r, + gen_helper_sve_ldnf1hdu_le_r, =20 - gen_helper_sve_ldnf1hds_le_r, - gen_helper_sve_ldnf1hss_le_r, - gen_helper_sve_ldnf1ss_le_r, - gen_helper_sve_ldnf1sdu_le_r, + gen_helper_sve_ldnf1hds_le_r, + gen_helper_sve_ldnf1hss_le_r, + gen_helper_sve_ldnf1ss_le_r, + gen_helper_sve_ldnf1sdu_le_r, =20 - gen_helper_sve_ldnf1bds_r, - gen_helper_sve_ldnf1bss_r, - gen_helper_sve_ldnf1bhs_r, - gen_helper_sve_ldnf1dd_le_r }, + gen_helper_sve_ldnf1bds_r, + gen_helper_sve_ldnf1bss_r, + gen_helper_sve_ldnf1bhs_r, + gen_helper_sve_ldnf1dd_le_r }, =20 - /* Big-endian */ - { gen_helper_sve_ldnf1bb_r, - gen_helper_sve_ldnf1bhu_r, - gen_helper_sve_ldnf1bsu_r, - gen_helper_sve_ldnf1bdu_r, + /* mte inactive, big-endian */ + { gen_helper_sve_ldnf1bb_r, + gen_helper_sve_ldnf1bhu_r, + gen_helper_sve_ldnf1bsu_r, + gen_helper_sve_ldnf1bdu_r, =20 - gen_helper_sve_ldnf1sds_be_r, - gen_helper_sve_ldnf1hh_be_r, - gen_helper_sve_ldnf1hsu_be_r, - gen_helper_sve_ldnf1hdu_be_r, + gen_helper_sve_ldnf1sds_be_r, + gen_helper_sve_ldnf1hh_be_r, + gen_helper_sve_ldnf1hsu_be_r, + gen_helper_sve_ldnf1hdu_be_r, =20 - gen_helper_sve_ldnf1hds_be_r, - gen_helper_sve_ldnf1hss_be_r, - gen_helper_sve_ldnf1ss_be_r, - gen_helper_sve_ldnf1sdu_be_r, + gen_helper_sve_ldnf1hds_be_r, + gen_helper_sve_ldnf1hss_be_r, + gen_helper_sve_ldnf1ss_be_r, + gen_helper_sve_ldnf1sdu_be_r, =20 - gen_helper_sve_ldnf1bds_r, - gen_helper_sve_ldnf1bss_r, - gen_helper_sve_ldnf1bhs_r, - gen_helper_sve_ldnf1dd_be_r }, + gen_helper_sve_ldnf1bds_r, + gen_helper_sve_ldnf1bss_r, + gen_helper_sve_ldnf1bhs_r, + gen_helper_sve_ldnf1dd_be_r } }, + + { /* mte inactive, little-endian */ + { gen_helper_sve_ldnf1bb_r_mte, + gen_helper_sve_ldnf1bhu_r_mte, + gen_helper_sve_ldnf1bsu_r_mte, + gen_helper_sve_ldnf1bdu_r_mte, + + gen_helper_sve_ldnf1sds_le_r_mte, + gen_helper_sve_ldnf1hh_le_r_mte, + gen_helper_sve_ldnf1hsu_le_r_mte, + gen_helper_sve_ldnf1hdu_le_r_mte, + + gen_helper_sve_ldnf1hds_le_r_mte, + gen_helper_sve_ldnf1hss_le_r_mte, + gen_helper_sve_ldnf1ss_le_r_mte, + gen_helper_sve_ldnf1sdu_le_r_mte, + + gen_helper_sve_ldnf1bds_r_mte, + gen_helper_sve_ldnf1bss_r_mte, + gen_helper_sve_ldnf1bhs_r_mte, + gen_helper_sve_ldnf1dd_le_r_mte }, + + /* mte inactive, big-endian */ + { gen_helper_sve_ldnf1bb_r_mte, + gen_helper_sve_ldnf1bhu_r_mte, + gen_helper_sve_ldnf1bsu_r_mte, + gen_helper_sve_ldnf1bdu_r_mte, + + gen_helper_sve_ldnf1sds_be_r_mte, + gen_helper_sve_ldnf1hh_be_r_mte, + gen_helper_sve_ldnf1hsu_be_r_mte, + gen_helper_sve_ldnf1hdu_be_r_mte, + + gen_helper_sve_ldnf1hds_be_r_mte, + gen_helper_sve_ldnf1hss_be_r_mte, + gen_helper_sve_ldnf1ss_be_r_mte, + gen_helper_sve_ldnf1sdu_be_r_mte, + + gen_helper_sve_ldnf1bds_r_mte, + gen_helper_sve_ldnf1bss_r_mte, + gen_helper_sve_ldnf1bhs_r_mte, + gen_helper_sve_ldnf1dd_be_r_mte } }, }; =20 if (sve_access_check(s)) { @@ -4880,8 +4964,8 @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpr= i_load *a) TCGv_i64 addr =3D new_tmp_a64(s); =20 tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), off); - do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 0, false, - fns[s->be_data =3D=3D MO_BE][a->dtype]); + do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false, + fns[s->mte_active[0]][s->be_data =3D=3D MO_BE][a->dtype= ]); } return true; } --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185930; cv=none; d=zohomail.com; s=zohoarc; b=H2l7A5heALWmI3AU1GbQVBBFZuNynL1Z6y2LMI7apf0zHSbTUwQiX7PV9COmLPpAK/YmEeiDN8kfaVRPZAJFY5F7FJVUX+oS3uAEgh+vMwOq/QKXXAmvghucfZNVlYfpHWushohT7fUCYNbD6Luo3yRrR23WCIeOamI6gF0hrk0= ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We still need to handle tbi for user-only when mte is inactive. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-37-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.h | 1 + target/arm/translate-a64.c | 2 +- target/arm/translate-sve.c | 6 ++++-- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 781c4413999..49e4865918d 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -40,6 +40,7 @@ TCGv_ptr get_fpstatus_ptr(bool); bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); bool sve_access_check(DisasContext *s); +TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7a3774bfda7..e46c4a49e00 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -215,7 +215,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 sr= c) * of the write-back address. */ =20 -static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) +TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { TCGv_i64 clean =3D new_tmp_a64(s); #ifdef CONFIG_USER_ONLY diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index e4fbe484930..04eda9a1264 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4587,9 +4587,8 @@ static void do_mem_zpa(DisasContext *s, int zt, int p= g, TCGv_i64 addr, * For e.g. LD4, there are not enough arguments to pass all 4 * registers as pointers, so encode the regno into the data field. * For consistency, do this even for LD1. - * TODO: mte_n check here while callers are updated. */ - if (mte_n && s->mte_active[0]) { + if (s->mte_active[0]) { int msz =3D dtype_msz(dtype); =20 desc =3D FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); @@ -4599,7 +4598,10 @@ static void do_mem_zpa(DisasContext *s, int zt, int = pg, TCGv_i64 addr, desc =3D FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz); desc =3D FIELD_DP32(desc, MTEDESC, TSIZE, mte_n << msz); desc <<=3D SVE_MTEDESC_SHIFT; + } else { + addr =3D clean_data_tbi(s, addr); } + desc =3D simd_desc(vsz, vsz, zt | desc); t_desc =3D tcg_const_i32(desc); t_pg =3D tcg_temp_new_ptr(); --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593186179; cv=none; d=zohomail.com; s=zohoarc; b=U+Epa9SrZrPiiBwbcIs2ET3W3Iqk2pYXUV3HRkvH/Vu+jYadpgbZOvHrufctRAUNHal0bLouLGhPqcdH3SmyaQWeoq89SX3CosKgceyLtrF62zLPr9/EVtwbmHHHSn/pg0PPENXFowF1JWwDYLPACUpJDLPF/mKkox8+fVUScoQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593186179; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qjNpozwxLU54hGICp5UL23YT8kOgap7ValAV5L7E2UI=; b=my5lvMgyqymnZ+qiQ8/YiwYyTOATH+/4aHX0w8847JXMff0O4vKMNBaT5ta1C1AIOGHy/sEjiydJlndcNrmMKQ/Fq1tJ2dGQG00acjLKVj7TNbVvXc1hOwyYKeeWumYnuO8W7CZDSuttmCrrUmoChh06lF5q1I6svxJyetIqOxg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593186179107108.14695373239636; Fri, 26 Jun 2020 08:42:59 -0700 (PDT) Received: from localhost ([::1]:51942 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqVF-0001ra-G0 for importer@patchew.org; Fri, 26 Jun 2020 11:42:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4k-0003VD-2L for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:34 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:34922) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4e-0006jm-Jy for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:33 -0400 Received: by mail-wm1-x334.google.com with SMTP id l2so8228554wmf.0 for ; Fri, 26 Jun 2020 08:15:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Because the elements are non-sequential, we cannot eliminate many tests straight away like we can for sequential operations. But we often have the PTE details handy, so we can test for Tagged. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-38-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-sve.h | 285 ++++++++++++++++ target/arm/sve_helper.c | 185 +++++++++-- target/arm/translate-sve.c | 650 +++++++++++++++++++++++++------------ 3 files changed, 872 insertions(+), 248 deletions(-) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index f48752eb421..63c4a087caa 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -1617,6 +1617,115 @@ DEF_HELPER_FLAGS_6(sve_ldsds_le_zd, TCG_CALL_NO_WG, DEF_HELPER_FLAGS_6(sve_ldsds_be_zd, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr, tl, i32) =20 +DEF_HELPER_FLAGS_6(sve_ldbsu_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhsu_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhsu_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldss_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldss_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldbss_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhss_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhss_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_6(sve_ldbsu_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhsu_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhsu_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldss_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldss_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldbss_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhss_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhss_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_6(sve_ldbdu_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhdu_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhdu_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldsdu_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldsdu_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_lddd_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_lddd_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldbds_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhds_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhds_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldsds_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldsds_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_6(sve_ldbdu_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhdu_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhdu_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldsdu_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldsdu_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_lddd_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_lddd_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldbds_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhds_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhds_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldsds_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldsds_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_6(sve_ldbdu_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhdu_le_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhdu_be_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldsdu_le_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldsdu_be_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_lddd_le_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_lddd_be_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldbds_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhds_le_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldhds_be_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldsds_le_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldsds_be_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + DEF_HELPER_FLAGS_6(sve_ldffbsu_zsu, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr, tl, i32) DEF_HELPER_FLAGS_6(sve_ldffhsu_le_zsu, TCG_CALL_NO_WG, @@ -1726,6 +1835,115 @@ DEF_HELPER_FLAGS_6(sve_ldffsds_le_zd, TCG_CALL_NO_W= G, DEF_HELPER_FLAGS_6(sve_ldffsds_be_zd, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr, tl, i32) =20 +DEF_HELPER_FLAGS_6(sve_ldffbsu_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhsu_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhsu_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffss_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffss_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffbss_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhss_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhss_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_6(sve_ldffbsu_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhsu_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhsu_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffss_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffss_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffbss_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhss_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhss_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_6(sve_ldffbdu_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhdu_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhdu_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffsdu_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffsdu_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffdd_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffdd_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffbds_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhds_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhds_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffsds_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffsds_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_6(sve_ldffbdu_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhdu_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhdu_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffsdu_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffsdu_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffdd_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffdd_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffbds_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhds_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhds_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffsds_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffsds_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_6(sve_ldffbdu_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhdu_le_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhdu_be_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffsdu_le_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffsdu_be_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffdd_le_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffdd_be_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffbds_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhds_le_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffhds_be_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffsds_le_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_ldffsds_be_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + DEF_HELPER_FLAGS_6(sve_stbs_zsu, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr, tl, i32) DEF_HELPER_FLAGS_6(sve_sths_le_zsu, TCG_CALL_NO_WG, @@ -1793,4 +2011,71 @@ DEF_HELPER_FLAGS_6(sve_stdd_le_zd, TCG_CALL_NO_WG, DEF_HELPER_FLAGS_6(sve_stdd_be_zd, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr, tl, i32) =20 +DEF_HELPER_FLAGS_6(sve_stbs_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_sths_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_sths_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stss_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stss_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_6(sve_stbs_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_sths_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_sths_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stss_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stss_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_6(sve_stbd_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_sthd_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_sthd_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stsd_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stsd_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stdd_le_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stdd_be_zsu_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_6(sve_stbd_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_sthd_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_sthd_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stsd_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stsd_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stdd_le_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stdd_be_zss_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_6(sve_stbd_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_sthd_le_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_sthd_be_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stsd_le_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stsd_be_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stdd_le_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_6(sve_stdd_be_zd_mte, TCG_CALL_NO_WG, + void, env, ptr, ptr, ptr, tl, i32) + DEF_HELPER_FLAGS_4(sve2_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 7aca4ad3840..ad974c2cc57 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5354,7 +5354,8 @@ static target_ulong off_zd_d(void *reg, intptr_t reg_= ofs) static inline QEMU_ALWAYS_INLINE void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, target_ulong base, uint32_t desc, uintptr_t retaddr, - int esize, int msize, zreg_off_fn *off_fn, + uint32_t mtedesc, int esize, int msize, + zreg_off_fn *off_fn, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { @@ -5382,7 +5383,9 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, cpu_check_watchpoint(env_cpu(env), addr, msize, info.attrs, BP_MEM_READ, reta= ddr); } - /* TODO: MTE check */ + if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { + mte_check1(env, mtedesc, addr, retaddr); + } host_fn(&scratch, reg_off, info.host); } else { /* Element crosses the page boundary. */ @@ -5393,7 +5396,9 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, msize, info.attrs, BP_MEM_READ, retaddr); } - /* TODO: MTE check */ + if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { + mte_check1(env, mtedesc, addr, retaddr); + } tlb_fn(env, &scratch, reg_off, addr, retaddr); } } @@ -5406,20 +5411,53 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t= *vg, void *vm, memcpy(vd, &scratch, reg_max); } =20 +static inline QEMU_ALWAYS_INLINE +void sve_ld1_z_mte(CPUARMState *env, void *vd, uint64_t *vg, void *vm, + target_ulong base, uint32_t desc, uintptr_t retaddr, + int esize, int msize, zreg_off_fn *off_fn, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + /* Remove mtedesc from the normal sve descriptor. */ + desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* + * ??? TODO: For the 32-bit offset extractions, base + ofs cannot + * offset base entirely over the address space hole to change the + * pointer tag, or change the bit55 selector. So we could here + * examine TBI + TCMA like we do for sve_ldN_r_mte(). + */ + sve_ld1_z(env, vd, vg, vm, base, desc, retaddr, mtedesc, + esize, msize, off_fn, host_fn, tlb_fn); +} + #define DO_LD1_ZPZ_S(MEM, OFS, MSZ) \ void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, = \ void *vm, target_ulong base, uint32_t des= c) \ { = \ - sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, = \ + sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 0, 4, 1 << MSZ, = \ off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); = \ +} = \ +void HELPER(sve_ld##MEM##_##OFS##_mte)(CPUARMState *env, void *vd, void *v= g, \ + void *vm, target_ulong base, uint32_t desc) = \ +{ = \ + sve_ld1_z_mte(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, = \ + off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb);= \ } =20 #define DO_LD1_ZPZ_D(MEM, OFS, MSZ) \ void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, = \ void *vm, target_ulong base, uint32_t des= c) \ { = \ - sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, = \ + sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 0, 8, 1 << MSZ, = \ off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); = \ +} = \ +void HELPER(sve_ld##MEM##_##OFS##_mte)(CPUARMState *env, void *vd, void *v= g, \ + void *vm, target_ulong base, uint32_t desc) = \ +{ = \ + sve_ld1_z_mte(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, = \ + off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb);= \ } =20 DO_LD1_ZPZ_S(bsu, zsu, MO_8) @@ -5498,7 +5536,8 @@ DO_LD1_ZPZ_D(dd_be, zd, MO_64) static inline QEMU_ALWAYS_INLINE void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, target_ulong base, uint32_t desc, uintptr_t retaddr, - const int esz, const int msz, zreg_off_fn *off_fn, + uint32_t mtedesc, const int esz, const int msz, + zreg_off_fn *off_fn, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { @@ -5523,6 +5562,9 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t= *vg, void *vm, * Probe the first element, allowing faults. */ addr =3D base + (off_fn(vm, reg_off) << scale); + if (mtedesc) { + mte_check1(env, mtedesc, addr, retaddr); + } tlb_fn(env, vd, reg_off, addr, retaddr); =20 /* After any fault, zero the other elements. */ @@ -5555,7 +5597,11 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_= t *vg, void *vm, (env_cpu(env), addr, msize) & BP_MEM_READ)) { goto fault; } - /* TODO: MTE check. */ + if (mtedesc && + arm_tlb_mte_tagged(&info.attrs) && + !mte_probe1(env, mtedesc, addr)) { + goto fault; + } =20 host_fn(vd, reg_off, info.host); } @@ -5568,20 +5614,58 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64= _t *vg, void *vm, record_fault(env, reg_off, reg_max); } =20 -#define DO_LDFF1_ZPZ_S(MEM, OFS, MSZ) \ -void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, = \ - void *vm, target_ulong base, uint32_t d= esc) \ -{ = \ - sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_32, MSZ, = \ - off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); = \ +static inline QEMU_ALWAYS_INLINE +void sve_ldff1_z_mte(CPUARMState *env, void *vd, uint64_t *vg, void *vm, + target_ulong base, uint32_t desc, uintptr_t retaddr, + const int esz, const int msz, + zreg_off_fn *off_fn, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + /* Remove mtedesc from the normal sve descriptor. */ + desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* + * ??? TODO: For the 32-bit offset extractions, base + ofs cannot + * offset base entirely over the address space hole to change the + * pointer tag, or change the bit55 selector. So we could here + * examine TBI + TCMA like we do for sve_ldN_r_mte(). + */ + sve_ldff1_z(env, vd, vg, vm, base, desc, retaddr, mtedesc, + esz, msz, off_fn, host_fn, tlb_fn); } =20 -#define DO_LDFF1_ZPZ_D(MEM, OFS, MSZ) \ -void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, = \ - void *vm, target_ulong base, uint32_t d= esc) \ -{ = \ - sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_64, MSZ, = \ - off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); = \ +#define DO_LDFF1_ZPZ_S(MEM, OFS, MSZ) \ +void HELPER(sve_ldff##MEM##_##OFS) \ + (CPUARMState *env, void *vd, void *vg, \ + void *vm, target_ulong base, uint32_t desc) \ +{ \ + sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), 0, MO_32, MSZ, \ + off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \ +} \ +void HELPER(sve_ldff##MEM##_##OFS##_mte) \ + (CPUARMState *env, void *vd, void *vg, \ + void *vm, target_ulong base, uint32_t desc) \ +{ \ + sve_ldff1_z_mte(env, vd, vg, vm, base, desc, GETPC(), MO_32, MSZ, \ + off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb= ); \ +} + +#define DO_LDFF1_ZPZ_D(MEM, OFS, MSZ) \ +void HELPER(sve_ldff##MEM##_##OFS) \ + (CPUARMState *env, void *vd, void *vg, \ + void *vm, target_ulong base, uint32_t desc) \ +{ \ + sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), 0, MO_64, MSZ, \ + off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \ +} \ +void HELPER(sve_ldff##MEM##_##OFS##_mte) \ + (CPUARMState *env, void *vd, void *vg, \ + void *vm, target_ulong base, uint32_t desc) \ +{ \ + sve_ldff1_z_mte(env, vd, vg, vm, base, desc, GETPC(), MO_64, MSZ, \ + off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb= ); \ } =20 DO_LDFF1_ZPZ_S(bsu, zsu, MO_8) @@ -5653,7 +5737,8 @@ DO_LDFF1_ZPZ_D(dd_be, zd, MO_64) static inline QEMU_ALWAYS_INLINE void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, target_ulong base, uint32_t desc, uintptr_t retaddr, - int esize, int msize, zreg_off_fn *off_fn, + uint32_t mtedesc, int esize, int msize, + zreg_off_fn *off_fn, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { @@ -5697,7 +5782,10 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t = *vg, void *vm, cpu_check_watchpoint(env_cpu(env), addr, msize, info.attrs, BP_MEM_WRITE, retaddr= ); } - /* TODO: MTE check. */ + + if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { + mte_check1(env, mtedesc, addr, retaddr); + } } i +=3D 1; reg_off +=3D esize; @@ -5727,20 +5815,53 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t= *vg, void *vm, } while (reg_off < reg_max); } =20 -#define DO_ST1_ZPZ_S(MEM, OFS, MSZ) \ -void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, = \ - void *vm, target_ulong base, uint32_t des= c) \ -{ = \ - sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, = \ - off_##OFS##_s, sve_st1##MEM##_host, sve_st1##MEM##_tlb); = \ +static inline QEMU_ALWAYS_INLINE +void sve_st1_z_mte(CPUARMState *env, void *vd, uint64_t *vg, void *vm, + target_ulong base, uint32_t desc, uintptr_t retaddr, + int esize, int msize, zreg_off_fn *off_fn, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + /* Remove mtedesc from the normal sve descriptor. */ + desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* + * ??? TODO: For the 32-bit offset extractions, base + ofs cannot + * offset base entirely over the address space hole to change the + * pointer tag, or change the bit55 selector. So we could here + * examine TBI + TCMA like we do for sve_ldN_r_mte(). + */ + sve_st1_z(env, vd, vg, vm, base, desc, retaddr, mtedesc, + esize, msize, off_fn, host_fn, tlb_fn); } =20 -#define DO_ST1_ZPZ_D(MEM, OFS, MSZ) \ -void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, = \ +#define DO_ST1_ZPZ_S(MEM, OFS, MSZ) \ +void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \ void *vm, target_ulong base, uint32_t des= c) \ -{ = \ - sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, = \ - off_##OFS##_d, sve_st1##MEM##_host, sve_st1##MEM##_tlb); = \ +{ \ + sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 0, 4, 1 << MSZ, \ + off_##OFS##_s, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \ +} \ +void HELPER(sve_st##MEM##_##OFS##_mte)(CPUARMState *env, void *vd, void *v= g, \ + void *vm, target_ulong base, uint32_t desc) \ +{ \ + sve_st1_z_mte(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \ + off_##OFS##_s, sve_st1##MEM##_host, sve_st1##MEM##_tlb);= \ +} + +#define DO_ST1_ZPZ_D(MEM, OFS, MSZ) \ +void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \ + void *vm, target_ulong base, uint32_t des= c) \ +{ \ + sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 0, 8, 1 << MSZ, \ + off_##OFS##_d, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \ +} \ +void HELPER(sve_st##MEM##_##OFS##_mte)(CPUARMState *env, void *vd, void *v= g, \ + void *vm, target_ulong base, uint32_t desc) \ +{ \ + sve_st1_z_mte(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \ + off_##OFS##_d, sve_st1##MEM##_host, sve_st1##MEM##_tlb);= \ } =20 DO_ST1_ZPZ_S(bs, zsu, MO_8) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 04eda9a1264..f318ca265f2 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5261,7 +5261,7 @@ static bool trans_ST_zpri(DisasContext *s, arg_rpri_s= tore *a) */ =20 static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, - int scale, TCGv_i64 scalar, int msz, + int scale, TCGv_i64 scalar, int msz, bool is_write, gen_helper_gvec_mem_scatter *fn) { unsigned vsz =3D vec_full_reg_size(s); @@ -5269,8 +5269,16 @@ static void do_mem_zpz(DisasContext *s, int zt, int = pg, int zm, TCGv_ptr t_pg =3D tcg_temp_new_ptr(); TCGv_ptr t_zt =3D tcg_temp_new_ptr(); TCGv_i32 t_desc; - int desc; + int desc =3D 0; =20 + if (s->mte_active[0]) { + desc =3D FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); + desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); + desc =3D FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz); + desc <<=3D SVE_MTEDESC_SHIFT; + } desc =3D simd_desc(vsz, vsz, scale); t_desc =3D tcg_const_i32(desc); =20 @@ -5285,176 +5293,339 @@ static void do_mem_zpz(DisasContext *s, int zt, i= nt pg, int zm, tcg_temp_free_i32(t_desc); } =20 -/* Indexed by [be][ff][xs][u][msz]. */ -static gen_helper_gvec_mem_scatter * const gather_load_fn32[2][2][2][2][3]= =3D { - /* Little-endian */ - { { { { gen_helper_sve_ldbss_zsu, - gen_helper_sve_ldhss_le_zsu, - NULL, }, - { gen_helper_sve_ldbsu_zsu, - gen_helper_sve_ldhsu_le_zsu, - gen_helper_sve_ldss_le_zsu, } }, - { { gen_helper_sve_ldbss_zss, - gen_helper_sve_ldhss_le_zss, - NULL, }, - { gen_helper_sve_ldbsu_zss, - gen_helper_sve_ldhsu_le_zss, - gen_helper_sve_ldss_le_zss, } } }, +/* Indexed by [mte][be][ff][xs][u][msz]. */ +static gen_helper_gvec_mem_scatter * const +gather_load_fn32[2][2][2][2][2][3] =3D { + { /* MTE Inactive */ + { /* Little-endian */ + { { { gen_helper_sve_ldbss_zsu, + gen_helper_sve_ldhss_le_zsu, + NULL, }, + { gen_helper_sve_ldbsu_zsu, + gen_helper_sve_ldhsu_le_zsu, + gen_helper_sve_ldss_le_zsu, } }, + { { gen_helper_sve_ldbss_zss, + gen_helper_sve_ldhss_le_zss, + NULL, }, + { gen_helper_sve_ldbsu_zss, + gen_helper_sve_ldhsu_le_zss, + gen_helper_sve_ldss_le_zss, } } }, =20 - /* First-fault */ - { { { gen_helper_sve_ldffbss_zsu, - gen_helper_sve_ldffhss_le_zsu, - NULL, }, - { gen_helper_sve_ldffbsu_zsu, - gen_helper_sve_ldffhsu_le_zsu, - gen_helper_sve_ldffss_le_zsu, } }, - { { gen_helper_sve_ldffbss_zss, - gen_helper_sve_ldffhss_le_zss, - NULL, }, - { gen_helper_sve_ldffbsu_zss, - gen_helper_sve_ldffhsu_le_zss, - gen_helper_sve_ldffss_le_zss, } } } }, + /* First-fault */ + { { { gen_helper_sve_ldffbss_zsu, + gen_helper_sve_ldffhss_le_zsu, + NULL, }, + { gen_helper_sve_ldffbsu_zsu, + gen_helper_sve_ldffhsu_le_zsu, + gen_helper_sve_ldffss_le_zsu, } }, + { { gen_helper_sve_ldffbss_zss, + gen_helper_sve_ldffhss_le_zss, + NULL, }, + { gen_helper_sve_ldffbsu_zss, + gen_helper_sve_ldffhsu_le_zss, + gen_helper_sve_ldffss_le_zss, } } } }, =20 - /* Big-endian */ - { { { { gen_helper_sve_ldbss_zsu, - gen_helper_sve_ldhss_be_zsu, - NULL, }, - { gen_helper_sve_ldbsu_zsu, - gen_helper_sve_ldhsu_be_zsu, - gen_helper_sve_ldss_be_zsu, } }, - { { gen_helper_sve_ldbss_zss, - gen_helper_sve_ldhss_be_zss, - NULL, }, - { gen_helper_sve_ldbsu_zss, - gen_helper_sve_ldhsu_be_zss, - gen_helper_sve_ldss_be_zss, } } }, + { /* Big-endian */ + { { { gen_helper_sve_ldbss_zsu, + gen_helper_sve_ldhss_be_zsu, + NULL, }, + { gen_helper_sve_ldbsu_zsu, + gen_helper_sve_ldhsu_be_zsu, + gen_helper_sve_ldss_be_zsu, } }, + { { gen_helper_sve_ldbss_zss, + gen_helper_sve_ldhss_be_zss, + NULL, }, + { gen_helper_sve_ldbsu_zss, + gen_helper_sve_ldhsu_be_zss, + gen_helper_sve_ldss_be_zss, } } }, =20 - /* First-fault */ - { { { gen_helper_sve_ldffbss_zsu, - gen_helper_sve_ldffhss_be_zsu, - NULL, }, - { gen_helper_sve_ldffbsu_zsu, - gen_helper_sve_ldffhsu_be_zsu, - gen_helper_sve_ldffss_be_zsu, } }, - { { gen_helper_sve_ldffbss_zss, - gen_helper_sve_ldffhss_be_zss, - NULL, }, - { gen_helper_sve_ldffbsu_zss, - gen_helper_sve_ldffhsu_be_zss, - gen_helper_sve_ldffss_be_zss, } } } }, + /* First-fault */ + { { { gen_helper_sve_ldffbss_zsu, + gen_helper_sve_ldffhss_be_zsu, + NULL, }, + { gen_helper_sve_ldffbsu_zsu, + gen_helper_sve_ldffhsu_be_zsu, + gen_helper_sve_ldffss_be_zsu, } }, + { { gen_helper_sve_ldffbss_zss, + gen_helper_sve_ldffhss_be_zss, + NULL, }, + { gen_helper_sve_ldffbsu_zss, + gen_helper_sve_ldffhsu_be_zss, + gen_helper_sve_ldffss_be_zss, } } } } }, + { /* MTE Active */ + { /* Little-endian */ + { { { gen_helper_sve_ldbss_zsu_mte, + gen_helper_sve_ldhss_le_zsu_mte, + NULL, }, + { gen_helper_sve_ldbsu_zsu_mte, + gen_helper_sve_ldhsu_le_zsu_mte, + gen_helper_sve_ldss_le_zsu_mte, } }, + { { gen_helper_sve_ldbss_zss_mte, + gen_helper_sve_ldhss_le_zss_mte, + NULL, }, + { gen_helper_sve_ldbsu_zss_mte, + gen_helper_sve_ldhsu_le_zss_mte, + gen_helper_sve_ldss_le_zss_mte, } } }, + + /* First-fault */ + { { { gen_helper_sve_ldffbss_zsu_mte, + gen_helper_sve_ldffhss_le_zsu_mte, + NULL, }, + { gen_helper_sve_ldffbsu_zsu_mte, + gen_helper_sve_ldffhsu_le_zsu_mte, + gen_helper_sve_ldffss_le_zsu_mte, } }, + { { gen_helper_sve_ldffbss_zss_mte, + gen_helper_sve_ldffhss_le_zss_mte, + NULL, }, + { gen_helper_sve_ldffbsu_zss_mte, + gen_helper_sve_ldffhsu_le_zss_mte, + gen_helper_sve_ldffss_le_zss_mte, } } } }, + + { /* Big-endian */ + { { { gen_helper_sve_ldbss_zsu_mte, + gen_helper_sve_ldhss_be_zsu_mte, + NULL, }, + { gen_helper_sve_ldbsu_zsu_mte, + gen_helper_sve_ldhsu_be_zsu_mte, + gen_helper_sve_ldss_be_zsu_mte, } }, + { { gen_helper_sve_ldbss_zss_mte, + gen_helper_sve_ldhss_be_zss_mte, + NULL, }, + { gen_helper_sve_ldbsu_zss_mte, + gen_helper_sve_ldhsu_be_zss_mte, + gen_helper_sve_ldss_be_zss_mte, } } }, + + /* First-fault */ + { { { gen_helper_sve_ldffbss_zsu_mte, + gen_helper_sve_ldffhss_be_zsu_mte, + NULL, }, + { gen_helper_sve_ldffbsu_zsu_mte, + gen_helper_sve_ldffhsu_be_zsu_mte, + gen_helper_sve_ldffss_be_zsu_mte, } }, + { { gen_helper_sve_ldffbss_zss_mte, + gen_helper_sve_ldffhss_be_zss_mte, + NULL, }, + { gen_helper_sve_ldffbsu_zss_mte, + gen_helper_sve_ldffhsu_be_zss_mte, + gen_helper_sve_ldffss_be_zss_mte, } } } } }, }; =20 /* Note that we overload xs=3D2 to indicate 64-bit offset. */ -static gen_helper_gvec_mem_scatter * const gather_load_fn64[2][2][3][2][4]= =3D { - /* Little-endian */ - { { { { gen_helper_sve_ldbds_zsu, - gen_helper_sve_ldhds_le_zsu, - gen_helper_sve_ldsds_le_zsu, - NULL, }, - { gen_helper_sve_ldbdu_zsu, - gen_helper_sve_ldhdu_le_zsu, - gen_helper_sve_ldsdu_le_zsu, - gen_helper_sve_lddd_le_zsu, } }, - { { gen_helper_sve_ldbds_zss, - gen_helper_sve_ldhds_le_zss, - gen_helper_sve_ldsds_le_zss, - NULL, }, - { gen_helper_sve_ldbdu_zss, - gen_helper_sve_ldhdu_le_zss, - gen_helper_sve_ldsdu_le_zss, - gen_helper_sve_lddd_le_zss, } }, - { { gen_helper_sve_ldbds_zd, - gen_helper_sve_ldhds_le_zd, - gen_helper_sve_ldsds_le_zd, - NULL, }, - { gen_helper_sve_ldbdu_zd, - gen_helper_sve_ldhdu_le_zd, - gen_helper_sve_ldsdu_le_zd, - gen_helper_sve_lddd_le_zd, } } }, +static gen_helper_gvec_mem_scatter * const +gather_load_fn64[2][2][2][3][2][4] =3D { + { /* MTE Inactive */ + { /* Little-endian */ + { { { gen_helper_sve_ldbds_zsu, + gen_helper_sve_ldhds_le_zsu, + gen_helper_sve_ldsds_le_zsu, + NULL, }, + { gen_helper_sve_ldbdu_zsu, + gen_helper_sve_ldhdu_le_zsu, + gen_helper_sve_ldsdu_le_zsu, + gen_helper_sve_lddd_le_zsu, } }, + { { gen_helper_sve_ldbds_zss, + gen_helper_sve_ldhds_le_zss, + gen_helper_sve_ldsds_le_zss, + NULL, }, + { gen_helper_sve_ldbdu_zss, + gen_helper_sve_ldhdu_le_zss, + gen_helper_sve_ldsdu_le_zss, + gen_helper_sve_lddd_le_zss, } }, + { { gen_helper_sve_ldbds_zd, + gen_helper_sve_ldhds_le_zd, + gen_helper_sve_ldsds_le_zd, + NULL, }, + { gen_helper_sve_ldbdu_zd, + gen_helper_sve_ldhdu_le_zd, + gen_helper_sve_ldsdu_le_zd, + gen_helper_sve_lddd_le_zd, } } }, =20 - /* First-fault */ - { { { gen_helper_sve_ldffbds_zsu, - gen_helper_sve_ldffhds_le_zsu, - gen_helper_sve_ldffsds_le_zsu, - NULL, }, - { gen_helper_sve_ldffbdu_zsu, - gen_helper_sve_ldffhdu_le_zsu, - gen_helper_sve_ldffsdu_le_zsu, - gen_helper_sve_ldffdd_le_zsu, } }, - { { gen_helper_sve_ldffbds_zss, - gen_helper_sve_ldffhds_le_zss, - gen_helper_sve_ldffsds_le_zss, - NULL, }, - { gen_helper_sve_ldffbdu_zss, - gen_helper_sve_ldffhdu_le_zss, - gen_helper_sve_ldffsdu_le_zss, - gen_helper_sve_ldffdd_le_zss, } }, - { { gen_helper_sve_ldffbds_zd, - gen_helper_sve_ldffhds_le_zd, - gen_helper_sve_ldffsds_le_zd, - NULL, }, - { gen_helper_sve_ldffbdu_zd, - gen_helper_sve_ldffhdu_le_zd, - gen_helper_sve_ldffsdu_le_zd, - gen_helper_sve_ldffdd_le_zd, } } } }, + /* First-fault */ + { { { gen_helper_sve_ldffbds_zsu, + gen_helper_sve_ldffhds_le_zsu, + gen_helper_sve_ldffsds_le_zsu, + NULL, }, + { gen_helper_sve_ldffbdu_zsu, + gen_helper_sve_ldffhdu_le_zsu, + gen_helper_sve_ldffsdu_le_zsu, + gen_helper_sve_ldffdd_le_zsu, } }, + { { gen_helper_sve_ldffbds_zss, + gen_helper_sve_ldffhds_le_zss, + gen_helper_sve_ldffsds_le_zss, + NULL, }, + { gen_helper_sve_ldffbdu_zss, + gen_helper_sve_ldffhdu_le_zss, + gen_helper_sve_ldffsdu_le_zss, + gen_helper_sve_ldffdd_le_zss, } }, + { { gen_helper_sve_ldffbds_zd, + gen_helper_sve_ldffhds_le_zd, + gen_helper_sve_ldffsds_le_zd, + NULL, }, + { gen_helper_sve_ldffbdu_zd, + gen_helper_sve_ldffhdu_le_zd, + gen_helper_sve_ldffsdu_le_zd, + gen_helper_sve_ldffdd_le_zd, } } } }, + { /* Big-endian */ + { { { gen_helper_sve_ldbds_zsu, + gen_helper_sve_ldhds_be_zsu, + gen_helper_sve_ldsds_be_zsu, + NULL, }, + { gen_helper_sve_ldbdu_zsu, + gen_helper_sve_ldhdu_be_zsu, + gen_helper_sve_ldsdu_be_zsu, + gen_helper_sve_lddd_be_zsu, } }, + { { gen_helper_sve_ldbds_zss, + gen_helper_sve_ldhds_be_zss, + gen_helper_sve_ldsds_be_zss, + NULL, }, + { gen_helper_sve_ldbdu_zss, + gen_helper_sve_ldhdu_be_zss, + gen_helper_sve_ldsdu_be_zss, + gen_helper_sve_lddd_be_zss, } }, + { { gen_helper_sve_ldbds_zd, + gen_helper_sve_ldhds_be_zd, + gen_helper_sve_ldsds_be_zd, + NULL, }, + { gen_helper_sve_ldbdu_zd, + gen_helper_sve_ldhdu_be_zd, + gen_helper_sve_ldsdu_be_zd, + gen_helper_sve_lddd_be_zd, } } }, =20 - /* Big-endian */ - { { { { gen_helper_sve_ldbds_zsu, - gen_helper_sve_ldhds_be_zsu, - gen_helper_sve_ldsds_be_zsu, - NULL, }, - { gen_helper_sve_ldbdu_zsu, - gen_helper_sve_ldhdu_be_zsu, - gen_helper_sve_ldsdu_be_zsu, - gen_helper_sve_lddd_be_zsu, } }, - { { gen_helper_sve_ldbds_zss, - gen_helper_sve_ldhds_be_zss, - gen_helper_sve_ldsds_be_zss, - NULL, }, - { gen_helper_sve_ldbdu_zss, - gen_helper_sve_ldhdu_be_zss, - gen_helper_sve_ldsdu_be_zss, - gen_helper_sve_lddd_be_zss, } }, - { { gen_helper_sve_ldbds_zd, - gen_helper_sve_ldhds_be_zd, - gen_helper_sve_ldsds_be_zd, - NULL, }, - { gen_helper_sve_ldbdu_zd, - gen_helper_sve_ldhdu_be_zd, - gen_helper_sve_ldsdu_be_zd, - gen_helper_sve_lddd_be_zd, } } }, + /* First-fault */ + { { { gen_helper_sve_ldffbds_zsu, + gen_helper_sve_ldffhds_be_zsu, + gen_helper_sve_ldffsds_be_zsu, + NULL, }, + { gen_helper_sve_ldffbdu_zsu, + gen_helper_sve_ldffhdu_be_zsu, + gen_helper_sve_ldffsdu_be_zsu, + gen_helper_sve_ldffdd_be_zsu, } }, + { { gen_helper_sve_ldffbds_zss, + gen_helper_sve_ldffhds_be_zss, + gen_helper_sve_ldffsds_be_zss, + NULL, }, + { gen_helper_sve_ldffbdu_zss, + gen_helper_sve_ldffhdu_be_zss, + gen_helper_sve_ldffsdu_be_zss, + gen_helper_sve_ldffdd_be_zss, } }, + { { gen_helper_sve_ldffbds_zd, + gen_helper_sve_ldffhds_be_zd, + gen_helper_sve_ldffsds_be_zd, + NULL, }, + { gen_helper_sve_ldffbdu_zd, + gen_helper_sve_ldffhdu_be_zd, + gen_helper_sve_ldffsdu_be_zd, + gen_helper_sve_ldffdd_be_zd, } } } } }, + { /* MTE Active */ + { /* Little-endian */ + { { { gen_helper_sve_ldbds_zsu_mte, + gen_helper_sve_ldhds_le_zsu_mte, + gen_helper_sve_ldsds_le_zsu_mte, + NULL, }, + { gen_helper_sve_ldbdu_zsu_mte, + gen_helper_sve_ldhdu_le_zsu_mte, + gen_helper_sve_ldsdu_le_zsu_mte, + gen_helper_sve_lddd_le_zsu_mte, } }, + { { gen_helper_sve_ldbds_zss_mte, + gen_helper_sve_ldhds_le_zss_mte, + gen_helper_sve_ldsds_le_zss_mte, + NULL, }, + { gen_helper_sve_ldbdu_zss_mte, + gen_helper_sve_ldhdu_le_zss_mte, + gen_helper_sve_ldsdu_le_zss_mte, + gen_helper_sve_lddd_le_zss_mte, } }, + { { gen_helper_sve_ldbds_zd_mte, + gen_helper_sve_ldhds_le_zd_mte, + gen_helper_sve_ldsds_le_zd_mte, + NULL, }, + { gen_helper_sve_ldbdu_zd_mte, + gen_helper_sve_ldhdu_le_zd_mte, + gen_helper_sve_ldsdu_le_zd_mte, + gen_helper_sve_lddd_le_zd_mte, } } }, =20 - /* First-fault */ - { { { gen_helper_sve_ldffbds_zsu, - gen_helper_sve_ldffhds_be_zsu, - gen_helper_sve_ldffsds_be_zsu, - NULL, }, - { gen_helper_sve_ldffbdu_zsu, - gen_helper_sve_ldffhdu_be_zsu, - gen_helper_sve_ldffsdu_be_zsu, - gen_helper_sve_ldffdd_be_zsu, } }, - { { gen_helper_sve_ldffbds_zss, - gen_helper_sve_ldffhds_be_zss, - gen_helper_sve_ldffsds_be_zss, - NULL, }, - { gen_helper_sve_ldffbdu_zss, - gen_helper_sve_ldffhdu_be_zss, - gen_helper_sve_ldffsdu_be_zss, - gen_helper_sve_ldffdd_be_zss, } }, - { { gen_helper_sve_ldffbds_zd, - gen_helper_sve_ldffhds_be_zd, - gen_helper_sve_ldffsds_be_zd, - NULL, }, - { gen_helper_sve_ldffbdu_zd, - gen_helper_sve_ldffhdu_be_zd, - gen_helper_sve_ldffsdu_be_zd, - gen_helper_sve_ldffdd_be_zd, } } } }, + /* First-fault */ + { { { gen_helper_sve_ldffbds_zsu_mte, + gen_helper_sve_ldffhds_le_zsu_mte, + gen_helper_sve_ldffsds_le_zsu_mte, + NULL, }, + { gen_helper_sve_ldffbdu_zsu_mte, + gen_helper_sve_ldffhdu_le_zsu_mte, + gen_helper_sve_ldffsdu_le_zsu_mte, + gen_helper_sve_ldffdd_le_zsu_mte, } }, + { { gen_helper_sve_ldffbds_zss_mte, + gen_helper_sve_ldffhds_le_zss_mte, + gen_helper_sve_ldffsds_le_zss_mte, + NULL, }, + { gen_helper_sve_ldffbdu_zss_mte, + gen_helper_sve_ldffhdu_le_zss_mte, + gen_helper_sve_ldffsdu_le_zss_mte, + gen_helper_sve_ldffdd_le_zss_mte, } }, + { { gen_helper_sve_ldffbds_zd_mte, + gen_helper_sve_ldffhds_le_zd_mte, + gen_helper_sve_ldffsds_le_zd_mte, + NULL, }, + { gen_helper_sve_ldffbdu_zd_mte, + gen_helper_sve_ldffhdu_le_zd_mte, + gen_helper_sve_ldffsdu_le_zd_mte, + gen_helper_sve_ldffdd_le_zd_mte, } } } }, + { /* Big-endian */ + { { { gen_helper_sve_ldbds_zsu_mte, + gen_helper_sve_ldhds_be_zsu_mte, + gen_helper_sve_ldsds_be_zsu_mte, + NULL, }, + { gen_helper_sve_ldbdu_zsu_mte, + gen_helper_sve_ldhdu_be_zsu_mte, + gen_helper_sve_ldsdu_be_zsu_mte, + gen_helper_sve_lddd_be_zsu_mte, } }, + { { gen_helper_sve_ldbds_zss_mte, + gen_helper_sve_ldhds_be_zss_mte, + gen_helper_sve_ldsds_be_zss_mte, + NULL, }, + { gen_helper_sve_ldbdu_zss_mte, + gen_helper_sve_ldhdu_be_zss_mte, + gen_helper_sve_ldsdu_be_zss_mte, + gen_helper_sve_lddd_be_zss_mte, } }, + { { gen_helper_sve_ldbds_zd_mte, + gen_helper_sve_ldhds_be_zd_mte, + gen_helper_sve_ldsds_be_zd_mte, + NULL, }, + { gen_helper_sve_ldbdu_zd_mte, + gen_helper_sve_ldhdu_be_zd_mte, + gen_helper_sve_ldsdu_be_zd_mte, + gen_helper_sve_lddd_be_zd_mte, } } }, + + /* First-fault */ + { { { gen_helper_sve_ldffbds_zsu_mte, + gen_helper_sve_ldffhds_be_zsu_mte, + gen_helper_sve_ldffsds_be_zsu_mte, + NULL, }, + { gen_helper_sve_ldffbdu_zsu_mte, + gen_helper_sve_ldffhdu_be_zsu_mte, + gen_helper_sve_ldffsdu_be_zsu_mte, + gen_helper_sve_ldffdd_be_zsu_mte, } }, + { { gen_helper_sve_ldffbds_zss_mte, + gen_helper_sve_ldffhds_be_zss_mte, + gen_helper_sve_ldffsds_be_zss_mte, + NULL, }, + { gen_helper_sve_ldffbdu_zss_mte, + gen_helper_sve_ldffhdu_be_zss_mte, + gen_helper_sve_ldffsdu_be_zss_mte, + gen_helper_sve_ldffdd_be_zss_mte, } }, + { { gen_helper_sve_ldffbds_zd_mte, + gen_helper_sve_ldffhds_be_zd_mte, + gen_helper_sve_ldffsds_be_zd_mte, + NULL, }, + { gen_helper_sve_ldffbdu_zd_mte, + gen_helper_sve_ldffhdu_be_zd_mte, + gen_helper_sve_ldffsdu_be_zd_mte, + gen_helper_sve_ldffdd_be_zd_mte, } } } } }, }; =20 static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a) { gen_helper_gvec_mem_scatter *fn =3D NULL; - int be =3D s->be_data =3D=3D MO_BE; + bool be =3D s->be_data =3D=3D MO_BE; + bool mte =3D s->mte_active[0]; =20 if (!sve_access_check(s)) { return true; @@ -5462,23 +5633,24 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1= _zprz *a) =20 switch (a->esz) { case MO_32: - fn =3D gather_load_fn32[be][a->ff][a->xs][a->u][a->msz]; + fn =3D gather_load_fn32[mte][be][a->ff][a->xs][a->u][a->msz]; break; case MO_64: - fn =3D gather_load_fn64[be][a->ff][a->xs][a->u][a->msz]; + fn =3D gather_load_fn64[mte][be][a->ff][a->xs][a->u][a->msz]; break; } assert(fn !=3D NULL); =20 do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, - cpu_reg_sp(s, a->rn), a->msz, fn); + cpu_reg_sp(s, a->rn), a->msz, false, fn); return true; } =20 static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) { gen_helper_gvec_mem_scatter *fn =3D NULL; - int be =3D s->be_data =3D=3D MO_BE; + bool be =3D s->be_data =3D=3D MO_BE; + bool mte =3D s->mte_active[0]; TCGv_i64 imm; =20 if (a->esz < a->msz || (a->esz =3D=3D a->msz && !a->u)) { @@ -5490,10 +5662,10 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1= _zpiz *a) =20 switch (a->esz) { case MO_32: - fn =3D gather_load_fn32[be][a->ff][0][a->u][a->msz]; + fn =3D gather_load_fn32[mte][be][a->ff][0][a->u][a->msz]; break; case MO_64: - fn =3D gather_load_fn64[be][a->ff][2][a->u][a->msz]; + fn =3D gather_load_fn64[mte][be][a->ff][2][a->u][a->msz]; break; } assert(fn !=3D NULL); @@ -5502,63 +5674,108 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD= 1_zpiz *a) * by loading the immediate into the scalar parameter. */ imm =3D tcg_const_i64(a->imm << a->msz); - do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, fn); + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, false, fn); tcg_temp_free_i64(imm); return true; } =20 -/* Indexed by [be][xs][msz]. */ -static gen_helper_gvec_mem_scatter * const scatter_store_fn32[2][2][3] =3D= { - /* Little-endian */ - { { gen_helper_sve_stbs_zsu, - gen_helper_sve_sths_le_zsu, - gen_helper_sve_stss_le_zsu, }, - { gen_helper_sve_stbs_zss, - gen_helper_sve_sths_le_zss, - gen_helper_sve_stss_le_zss, } }, - /* Big-endian */ - { { gen_helper_sve_stbs_zsu, - gen_helper_sve_sths_be_zsu, - gen_helper_sve_stss_be_zsu, }, - { gen_helper_sve_stbs_zss, - gen_helper_sve_sths_be_zss, - gen_helper_sve_stss_be_zss, } }, +/* Indexed by [mte][be][xs][msz]. */ +static gen_helper_gvec_mem_scatter * const scatter_store_fn32[2][2][2][3] = =3D { + { /* MTE Inactive */ + { /* Little-endian */ + { gen_helper_sve_stbs_zsu, + gen_helper_sve_sths_le_zsu, + gen_helper_sve_stss_le_zsu, }, + { gen_helper_sve_stbs_zss, + gen_helper_sve_sths_le_zss, + gen_helper_sve_stss_le_zss, } }, + { /* Big-endian */ + { gen_helper_sve_stbs_zsu, + gen_helper_sve_sths_be_zsu, + gen_helper_sve_stss_be_zsu, }, + { gen_helper_sve_stbs_zss, + gen_helper_sve_sths_be_zss, + gen_helper_sve_stss_be_zss, } } }, + { /* MTE Active */ + { /* Little-endian */ + { gen_helper_sve_stbs_zsu_mte, + gen_helper_sve_sths_le_zsu_mte, + gen_helper_sve_stss_le_zsu_mte, }, + { gen_helper_sve_stbs_zss_mte, + gen_helper_sve_sths_le_zss_mte, + gen_helper_sve_stss_le_zss_mte, } }, + { /* Big-endian */ + { gen_helper_sve_stbs_zsu_mte, + gen_helper_sve_sths_be_zsu_mte, + gen_helper_sve_stss_be_zsu_mte, }, + { gen_helper_sve_stbs_zss_mte, + gen_helper_sve_sths_be_zss_mte, + gen_helper_sve_stss_be_zss_mte, } } }, }; =20 /* Note that we overload xs=3D2 to indicate 64-bit offset. */ -static gen_helper_gvec_mem_scatter * const scatter_store_fn64[2][3][4] =3D= { - /* Little-endian */ - { { gen_helper_sve_stbd_zsu, - gen_helper_sve_sthd_le_zsu, - gen_helper_sve_stsd_le_zsu, - gen_helper_sve_stdd_le_zsu, }, - { gen_helper_sve_stbd_zss, - gen_helper_sve_sthd_le_zss, - gen_helper_sve_stsd_le_zss, - gen_helper_sve_stdd_le_zss, }, - { gen_helper_sve_stbd_zd, - gen_helper_sve_sthd_le_zd, - gen_helper_sve_stsd_le_zd, - gen_helper_sve_stdd_le_zd, } }, - /* Big-endian */ - { { gen_helper_sve_stbd_zsu, - gen_helper_sve_sthd_be_zsu, - gen_helper_sve_stsd_be_zsu, - gen_helper_sve_stdd_be_zsu, }, - { gen_helper_sve_stbd_zss, - gen_helper_sve_sthd_be_zss, - gen_helper_sve_stsd_be_zss, - gen_helper_sve_stdd_be_zss, }, - { gen_helper_sve_stbd_zd, - gen_helper_sve_sthd_be_zd, - gen_helper_sve_stsd_be_zd, - gen_helper_sve_stdd_be_zd, } }, +static gen_helper_gvec_mem_scatter * const scatter_store_fn64[2][2][3][4] = =3D { + { /* MTE Inactive */ + { /* Little-endian */ + { gen_helper_sve_stbd_zsu, + gen_helper_sve_sthd_le_zsu, + gen_helper_sve_stsd_le_zsu, + gen_helper_sve_stdd_le_zsu, }, + { gen_helper_sve_stbd_zss, + gen_helper_sve_sthd_le_zss, + gen_helper_sve_stsd_le_zss, + gen_helper_sve_stdd_le_zss, }, + { gen_helper_sve_stbd_zd, + gen_helper_sve_sthd_le_zd, + gen_helper_sve_stsd_le_zd, + gen_helper_sve_stdd_le_zd, } }, + { /* Big-endian */ + { gen_helper_sve_stbd_zsu, + gen_helper_sve_sthd_be_zsu, + gen_helper_sve_stsd_be_zsu, + gen_helper_sve_stdd_be_zsu, }, + { gen_helper_sve_stbd_zss, + gen_helper_sve_sthd_be_zss, + gen_helper_sve_stsd_be_zss, + gen_helper_sve_stdd_be_zss, }, + { gen_helper_sve_stbd_zd, + gen_helper_sve_sthd_be_zd, + gen_helper_sve_stsd_be_zd, + gen_helper_sve_stdd_be_zd, } } }, + { /* MTE Inactive */ + { /* Little-endian */ + { gen_helper_sve_stbd_zsu_mte, + gen_helper_sve_sthd_le_zsu_mte, + gen_helper_sve_stsd_le_zsu_mte, + gen_helper_sve_stdd_le_zsu_mte, }, + { gen_helper_sve_stbd_zss_mte, + gen_helper_sve_sthd_le_zss_mte, + gen_helper_sve_stsd_le_zss_mte, + gen_helper_sve_stdd_le_zss_mte, }, + { gen_helper_sve_stbd_zd_mte, + gen_helper_sve_sthd_le_zd_mte, + gen_helper_sve_stsd_le_zd_mte, + gen_helper_sve_stdd_le_zd_mte, } }, + { /* Big-endian */ + { gen_helper_sve_stbd_zsu_mte, + gen_helper_sve_sthd_be_zsu_mte, + gen_helper_sve_stsd_be_zsu_mte, + gen_helper_sve_stdd_be_zsu_mte, }, + { gen_helper_sve_stbd_zss_mte, + gen_helper_sve_sthd_be_zss_mte, + gen_helper_sve_stsd_be_zss_mte, + gen_helper_sve_stdd_be_zss_mte, }, + { gen_helper_sve_stbd_zd_mte, + gen_helper_sve_sthd_be_zd_mte, + gen_helper_sve_stsd_be_zd_mte, + gen_helper_sve_stdd_be_zd_mte, } } }, }; =20 static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a) { gen_helper_gvec_mem_scatter *fn; - int be =3D s->be_data =3D=3D MO_BE; + bool be =3D s->be_data =3D=3D MO_BE; + bool mte =3D s->mte_active[0]; =20 if (a->esz < a->msz || (a->msz =3D=3D 0 && a->scale)) { return false; @@ -5568,23 +5785,24 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1= _zprz *a) } switch (a->esz) { case MO_32: - fn =3D scatter_store_fn32[be][a->xs][a->msz]; + fn =3D scatter_store_fn32[mte][be][a->xs][a->msz]; break; case MO_64: - fn =3D scatter_store_fn64[be][a->xs][a->msz]; + fn =3D scatter_store_fn64[mte][be][a->xs][a->msz]; break; default: g_assert_not_reached(); } do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, - cpu_reg_sp(s, a->rn), a->msz, fn); + cpu_reg_sp(s, a->rn), a->msz, true, fn); return true; } =20 static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) { gen_helper_gvec_mem_scatter *fn =3D NULL; - int be =3D s->be_data =3D=3D MO_BE; + bool be =3D s->be_data =3D=3D MO_BE; + bool mte =3D s->mte_active[0]; TCGv_i64 imm; =20 if (a->esz < a->msz) { @@ -5596,10 +5814,10 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1= _zpiz *a) =20 switch (a->esz) { case MO_32: - fn =3D scatter_store_fn32[be][0][a->msz]; + fn =3D scatter_store_fn32[mte][be][0][a->msz]; break; case MO_64: - fn =3D scatter_store_fn64[be][2][a->msz]; + fn =3D scatter_store_fn64[mte][be][2][a->msz]; break; } assert(fn !=3D NULL); @@ -5608,7 +5826,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_z= piz *a) * by loading the immediate into the scalar parameter. */ imm =3D tcg_const_i64(a->imm << a->msz); - do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, fn); + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, true, fn); tcg_temp_free_i64(imm); return true; } --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593185916; cv=none; d=zohomail.com; s=zohoarc; b=dAwfZ4eqZ36fk0biQpR4/Oo1OYylCGVQJ9qi4qmjFIBWLszYXKR+gwjGYU9GOYEX10ggkG3z2snJXYGxgbrU7R7jaToO8jPu/0jChKytJYaVbA65DAZPMf8hp7TewqEeMV3cGrvAxJ3YJf6EBg/2pyvlF75JoO2G7Stl00Tedcc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593185916; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0oVfTOhMQ6Tde7hKNa/ourLtYXrK2B3QeNm/nMxWem8=; b=AIbX2vrSphHEfHFSMt33BLpI0mkVOlKWhU7EQWb6VyL8vOglw/tWv6F8qiCdoEapk42Gt6/duToCT23rcTicQH589RhTJ/i8IkGLbCeIgt+Bv96RV1MZ02WmGjkDH0Qmg9uCIDdHSqwx91y7hjpgDvp+bblOVRxO36ZBR5Vqis4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593185916802569.8322430319098; Fri, 26 Jun 2020 08:38:36 -0700 (PDT) Received: from localhost ([::1]:34114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqR1-0002gO-GG for importer@patchew.org; Fri, 26 Jun 2020 11:38:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36228) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4g-0003KZ-Gl for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:30 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:46453) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4e-0006jp-Kc for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:30 -0400 Received: by mail-wr1-x42c.google.com with SMTP id r12so9805957wrj.13 for ; Fri, 26 Jun 2020 08:15:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0oVfTOhMQ6Tde7hKNa/ourLtYXrK2B3QeNm/nMxWem8=; b=qkqfW5DWWVce1lt2gMkWTq63P2U/IlsJCEsJ+9vfWvJqhzA712wi57+DXM0ky4yZmF k7Rmwj8ojD2TeI0FKBIZJHmroIvyTEJ26BZjETbVSaG8rOFDJltxjbmFQmBeX7cZFG0g LSPUxyrCWag8gN6JqmRjSJEGOep+XQypwyUigkYYuJ9BVryveQHmgnz69Z7lK+Y5bEqn TM69nYosX1he6vXjnp5oH6QRFhcKcmGNqG67gk62nuOBinrWWX+rOUi4g/ToeoD/v7Na pGktQgXe94INIKwcnrWPU8iXmCHe0R0EHIfPwx2YZEU19etkhU0LeZkwTx1JHQlDr4lC fRIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0oVfTOhMQ6Tde7hKNa/ourLtYXrK2B3QeNm/nMxWem8=; b=gRhRB8YxqcJXdB61h64QMwahGkD68YCCkoXfUNBdVgoJkynoUAO7JmCX50S09SUJ8L D2BZ7Utgt2TVj+aRnyDXwDGkP27YlWYp9TY5YetbgAL4I0RIMCmTRZKJ16tR8ltR+qi3 4hbtVQqs2arJ/1/nOSzHWWlnKKK3uwtEiuOLBJGUIQBIos4BfIz+AvkTbmgo4j4fqHlr vsF27Qfyxa+tLD0v4xbjx4FTITX3aAaTOSlSr7DvJCwfpBvFwgipyhvwt7Qp5eaqpLbJ TmgAzhUWvzKXlHO480Lt4j4jVwNpJ+WoJmrhpJvvmUzWFECxDeoEBeYQZlqOry+nGIJ1 afYQ== X-Gm-Message-State: AOAM532NXToViRbBmbFIn6ZHBv02cQMdRE2wn3SOFSVpnYvh5pTSkqlG u8/OTbRR9DIrZENke1w7VsLRPfoOF9J8Yg== X-Google-Smtp-Source: ABdhPJy7U7eIeuCTerVABvOSikTiIMfjD1e/o9NWRGOfceLWauuzsNrozOzyVNCTTq7/26scAircHw== X-Received: by 2002:adf:de01:: with SMTP id b1mr4163979wrm.305.1593184526971; Fri, 26 Jun 2020 08:15:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 50/57] target/arm: Complete TBI clearing for user-only for SVE Date: Fri, 26 Jun 2020 16:14:17 +0100 Message-Id: <20200626151424.30117-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson There are a number of paths by which the TBI is still intact for user-only in the SVE helpers. Because we currently always set TBI for user-only, we do not need to pass down the actual TBI setting from above, and we can remove the top byte in the inner-most primitives, so that none are forgotten. Moreover, this keeps the "dirty" pointer around at the higher levels, where we need it for any MTE checking. Since the normal case, especially for user-only, goes through RAM, this clearing merely adds two insns per page lookup, which will be completely in the noise. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-39-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 3 +++ target/arm/sve_helper.c | 19 +++++++++++++++++-- target/arm/translate-a64.c | 5 +++++ 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d9876337c05..afe81e9b6c0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -203,6 +203,9 @@ static void arm_cpu_reset(DeviceState *dev) * Enable TBI0 and TBI1. While the real kernel only enables TBI0, * turning on both here will produce smaller code and otherwise * make no difference to the user-level emulation. + * + * In sve_probe_page, we assume that this is set. + * Do not modify this without other changes. */ env->cp15.tcr_el[1].raw_tcr =3D (3ULL << 37); #else diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index ad974c2cc57..382fa82bc8a 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -3966,14 +3966,16 @@ static void sve_##NAME##_host(void *vd, intptr_t re= g_off, void *host) \ static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,= \ target_ulong addr, uintptr_t ra) = \ { = \ - *(TYPEE *)(vd + H(reg_off)) =3D (TYPEM)TLB(env, addr, ra); = \ + *(TYPEE *)(vd + H(reg_off)) =3D = \ + (TYPEM)TLB(env, useronly_clean_ptr(addr), ra); = \ } =20 #define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \ static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,= \ target_ulong addr, uintptr_t ra) = \ { = \ - TLB(env, addr, (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); = \ + TLB(env, useronly_clean_ptr(addr), = \ + (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); = \ } =20 #define DO_LD_PRIM_1(NAME, H, TE, TM) \ @@ -4091,6 +4093,19 @@ static bool sve_probe_page(SVEHostPage *info, bool n= ofault, int flags; =20 addr +=3D mem_off; + + /* + * User-only currently always issues with TBI. See the comment + * above useronly_clean_ptr. Usually we clean this top byte away + * during translation, but we can't do that for e.g. vector + imm + * addressing modes. + * + * We currently always enable TBI for user-only, and do not provide + * a way to turn it off. So clean the pointer unconditionally here, + * rather than look it up here, or pass it down from above. + */ + addr =3D useronly_clean_ptr(addr); + flags =3D probe_access_flags(env, addr, access_type, mmu_idx, nofault, &info->host, retaddr); info->flags =3D flags; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e46c4a49e00..c20af6ee9d0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14634,6 +14634,11 @@ static void aarch64_tr_init_disas_context(DisasCon= textBase *dcbase, dc->features =3D env->features; dc->dcz_blocksize =3D arm_cpu->dcz_blocksize; =20 +#ifdef CONFIG_USER_ONLY + /* In sve_probe_page, we assume TBI is enabled. */ + tcg_debug_assert(dc->tbid & 1); +#endif + /* Single step state. The code-generation logic here is: * SS_ACTIVE =3D=3D 0: * generate code with no special handling for single-stepping (except --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593186297; cv=none; d=zohomail.com; s=zohoarc; b=SpPpxShPGfKw7XDUrtUCKLwxcevZSj6jXPvN3cziM8i348u6OrjLqAyIenPCg77t0UlPfAi+F5MP42BPFrEFFnwKVMS2h9xe5Wafq358umeNz0Lwf2b+KVtZ2E2ZOR08jlNbJJdDcq2kwVn1CuFcco1iX5qzV8uwJIPuvJ+xaTI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593186297; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YHSAI+M5IEuzEQaVNFGEaurDNFpxI355l7zrjOZ1Ak0=; b=e2iOJVJaL3+mAAIOZsCm1Ci/u7n+RME2BBiHQJjulQwAdZ21kDKWTePa8fvALVQAlEtV8pnBlOrmqf1x9salCz3lL7rz9NYAY0MCknM0pjqUTK0lh23mSnyV/+hBtSxGaKvpqO6301C/nXVnT75rxKVYiBCJjwZFLRMsktmsbH0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593186297576292.23872683964305; Fri, 26 Jun 2020 08:44:57 -0700 (PDT) Received: from localhost ([::1]:60618 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqXA-0005PR-DL for importer@patchew.org; Fri, 26 Jun 2020 11:44:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4i-0003Px-F9 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:32 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:38043) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4g-0006k6-FV for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:32 -0400 Received: by mail-wm1-x331.google.com with SMTP id f18so9721207wml.3 for ; Fri, 26 Jun 2020 08:15:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YHSAI+M5IEuzEQaVNFGEaurDNFpxI355l7zrjOZ1Ak0=; b=ANWIGvaue7AZ47hR7sNriXp/K53xsnf8bp9waIEulaBNR2DjbatLGa91enIC4z3TVS nCo1kaqYI60NA/+OOCKK3jouq0RZVApE1bg2IagV8fLmZMnkmRoDbCHJt+BBtgNXSrc4 fFmp27a0Nvo/YByonAbLDlxP8k905ZgD34eKExmzLS/QYpyXak66tzlUSUKMHukUMrfm hHNeNiNTQijIeSLCiFf4EiAOkwsI5TXj6J03pKdfisZlRFd12hU0hSBh5MZJKDSiSJoX XE3ENZELWmQccEE7IsmTfwvYy9dPt1+2JBzpXl9dJrI4tFZxXQkSWkezqOvnRP31N2N0 yGQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YHSAI+M5IEuzEQaVNFGEaurDNFpxI355l7zrjOZ1Ak0=; b=CiBmjOx6dCU5FdDGTaRiFZ3xXpPNoaFd5nrYmNiL77Knjfm85YppJ4i5FoSt52ejPr axYTTQUXI1xeE4tXh27LTUUTDCxPM8UJHhyBT1/ucdxyydVIJPO6al1lbQVQ7SqDgr3z lwSDMsejV0tC4laqij03fFjbycBUDqtRNs4HzLYHG2ZlOt3yGtLz4CJs9ib201trRpC5 cEUbmy/5SycZ6H1cwfFTUaVlfFOom/AQwpD6WPzxOHyaZuZZLGoOw7Zc5ANZkhkLzLbu 7uVjRm6kjXDqdAr07Nq9pK1wp908wGnFwJBjGzgZehCo4Sz3INVeG2Bq9UUgvHzReknE PpCg== X-Gm-Message-State: AOAM533Kto41djvGWy7BRtcSEFBaVD6IBWvylqoZCqVL7VYfZgX5mu/I AkD6swdxPol2KMxoMuEnFXpnJLiePqt2kQ== X-Google-Smtp-Source: ABdhPJxdHMzRafuKFxGgGOK4BtDlRjfDP4F39S4JRukTqa+/DUOCQphcKs0hj4tj+WIYV7q8x0N1WQ== X-Received: by 2002:a7b:c3c7:: with SMTP id t7mr3309338wmj.97.1593184528029; Fri, 26 Jun 2020 08:15:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 51/57] target/arm: Implement data cache set allocation tags Date: Fri, 26 Jun 2020 16:14:18 +0100 Message-Id: <20200626151424.30117-52-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is DC GVA and DC GZVA, and the tag check for DC ZVA. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-40-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 +++- target/arm/helper.c | 16 ++++++++++++++++ target/arm/translate-a64.c | 39 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3bf0518ca49..513c38970cc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2360,7 +2360,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpreg= id) #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 diff --git a/target/arm/helper.c b/target/arm/helper.c index 44a3f9fb480..23cf44fcf42 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6998,6 +6998,22 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_GVA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 3, + .access =3D PL0_W, .type =3D ARM_CP_DC_GVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode= */ + .accessfn =3D aa64_zva_access, +#endif + }, + { .name =3D "DC_GZVA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 4, + .access =3D PL0_W, .type =3D ARM_CP_DC_GZVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode= */ + .accessfn =3D aa64_zva_access, +#endif + }, REGINFO_SENTINEL }; =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c20af6ee9d0..73d753f11fb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1874,6 +1874,45 @@ static void handle_sys(DisasContext *s, uint32_t ins= n, bool isread, } gen_helper_dc_zva(cpu_env, tcg_rt); return; + case ARM_CP_DC_GVA: + { + TCGv_i64 clean_addr, tag; + + /* + * DC_GVA, like DC_ZVA, requires that we supply the original + * pointer for an invalid page. Probe that address first. + */ + tcg_rt =3D cpu_reg(s, rt); + clean_addr =3D clean_data_tbi(s, tcg_rt); + gen_probe_access(s, clean_addr, MMU_DATA_STORE, MO_8); + + if (s->ata) { + /* Extract the tag from the register to match STZGM. */ + tag =3D tcg_temp_new_i64(); + tcg_gen_shri_i64(tag, tcg_rt, 56); + gen_helper_stzgm_tags(cpu_env, clean_addr, tag); + tcg_temp_free_i64(tag); + } + } + return; + case ARM_CP_DC_GZVA: + { + TCGv_i64 clean_addr, tag; + + /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */ + tcg_rt =3D cpu_reg(s, rt); + clean_addr =3D clean_data_tbi(s, tcg_rt); + gen_helper_dc_zva(cpu_env, clean_addr); + + if (s->ata) { + /* Extract the tag from the register to match STZGM. */ + tag =3D tcg_temp_new_i64(); + tcg_gen_shri_i64(tag, tcg_rt, 56); + gen_helper_stzgm_tags(cpu_env, clean_addr, tag); + tcg_temp_free_i64(tag); + } + } + return; default: break; } --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593186072; cv=none; d=zohomail.com; s=zohoarc; b=a84xjwdUGHJKKyAICXxskXPcixKEjSZjZspqhtChDyUfkN/HMopS8Av2cWFITobMG/Okq6gFdCTQ3rBjMqFGDMN5B4HGNlyeE17xFObxKQ4q6mP+RpRgif2buXO8eD/+zxHCcE15bN3rFIjPvLJvFsIB9r/9RKhlRVTsPSrpm5k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593186072; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QI9bNB2EpS4MZeeUod3oWI+GTuJGD4bNcPhcROXkwsU=; b=PyB0dGvwqpNW20yZpoAjJWuo5zoOFsRn02K5XkHbfMK+2gJfnNlYurf9ExKiljrqJCMjciqu7omBj9ITo+qwPz4pew1vrBcfZUbzTH6StVlH6duzbFwHypzbcuvVQf98bgHUrhpLjS/Lo6u6FY0SyeoDKluVdNudMeI9Q4rU17A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159318607201034.13787792552023; Fri, 26 Jun 2020 08:41:12 -0700 (PDT) Received: from localhost ([::1]:43210 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqTW-0006ZF-FW for importer@patchew.org; Fri, 26 Jun 2020 11:41:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36268) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4j-0003TQ-FM for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:33 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:42037) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4h-0006kS-Pt for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:33 -0400 Received: by mail-wr1-x444.google.com with SMTP id o11so9851344wrv.9 for ; Fri, 26 Jun 2020 08:15:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QI9bNB2EpS4MZeeUod3oWI+GTuJGD4bNcPhcROXkwsU=; b=ioqI5UDsqy8wD18Qr6O9qqbqnZFfzrtpxQ4TGDEveTKHRP8aSK0tsTfzmvj/SE9XHc k+dITtsv+OKmiFimAXcsyu3fkdZyEPoXNNx1VXYoj1n19Xye4S1KAm29tadHbQh2IsWC 6N2fTz8Evo4sel7uZtoq+IMBL9MJ3jSRdf0bnY0XZHTqW6N/0Kk4nIh8WVPMUUdCKzkf EwPJ/+9ndwFMLYl7iqbbHu1WY9l4M/AL4f9AvuWt0oXnUKXiGjVAdk6VDUpIwtYUsmt5 ub/He9JimaCJE5/50+GXusxgduypksDxRhpGVPoR8TkX/HmAR2sjn2D7WsjNmQIEFwLT PsCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QI9bNB2EpS4MZeeUod3oWI+GTuJGD4bNcPhcROXkwsU=; b=qdg5OC3AIzr6qVygGoNdg+bltCIeivoY8c1BQpfHoPko14hZHFOfhdDdm24Lmf6oUl PayKaAFLuM2WdrrA63M6H42Q3uP3Cbf0qzkYYBEVcHqiD+28H+S/ntaoIOnklt1637Je vbHwMg5d942l7c4Tqs7ZlhoDSH3e8b2dr0kjLjihNPTXB4fvQD+00Ivk51vuTtYtElz9 e2JOvza8LeqL0PtwQ5QFd/vmfuUjvQ8zyDeQgZfqnCvaB7jA8eUdocbDFPw0X3hOIzwg YvrAhDwS8li+HvC1HOL8pa/i8+Nsg7ph1d7xY0CFpZl/zlDtWBFBlTtSj61kWUwmPEXl toIg== X-Gm-Message-State: AOAM531iHDDS+aqge1U5lRAusy63DGOgQLQkMtne5ND28ZUQVXBMiO6K F8BUvGWRW80/O2Xs5/iIxrrqj4v1ztnoSw== X-Google-Smtp-Source: ABdhPJx6cRpwV6zWFLeWLT0IruPvgsQPqP/rVQsMeCPX2Y7lEn/mCIGFW2FEAXSFp5Cf1yX/zbeaMw== X-Received: by 2002:adf:97d6:: with SMTP id t22mr4107725wrb.385.1593184530175; Fri, 26 Jun 2020 08:15:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 52/57] target/arm: Set PSTATE.TCO on exception entry Date: Fri, 26 Jun 2020 16:14:19 +0100 Message-Id: <20200626151424.30117-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson D1.10 specifies that exception handlers begin with tag checks overridden. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-41-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 23cf44fcf42..d220612a201 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9704,6 +9704,9 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) break; } } + if (cpu_isar_feature(aa64_mte, cpu)) { + new_mode |=3D PSTATE_TCO; + } =20 pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 =3D 1; --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593186106; cv=none; d=zohomail.com; s=zohoarc; b=GIoYcfFqQ0ClQVLqlJ5nsC2n/qW9mBJdb0RGW5fvof5P/DQSfkbpOPaS1ARu6Rad7jecOMzAxYrBPzphKCrSC9e9Ioblvq48JUfILQCAQ+mTLFV8CudIVEx3vbuEc5Caj37GvZvdkiNBjPwGZk8kUetq0BLM9VB2NVxhIeTeoYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593186106; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iTxcqRTY2S8VoqFThsxJvyU7UjcgzSkRiFgzJQqGrww=; b=nGCKDaL0YUxrw7pc0zdmv4jdKqES3b1uPP/gJ9mOvawbmB1GhbRSvSo99wwjuHnt/KD9yfiyQqRD/nhn367pyw2qJX/78yhmNtC6QN6FcD2+xWwFxHu6Fa6XENR4MFXFjuwIvpP/hxAcl0ZySOwoymPOeScVixWu2H8KMvqc+ao= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593186106822869.1706549593187; Fri, 26 Jun 2020 08:41:46 -0700 (PDT) Received: from localhost ([::1]:46722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqU5-0008Bw-GF for importer@patchew.org; Fri, 26 Jun 2020 11:41:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36292) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4l-0003YL-Cr for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:35 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:53876) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4j-0006ka-4p for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:35 -0400 Received: by mail-wm1-x32c.google.com with SMTP id j18so9160575wmi.3 for ; Fri, 26 Jun 2020 08:15:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=iTxcqRTY2S8VoqFThsxJvyU7UjcgzSkRiFgzJQqGrww=; b=RGeq8dywDLjUmhWT3hmpLLp3igIU7QmJZIU8kNAntX4nioDTEgdesdaphcOQje9hzt +SadvKuw1ejgzLS+3ljFK2X8xd+oYNwOOjZyAvCNLPtIJzNqDdse/5vIfIZ/nEGnvrWd sE3tmzu2d92EFqc2TrEpJoAKHj61T95dKBxWP2S2sap0ZadbZXnVXkqvahC8taEOrW13 LZ8a94rEch2u5mFuo5/DQpXOecrkQ2gyuI/Htvmq0uefYi98wYAptyJ3IOn5L0ethsBj u6hXYnLAYR9ruFn5sWyM0+wZmN3occwLDbU/BuSARHsqr4to6Se1rBV1bImf3fU9Up0p kw0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iTxcqRTY2S8VoqFThsxJvyU7UjcgzSkRiFgzJQqGrww=; b=Puvb9bST/lFQnfbqBzEFJeo4sTQnC8Xxll1IpLXhtrXqKYVLPijeCJ+L01+ZTnNvP9 0OMxaiS1Ui/LxhVdHVppLbVOfyf6pVCX0sVAEyfqCykulTXMJBoQW6cRycrz5ubjCTOp scP2RNJrR0qfzx6qLccMjgSbbjEMbNgxsksCUcBwMoRbFFucbfppKcRWw4vOBwDk4VyY KdJnFNtt3RaUIywvv+ZL5eDG9yfCGjSmxUzaWhfE3BDL71du0UqLah7t+YxcO5msH4Os 6fStQsUwj8FTlUKzT0649MEsvWTuFmJ1JpGmxgOdf5eFUgx1Vmo1OJoGZ7NRJCdXVLkT Ka3w== X-Gm-Message-State: AOAM532XAlViNeNFixhOwmtIHf8K2O5m+OcgOHlh6h2NyVG9Uc+n6+j1 4RWzH9B4v2E+UywkhQVzk3mif8GQfbxYkw== X-Google-Smtp-Source: ABdhPJzmG9f8683z7PSB/p/cDCtbsWp7B19cGSdfuq4Gi4DZjecBUj2D9lr5bJe12u5piHZo6ObuHQ== X-Received: by 2002:a1c:d5:: with SMTP id 204mr3874988wma.174.1593184531457; Fri, 26 Jun 2020 08:15:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 53/57] target/arm: Always pass cacheattr to get_phys_addr Date: Fri, 26 Jun 2020 16:14:20 +0100 Message-Id: <20200626151424.30117-54-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We need to check the memattr of a page in order to determine whether it is Tagged for MTE. Between Stage1 and Stage2, this becomes simpler if we always collect this data, instead of occasionally being presented with NULL. Use the nonnull attribute to allow the compiler to check that all pointer arguments are non-null. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-42-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 3 ++- target/arm/helper.c | 60 ++++++++++++++++++++--------------------- target/arm/m_helper.c | 11 +++++--- target/arm/tlb_helper.c | 4 ++- 4 files changed, 42 insertions(+), 36 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3306c4f8292..ae99725d2b5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1294,7 +1294,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) + __attribute__((nonnull)); =20 void arm_log_exception(int idx); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index d220612a201..2072db2f92d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -44,7 +44,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_u= long address, bool s1_is_el0, hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs); + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) + __attribute__((nonnull)); #endif =20 static void switch_mode(CPUARMState *env, int mode); @@ -11101,19 +11102,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, = target_ulong address, arm_tlb_bti_gp(txattrs) =3D true; } =20 - if (cacheattrs !=3D NULL) { - if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { - cacheattrs->attrs =3D convert_stage2_attrs(env, - extract32(attrs, 0, 4= )); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx =3D extract32(attrs, 0, 3); - uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <=3D 7); - cacheattrs->attrs =3D extract64(mair, attrindx * 8, 8); - } - cacheattrs->shareability =3D extract32(attrs, 6, 2); + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + cacheattrs->attrs =3D convert_stage2_attrs(env, extract32(attrs, 0= , 4)); + } else { + /* Index into MAIR registers for cache attributes */ + uint8_t attrindx =3D extract32(attrs, 0, 3); + uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + assert(attrindx <=3D 7); + cacheattrs->attrs =3D extract64(mair, attrindx * 8, 8); } + cacheattrs->shareability =3D extract32(attrs, 6, 2); =20 *phys_ptr =3D descaddr; *page_size_ptr =3D page_size; @@ -11948,28 +11946,29 @@ bool get_phys_addr(CPUARMState *env, target_ulong= address, ret =3D get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_St= age2, mmu_idx =3D=3D ARMMMUIdx_E10_0, phys_ptr, attrs, &s2_prot, - page_size, fi, - cacheattrs !=3D NULL ? &cacheattrs2 := NULL); + page_size, fi, &cacheattrs2); fi->s2addr =3D ipa; /* Combine the S1 and S2 perms. */ *prot &=3D s2_prot; =20 - /* Combine the S1 and S2 cache attributes, if needed */ - if (!ret && cacheattrs !=3D NULL) { - if (env->cp15.hcr_el2 & HCR_DC) { - /* - * HCR.DC forces the first stage attributes to - * Normal Non-Shareable, - * Inner Write-Back Read-Allocate Write-Allocate, - * Outer Write-Back Read-Allocate Write-Allocate. - */ - cacheattrs->attrs =3D 0xff; - cacheattrs->shareability =3D 0; - } - *cacheattrs =3D combine_cacheattrs(*cacheattrs, cacheattrs= 2); + /* If S2 fails, return early. */ + if (ret) { + return ret; } =20 - return ret; + /* Combine the S1 and S2 cache attributes. */ + if (env->cp15.hcr_el2 & HCR_DC) { + /* + * HCR.DC forces the first stage attributes to + * Normal Non-Shareable, + * Inner Write-Back Read-Allocate Write-Allocate, + * Outer Write-Back Read-Allocate Write-Allocate. + */ + cacheattrs->attrs =3D 0xff; + cacheattrs->shareability =3D 0; + } + *cacheattrs =3D combine_cacheattrs(*cacheattrs, cacheattrs2); + return 0; } else { /* * For non-EL2 CPUs a stage1+stage2 translation is just stage = 1. @@ -12094,11 +12093,12 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState= *cs, vaddr addr, bool ret; ARMMMUFaultInfo fi =3D {}; ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); + ARMCacheAttrs cacheattrs =3D {}; =20 *attrs =3D (MemTxAttrs) {}; =20 ret =3D get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, - attrs, &prot, &page_size, &fi, NULL); + attrs, &prot, &page_size, &fi, &cacheattrs); =20 if (ret) { return -1; diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 5e8a795d202..036454234c7 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -187,12 +187,13 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t add= r, uint32_t value, hwaddr physaddr; int prot; ARMMMUFaultInfo fi =3D {}; + ARMCacheAttrs cacheattrs =3D {}; bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; int exc; bool exc_secure; =20 if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, NULL)) { + &attrs, &prot, &page_size, &fi, &cacheattrs)) { /* MPU/SAU lookup failed */ if (fi.type =3D=3D ARMFault_QEMU_SFault) { if (mode =3D=3D STACK_LAZYFP) { @@ -279,13 +280,14 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *des= t, uint32_t addr, hwaddr physaddr; int prot; ARMMMUFaultInfo fi =3D {}; + ARMCacheAttrs cacheattrs =3D {}; bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; int exc; bool exc_secure; uint32_t value; =20 if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, NULL)) { + &attrs, &prot, &page_size, &fi, &cacheattrs)) { /* MPU/SAU lookup failed */ if (fi.type =3D=3D ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, @@ -1928,6 +1930,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, V8M_SAttributes sattrs =3D {}; MemTxAttrs attrs =3D {}; ARMMMUFaultInfo fi =3D {}; + ARMCacheAttrs cacheattrs =3D {}; MemTxResult txres; target_ulong page_size; hwaddr physaddr; @@ -1945,8 +1948,8 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, "...really SecureFault with SFSR.INVEP\n"); return false; } - if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, - &physaddr, &attrs, &prot, &page_size, &fi, NULL)) { + if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &physaddr, + &attrs, &prot, &page_size, &fi, &cacheattrs)) { /* the MPU lookup failed */ env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_IACCVIOL_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secur= e); diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 522a6442a48..89d90465a32 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -166,6 +166,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, int prot, ret; MemTxAttrs attrs =3D {}; ARMMMUFaultInfo fi =3D {}; + ARMCacheAttrs cacheattrs =3D {}; =20 /* * Walk the page table and (if the mapping exists) add the page @@ -175,7 +176,8 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, */ ret =3D get_phys_addr(&cpu->env, address, access_type, core_to_arm_mmu_idx(&cpu->env, mmu_idx), - &phys_addr, &attrs, &prot, &page_size, &fi, NULL); + &phys_addr, &attrs, &prot, &page_size, + &fi, &cacheattrs); if (likely(!ret)) { /* * Map a single [sub]page. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This "bit" is a particular value of the page's MemAttr. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-43-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 48 ++++++++++++++++++++++++++++++++++++++--- target/arm/tlb_helper.c | 5 +++++ 2 files changed, 50 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2072db2f92d..dc9c29f998f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11834,9 +11834,19 @@ static uint8_t combine_cacheattr_nibble(uint8_t s1= , uint8_t s2) */ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) { - uint8_t s1lo =3D extract32(s1.attrs, 0, 4), s2lo =3D extract32(s2.attr= s, 0, 4); - uint8_t s1hi =3D extract32(s1.attrs, 4, 4), s2hi =3D extract32(s2.attr= s, 4, 4); + uint8_t s1lo, s2lo, s1hi, s2hi; ARMCacheAttrs ret; + bool tagged =3D false; + + if (s1.attrs =3D=3D 0xf0) { + tagged =3D true; + s1.attrs =3D 0xff; + } + + s1lo =3D extract32(s1.attrs, 0, 4); + s2lo =3D extract32(s2.attrs, 0, 4); + s1hi =3D extract32(s1.attrs, 4, 4); + s2hi =3D extract32(s2.attrs, 4, 4); =20 /* Combine shareability attributes (table D4-43) */ if (s1.shareability =3D=3D 2 || s2.shareability =3D=3D 2) { @@ -11884,6 +11894,11 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAt= trs s1, ARMCacheAttrs s2) } } =20 + /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */ + if (tagged && ret.attrs =3D=3D 0xff) { + ret.attrs =3D 0xf0; + } + return ret; } =20 @@ -11963,8 +11978,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong = address, * Normal Non-Shareable, * Inner Write-Back Read-Allocate Write-Allocate, * Outer Write-Back Read-Allocate Write-Allocate. + * Do not overwrite Tagged within attrs. */ - cacheattrs->attrs =3D 0xff; + if (cacheattrs->attrs !=3D 0xf0) { + cacheattrs->attrs =3D 0xff; + } cacheattrs->shareability =3D 0; } *cacheattrs =3D combine_cacheattrs(*cacheattrs, cacheattrs2); @@ -12029,6 +12047,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, /* Definitely a real MMU, not an MPU */ =20 if (regime_translation_disabled(env, mmu_idx)) { + uint64_t hcr; + uint8_t memattr; + /* * MMU disabled. S1 addresses within aa64 translation regimes are * still checked for bounds -- see AArch64.TranslateAddressS1Off. @@ -12066,6 +12087,27 @@ bool get_phys_addr(CPUARMState *env, target_ulong = address, *phys_ptr =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; *page_size =3D TARGET_PAGE_SIZE; + + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ + hcr =3D arm_hcr_el2_eff(env); + cacheattrs->shareability =3D 0; + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr =3D 0xff; /* Normal, WB, RWA */ + } + } else if (access_type =3D=3D MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr =3D 0xee; /* Normal, WT, RA, NT */ + } else { + memattr =3D 0x44; /* Normal, NC, No */ + } + cacheattrs->shareability =3D 2; /* outer sharable */ + } else { + memattr =3D 0x00; /* Device, nGnRnE */ + } + cacheattrs->attrs =3D memattr; return 0; } =20 diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 89d90465a32..b35dc8a0118 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -188,6 +188,11 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, phys_addr &=3D TARGET_PAGE_MASK; address &=3D TARGET_PAGE_MASK; } + /* Notice and record tagged memory. */ + if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs =3D=3D 0xf= 0) { + arm_tlb_mte_tagged(&attrs) =3D true; + } + tlb_set_page_with_attrs(cs, address, phys_addr, attrs, prot, mmu_idx, page_size); return true; --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593186210; cv=none; d=zohomail.com; s=zohoarc; b=OVGYwewa1mitAn6wOw7YW1EFv7ispKlrZKvrUZ2D3BUgDSfBruMiRsNQ/clfwVTApNU6CcnSXtUVfoSIoNUZWByMT0kc1/6lI5VYi9GOSw4CQuTUf6C98dwo6SjsMou8Xk39Qo/fHX3MljApAIg1F24o/58olHtOuzcGt4qhQKo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593186210; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h/3DnkQWRTMLrqyNSK2kflfIoP8tD7HC02FZ4qjgwGY=; b=USVNXXstZtHATFHJd6PXby/UaooA9bLgAghGRS2RpBlDFHs9+8pJS5UPe01Uf2/b6mDcanuxUkpxQPPPZiW3ZSUyabh+JqgJp9+NhEdmyyEkE4HFal08Gn1SAyWft8ENa5EO+r1TqwDrA19kLQv8uN3chYNInS5VQ3wk7/gn3Qk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593186210482847.6579017522404; Fri, 26 Jun 2020 08:43:30 -0700 (PDT) Received: from localhost ([::1]:54570 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqVi-0002vY-4w for importer@patchew.org; Fri, 26 Jun 2020 11:43:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36348) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4o-0003gi-F0 for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:38 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:35869) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4l-0006lZ-CA for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:38 -0400 Received: by mail-wm1-x332.google.com with SMTP id 17so9712872wmo.1 for ; Fri, 26 Jun 2020 08:15:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20200626033144.790098-44-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 6 ++++++ hw/arm/virt.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++-- target/arm/cpu.c | 52 +++++++++++++++++++++++++++++++++++++++++---- 3 files changed, 107 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 513c38970cc..cf99dcca9f3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -792,6 +792,10 @@ struct ARMCPU { /* MemoryRegion to use for secure physical accesses */ MemoryRegion *secure_memory; =20 + /* MemoryRegion to use for allocation tag accesses */ + MemoryRegion *tag_memory; + MemoryRegion *secure_tag_memory; + /* For v8M, pointer to the IDAU interface provided by board/SoC */ Object *idau; =20 @@ -2985,6 +2989,8 @@ typedef enum ARMMMUIdxBit { typedef enum ARMASIdx { ARMASIdx_NS =3D 0, ARMASIdx_S =3D 1, + ARMASIdx_TagNS =3D 2, + ARMASIdx_TagS =3D 3, } ARMASIdx; =20 /* Return the Exception Level targeted by debug exceptions. */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 402c362c144..22ce6d61998 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1390,8 +1390,19 @@ static void create_platform_bus(VirtMachineState *vm= s) sysbus_mmio_get_region(s, 0)); } =20 +static void create_tag_ram(MemoryRegion *tag_sysmem, + hwaddr base, hwaddr size, + const char *name) +{ + MemoryRegion *tagram =3D g_new(MemoryRegion, 1); + + memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); + memory_region_add_subregion(tag_sysmem, base / 32, tagram); +} + static void create_secure_ram(VirtMachineState *vms, - MemoryRegion *secure_sysmem) + MemoryRegion *secure_sysmem, + MemoryRegion *secure_tag_sysmem) { MemoryRegion *secram =3D g_new(MemoryRegion, 1); char *nodename; @@ -1409,6 +1420,10 @@ static void create_secure_ram(VirtMachineState *vms, qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); =20 + if (secure_tag_sysmem) { + create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-ta= g"); + } + g_free(nodename); } =20 @@ -1665,6 +1680,8 @@ static void machvirt_init(MachineState *machine) const CPUArchIdList *possible_cpus; MemoryRegion *sysmem =3D get_system_memory(); MemoryRegion *secure_sysmem =3D NULL; + MemoryRegion *tag_sysmem =3D NULL; + MemoryRegion *secure_tag_sysmem =3D NULL; int n, virt_max_cpus; bool firmware_loaded; bool aarch64 =3D true; @@ -1819,6 +1836,35 @@ static void machvirt_init(MachineState *machine) "secure-memory", &error_abort); } =20 + /* + * The cpu adds the property if and only if MemTag is supported. + * If it is, we must allocate the ram to back that up. + */ + if (object_property_find(cpuobj, "tag-memory", NULL)) { + if (!tag_sysmem) { + tag_sysmem =3D g_new(MemoryRegion, 1); + memory_region_init(tag_sysmem, OBJECT(machine), + "tag-memory", UINT64_MAX / 32); + + if (vms->secure) { + secure_tag_sysmem =3D g_new(MemoryRegion, 1); + memory_region_init(secure_tag_sysmem, OBJECT(machine), + "secure-tag-memory", UINT64_MAX / 3= 2); + + /* As with ram, secure-tag takes precedence over tag. = */ + memory_region_add_subregion_overlap(secure_tag_sysmem,= 0, + tag_sysmem, -1); + } + } + + object_property_set_link(cpuobj, OBJECT(tag_sysmem), + "tag-memory", &error_abort); + if (vms->secure) { + object_property_set_link(cpuobj, OBJECT(secure_tag_sysmem), + "secure-tag-memory", &error_abort= ); + } + } + qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); object_unref(cpuobj); } @@ -1857,10 +1903,15 @@ static void machvirt_init(MachineState *machine) create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); =20 if (vms->secure) { - create_secure_ram(vms, secure_sysmem); + create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); } =20 + if (tag_sysmem) { + create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, + machine->ram_size, "mach-virt.tag"); + } + vms->highmem_ecam &=3D vms->highmem && (!firmware_loaded || aarch64); =20 create_rtc(vms); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index afe81e9b6c0..5050e1843a8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1252,6 +1252,25 @@ void arm_cpu_post_init(Object *obj) if (kvm_enabled()) { kvm_arm_add_vcpu_properties(obj); } + +#ifndef CONFIG_USER_ONLY + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_mte, cpu)) { + object_property_add_link(obj, "tag-memory", + TYPE_MEMORY_REGION, + (Object **)&cpu->tag_memory, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { + object_property_add_link(obj, "secure-tag-memory", + TYPE_MEMORY_REGION, + (Object **)&cpu->secure_tag_memory, + qdev_prop_allow_set_link_before_reali= ze, + OBJ_PROP_LINK_STRONG); + } + } +#endif } =20 static void arm_cpu_finalizefn(Object *obj) @@ -1741,18 +1760,43 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); unsigned int smp_cpus =3D ms->smp.cpus; + bool has_secure =3D cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SEC= URITY); =20 - if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { - cs->num_ases =3D 2; + /* + * We must set cs->num_ases to the final value before + * the first call to cpu_address_space_init. + */ + if (cpu->tag_memory !=3D NULL) { + cs->num_ases =3D 3 + has_secure; + } else { + cs->num_ases =3D 1 + has_secure; + } =20 + if (has_secure) { if (!cpu->secure_memory) { cpu->secure_memory =3D cs->memory; } cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", cpu->secure_memory); - } else { - cs->num_ases =3D 1; } + + if (cpu->tag_memory !=3D NULL) { + cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", + cpu->tag_memory); + if (has_secure) { + cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", + cpu->secure_tag_memory); + } + } else if (cpu_isar_feature(aa64_mte, cpu)) { + /* + * Since there is no tag memory, we can't meaningfully support MTE + * to its fullest. To avoid problems later, when we would come to + * use the tag memory, downgrade support to insns only. + */ + cpu->isar.id_aa64pfr1 =3D + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); + } + cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); =20 /* No core_count specified, default to smp_cpus. */ --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593186093; cv=none; d=zohomail.com; s=zohoarc; b=BOTjdtx7b4T9d3RLMlTEjYAhSIH2UaxhHssAMoUw32sOAWX1uX/AFz0paIvFDJJ2xKm3oItjI83Gs8MzkUplzurJkYNvbJhEiql/mKvNx30fohtvis05CAK61Tcls554eJN0spmppIpLKf8SbjB2vYjjADr6rMPoRsFZAtPvx7o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593186093; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5+9scEeG4yNntnWLNUGiOItv0SsM9bx+/uT7ZxipYNE=; b=BvvJG5HnYJuXp/c6TRVM50/c4ubF8Fu9I70hy2FUmYThbE1MPtu66Z9S89XXGfJotOL299AzdTGfWhKTpSMeMcaZ3hDz2rsmfnTE6oEgCpHSOQpYU6XLpTIgTwBbi0xDuUGNZW3juC3PKThac6EPDp4n3ylxfjh+nhGblFsBH7M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593186093097833.8662822424384; Fri, 26 Jun 2020 08:41:33 -0700 (PDT) Received: from localhost ([::1]:45308 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqTr-0007d9-Nj for importer@patchew.org; Fri, 26 Jun 2020 11:41:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36362) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4o-0003ht-Tk for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:38 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:50443) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4m-0006mj-KM for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:38 -0400 Received: by mail-wm1-x32a.google.com with SMTP id l17so9183185wmj.0 for ; Fri, 26 Jun 2020 08:15:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5+9scEeG4yNntnWLNUGiOItv0SsM9bx+/uT7ZxipYNE=; b=oWYmYQvMhm/DdnJ0Ol2d5wxfA3yhLgtEhmOHDlWbwyRo0JAB8Ub1wvbxfDVcZfkzVc NTe0IEpwE39PPq7O+SpHXkrmgMycOcUgAiQPkIW94/1BUUZQPRxdNSfJAMyI98W2HUDv CnxkFw3f1jY0z7shh5hcso391TnhRPWzxcId8s84l9EzP1UI8te1RXuAQH3wV8Hilegv oorQS1hO7ODGDvuEcaTum3OTS6bZgIdpWgZM+3vzDfKVaDevItytRiMceFvGq93DUQL0 MdLloETPYFt+2bVFOGIeaLy+yQocva41LebZtoLL+1kYKa6NWwd06baGtKOFefWQa5IL kPug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5+9scEeG4yNntnWLNUGiOItv0SsM9bx+/uT7ZxipYNE=; b=drFi/sTZMbOQ/TslCG/RWukiN+clu8x1I+77DBMuBN+nFitVUCUEJoNlPDCjsVV5sr ymoHRMoKaC1KjHbHhsuKIJuAFHTsma7XdtSa+JlRMmiVBQnF0QddXyY5bbfUkaNGy/0F Vfzuh/ED3oJQNN4U4PedzHq+WBHKw/MLHkksbSGplecHJj2JeIHZUaq1tA97l5I9pt6D MWDK5A9CyqBamrQ0PHbhfeD+yoms7h1W/bN557859HDB1zjYPxFOmmqjjsJEuzSmBgiy /9+a9H0erniJ4V7bY5Ts07154Xft34CpuVgZXOfZtwsj+WbJv5VJmhzG6RVNwnMeeeK/ K3LA== X-Gm-Message-State: AOAM531F2EBsCNz9Z6j8OzzuHWGg27Bm36UgDVSt28fy2pU02DmGlXH5 3EEfhGptCHtMsFzHkfVNeYdk3LPdoGqE2g== X-Google-Smtp-Source: ABdhPJwCkn7IFkjfyT0dQ8MjnRd3/UlSUXokzEMiXwVTmLZaT8JokZ/mqBtOU201t68/F3uFMel7qA== X-Received: by 2002:a1c:4185:: with SMTP id o127mr3931727wma.8.1593184534754; Fri, 26 Jun 2020 08:15:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 56/57] target/arm: Add allocation tag storage for system mode Date: Fri, 26 Jun 2020 16:14:23 +0100 Message-Id: <20200626151424.30117-57-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Look up the physical address for the given virtual address, convert that to a tag physical address, and finally return the host address that backs it. Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-45-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/mte_helper.c | 131 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 4f9bd3add3d..5ea57d487a4 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/ram_addr.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" =20 @@ -74,8 +75,138 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, int ptr_size, MMUAccessType tag_access, int tag_size, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY /* Tag storage not implemented. */ return NULL; +#else + uintptr_t index; + CPUIOTLBEntry *iotlbentry; + int in_page, flags; + ram_addr_t ptr_ra; + hwaddr ptr_paddr, tag_paddr, xlat; + MemoryRegion *mr; + ARMASIdx tag_asi; + AddressSpace *tag_as; + void *host; + + /* + * Probe the first byte of the virtual address. This raises an + * exception for inaccessible pages, and resolves the virtual address + * into the softmmu tlb. + * + * When RA =3D=3D 0, this is for mte_probe1. The page is expected to = be + * valid. Indicate to probe_access_flags no-fault, then assert that + * we received a valid page. + */ + flags =3D probe_access_flags(env, ptr, ptr_access, ptr_mmu_idx, + ra =3D=3D 0, &host, ra); + assert(!(flags & TLB_INVALID_MASK)); + + /* + * Find the iotlbentry for ptr. This *must* be present in the TLB + * because we just found the mapping. + * TODO: Perhaps there should be a cputlb helper that returns a + * matching tlb entry + iotlb entry. + */ + index =3D tlb_index(env, ptr_mmu_idx, ptr); +# ifdef CONFIG_DEBUG_TCG + { + CPUTLBEntry *entry =3D tlb_entry(env, ptr_mmu_idx, ptr); + target_ulong comparator =3D (ptr_access =3D=3D MMU_DATA_LOAD + ? entry->addr_read + : tlb_addr_write(entry)); + g_assert(tlb_hit(comparator, ptr)); + } +# endif + iotlbentry =3D &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; + + /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ + if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) { + return NULL; + } + + /* + * If not backed by host ram, there is no tag storage: access unchecke= d. + * This is probably a guest os bug though, so log it. + */ + if (unlikely(flags & TLB_MMIO)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Page @ 0x%" PRIx64 " indicates Tagged Normal memory= " + "but is not backed by host ram\n", ptr); + return NULL; + } + + /* + * The Normal memory access can extend to the next page. E.g. a single + * 8-byte access to the last byte of a page will check only the last + * tag on the first page. + * Any page access exception has priority over tag check exception. + */ + in_page =3D -(ptr | TARGET_PAGE_MASK); + if (unlikely(ptr_size > in_page)) { + void *ignore; + flags |=3D probe_access_flags(env, ptr + in_page, ptr_access, + ptr_mmu_idx, ra =3D=3D 0, &ignore, ra); + assert(!(flags & TLB_INVALID_MASK)); + } + + /* Any debug exception has priority over a tag check exception. */ + if (unlikely(flags & TLB_WATCHPOINT)) { + int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; + assert(ra !=3D 0); + cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, + iotlbentry->attrs, wp, ra); + } + + /* + * Find the physical address within the normal mem space. + * The memory region lookup must succeed because TLB_MMIO was + * not set in the cputlb lookup above. + */ + mr =3D memory_region_from_host(host, &ptr_ra); + tcg_debug_assert(mr !=3D NULL); + tcg_debug_assert(memory_region_is_ram(mr)); + ptr_paddr =3D ptr_ra; + do { + ptr_paddr +=3D mr->addr; + mr =3D mr->container; + } while (mr); + + /* Convert to the physical address in tag space. */ + tag_paddr =3D ptr_paddr >> (LOG2_TAG_GRANULE + 1); + + /* Look up the address in tag space. */ + tag_asi =3D iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; + tag_as =3D cpu_get_address_space(env_cpu(env), tag_asi); + mr =3D address_space_translate(tag_as, tag_paddr, &xlat, NULL, + tag_access =3D=3D MMU_DATA_STORE, + iotlbentry->attrs); + + /* + * Note that @mr will never be NULL. If there is nothing in the addre= ss + * space at @tag_paddr, the translation will return the unallocated me= mory + * region. For our purposes, the result must be ram. + */ + if (unlikely(!memory_region_is_ram(mr))) { + /* ??? Failure is a board configuration error. */ + qemu_log_mask(LOG_UNIMP, + "Tag Memory @ 0x%" HWADDR_PRIx " not found for " + "Normal Memory @ 0x%" HWADDR_PRIx "\n", + tag_paddr, ptr_paddr); + return NULL; + } + + /* + * Ensure the tag memory is dirty on write, for migration. + * Tag memory can never contain code or display memory (vga). + */ + if (tag_access =3D=3D MMU_DATA_STORE) { + ram_addr_t tag_ra =3D memory_region_get_ram_addr(mr) + xlat; + cpu_physical_memory_set_dirty_flag(tag_ra, DIRTY_MEMORY_MIGRATION); + } + + return memory_region_get_ram_ptr(mr) + xlat; +#endif } =20 uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) --=20 2.20.1 From nobody Sat May 4 09:00:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593186290; cv=none; d=zohomail.com; s=zohoarc; b=Spm/fwzVfK4SlU0sLZZy/0iNUdmU2bdwBmlFhnJvlOYIPCa1j7t0U7Uv9itF102OWwkBz1CRxd98FTcYKU8NBICSUSEhPumllRY0ZkAsG/7l4D7pdB7KkjqD/NzAIpY8yIJ7whjWeLYwdAd2CfrG9GE18OizS8EGiW99LxU43wg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593186290; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uTu7OHovsUuRycqX60tPTOf1KxCYgUCqmiTf0JQrhhE=; b=Cu5ogFDgEGjponUAvOivK6VLADWZCAEj4C5xInbeDC48IMW8S9QsheMg1BrQJvJ/rJ5x+b3QYKOJoFRsSuCyPKRkZNw9pfpCdMD6ftFl2qsKsm5Zm+5DQTENnq9ek4bJya3v6Fq5CTYGv5qe5tt46pGjwmKAcjwSiIBrY+fp2qA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593186290248403.02500352958214; Fri, 26 Jun 2020 08:44:50 -0700 (PDT) Received: from localhost ([::1]:60174 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joqX2-0005D5-VQ for importer@patchew.org; Fri, 26 Jun 2020 11:44:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36380) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1joq4q-0003lG-Jk for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:40 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:45353) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1joq4n-0006nV-MO for qemu-devel@nongnu.org; Fri, 26 Jun 2020 11:15:40 -0400 Received: by mail-wr1-x442.google.com with SMTP id s10so9825365wrw.12 for ; Fri, 26 Jun 2020 08:15:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm37838852wrr.67.2020.06.26.08.15.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2020 08:15:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uTu7OHovsUuRycqX60tPTOf1KxCYgUCqmiTf0JQrhhE=; b=colkzIorq2oOsFQbS+gxoXgnDw0KuD3gCQI5SgWoj3LD1r6nBUFjLf4YdKsjnsS6YW JlE4+0EgreKWXcimb1LN3CFwOBFnIbCW99+6ByD18f6IG/yyv8CZsTHPCEq8cFwpI9V+ dMeZ1C0RuB5i7sNwRJyQRzm5D3h84gqWMyDhfc5SzJRRAUICufJO1vDPi3FeqSHqqjac um3+U6xDcTANHvtBhk59KuiPsHeTTzWT/rT6XDREqETaSoLc/yQjW68btc6e20hmVjvh JcxKpv8izdoAOyBa5oqM2FQW2D9I/V1rmc66dtUkNDsuXhvmUDxnF01VvGZ/VGTuhqfZ 2Afw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uTu7OHovsUuRycqX60tPTOf1KxCYgUCqmiTf0JQrhhE=; b=JA+IIIgMdAq0lYBSxSMZ8cXUfCU2P5EXoG/cGZ1kHT/DT43nwCIbAP1loewQByPR5t gqrNtVRSlNwSmuP7alydZolnUcYtla/Hser9CQyFxWTv6Z9JG4L2809VAepDldT1fPZ+ NluXib6jZ4Nb01Zxbu4EWgC//DeVUbOXHY1Np9jaxhBM2dlg9gmuf/boYYZkhxQZK6Q7 HmDyOfG+KPZtbiUivGGLq8UoBSNO/UBBh99Jazr1MK7uDGWxcoM6lCGmQE5WPzpmMU1I 68iNBGO4XaToS0AVVovlIrox2HpKwaeLNX30SJKy+XURM+w4MRAOYJaM9SeRMDDsxZrl 2gOw== X-Gm-Message-State: AOAM5323VFEG+Z2j8jla3BM58GWAuuVBsSQsCBwp/7so7qwDKXw+zlJm zzXe6tpzMFWOyGjGCu80zTLLiGJK0ZeQcA== X-Google-Smtp-Source: ABdhPJzP9Wz11R466OpgQIj+Twe84ndMwp38eWxzz+tZBSdy3rGUaD7D+rkBFx6M5GxEy1NATLu0GA== X-Received: by 2002:adf:f885:: with SMTP id u5mr4225800wrp.402.1593184536129; Fri, 26 Jun 2020 08:15:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 57/57] target/arm: Enable MTE Date: Fri, 26 Jun 2020 16:14:24 +0100 Message-Id: <20200626151424.30117-58-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200626151424.30117-1-peter.maydell@linaro.org> References: <20200626151424.30117-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We now implement all of the components of MTE, without actually supporting any tagged memory. All MTE instructions will work, trivially, so we can enable support. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-46-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a0c1d8894b7..a2f4733eed6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -654,6 +654,11 @@ static void aarch64_max_initfn(Object *obj) =20 t =3D cpu->isar.id_aa64pfr1; t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); + /* + * Begin with full support for MTE; will be downgraded to MTE=3D1 + * during realize if the board provides no tag memory. + */ + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 2); cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; --=20 2.20.1