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bh=QR/HakmSlchkW8rUsYtzabgqq8Ooc2VYeCjnvOodyD0=; b=SRRgL/ypEElCrDFN5OEuW0hzlkvgvczZsDBVSjbtGQ3dPQxzSTRIcFuovxET/sjm5VOheF A6rxyrDyOlkJ0+DLi/nkh7RRTy+x8xlY6CGWZ1R1uzXJ5HvYCoiBGvgJxwqxxQktymDYVv +JhQSpdwUpDvmYvwykoJCd4v9RcwvOY= X-MC-Unique: zMWRtc4GMnOfaMwHVydwxg-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, pbonzini@redhat.com, jean-philippe@linaro.org, bbhushan2@marvell.com, peterx@redhat.com Subject: [PATCH v6 5/5] hw/arm/virt: Let the virtio-iommu bypass MSIs Date: Fri, 26 Jun 2020 12:30:57 +0200 Message-Id: <20200626103057.11263-6-eric.auger@redhat.com> In-Reply-To: <20200626103057.11263-1-eric.auger@redhat.com> References: <20200626103057.11263-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" At the moment the virtio-iommu translates MSI transactions. This behavior is inherited from ARM SMMU. The virt machine code knows where the guest MSI doorbells are so we can easily declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that setting the guest will not map MSIs through the IOMMU and those transactions will be simply bypassed. Depending on which MSI controller is in use (ITS or GICV2M), we declare either: - the ITS interrupt translation space (ITS_base + 0x10000), containing the GITS_TRANSLATOR or - The GICV2M single frame, containing the MSI_SETSP_NS register. Signed-off-by: Eric Auger --- v5 -> v6: - do not hardcode doorbell base and size - removed Jean's R-b v3 -> v4: - use ':' as separators v2 -> v3: - Add a new value to VirtMSIControllerType v1 -> v2: - Test which MSI controller is instantiated - If GICV2M is in use, declare its doorbell as an MSI doorbell too --- include/hw/arm/virt.h | 7 +++++++ hw/arm/virt.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 31878ddc72..a18b6b397b 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -96,6 +96,12 @@ typedef enum VirtIOMMUType { VIRT_IOMMU_VIRTIO, } VirtIOMMUType; =20 +typedef enum VirtMSIControllerType { + VIRT_MSI_CTRL_NONE, + VIRT_MSI_CTRL_GICV2M, + VIRT_MSI_CTRL_ITS, +} VirtMSIControllerType; + typedef enum VirtGICType { VIRT_GIC_VERSION_MAX, VIRT_GIC_VERSION_HOST, @@ -136,6 +142,7 @@ typedef struct { OnOffAuto acpi; VirtGICType gic_version; VirtIOMMUType iommu; + VirtMSIControllerType msi_controller; uint16_t virtio_iommu_bdf; struct arm_boot_info bootinfo; MemMapEntry *memmap; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 402c362c14..5ba62d6568 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -602,6 +602,7 @@ static void create_its(VirtMachineState *vms) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base= ); =20 fdt_add_its_gic_node(vms); + vms->msi_controller =3D VIRT_MSI_CTRL_ITS; } =20 static void create_v2m(VirtMachineState *vms) @@ -622,6 +623,7 @@ static void create_v2m(VirtMachineState *vms) } =20 fdt_add_v2m_gic_node(vms); + vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; } =20 static void create_gic(VirtMachineState *vms) @@ -2149,8 +2151,36 @@ out: static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { + VirtMachineState *vms =3D VIRT_MACHINE(hotplug_dev); + if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { virt_memory_pre_plug(hotplug_dev, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { + hwaddr db_start =3D 0, db_end =3D 0; + char *resv_prop_str; + + switch (vms->msi_controller) { + case VIRT_MSI_CTRL_NONE: + return; + case VIRT_MSI_CTRL_ITS: + /* GITS_TRANSLATER page */ + db_start =3D base_memmap[VIRT_GIC_ITS].base + 0x10000; + db_end =3D base_memmap[VIRT_GIC_ITS].base + + base_memmap[VIRT_GIC_ITS].size - 1; + break; + case VIRT_MSI_CTRL_GICV2M: + /* MSI_SETSPI_NS page */ + db_start =3D base_memmap[VIRT_GIC_V2M].base; + db_end =3D db_start + base_memmap[VIRT_GIC_V2M].size - 1; + break; + } + resv_prop_str =3D g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", + db_start, db_end, + VIRTIO_IOMMU_RESV_MEM_T_MSI); + + qdev_prop_set_uint32(dev, "len-reserved-regions", 1); + qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str); + g_free(resv_prop_str); } } =20 --=20 2.20.1