From nobody Tue Feb 10 17:46:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1593143096; cv=none; d=zohomail.com; s=zohoarc; b=lpLlu8+VCl98IcvHK/VvydQubcwSFFaHCbYY4WTbSwFGUAz6ZJzgYc0RjuT2D1Th5s+dqEseYTl9aqEMJUZfTaP3YtwUmmd/HIPYXSYYGkXIICDEK/GNIdMSnM56Eo0DYFj7uIiSC5dbpDYAOubDfxHWnfF6uimUnLjo7PaPMAM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593143096; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HSjBCHwavjNr37NIxaEpavJpEI8ou/nda9kEqEE9VlM=; b=J3TvpmxhvMqsWFdxYmU3ItHeFKQDz39jnwKbHh5M/xrD+awFCDSGOAJ6yPwiksymft+dweMixtpIBVYFLWTqvPTLkU7SYlk+VsK6+wkAcIogwNzs45Uq1FlsBbzyDoAwpqBC1rEyRLLVzq8ysY0VF75k9dmeHGBu8TPh2mL8IG0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159314309684386.17447747574806; Thu, 25 Jun 2020 20:44:56 -0700 (PDT) Received: from localhost ([::1]:54284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jofIN-0006ao-B0 for importer@patchew.org; Thu, 25 Jun 2020 23:44:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42322) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jof68-0000Ay-LV for qemu-devel@nongnu.org; Thu, 25 Jun 2020 23:32:16 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:33140) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jof66-0001uU-In for qemu-devel@nongnu.org; Thu, 25 Jun 2020 23:32:16 -0400 Received: by mail-pl1-x644.google.com with SMTP id 35so3769852ple.0 for ; Thu, 25 Jun 2020 20:32:14 -0700 (PDT) Received: from localhost.localdomain (174-21-143-238.tukw.qwest.net. [174.21.143.238]) by smtp.gmail.com with ESMTPSA id y27sm1605256pgc.56.2020.06.25.20.32.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2020 20:32:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HSjBCHwavjNr37NIxaEpavJpEI8ou/nda9kEqEE9VlM=; b=miWWnPz5TKHVh/oD5UPi0M1GOkbPbVTeLTbRbcTS8bgzkBgBZs7w3Sg1qvqA0ZdhyO 7Zp4rEDoATiAm6kLy33kZjmLKYpUdvi4tdJFIf3Lq1o46Y4uGUhSUx+M1SMNjIUOXw0j MA8JsPxyhFAkWWG4Am/Wn0LPvlNrWHna4lZPDNGzu3kkIrF4/cRo9yiDJq7IsMFCsLGl 9BYrZi3Psr4vGiOHK7h7lmbXXr1HVC5IoJ9SVu9KD9WFr0YaMoyYr1eTxhtf/7UR8UDx 8UCkyk4ISQoakvFzDc7/PQa4YhGI2DIG67v4xKqBVDLoohHjfNMgr27yv156yZUMfw6y eFLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HSjBCHwavjNr37NIxaEpavJpEI8ou/nda9kEqEE9VlM=; b=YcyDrjTFNG05nIQDR/m+NMWOVNgCBzaUNIzswAKYfIQygPvJzCUQ9JoykCdG7PJKJU nPHn98z+C/OJMR3rXUQ5xUhTq4qyfexW9C8gwzRvX4XeZOcUJ3YficSCWuSIbJglitYb yAXgAvJT5SCTwPCp6oE3o9d8nSMotj4Lq26/+HjDz7o3KxbalfcMDFj2Yk2KEtHNmpO1 vmfn6mky6MNBHMRgvsu3bL19HGVsU0UUcwlMJ02JZR68sOE+2ijDTuczKxhH5PbgNpim m9Xq31k4Rnt8gPCVSSPDyNoHhUVcgGq/e5ax+46sLav6iZ6pPktX8ys78NBSebbEHdxz uIbw== X-Gm-Message-State: AOAM533SsNExnCT7YckYRFL0gx66eJDxCRbtJGHiPeKy1EZdx5IYqdFb lhtvMtcl/dPCg3ihh2n4PN0IHV1M6vg= X-Google-Smtp-Source: ABdhPJyk2/Yu6AAaHM5w0vB8R3JWjjoPoQn+/Eq5TlkIh3oVrYtUno91PrU9QiGQA6AC6hLipPseTw== X-Received: by 2002:a17:90a:a62:: with SMTP id o89mr1093458pjo.188.1593142332856; Thu, 25 Jun 2020 20:32:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 20/46] target/arm: Implement the access tag cache flushes Date: Thu, 25 Jun 2020 20:31:18 -0700 Message-Id: <20200626033144.790098-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200626033144.790098-1-richard.henderson@linaro.org> References: <20200626033144.790098-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, david.spickett@linaro.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Like the regular data cache flushes, these are nops within qemu. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v6: Split out and handle el0 cache ops properly. --- target/arm/helper.c | 65 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2c6ec244af..d8c31d03da 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6929,6 +6929,32 @@ static const ARMCPRegInfo mte_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, .type =3D ARM_CP_NO_RAW, .access =3D PL0_RW, .readfn =3D tco_read, .writefn =3D tco_write }, + { .name =3D "DC_IGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL1_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_IGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_IGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL1_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_IGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CIGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CIGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, REGINFO_SENTINEL }; =20 @@ -6938,6 +6964,43 @@ static const ARMCPRegInfo mte_tco_ro_reginfo[] =3D { .type =3D ARM_CP_CONST, .access =3D PL0_RW, }, REGINFO_SENTINEL }; + +static const ARMCPRegInfo mte_el0_cacheop_reginfo[] =3D { + { .name =3D "DC_CGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGVAP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGDVAP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGVADP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGDVADP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CIGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CIGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + REGINFO_SENTINEL +}; + #endif =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -8071,8 +8134,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) */ if (cpu_isar_feature(aa64_mte, cpu)) { define_arm_cp_regs(cpu, mte_reginfo); + define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { define_arm_cp_regs(cpu, mte_tco_ro_reginfo); + define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } #endif =20 --=20 2.25.1