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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id y27sm1605256pgc.56.2020.06.25.20.32.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2020 20:32:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2NZq7MwSZVbDTTVTgGqliRVuFgoYZu09YHrFiII9iDw=; b=RIb9kVzwYaarnoG6gExGMCaFZKMkcfeueM1HUKvdnlUI05Xyn97uZITOyyGBOlybRd VUtVeFdM2QMm+q3P3BMaUTgzAtyAS7fmS80KaZSk1wzTv5GgSdiv6fiHYxZuhssSDu0I AFFAfvJ/uCjRS6olsmcPpxW3rnFxpdeMm/+qJyWy/XgUUGQUczLt43OpwBm+cmjGE1+u y+eXTrqBuguHnmwj8oIznrHWQcFY6BAMUQcTvFjmIg/JcNCQF6IZ6okZcGqJHAzhwfzy IQ880rxwED1IJ4Zs5bKq6aBeZRYsSf41sxLLoyQGCLtP1fpp4nzlendCC6nSpFQfvkj2 pb9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2NZq7MwSZVbDTTVTgGqliRVuFgoYZu09YHrFiII9iDw=; b=VYkqZh6FeJTjjMM7S61GJcySQlh24eWm3Gvl3bp8pF64NpbiinLu7upR+OHykG/KDC N1Yph9yrkvDQ3L8NWN3ZB71U//Cb8cOi6qsWszqnmdZcVfjyEePQOVZhZN9qJ+VtwhpH /RkTgZ6Egu450kZD4/ei7jUC+oMwOqMygB/abW1PN623G+KWDHAsTcNJt8xPkffk8lZi kXS17aQNgzFdB9zgKGeONcyR3iE2+cH3wObkWNj1BhbpxzLSLeUMJnRZgBPn3ui45r6N HyGZWMtNihUj5bIZCNY3QkK4fWpfqbDB+hXXlDtkUvVYorQGnokiRWayaUJgKJAx1uS7 N0Gg== X-Gm-Message-State: AOAM533y+4oBIqkFpPqI77AsBGMFBs66nMJpnn53FXj/iMCrMV5QrqFE aqytiJko0Yb4inPlTB+fsKMCyCgWF7E= X-Google-Smtp-Source: ABdhPJyXsYxdwbFWStKVmmgP0q5uIDWqbb9khesvn9QjB8PRjw0jfsbC3n9DD1n+A1VqMxOJXaix+Q== X-Received: by 2002:a62:7883:: with SMTP id t125mr559197pfc.229.1593142325213; Thu, 25 Jun 2020 20:32:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 14/46] target/arm: Define arm_cpu_do_unaligned_access for user-only Date: Thu, 25 Jun 2020 20:31:12 -0700 Message-Id: <20200626033144.790098-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200626033144.790098-1-richard.henderson@linaro.org> References: <20200626033144.790098-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, david.spickett@linaro.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use the same code as system mode, so that we generate the same exception + syndrome for the unaligned access. For the moment, if MTE is enabled so that this path is reachable, this would generate a SIGSEGV in the user-only cpu_loop. Decoding the syndrome to produce the proper SIGBUS will be done later. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v8: Raise the normal data exception + syndrome. --- target/arm/cpu.c | 2 +- target/arm/tlb_helper.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e44e18062c..d9b8ec791e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2169,8 +2169,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->tlb_fill =3D arm_cpu_tlb_fill; cc->debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; -#if !defined(CONFIG_USER_ONLY) cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; +#if !defined(CONFIG_USER_ONLY) cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; cc->adjust_watchpoint_address =3D arm_adjust_watchpoint_address; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 7388494a55..522a6442a4 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -10,8 +10,6 @@ #include "internals.h" #include "exec/exec-all.h" =20 -#if !defined(CONFIG_USER_ONLY) - static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, bool same_el, bool ea, @@ -122,6 +120,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr va= ddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } =20 +#if !defined(CONFIG_USER_ONLY) + /* * arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort --=20 2.25.1