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charset="utf-8" Currently, all riscv machines except sifive_u have identical reset vector code implementations with memory addresses being different for all machines. They can be easily combined into a single function in common code. Move it to common function and let all the machines use the common function. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/boot.c | 45 +++++++++++++++++++++++++++++++++++++++++ hw/riscv/sifive_u.c | 1 - hw/riscv/spike.c | 41 +++---------------------------------- hw/riscv/virt.c | 40 +++--------------------------------- include/hw/riscv/boot.h | 2 ++ 5 files changed, 53 insertions(+), 76 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index adb421b91b68..482b78147993 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -26,8 +26,11 @@ #include "hw/loader.h" #include "hw/riscv/boot.h" #include "elf.h" +#include "sysemu/device_tree.h" #include "sysemu/qtest.h" =20 +#include + #if defined(TARGET_RISCV32) # define KERNEL_BOOT_ADDRESS 0x80400000 #else @@ -155,3 +158,45 @@ hwaddr riscv_load_initrd(const char *filename, uint64_= t mem_size, =20 return *start + size; } + +void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, + hwaddr rom_size, void *fdt) +{ + int i; + /* reset vector */ + uint32_t reset_vec[8] =3D { + 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ + 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ + 0xf1402573, /* csrr a0, mhartid */ +#if defined(TARGET_RISCV32) + 0x0182a283, /* lw t0, 24(t0) */ +#elif defined(TARGET_RISCV64) + 0x0182b283, /* ld t0, 24(t0) */ +#endif + 0x00028067, /* jr t0 */ + 0x00000000, + start_addr, /* start: .dword */ + 0x00000000, + /* dtb: */ + }; + + /* copy in the reset vector in little_endian byte order */ + for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { + reset_vec[i] =3D cpu_to_le32(reset_vec[i]); + } + rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), + rom_base, &address_space_memory); + + /* copy in the device tree */ + if (fdt_pack(fdt) || fdt_totalsize(fdt) > + rom_size - sizeof(reset_vec)) { + error_report("not enough space to store device-tree"); + exit(1); + } + qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); + rom_add_blob_fixed_as("mrom.fdt", fdt, fdt_totalsize(fdt), + rom_base + sizeof(reset_vec), + &address_space_memory); + + return; +} diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7d051e7c9299..395b21703ab4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -56,7 +56,6 @@ #include "sysemu/device_tree.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" =20 #include =20 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 3c87e04fdceb..c696077cbc16 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -41,9 +41,6 @@ #include "sysemu/device_tree.h" #include "sysemu/qtest.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" - -#include =20 #if defined(TARGET_RISCV32) # define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf" @@ -165,7 +162,6 @@ static void spike_board_init(MachineState *machine) MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); - int i; unsigned int smp_cpus =3D machine->smp.cpus; =20 /* Initialize SOC */ @@ -212,40 +208,9 @@ static void spike_board_init(MachineState *machine) } } =20 - /* reset vector */ - uint32_t reset_vec[8] =3D { - 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ - 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ - 0xf1402573, /* csrr a0, mhartid */ -#if defined(TARGET_RISCV32) - 0x0182a283, /* lw t0, 24(t0) */ -#elif defined(TARGET_RISCV64) - 0x0182b283, /* ld t0, 24(t0) */ -#endif - 0x00028067, /* jr t0 */ - 0x00000000, - memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */ - 0x00000000, - /* dtb: */ - }; - - /* copy in the reset vector in little_endian byte order */ - for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { - reset_vec[i] =3D cpu_to_le32(reset_vec[i]); - } - rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), - memmap[SPIKE_MROM].base, &address_space_memory); - - /* copy in the device tree */ - if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > - memmap[SPIKE_MROM].size - sizeof(reset_vec)) { - error_report("not enough space to store device-tree"); - exit(1); - } - qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); - rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), - memmap[SPIKE_MROM].base + sizeof(reset_vec), - &address_space_memory); + /* load the reset vector */ + riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].= base, + memmap[SPIKE_MROM].size, s->fdt); =20 /* initialize HTIF using symbols found in load_kernel */ htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(= 0)); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 616db6f5aced..8ec77e43de26 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -39,12 +39,9 @@ #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" =20 -#include - #if defined(TARGET_RISCV32) # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin" #else @@ -535,40 +532,9 @@ static void virt_machine_init(MachineState *machine) start_addr =3D virt_memmap[VIRT_FLASH].base; } =20 - /* reset vector */ - uint32_t reset_vec[8] =3D { - 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ - 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ - 0xf1402573, /* csrr a0, mhartid */ -#if defined(TARGET_RISCV32) - 0x0182a283, /* lw t0, 24(t0) */ -#elif defined(TARGET_RISCV64) - 0x0182b283, /* ld t0, 24(t0) */ -#endif - 0x00028067, /* jr t0 */ - 0x00000000, - start_addr, /* start: .dword */ - 0x00000000, - /* dtb: */ - }; - - /* copy in the reset vector in little_endian byte order */ - for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { - reset_vec[i] =3D cpu_to_le32(reset_vec[i]); - } - rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), - memmap[VIRT_MROM].base, &address_space_memory); - - /* copy in the device tree */ - if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > - memmap[VIRT_MROM].size - sizeof(reset_vec)) { - error_report("not enough space to store device-tree"); - exit(1); - } - qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); - rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), - memmap[VIRT_MROM].base + sizeof(reset_vec), - &address_space_memory); + /* load the reset vector */ + riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base, + virt_memmap[VIRT_MROM].size, s->fdt); =20 /* create PLIC hart topology configuration string */ plic_hart_config_len =3D (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpu= s; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 9daa98da08d7..3e9759c89aa2 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -35,5 +35,7 @@ target_ulong riscv_load_kernel(const char *kernel_filenam= e, symbol_fn_t sym_cb); hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, uint64_t kernel_entry, hwaddr *start); +void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base, + hwaddr rom_size, void *fdt); =20 #endif /* RISCV_BOOT_H */ --=20 2.26.2 From nobody Thu May 2 01:00:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="140958186" IronPort-SDR: tH0hzd/ENAuCUYSxmw0+pUoFHgy4xcIPZHlGbD5Jvaq5MaFfLdUy3OR416Z7VpTt6PBVdzsesA PpiEWoP1Em2O6eCeOU0jdlsZMN1xjp6Ww= IronPort-SDR: Yvg1hWvnnsDju+oMxECDP7Y6ONXVQsJiozGTUSDL6A2i3TGefqXRAmxfA5GYf8JQwR5IyxeBoQ I1ECTXx96Khg== WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM Date: Thu, 25 Jun 2020 17:33:12 -0700 Message-Id: <20200626003313.715355-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200626003313.715355-1-atish.patra@wdc.com> References: <20200626003313.715355-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=4399c1bdf=atish.patra@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/25 20:33:16 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , Atish Patra , Alistair Francis , Alexander Richardson , Palmer Dabbelt , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently, the fdt is copied to the ROM after the reset vector. The firmware has to copy it to DRAM. Instead of this, directly copy the device tree to a pre-computed dram address. The device tree load address should be as far as possible from kernel and initrd images. That's why it is kept at the end of the DRAM or 4GB whichever is lesser. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis --- hw/riscv/boot.c | 57 +++++++++++++++++++++++++++++------------ hw/riscv/sifive_u.c | 32 +++++++++++------------ hw/riscv/spike.c | 7 ++++- hw/riscv/virt.c | 7 ++++- include/hw/riscv/boot.h | 5 +++- 5 files changed, 71 insertions(+), 37 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 482b78147993..02c4018a8105 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -159,44 +159,67 @@ hwaddr riscv_load_initrd(const char *filename, uint64= _t mem_size, return *start + size; } =20 +hwaddr riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) +{ + hwaddr temp, fdt_addr; + hwaddr dram_end =3D dram_base + mem_size; + int fdtsize =3D fdt_totalsize(fdt); + + if (fdtsize <=3D 0) { + error_report("invalid device-tree"); + exit(1); + } + + /* + * We should put fdt as far as possible to avoid kernel/initrd overwri= ting + * its content. But it should be addressable by 32 bit system as well. + * Thus, put it at an aligned address that less than fdt size from end= of + * dram or 4GB whichever is lesser. + */ + temp =3D MIN(dram_end, 4096 * MiB); + fdt_addr =3D QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); + + fdt_pack(fdt); + /* copy in the device tree */ + qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); + + rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, + &address_space_memory); + + return fdt_addr; +} + void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, - hwaddr rom_size, void *fdt) + hwaddr rom_size, + hwaddr fdt_load_addr, void *fdt) { int i; /* reset vector */ - uint32_t reset_vec[8] =3D { - 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ - 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ + uint32_t reset_vec[10] =3D { + 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 0xf1402573, /* csrr a0, mhartid */ #if defined(TARGET_RISCV32) + 0x0202a583, /* lw a1, 32(t0) */ 0x0182a283, /* lw t0, 24(t0) */ #elif defined(TARGET_RISCV64) + 0x0202b583, /* ld a1, 32(t0) */ 0x0182b283, /* ld t0, 24(t0) */ #endif 0x00028067, /* jr t0 */ 0x00000000, start_addr, /* start: .dword */ 0x00000000, - /* dtb: */ + fdt_load_addr, /* fdt_laddr: .dword */ + 0x00000000, + /* fw_dyn: */ }; =20 /* copy in the reset vector in little_endian byte order */ - for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { + for (i =3D 0; i < ARRAY_SIZE(reset_vec); i++) { reset_vec[i] =3D cpu_to_le32(reset_vec[i]); } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_base, &address_space_memory); =20 - /* copy in the device tree */ - if (fdt_pack(fdt) || fdt_totalsize(fdt) > - rom_size - sizeof(reset_vec)) { - error_report("not enough space to store device-tree"); - exit(1); - } - qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); - rom_add_blob_fixed_as("mrom.fdt", fdt, fdt_totalsize(fdt), - rom_base + sizeof(reset_vec), - &address_space_memory); - return; } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 395b21703ab4..7d39a4e4ec6d 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -379,6 +379,7 @@ static void sifive_u_machine_init(MachineState *machine) MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); target_ulong start_addr =3D memmap[SIFIVE_U_DRAM].base; int i; + hwaddr fdt_load_addr; =20 /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_= SOC); @@ -450,40 +451,37 @@ static void sifive_u_machine_init(MachineState *machi= ne) } } =20 + /* Compute the fdt load address in dram */ + fdt_load_addr =3D riscv_load_fdt(memmap[SIFIVE_U_DRAM].base, + machine->ram_size, s->fdt); + /* reset vector */ - uint32_t reset_vec[8] =3D { + uint32_t reset_vec[11] =3D { s->msel, /* MSEL pin state */ - 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ - 0x01c28593, /* addi a1, t0, %pcrel_lo(1b)= */ + 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn)= */ 0xf1402573, /* csrr a0, mhartid */ #if defined(TARGET_RISCV32) + 0x0202a583, /* lw a1, 32(t0) */ 0x0182a283, /* lw t0, 24(t0) */ #elif defined(TARGET_RISCV64) - 0x0182e283, /* lwu t0, 24(t0) */ + 0x0202b583, /* ld a1, 32(t0) */ + 0x0182b283, /* ld t0, 24(t0) */ #endif 0x00028067, /* jr t0 */ 0x00000000, start_addr, /* start: .dword */ - /* dtb: */ + 0x00000000, + fdt_load_addr, /* fdt_laddr: .dword */ + 0x00000000, + /* fw_dyn: */ }; =20 /* copy in the reset vector in little_endian byte order */ - for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { + for (i =3D 0; i < ARRAY_SIZE(reset_vec); i++) { reset_vec[i] =3D cpu_to_le32(reset_vec[i]); } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), memmap[SIFIVE_U_MROM].base, &address_space_memor= y); - - /* copy in the device tree */ - if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > - memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { - error_report("not enough space to store device-tree"); - exit(1); - } - qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); - rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), - memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), - &address_space_memory); } =20 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index c696077cbc16..69f050c07e5a 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -163,6 +163,7 @@ static void spike_board_init(MachineState *machine) MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); unsigned int smp_cpus =3D machine->smp.cpus; + hwaddr fdt_load_addr; =20 /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, @@ -208,9 +209,13 @@ static void spike_board_init(MachineState *machine) } } =20 + /* Compute the fdt load address in dram */ + fdt_load_addr =3D riscv_load_fdt(memmap[SPIKE_DRAM].base, + machine->ram_size, s->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].= base, - memmap[SPIKE_MROM].size, s->fdt); + memmap[SPIKE_MROM].size, + fdt_load_addr, s->fdt); =20 /* initialize HTIF using symbols found in load_kernel */ htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(= 0)); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 8ec77e43de26..639e284fc2e3 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -478,6 +478,7 @@ static void virt_machine_init(MachineState *machine) char *plic_hart_config; size_t plic_hart_config_len; target_ulong start_addr =3D memmap[VIRT_DRAM].base; + hwaddr fdt_load_addr; int i; unsigned int smp_cpus =3D machine->smp.cpus; =20 @@ -532,9 +533,13 @@ static void virt_machine_init(MachineState *machine) start_addr =3D virt_memmap[VIRT_FLASH].base; } =20 + /* Compute the fdt load address in dram */ + fdt_load_addr =3D riscv_load_fdt(memmap[VIRT_DRAM].base, + machine->ram_size, s->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base, - virt_memmap[VIRT_MROM].size, s->fdt); + virt_memmap[VIRT_MROM].size, + fdt_load_addr, s->fdt); =20 /* create PLIC hart topology configuration string */ plic_hart_config_len =3D (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpu= s; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 3e9759c89aa2..f64fcadd2390 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -35,7 +35,10 @@ target_ulong riscv_load_kernel(const char *kernel_filena= me, symbol_fn_t sym_cb); hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, uint64_t kernel_entry, hwaddr *start); +hwaddr riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, + void *fdt); void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base, - hwaddr rom_size, void *fdt); + hwaddr rom_size, + hwaddr fdt_load_addr, void *fdt); =20 #endif /* RISCV_BOOT_H */ --=20 2.26.2 From nobody Thu May 2 01:00:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1593131793; cv=none; d=zohomail.com; s=zohoarc; b=UlXLWlx7LwtngJFa9PmhbfMfl5u+KvnItP6Wf9Fpma5mben+ASwW+exRbgG5zyzsWHS05Wr7kzVYXfHM3MLC997C9wEgRkavXgc7fCIwfMPgOyRsxKPysS2Zs43kTXDCAHpyGLuZ2HbnqZK0uXe+Xb8bDUzR3ueBBhdqld6In+E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593131793; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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IronPort-SDR: 072/+fqR03/AkprrcHIIjPJ4x+fOb9GqG7rcs9j7fIKu8pWd8HIeczREconsLNjOzcuL236f5I b5gx+fP3S1gBzkI9eOPk9VojI0pzNXshptj5sn2GRu87Z+MX3dlz8iLsGaojuoZAabjl+f7HVx I1FSkfm2F14np5ST83GUETiIK00o+5sc0ZV64ozWNufR3gaHh9UVMuNual37WC2bFrOyBJBRF4 X0jlAXSk00d61DUoDOQs8nqMgoA4zp6KL69UIAULnjPe1ptMth/Z/eByakGXLehhK9jVS98uax aHk= X-IronPort-AV: E=Sophos;i="5.75,281,1589212800"; d="scan'208";a="140958188" IronPort-SDR: OyVF0QaCY4UKxf2kKFwyP5a9SEW6kwBbScMHzAv/2ulmOdWYsytjdZWJ1WRmRsmpEP9hFTvyLP XfITLqGDuYOXN27LalMPTJUAoz1F/KhKU= IronPort-SDR: AoJ8ovwBwTnfAgQEPxKHcI66QVGTx0PvgGpKNhUWXlzHNEe2E76upl3A7yQxlzpeDJgvu+Emhi iGNHUQwpw89w== WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v3 3/3] riscv: Add opensbi firmware dynamic support Date: Thu, 25 Jun 2020 17:33:13 -0700 Message-Id: <20200626003313.715355-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200626003313.715355-1-atish.patra@wdc.com> References: <20200626003313.715355-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=4399c1bdf=atish.patra@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/25 20:33:16 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , Atish Patra , Alistair Francis , Alexander Richardson , Palmer Dabbelt , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" OpenSBI is the default firmware in Qemu and has various firmware loading options. Currently, qemu loader uses fw_jump which has a compile time pre-defined address where fdt & kernel image must reside. This puts a constraint on image size of the Linux kernel depending on the fdt location and available memory. However, fw_dynamic allows the loader to specify the next stage location (i.e. Linux kernel/U-boot) in memory and other configurable boot options available in OpenSBI. Add support for OpenSBI dynamic firmware loading support. This doesn't break existing setup and fw_jump will continue to work as it is. Any other firmware will continue to work without any issues as long as it doesn't expect anything specific from loader in "a2" register. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis --- hw/riscv/boot.c | 39 ++++++++++++++++++++-- hw/riscv/sifive_u.c | 15 +++++++-- hw/riscv/spike.c | 11 +++++-- hw/riscv/virt.c | 11 +++++-- include/hw/riscv/boot.h | 5 ++- include/hw/riscv/boot_opensbi.h | 58 +++++++++++++++++++++++++++++++++ 6 files changed, 130 insertions(+), 9 deletions(-) create mode 100644 include/hw/riscv/boot_opensbi.h diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 02c4018a8105..c96249c73c9f 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -25,6 +25,7 @@ #include "hw/boards.h" #include "hw/loader.h" #include "hw/riscv/boot.h" +#include "hw/riscv/boot_opensbi.h" #include "elf.h" #include "sysemu/device_tree.h" #include "sysemu/qtest.h" @@ -33,8 +34,10 @@ =20 #if defined(TARGET_RISCV32) # define KERNEL_BOOT_ADDRESS 0x80400000 +#define fw_dynamic_info_data(__val) cpu_to_le32(__val) #else # define KERNEL_BOOT_ADDRESS 0x80200000 +#define fw_dynamic_info_data(__val) cpu_to_le64(__val) #endif =20 void riscv_find_and_load_firmware(MachineState *machine, @@ -189,14 +192,45 @@ hwaddr riscv_load_fdt(hwaddr dram_base, uint64_t mem_= size, void *fdt) return fdt_addr; } =20 +void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size, + uint32_t reset_vec_size, uint64_t kernel_ent= ry) +{ + struct fw_dynamic_info dinfo; + uint64_t dinfo_len; + + dinfo.magic =3D fw_dynamic_info_data(FW_DYNAMIC_INFO_MAGIC_VALUE); + dinfo.version =3D fw_dynamic_info_data(FW_DYNAMIC_INFO_VERSION); + dinfo.next_mode =3D fw_dynamic_info_data(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo.next_addr =3D fw_dynamic_info_data(kernel_entry); + dinfo.options =3D 0; + dinfo.boot_hart =3D 0; + dinfo_len =3D sizeof(dinfo); + + /** + * copy the dynamic firmware info. This information is specific to + * OpenSBI but doesn't break any other firmware as long as they don't + * expect any certain value in "a2" register. + */ + if (dinfo_len > (rom_size - reset_vec_size)) { + error_report("not enough space to store dynamic firmware info"); + exit(1); + } + + rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, + rom_base + reset_vec_size, + &address_space_memory); +} + void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, - hwaddr rom_size, + hwaddr rom_size, uint64_t kernel_entry, hwaddr fdt_load_addr, void *fdt) { int i; + /* reset vector */ uint32_t reset_vec[10] =3D { 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ + 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 0xf1402573, /* csrr a0, mhartid */ #if defined(TARGET_RISCV32) 0x0202a583, /* lw a1, 32(t0) */ @@ -206,7 +240,6 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwadd= r rom_base, 0x0182b283, /* ld t0, 24(t0) */ #endif 0x00028067, /* jr t0 */ - 0x00000000, start_addr, /* start: .dword */ 0x00000000, fdt_load_addr, /* fdt_laddr: .dword */ @@ -220,6 +253,8 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwadd= r rom_base, } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_base, &address_space_memory); + riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec), + kernel_entry); =20 return; } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7d39a4e4ec6d..de25e9ceb0e7 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -380,6 +380,7 @@ static void sifive_u_machine_init(MachineState *machine) target_ulong start_addr =3D memmap[SIFIVE_U_DRAM].base; int i; hwaddr fdt_load_addr; + uint64_t kernel_entry; =20 /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_= SOC); @@ -436,7 +437,7 @@ static void sifive_u_machine_init(MachineState *machine) riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL); =20 if (machine->kernel_filename) { - uint64_t kernel_entry =3D riscv_load_kernel(machine->kernel_filena= me, + kernel_entry =3D riscv_load_kernel(machine->kernel_filename, NULL); =20 if (machine->initrd_filename) { @@ -449,6 +450,12 @@ static void sifive_u_machine_init(MachineState *machin= e) qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", end); } + } else { + /* + * If dynamic firmware is used, it doesn't know where is the next m= ode + * if kernel argument is not set. + */ + kernel_entry =3D 0; } =20 /* Compute the fdt load address in dram */ @@ -459,6 +466,7 @@ static void sifive_u_machine_init(MachineState *machine) uint32_t reset_vec[11] =3D { s->msel, /* MSEL pin state */ 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn)= */ + 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 0xf1402573, /* csrr a0, mhartid */ #if defined(TARGET_RISCV32) 0x0202a583, /* lw a1, 32(t0) */ @@ -468,7 +476,6 @@ static void sifive_u_machine_init(MachineState *machine) 0x0182b283, /* ld t0, 24(t0) */ #endif 0x00028067, /* jr t0 */ - 0x00000000, start_addr, /* start: .dword */ 0x00000000, fdt_load_addr, /* fdt_laddr: .dword */ @@ -482,6 +489,10 @@ static void sifive_u_machine_init(MachineState *machin= e) } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), memmap[SIFIVE_U_MROM].base, &address_space_memor= y); + + riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base, + memmap[SIFIVE_U_MROM].size, + sizeof(reset_vec), kernel_entry); } =20 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 69f050c07e5a..1ede1a28e6d4 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -164,6 +164,7 @@ static void spike_board_init(MachineState *machine) MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); unsigned int smp_cpus =3D machine->smp.cpus; hwaddr fdt_load_addr; + uint64_t kernel_entry; =20 /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, @@ -194,7 +195,7 @@ static void spike_board_init(MachineState *machine) htif_symbol_callback); =20 if (machine->kernel_filename) { - uint64_t kernel_entry =3D riscv_load_kernel(machine->kernel_filena= me, + kernel_entry =3D riscv_load_kernel(machine->kernel_filename, htif_symbol_callback); =20 if (machine->initrd_filename) { @@ -207,6 +208,12 @@ static void spike_board_init(MachineState *machine) qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", end); } + } else { + /* + * If dynamic firmware is used, it doesn't know where is the next m= ode + * if kernel argument is not set. + */ + kernel_entry =3D 0; } =20 /* Compute the fdt load address in dram */ @@ -214,7 +221,7 @@ static void spike_board_init(MachineState *machine) machine->ram_size, s->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].= base, - memmap[SPIKE_MROM].size, + memmap[SPIKE_MROM].size, kernel_entry, fdt_load_addr, s->fdt); =20 /* initialize HTIF using symbols found in load_kernel */ diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 639e284fc2e3..25ac984e99f0 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -479,6 +479,7 @@ static void virt_machine_init(MachineState *machine) size_t plic_hart_config_len; target_ulong start_addr =3D memmap[VIRT_DRAM].base; hwaddr fdt_load_addr; + uint64_t kernel_entry; int i; unsigned int smp_cpus =3D machine->smp.cpus; =20 @@ -510,7 +511,7 @@ static void virt_machine_init(MachineState *machine) memmap[VIRT_DRAM].base, NULL); =20 if (machine->kernel_filename) { - uint64_t kernel_entry =3D riscv_load_kernel(machine->kernel_filena= me, + kernel_entry =3D riscv_load_kernel(machine->kernel_filename, NULL); =20 if (machine->initrd_filename) { @@ -523,6 +524,12 @@ static void virt_machine_init(MachineState *machine) qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", end); } + } else { + /* + * If dynamic firmware is used, it doesn't know where is the next m= ode + * if kernel argument is not set. + */ + kernel_entry =3D 0; } =20 if (drive_get(IF_PFLASH, 0, 0)) { @@ -538,7 +545,7 @@ static void virt_machine_init(MachineState *machine) machine->ram_size, s->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base, - virt_memmap[VIRT_MROM].size, + virt_memmap[VIRT_MROM].size, kernel_entry, fdt_load_addr, s->fdt); =20 /* create PLIC hart topology configuration string */ diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f64fcadd2390..0ccfd2285888 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -37,8 +37,11 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t = mem_size, uint64_t kernel_entry, hwaddr *start); hwaddr riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); +void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size, + uint32_t reset_vec_size, + uint64_t kernel_entry); void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base, - hwaddr rom_size, + hwaddr rom_size, uint64_t kernel_entry, hwaddr fdt_load_addr, void *fdt); =20 #endif /* RISCV_BOOT_H */ diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensb= i.h new file mode 100644 index 000000000000..0d5ddd6c3daf --- /dev/null +++ b/include/hw/riscv/boot_opensbi.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Based on include/sbi/{fw_dynamic.h,sbi_scratch.h} from the OpenSBI proj= ect. + */ +#ifndef OPENSBI_H +#define OPENSBI_H + +/** Expected value of info magic ('OSBI' ascii string in hex) */ +#define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f + +/** Maximum supported info version */ +#define FW_DYNAMIC_INFO_VERSION 0x2 + +/** Possible next mode values */ +#define FW_DYNAMIC_INFO_NEXT_MODE_U 0x0 +#define FW_DYNAMIC_INFO_NEXT_MODE_S 0x1 +#define FW_DYNAMIC_INFO_NEXT_MODE_M 0x3 + +enum sbi_scratch_options { + /** Disable prints during boot */ + SBI_SCRATCH_NO_BOOT_PRINTS =3D (1 << 0), + /** Enable runtime debug prints */ + SBI_SCRATCH_DEBUG_PRINTS =3D (1 << 1), +}; + +/** Representation dynamic info passed by previous booting stage */ +struct fw_dynamic_info { + /** Info magic */ + target_long magic; + /** Info version */ + target_long version; + /** Next booting stage address */ + target_long next_addr; + /** Next booting stage mode */ + target_long next_mode; + /** Options for OpenSBI library */ + target_long options; + /** + * Preferred boot HART id + * + * It is possible that the previous booting stage uses same link + * address as the FW_DYNAMIC firmware. In this case, the relocation + * lottery mechanism can potentially overwrite the previous booting + * stage while other HARTs are still running in the previous booting + * stage leading to boot-time crash. To avoid this boot-time crash, + * the previous booting stage can specify last HART that will jump + * to the FW_DYNAMIC firmware as the preferred boot HART. + * + * To avoid specifying a preferred boot HART, the previous booting + * stage can set it to -1UL which will force the FW_DYNAMIC firmware + * to use the relocation lottery mechanism. + */ + target_long boot_hart; +}; + +#endif --=20 2.26.2