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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id p12sm17927642pfq.69.2020.06.23.12.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2020 12:37:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EytV8fA8967EnswtTLvmJxzReykydC3hrRXQ99z0dGM=; b=e6gDYDn0gmxtvtTgGpUYnVmDY5uJKHESXD0FgLsPzNcID1nk9Jbdxwu1P+nKW2vYu/ 9PLS1oj+7Ks94oYTWNd7ZUISfuBwyD+dWiCLSoUy7jTd0s9txkxdXXkfxKKMc+1yS11R nsVIGSiEj+xG35FOeAamccnUBWYrH8UKgPN+dILJgL8BtEwaqyuJ8C4j0521FF3Ttwyw 6yRD+F2R6Ps4Fev6rcrrtmKmM8ItMS8zkoBvEaeTt77Ud3jUGtjRDbXUA8dW+rjDQUCZ BncDmq/yaMoyMBmpbXMNjC/O5w08XPKSQKY4pW5+Z3vX1bxWi8Tqg539cGHfA2ZVwZ4n a5yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EytV8fA8967EnswtTLvmJxzReykydC3hrRXQ99z0dGM=; b=aI3R1e1LljR2yVB3bTE2Hr2rbSRM5FP/dboIgX0j4EntA7wd2+FNUCAuayWnPSUzdQ rkQNNm1lGnFV7xvluC8Di6g7vfLnH/1tTjJkqRZoAfwn4Fp0IIDRZHhhnovsrO2Wqm5W fpAokdtfoU5nNHxTAEijhJFD7DUNHB7YmEx/7kYBfgC7Xr2Y5muOBJ6HXfgXnMZfpG3u q7vmwFLMXQDhADTZq54mInPS+HEr25fxjMGqZF/YyCNx1saDcHKrp6NJuyoNF2hY+Fh9 fF/GVXDuZqYKcU6ZyVqgISaEFZKm1LFBMj01sI5W6hZBYKEpNDhTL6pT/5A8fiCR9QxL jI+w== X-Gm-Message-State: AOAM530hxJBTovNVUVvS6wZclgGmshRLmqV93cLZxHv0XIOY2mgJsaPs xqY8oQ/aSKgthE80tR+B9rQdK0OLVE4= X-Google-Smtp-Source: ABdhPJwXHfatEWojjQDpJGK6AxfeypDKuuscB+hTk3N+DYTMIx+YP0rO5mI3e0u3oTYCwCJZHaGyJQ== X-Received: by 2002:a17:90a:49c5:: with SMTP id l5mr25343641pjm.31.1592941077976; Tue, 23 Jun 2020 12:37:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 42/45] target/arm: Cache the Tagged bit for a page in MemTxAttrs Date: Tue, 23 Jun 2020 12:36:55 -0700 Message-Id: <20200623193658.623279-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200623193658.623279-1-richard.henderson@linaro.org> References: <20200623193658.623279-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, david.spickett@linaro.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This "bit" is a particular value of the page's MemAttr. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v6: Test HCR_EL2.{DC,DCT}; test Stage2 attributes. v8: Fill in cacheattrs for S1 disabled; retain tagging when combining attributes; set mte_tagging in arm_cpu_tlb_fill. --- target/arm/helper.c | 48 ++++++++++++++++++++++++++++++++++++++--- target/arm/tlb_helper.c | 5 +++++ 2 files changed, 50 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2072db2f92..e614d7c4bd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11834,9 +11834,19 @@ static uint8_t combine_cacheattr_nibble(uint8_t s1= , uint8_t s2) */ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) { - uint8_t s1lo =3D extract32(s1.attrs, 0, 4), s2lo =3D extract32(s2.attr= s, 0, 4); - uint8_t s1hi =3D extract32(s1.attrs, 4, 4), s2hi =3D extract32(s2.attr= s, 4, 4); + uint8_t s1lo, s2lo, s1hi, s2hi; ARMCacheAttrs ret; + bool tagged =3D false; + + if (s1.attrs =3D=3D 0xf0) { + tagged =3D true; + s1.attrs =3D 0xff; + } + + s1lo =3D extract32(s1.attrs, 0, 4); + s2lo =3D extract32(s2.attrs, 0, 4); + s1hi =3D extract32(s1.attrs, 4, 4); + s2hi =3D extract32(s2.attrs, 4, 4); =20 /* Combine shareability attributes (table D4-43) */ if (s1.shareability =3D=3D 2 || s2.shareability =3D=3D 2) { @@ -11884,6 +11894,11 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAt= trs s1, ARMCacheAttrs s2) } } =20 + /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */ + if (tagged && ret.attrs =3D=3D 0xff) { + ret.attrs =3D 0xf0; + } + return ret; } =20 @@ -11963,8 +11978,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong = address, * Normal Non-Shareable, * Inner Write-Back Read-Allocate Write-Allocate, * Outer Write-Back Read-Allocate Write-Allocate. + * Do not overwrite Tagged within attrs. */ - cacheattrs->attrs =3D 0xff; + if (cacheattrs->attrs !=3D 0xf0) { + cacheattrs->attrs =3D 0xff; + } cacheattrs->shareability =3D 0; } *cacheattrs =3D combine_cacheattrs(*cacheattrs, cacheattrs2); @@ -12029,6 +12047,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, /* Definitely a real MMU, not an MPU */ =20 if (regime_translation_disabled(env, mmu_idx)) { + uint64_t hcr; + uint8_t memattr; + /* * MMU disabled. S1 addresses within aa64 translation regimes are * still checked for bounds -- see AArch64.TranslateAddressS1Off. @@ -12066,6 +12087,27 @@ bool get_phys_addr(CPUARMState *env, target_ulong = address, *phys_ptr =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; *page_size =3D TARGET_PAGE_SIZE; + + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ + hcr =3D arm_hcr_el2_eff(env); + cacheattrs->shareability =3D 0; + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr =3D 0xff; /* Normal, WB, RWA */ + } + } else if (access_type =3D=3D MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr =3D 0xee; /* Normal, WT, RA, NT */ + } else { + memattr =3D 0x44; /* Normal, NC, No */ + } + cacheattrs->shareability =3D 2; /* outersharable */ + } else { + memattr =3D 0x00; /* Device, nGnRnE */ + } + cacheattrs->attrs =3D memattr; return 0; } =20 diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 89d90465a3..b35dc8a011 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -188,6 +188,11 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, phys_addr &=3D TARGET_PAGE_MASK; address &=3D TARGET_PAGE_MASK; } + /* Notice and record tagged memory. */ + if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs =3D=3D 0xf= 0) { + arm_tlb_mte_tagged(&attrs) =3D true; + } + tlb_set_page_with_attrs(cs, address, phys_addr, attrs, prot, mmu_idx, page_size); return true; --=20 2.25.1