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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id p12sm17927642pfq.69.2020.06.23.12.37.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2020 12:37:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x8aLnTbJaNLIaCAiz76x9Qe9dWMjhM4HvVRSF6yOJsA=; b=GcBxor4WIP3+Ief5TrQJb9n5RvCon3vQJ2ucPPEstnKSu09KllXQqe/uqHGlcNwZS1 s9Qgsx/L70jdi6kPCkVB5CtorO10gw9YUN8WPs+6ULapqxik9iSddip7Ge1GkZF+fmt5 QppPfqryLrj8N7YAkHn4BHHMxBvuXcnJgc9uOYa0B8VC5rCYaKNCZUr+STvLULPWUy23 9Si05+bPTMiHukfQe7oMx9x4o2moLspgti/zYOOwd0bFAT5J54l/BT1oFLIUT90H3i1P Ebhz7Bb3yogW5ZwPMbry1TmVUlthk8lUPwPDvBZRH46fCcpSeog7vJjNwUdczZ8AEyav lM4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x8aLnTbJaNLIaCAiz76x9Qe9dWMjhM4HvVRSF6yOJsA=; b=GwbrukYAJ0EzbIpw6cbP9tGQ6NLuP2dI+krsWhiuCcuNVwZPTqJMWLByAD8+/PaxWL XsejE6/fsGChEP7xriXKSAnqVI4+4QSf82LUFyWqU3lmyaAqUEC2Z5+DV4RmfGWo0L4O DH6lTwtq8Yg527x6aXHs7GTmnwwEcTRZvka0qb+7stt4Jsf3t5pK73QCFgi4Jn1TIKsV HHVaUy2iz6ixBNdFY9h6mQAnHedHhy1xQDEE00/7Wa7DkXCk2zvqXqqOYsHzwsYXSMt+ Z4IiQQjvLZHgFAjLeoUgbaAgyv4quahGh3S4BaTIGp/y/wdMBR4vmhqVUh9ss00VHTkW 3UDA== X-Gm-Message-State: AOAM533WPlCpDP7+aeZ9q9WtTRy3hLkjTduv2p4VpGMjC6Z1P58uB5Rj NTtmxTGWAWtnlaX6hU/QrTFOFpNNGtU= X-Google-Smtp-Source: ABdhPJxAXOL3kzfvM12NdWSHAj5gknsYnEeu3hRPpjcHoF56LzAwPqxoOoT5RU4fpvXa1MxB9E17kw== X-Received: by 2002:a17:902:aa92:: with SMTP id d18mr25328419plr.210.1592941069985; Tue, 23 Jun 2020 12:37:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 36/45] target/arm: Handle TBI for sve scalar + int memory ops Date: Tue, 23 Jun 2020 12:36:49 -0700 Message-Id: <20200623193658.623279-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200623193658.623279-1-richard.henderson@linaro.org> References: <20200623193658.623279-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, david.spickett@linaro.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We still need to handle tbi for user-only when mte is inactive. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.h | 1 + target/arm/translate-a64.c | 2 +- target/arm/translate-sve.c | 6 ++++-- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 781c441399..49e4865918 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -40,6 +40,7 @@ TCGv_ptr get_fpstatus_ptr(bool); bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); bool sve_access_check(DisasContext *s); +TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ec2295393d..f35b122ded 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -215,7 +215,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 sr= c) * of the write-back address. */ =20 -static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) +TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { TCGv_i64 clean =3D new_tmp_a64(s); #ifdef CONFIG_USER_ONLY diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index e4fbe48493..04eda9a126 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4587,9 +4587,8 @@ static void do_mem_zpa(DisasContext *s, int zt, int p= g, TCGv_i64 addr, * For e.g. LD4, there are not enough arguments to pass all 4 * registers as pointers, so encode the regno into the data field. * For consistency, do this even for LD1. - * TODO: mte_n check here while callers are updated. */ - if (mte_n && s->mte_active[0]) { + if (s->mte_active[0]) { int msz =3D dtype_msz(dtype); =20 desc =3D FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); @@ -4599,7 +4598,10 @@ static void do_mem_zpa(DisasContext *s, int zt, int = pg, TCGv_i64 addr, desc =3D FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz); desc =3D FIELD_DP32(desc, MTEDESC, TSIZE, mte_n << msz); desc <<=3D SVE_MTEDESC_SHIFT; + } else { + addr =3D clean_data_tbi(s, addr); } + desc =3D simd_desc(vsz, vsz, zt | desc); t_desc =3D tcg_const_i32(desc); t_pg =3D tcg_temp_new_ptr(); --=20 2.25.1