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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id p12sm17927642pfq.69.2020.06.23.12.37.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2020 12:37:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NYe9wQzTvXU1gjsTjXV8P2ixn5lgpDK0SgGpjLrcDR0=; b=WPUH2VKLEEYBsG5KUb4kK9nNqBasrgtb3aqkNwu4mkG/WDy+P47OCm0428D3zglfVj 1GxBCWKjEJTIT6GgTPIkmGzR94Wr6/1pCfneD3OgYGqIB/9TS7EecdSF5DB1dE9X7/oH kQhmdJR0km2UqY5o5/9xV0X7mFvaR/NKf9sXEfXHAe/3zhWTHUJXSO4MDW/pxa7lrR4h /oEjc1ElT4KYmWCuJgtftbk9B9thA7sqC9IEkn2J7jbZxvX1xNEdGY+tix4whtuPs48w +xQsj10ZW+E6h8WRRsYRXWmJfcaApFJypW6MdOdHvMLqdyZqnevvNzzEr5D0o2iEXAdC +H6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NYe9wQzTvXU1gjsTjXV8P2ixn5lgpDK0SgGpjLrcDR0=; b=b6LEth1B8Zhh8uOep2/0ZbbUuaLLpx226TECqLQ6LrIifOpP2CstZMnpBb+0bN7UXa 2vS9rt/dFIpZ0yy6QgIjgbgv6v20AGuFa/k6nWRhtarndF9Itj39aQTxQKptL4F5Ox30 hxD7Ptj+4iB1atqY3OVTY+SzRkTO9ecm2BidCotPhVsoTWtF/8f9FNK1HMbcuysNctpX U7HgKVa/3tRefg0W0n4AFeA5JQ4aGPtCkmXtTLEcIhvCtB2NpppVz92iOhtBmPXVs42g D4wf/aTDtFNJEAF2e6TQJU1lLQt4T/l2ri1dsvF+U/mt4qTCMI1sEOzJ5GLhVyy5//bt aBzw== X-Gm-Message-State: AOAM5330K8yNFTc+pHpPRN3y9iPIIX79onGEq9c6u/tWuZL1SMlFCaRB 3cVkCHCTOXw+iztg4ODJ/Si+S1EHHKo= X-Google-Smtp-Source: ABdhPJzQCDrIt4AmHE7pC6RKy87LhqtBo2hrmZ066XPUzMC8GtICCRsusIon2A6benO+BjbUjY68Dw== X-Received: by 2002:a17:902:7785:: with SMTP id o5mr25538572pll.288.1592941064799; Tue, 23 Jun 2020 12:37:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 32/45] target/arm: Add arm_tlb_bti_gp Date: Tue, 23 Jun 2020 12:36:45 -0700 Message-Id: <20200623193658.623279-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200623193658.623279-1-richard.henderson@linaro.org> References: <20200623193658.623279-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, david.spickett@linaro.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Introduce an lvalue macro to wrap target_tlb_bit0. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 13 +++++++++++++ target/arm/helper.c | 2 +- target/arm/translate-a64.c | 2 +- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a5d3b6c9ee..3121836bdc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3393,6 +3393,19 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *e= nv, unsigned regno) /* Shared between translate-sve.c and sve_helper.c. */ extern const uint64_t pred_esz_masks[4]; =20 +/* Helper for the macros below, validating the argument type. */ +static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) +{ + return x; +} + +/* + * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. + * Using these should be a bit more self-documenting than using the + * generic target bits directly. + */ +#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) + /* * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in diff --git a/target/arm/helper.c b/target/arm/helper.c index 33f902387b..44a3f9fb48 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11079,7 +11079,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, } /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.= */ if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { - txattrs->target_tlb_bit0 =3D true; + arm_tlb_bti_gp(txattrs) =3D true; } =20 if (cacheattrs !=3D NULL) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7e8263e86f..ec2295393d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14446,7 +14446,7 @@ static bool is_guarded_page(CPUARMState *env, Disas= Context *s) * table entry even for that case. */ return (tlb_hit(entry->addr_code, addr) && - env_tlb(env)->d[mmu_idx].iotlb[index].attrs.target_tlb_bit0); + arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs)); #endif } =20 --=20 2.25.1