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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id p12sm17927642pfq.69.2020.06.23.12.37.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2020 12:37:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U/osoVY2cvsT8TlettyawEwRpLG++nKPsyGP4nM5lYM=; b=flHIFlX1pqd4Y9suzINtaevGpr6NVNvFa3joi85YcAbiTz22HHnbl25cdAKIDBf+e6 IMR16j8bqywv1XyJgLLcnNTqg1fZlJddANOlkGQNs7EQpBsVAUIx9egnL19GLQi/0bth PiW2d+rK1audsV1hw+pEi2rP45QK8zllFzy7mqeqN4vup2bq+iNcZhmXcIKB3MSPuLMr uJg4ejgljRTkm96jeWD1hRfUHG9i4PDMiA7ErA/G1MjMnJHD32a6DhHyxGzfQl49lsKS I7r8+goU7HhidmKLtQm8CJByAo7zjeCncamcnvtAkt87A7yz0FQujynChVSppMTmYsn/ OM5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U/osoVY2cvsT8TlettyawEwRpLG++nKPsyGP4nM5lYM=; b=uRNQl/3H8g881qgw/w7VClo1CQZSPDP/b7eDA9Eyz2Yt4Az4n89vF/AAOpGPb57/5a is+ubz+eWChY8r+p7hwd3QcdmG2hCogb2K9ma7Xj5Qjh7ebhe6jqE7FeEDUmYeQ9aKyi sxMpTTNbvKFTN0Lx41kmfkJyogFS6SelB8IGNb5e+Mm4P/l7ki3y0YVimrRLxCKpyKkh mzGZFi0Lv+Xt9yHSyj/ehZOnoeWkWO13BoLhkZR/NGL2KiS8G/uTUYSgXul8MQcGHxfI rmn0rei277w6FYcwuPJIORTpmII8m7fqJa1+DPy8LqSt1jfaDDk4KzZTFm0g56Rqveoz Znww== X-Gm-Message-State: AOAM531dYvXOsquJLbTJWQ3PoTOJPHUZU8RbihbRzTZWdHFaAa915lbG f9yY1y4Jyyvk084bwq98Whrn54wQLEI= X-Google-Smtp-Source: ABdhPJxUe6IcdP/MZbKgwO5xbMNjObscwlrTYPLfB5Q3sc8S67t5NrN70HqyaICIqILjdLPcK5wHEw== X-Received: by 2002:a05:6a00:84e:: with SMTP id q14mr26486265pfk.309.1592941045672; Tue, 23 Jun 2020 12:37:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 18/45] target/arm: Simplify DC_ZVA Date: Tue, 23 Jun 2020 12:36:31 -0700 Message-Id: <20200623193658.623279-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200623193658.623279-1-richard.henderson@linaro.org> References: <20200623193658.623279-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, david.spickett@linaro.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Now that we know that the operation is on a single page, we need not loop over pages while probing. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 94 +++++++++++------------------------------ 1 file changed, 25 insertions(+), 69 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index bc0649a44a..8682630ff6 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1119,85 +1119,41 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vadd= r_in) * (which matches the usual QEMU behaviour of not implementing either * alignment faults or any memory attribute handling). */ - - ARMCPU *cpu =3D env_archcpu(env); - uint64_t blocklen =3D 4 << cpu->dcz_blocksize; + int blocklen =3D 4 << env_archcpu(env)->dcz_blocksize; uint64_t vaddr =3D vaddr_in & ~(blocklen - 1); + int mmu_idx =3D cpu_mmu_index(env, false); + void *mem; + + /* + * Trapless lookup. In addition to actual invalid page, may + * return NULL for I/O, watchpoints, clean pages, etc. + */ + mem =3D tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx); =20 #ifndef CONFIG_USER_ONLY - { + if (unlikely(!mem)) { + uintptr_t ra =3D GETPC(); + /* - * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than - * the block size so we might have to do more than one TLB lookup. - * We know that in fact for any v8 CPU the page size is at least 4K - * and the block size must be 2K or less, but TARGET_PAGE_SIZE is = only - * 1K as an artefact of legacy v5 subpage support being present in= the - * same QEMU executable. So in practice the hostaddr[] array has - * two entries, given the current setting of TARGET_PAGE_BITS_MIN. + * Trap if accessing an invalid page. DC_ZVA requires that we sup= ply + * the original pointer for an invalid page. But watchpoints requ= ire + * that we probe the actual space. So do both. */ - int maxidx =3D DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); - void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)]; - int try, i; - unsigned mmu_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + (void) probe_write(env, vaddr_in, 1, mmu_idx, ra); + mem =3D probe_write(env, vaddr, blocklen, mmu_idx, ra); =20 - assert(maxidx <=3D ARRAY_SIZE(hostaddr)); - - for (try =3D 0; try < 2; try++) { - - for (i =3D 0; i < maxidx; i++) { - hostaddr[i] =3D tlb_vaddr_to_host(env, - vaddr + TARGET_PAGE_SIZE *= i, - 1, mmu_idx); - if (!hostaddr[i]) { - break; - } - } - if (i =3D=3D maxidx) { - /* - * If it's all in the TLB it's fair game for just writing = to; - * we know we don't need to update dirty status, etc. - */ - for (i =3D 0; i < maxidx - 1; i++) { - memset(hostaddr[i], 0, TARGET_PAGE_SIZE); - } - memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); - return; - } + if (unlikely(!mem)) { /* - * OK, try a store and see if we can populate the tlb. This - * might cause an exception if the memory isn't writable, - * in which case we will longjmp out of here. We must for - * this purpose use the actual register value passed to us - * so that we get the fault address right. + * The only remaining reason for mem =3D=3D NULL is I/O. + * Just do a series of byte writes as the architecture demands. */ - helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); - /* Now we can populate the other TLB entries, if any */ - for (i =3D 0; i < maxidx; i++) { - uint64_t va =3D vaddr + TARGET_PAGE_SIZE * i; - if (va !=3D (vaddr_in & TARGET_PAGE_MASK)) { - helper_ret_stb_mmu(env, va, 0, oi, GETPC()); - } + for (int i =3D 0; i < blocklen; i++) { + cpu_stb_mmuidx_ra(env, vaddr + i, 0, mmu_idx, ra); } - } - - /* - * Slow path (probably attempt to do this to an I/O device or - * similar, or clearing of a block of code we have translations - * cached for). Just do a series of byte writes as the architecture - * demands. It's not worth trying to use a cpu_physical_memory_map= (), - * memset(), unmap() sequence here because: - * + we'd need to account for the blocksize being larger than a p= age - * + the direct-RAM access case is almost always going to be dealt - * with in the fastpath code above, so there's no speed benefit - * + we would have to deal with the map returning NULL because the - * bounce buffer was in use - */ - for (i =3D 0; i < blocklen; i++) { - helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); + return; } } -#else - memset(g2h(vaddr), 0, blocklen); #endif + + memset(mem, 0, blocklen); } --=20 2.25.1