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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id p12sm17927642pfq.69.2020.06.23.12.37.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2020 12:37:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HXdDbBi3bOiwXrXGTwrvFGKvOYNgFlf/lfsSkNgOuZg=; b=RvwN7JqUBDJu4NNvDP1Pi3tXUvQOkwbwPz6nncUYuJwgmJVsDU9zHH2Z246coIbanQ 3An/HmpLr1VCZYjQEicbhPMsnSxrfGxgHUS6lNVsB5IrQWbAvk1LKm3iv/vPmKm5D8Wc txEF1MKiDrcQpZpSudoyzilhuqNoJZfTykRbXbZM3rYBIFo5dWJRBrVMTVt/wDptzu4E ugagcgLoB5Na8mowuVlAEIY+2KdTigxAZIU6WGScTzU1C9xb9Napsb8HK4Vt1WxXIIuE CfK54Mw0T7c013UOwG8fHq8KRBmRY4t8ZKYfEBg6vFABDMfCJUF38Xr+QhDwJ2ec4Xfo /FIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HXdDbBi3bOiwXrXGTwrvFGKvOYNgFlf/lfsSkNgOuZg=; b=GBWPc3J0fl63s1Or1Ld1Xbf8GhapLOAtM1WpGnr47L5E0VUcsAjGY9Sf/AZncs9dli 6Dfp/Vx3EASk6MxAbsREzeo1dn/ktNLiCWHOgaaMwwA2rVemUsPT6xfPgbk6bCas+C1q lii1hBFEea91VWMNWDJziRXkRE0l1ZDl4NaPlis718nxrIvvjq8Vv7jOVer/2/Rw+G+E ZO+vDDdQCNMitwYjaYJaLlqwhBinZsDKMl6x6KP0viP/y5Gl4hOlks/Q+RF8pHb/eA/0 cgc4fCTF2tknf5Fq3etQDIuR/BoEfveO0ZFtoNmmAKNL2zweo5igY7LjSlUsG9+SuuTp HoPw== X-Gm-Message-State: AOAM530gRI6lijO/iLizyRd5WTGs8DlSu1OhkZaBHiK+HFyb3kGW3spN PPJdbhBGLeDOCw5ZsxmRpeleA+0//Fo= X-Google-Smtp-Source: ABdhPJytNTDKXCMsnBDLwlHL+aHwsVjh5taOoYmzoYWfXwK06bDZe2HtD5Ghu8ah7EeWL/H7u9vgqA== X-Received: by 2002:a62:1b82:: with SMTP id b124mr25980743pfb.172.1592941044414; Tue, 23 Jun 2020 12:37:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 17/45] target/arm: Restrict the values of DCZID.BS under TCG Date: Tue, 23 Jun 2020 12:36:30 -0700 Message-Id: <20200623193658.623279-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200623193658.623279-1-richard.henderson@linaro.org> References: <20200623193658.623279-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, david.spickett@linaro.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We can simplify our DC_ZVA if we recognize that the largest BS that we actually use in system mode is 64. Let us just assert that it fits within TARGET_PAGE_SIZE. For DC_GVA and STZGM, we want to be able to write whole bytes of tag memory, so assert that BS is >=3D 2 * TAG_GRANULE, or 32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 10677c0c23..f09efc4370 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1758,6 +1758,30 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) } #endif =20 + if (tcg_enabled()) { + int dcz_blocklen =3D 4 << cpu->dcz_blocksize; + + /* + * We only support DCZ blocklen that fits on one page. + * + * Architectually this is always true. However TARGET_PAGE_SIZE + * is variable and, for compatibility with -machine virt-2.7, + * is only 1KiB, as an artifact of legacy ARMv5 subpage support. + * But even then, while the largest architectural DCZ blocklen + * is 2KiB, no cpu actually uses such a large blocklen. + */ + assert(dcz_blocklen <=3D TARGET_PAGE_SIZE); + + /* + * We only support DCZ blocksize >=3D 2*TAG_GRANULE, which is to s= ay + * both nibbles of each byte storing tag data may be written at on= ce. + * Since TAG_GRANULE is 16, this means that blocklen must be >=3D = 32. + */ + if (cpu_isar_feature(aa64_mte, cpu)) { + assert(dcz_blocklen >=3D 2 * TAG_GRANULE); + } + } + qemu_init_vcpu(cs); cpu_reset(cs); =20 --=20 2.25.1