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[83.51.162.1]) by smtp.gmail.com with ESMTPSA id o10sm13779362wrj.37.2020.06.21.05.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 05:48:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BGnnG9Xy3PNvVbxTp72sTTRXPqYJOpLdaAYtg1CD7cQ=; b=moQdMDv2b3hG3cbKZ64kdvpDlgHfyazD4vFFY7sDOaSEzOoRssJznAnGCd5cKnjphL qArAGQkLOnBTCSpp5hVb+hHMyVLNe3MSY43bD33EwNxPAEhecxi8y8qVRvt661eFn4Sd OpUhJogrCQDmeUpD333NBBUC6UPVAewOSx4GGnCjQhFgdDdLZnPkOO+tHXzoGba6faaC YRYosVQA4GbhbXjHRigkzhRFWC4OYlnGl2q7cAo3UnpSh8k3h7twYRi8qKsxLub8iTbe jk2Ec2/gc+eyuy+2bHhy94IpGp4MEUmrhenk5+Wysb2aVkwoKkoEwKXuWaYpcXE8YOIS gFZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=BGnnG9Xy3PNvVbxTp72sTTRXPqYJOpLdaAYtg1CD7cQ=; b=djZDCeEAmeAO4R01XfHgq91mGE3dj6uuQ/26skwfJC5ruWqRDVdfIq+5WjHtjWvtHZ EwTeBLnX32SVtC89IpG8jVdsO23JkgxRJbPeePNu0+ozS99Rh0M1Lj9afb0fIqAnGIeJ +uOJXyh22Euuah+lUhjNzXQBL0gckNW72K+/vEaXNOfe6YozAOG+0PHBgMC/enbYN1vl yuPaU5/71mts+7bqd/+XvVLvPTCo+wiyixg2rSBIEopBQaUmrcVHmyGK11G7PoTbzjAe 8vYCFTjxgwEMiwzS6nzyuTDd67OAMal5wTY6xcBvlC+xqi5wyp4T4igR+5rxfkAPmkqK sdhA== X-Gm-Message-State: AOAM530JgkoywpEiyF6I7RDI2FlYPF6NzPGYE00sKZc0uvklPVGnCD3C COPzKVAVsSHAMe2B80ZtOUkhPfui X-Google-Smtp-Source: ABdhPJzvGyj9nSDUbQTkREkquGwTNNUj1lshOJk+W+U+b0ebIwwzchdo9zJQDYgW50o7nNnMJ41Zkg== X-Received: by 2002:a7b:c93a:: with SMTP id h26mr12571593wml.57.1592743691186; Sun, 21 Jun 2020 05:48:11 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 01/15] MAINTAINERS: Cover sh_intc files in the R2D/Shix machine sections Date: Sun, 21 Jun 2020 14:47:53 +0200 Message-Id: <20200621124807.17226-2-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200621124807.17226-1-f4bug@amsat.org> References: <20200621124807.17226-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Yoshinori Sato , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Commit 81527b94ad added hw/intc/sh_intc.c, but only to the R2D machine (it is also used by the Shix machine). Complete the previous commit by adding the header to the R2D section, and both source + header to the Shix section. Suggested-by: Thomas Huth Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 955cc8dd5c..67c495e841 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1261,12 +1261,15 @@ S: Maintained F: hw/sh4/r2d.c F: hw/intc/sh_intc.c F: hw/timer/sh_timer.c +F: include/hw/sh4/sh_intc.h =20 Shix M: Yoshinori Sato R: Magnus Damm S: Odd Fixes F: hw/sh4/shix.c +F: hw/intc/sh_intc.c +F: include/hw/sh4/sh_intc.h =20 SPARC Machines -------------- --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1592743990; cv=none; d=zohomail.com; s=zohoarc; b=QVGmAv7n4ssKwcLw26FMaTHzdyBD4sIhn33YUIp9Qh92E/AIii0+Wev6tw3kpMPmKsNGHYJppKedRuKvm6CEoAvIw6GtAI9X2S580EmyKp5MPLSOZkL9JFGhz9F3as9G5p8NkNn5nOGsQP8UcYz9jpii8ypS2w226qiFZ8F61oI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592743990; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pnYwqyRw7PrUBqK6RMzPW7ocbdUWT8/A3afeCH6DRm0=; b=htpa4UhvpJxxWOoEB5TzgmJ31vwnpPA2cD2QcUEwnQle7OkqE4wQv0Wbtc9O1mdO8TwIGVTK2vNFwTgSEfg9dofAWztPi8AicezQnHrWQKmabqrGQt5/3qBgazk2Pkgc/mKMj3tsYNoaJR0MZVhI3qqoHRDPeY1cb8it9GINDfI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592743990117848.969250362906; Sun, 21 Jun 2020 05:53:10 -0700 (PDT) Received: from localhost ([::1]:38488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jmzTA-0004BI-St for importer@patchew.org; Sun, 21 Jun 2020 08:53:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47436) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jmzOS-000530-09 for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:16 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:50454) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jmzOQ-0002ov-03 for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:15 -0400 Received: by mail-wm1-x32a.google.com with SMTP id l17so12463786wmj.0 for ; Sun, 21 Jun 2020 05:48:13 -0700 (PDT) Received: from localhost.localdomain (1.red-83-51-162.dynamicip.rima-tde.net. [83.51.162.1]) by smtp.gmail.com with ESMTPSA id o10sm13779362wrj.37.2020.06.21.05.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 05:48:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pnYwqyRw7PrUBqK6RMzPW7ocbdUWT8/A3afeCH6DRm0=; b=SZB0py3/NsMkhmmaQcks++xtuTP0epgST/ofB1+Rp2r5Q+J4kzfLXZr8/GvW3X9JMK mnzyD7pFf/myceJECBg7oG2XRi5w9CAn4Fx3RewBrrf54Zba0xSWvmTYILxAMKY+qQQ4 oZ4ZBhS2yn8EOsefJIOZcLBL1hJuFB8uPptTFOY6/VC9y0rQbjl2twZ45Kt3SccligqB jwL2o7g1bfh39+yRKvU6Z/nc4ZJWoTRJ+CFThF5BOfNVgQHUXIKAdEIpem83t+LfMKtp MjnQP4To8Q2P5ZdEtXoe0cB9UknAIYs+RRd1rK4Cb+Hs9rFhl6hlZEpQYVJ513qKe8NA GQZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pnYwqyRw7PrUBqK6RMzPW7ocbdUWT8/A3afeCH6DRm0=; b=GRKMa1KrXqbms7Eu6SOvma2nISedD/FzyvyymH6Th9j6tlrg7Zj5Z8dUjdODvwZ8Kj Xk4nTA1phuVwIL+8RLf4TqgEgH9IGs1ZJ6oFKVNL/7r9TjNTUoH6FApET4oURPdci3P7 ZgcJ4K20rqtwjJoQjZ6xKkU64jAhFZ64FrTWIj2+RSz06tMg+rQb0qc9ZYzsM9A40rMp k+0/mQ2u4geMFlMR9Vtta3NVHmxfKkmrg9GSpupKXrq9rKmjXP5Nmkh768Wu2LfjVFpp MnRtU9daoVU2Lbke7SBX8tyRmi15X/Npkgz5mxPWTJdz9xDIYLvCFPRYUPu1+eeo/xLu QmdQ== X-Gm-Message-State: AOAM533qfBPQCS9iZRcXX+gci5/vCYoIOWaubW7QO08JdTpE3FnYDEJM qNvUzkZ8QxVkqKGEPATr8N3CmJiL X-Google-Smtp-Source: ABdhPJx8ohIxa0APdMMlMc7rZiBX+zEzRFJb7VSgxJz3Ko4N0aBVi7+QpFH9TDeZESyfX4Si5E3pHQ== X-Received: by 2002:a1c:4105:: with SMTP id o5mr12981900wma.168.1592743692445; Sun, 21 Jun 2020 05:48:12 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 02/15] MAINTAINERS: Add an entry for common Renesas peripherals Date: Sun, 21 Jun 2020 14:47:54 +0200 Message-Id: <20200621124807.17226-3-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200621124807.17226-1-f4bug@amsat.org> References: <20200621124807.17226-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , Richard Henderson , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Renesas peripherals are common to SH4/RX based MCUs. Their datasheets share common sections. It makes sense to maintain them altogether. Add the uncovered UART SCI peripheral. The current names are misleading (see the 'sh_' prefix). In another series we will remove these peripherals with the 'renesas_' prefix. Out of the scope of this change in MAINTAINERS. Cc: Magnus Damm Cc: Yoshinori Sato Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- MAINTAINERS | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 67c495e841..f1ae0775f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1260,7 +1260,6 @@ R: Magnus Damm S: Maintained F: hw/sh4/r2d.c F: hw/intc/sh_intc.c -F: hw/timer/sh_timer.c F: include/hw/sh4/sh_intc.h =20 Shix @@ -1964,6 +1963,14 @@ F: hw/*/*xive* F: include/hw/*/*xive* F: docs/*/*xive* =20 +Renesas peripherals +M: Yoshinori Sato +R: Magnus Damm +S: Maintained +F: hw/char/sh_serial.c +F: hw/timer/sh_timer.c +F: include/hw/sh4/sh.h + Subsystems ---------- Audio --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1592743781; cv=none; d=zohomail.com; s=zohoarc; b=MD88wol+4cEa4eNe7IkZrNjObkQ/frbzNz0ysgfhOsSPLdx/3yAtfR4V5mU044FpwE8qlejs+60HpzY4QLA7KPazOr1F3Ilq4TTQ6ZpJHgDxy1ghLwAVufxlg3OTD9fM9bRPWnysNb3GmD7ujW9jMs/EBIOiLSO4h7ycUTu7ieA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592743781; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B90u68HWanE8Ef/dq5GEfdfCsFqZeY71gyQo1Aa7Eho=; b=JzzmDveromwAmh1QqRN4HhqZHkoN9oKmFlMmOoYFjfrEMni8sm4EwcpcwtctfIx9TwstOVReyz/s/bGEGtt3c+7j8wGXVOJVCoY/EmYs0qUc25ELsE/AZpoZuUDrTHQCmuxh9+k4sBON1IVKueE6fODwsvNGJJSx/BZVTnUnWEI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592743781962892.1099339927689; Sun, 21 Jun 2020 05:49:41 -0700 (PDT) Received: from localhost ([::1]:53948 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jmzPo-0006iG-JI for importer@patchew.org; Sun, 21 Jun 2020 08:49:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jmzOS-00053s-Ho for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:16 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:52370) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jmzOQ-0002pA-SH for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:16 -0400 Received: by mail-wm1-x344.google.com with SMTP id r9so12448184wmh.2 for ; Sun, 21 Jun 2020 05:48:14 -0700 (PDT) Received: from localhost.localdomain (1.red-83-51-162.dynamicip.rima-tde.net. [83.51.162.1]) by smtp.gmail.com with ESMTPSA id o10sm13779362wrj.37.2020.06.21.05.48.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 05:48:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B90u68HWanE8Ef/dq5GEfdfCsFqZeY71gyQo1Aa7Eho=; b=fDm/Defoy+MDv9gG69+oVhdZUeh07HrddWE4eVoyI7hD0Jdl3/qS4VLOwkRXkOBQ0I nFVUyvLSgfEe7bdt99C6yQBajQCN6HX6V8a1f3pGaW1Q3yLoihBg6FAujCapFvqG2EgF ATxEDXPx6cG9ETtxPge8L7U5T9cvVJorvllu89x/+QTLlGE6y3NiFRRyDGiONJ31aGgB xAMDJ25FHzephkKmbCU+le3imW4aJpiXjMX61sg4/blXRPfTt8SfnEX/h2vAl7vgYn99 E8dEFrDUur38QMxl5C6WnJ9pJ4FBqBi3luPZmxhdAk1A04z85g7CninlP8M161DVIHqG 658g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=B90u68HWanE8Ef/dq5GEfdfCsFqZeY71gyQo1Aa7Eho=; b=dmxMaM6BWdQLhHEtc62cvzLvycZh3uA0dp1umgc6oRkYRDJZ2fr5clSH9gxLjHhXqz mITOhMI3SIWhKNdfjx/JwrhWDAwQcPtGCeiCjlvbQBBFnMY9x48iSN8xM1sdyMxhH+B3 DKIjw4w1O8P7r/aSmXDn2w5ngN+3DpUqy83lRHUir7IMeve5qwOusIwPwSiYvRDvQm00 7dti177rmlcNpOr6c9+j0HKgzkw/Iww0wK5y/3TEP5PZUax4f8BjSh4StB64PfwNl5Nn 3GtZ63RxLulIZ4qmnjKOenyXtgNoZig74YtUybv6WsanlvlV+gB39J4gtaUip2z8kP8c Aq9g== X-Gm-Message-State: AOAM532RxkFjLO/cKaKQiDSnh+73JUWQSJj6WF4GoWNU9gfIJCcw378i eQ6f/JwM8wVIioltIbw5gANFV8gj X-Google-Smtp-Source: ABdhPJzS6/z49w11SeX/vO+j7p9cEGA0RkhEkK32X3UZqocOPs+C+XFqnAEgISFESPFh41842J81qg== X-Received: by 2002:a1c:6a01:: with SMTP id f1mr12970847wmc.52.1592743693554; Sun, 21 Jun 2020 05:48:13 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 03/15] hw/sh4: Use MemoryRegion typedef Date: Sun, 21 Jun 2020 14:47:55 +0200 Message-Id: <20200621124807.17226-4-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200621124807.17226-1-f4bug@amsat.org> References: <20200621124807.17226-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Yoshinori Sato , Richard Henderson , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Use the MemoryRegion type defined in "qemu/typedefs.h", to keep the repository style consistent. Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/sh4/sh.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index 767a2df7e2..fe773cb01d 100644 --- a/include/hw/sh4/sh.h +++ b/include/hw/sh4/sh.h @@ -10,9 +10,8 @@ =20 /* sh7750.c */ struct SH7750State; -struct MemoryRegion; =20 -struct SH7750State *sh7750_init(SuperHCPU *cpu, struct MemoryRegion *sysme= m); +struct SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem); =20 typedef struct { /* The callback will be triggered if any of the designated lines chang= e */ @@ -32,7 +31,7 @@ int sh7750_register_io_device(struct SH7750State *s, #define TMU012_FEAT_TOCR (1 << 0) #define TMU012_FEAT_3CHAN (1 << 1) #define TMU012_FEAT_EXTCLK (1 << 2) -void tmu012_init(struct MemoryRegion *sysmem, hwaddr base, +void tmu012_init(MemoryRegion *sysmem, hwaddr base, int feat, uint32_t freq, qemu_irq ch0_irq, qemu_irq ch1_irq, qemu_irq ch2_irq0, qemu_irq ch2_irq1); --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1592743784; cv=none; d=zohomail.com; s=zohoarc; b=OzlbKzduXsuhiFoUbufi0OfVvqnK1M58d2kp1IxH8NDVkAvgunpKbXn0wkN2RlCpVZjzID87FbsUESEAuAdWu7cBv0EbiNc3vQrVsZVu7lipPyiDYLqd8VHwOfcUeQseFb3ddyanQRbG2nHInO/DdLX6+2W/dbAN0KBykzwRDdE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592743784; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8b3HXRDRgYc7wWaPey7dft5cQmLY7o7QcJ77viT780g=; b=YYtIi3yLkezM26uPzGE84ITEjooslCeYkAZPgVyKn6UsfsjRII6aZexkzS1fR7+mmRLRz5qcqxomOm61axNZng6C/Fk1FFBnA1nqsCizAED6D8w0dXs71ton/oQA/tGr2GjdG66oWTWcZCYPh1yFnHGqZvnvueb3sHO6TnEMRi4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592743784690269.59619820887224; Sun, 21 Jun 2020 05:49:44 -0700 (PDT) Received: from localhost ([::1]:54322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jmzPr-0006rC-Fw for importer@patchew.org; Sun, 21 Jun 2020 08:49:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47452) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jmzOT-000565-P6 for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:17 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:46046) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jmzOS-0002pH-7F for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:17 -0400 Received: by mail-wr1-x42d.google.com with SMTP id c3so13946160wru.12 for ; Sun, 21 Jun 2020 05:48:15 -0700 (PDT) Received: from localhost.localdomain (1.red-83-51-162.dynamicip.rima-tde.net. [83.51.162.1]) by smtp.gmail.com with ESMTPSA id o10sm13779362wrj.37.2020.06.21.05.48.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 05:48:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8b3HXRDRgYc7wWaPey7dft5cQmLY7o7QcJ77viT780g=; b=QdFJ95ov2G/bwgUu2qIl3an5RDd02n7tpfcwCBuq59jVHl/xlE98vwljXu9oUVjumB 5sOJ5kJ04gJXrrzilgSuIx215hvOnR034TixT6gefoPifrS5SiOAqxekU1Z2BWNoqtAQ 4SZAywjMS1WS7sqYZ47sDKBq3skvSNsmMBuMaixOiqUv+G6He/bKPV9kJBaSXIDB4Kv5 AVu54m3jqZ6Ge79GiIusJnfTjJqhp7NpZaLtriZvVWhVOYIrftJDdtZhZHO58JtwyUyn 63YJm4ZXsGUQ6dM8ZH1DWZrUH2sDZR+VIU9y35iROpqNtMa7DLONFFjwwaCYoaa5Xe7a DVFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8b3HXRDRgYc7wWaPey7dft5cQmLY7o7QcJ77viT780g=; b=Kxtw9bauXqL/LZOumn4CcK6P2KfIFY4x6mSpdx7sWgGtz3zUqBn/KCXRbAFOzpSugt a9gEaA7KVc7082oyeTk9EcL1lMsich36bYP0q9cnicbwU4geHYVoePTHGm9yOHGlqijd IkTex7ejjcsr+EJNCGKtnMttzcV7gpFCRr5rGPDTpzfd4h6u0/XHtL3UKZ0y33GGl0c3 ym+6t7SPOkxkiMLljWQP7iUENhVhPdvo8TzBDdm1k4zV1PughtkAIZ+Qd2uaqFEK0vPy MtINMzkjKXEKVZSD7EQITmdCldGVHHjt9z2PKrU8k3gLHxolqNvcRGm6RJCrNAMo+fuf n/Bw== X-Gm-Message-State: AOAM530D9s9WGOacyuaPNuafCggO9n847VvzhNopyG5hDtQZ3QMcaJHp s/mMOCOWCX6JFIqKL+K9+0ZAj6VP X-Google-Smtp-Source: ABdhPJwZcU55jIxaqTgSqxEJIXY5PQ7rV81voWWmo3FlyVx5VK6go+YL8h2O/C8XJv/t+tkMGAlPbw== X-Received: by 2002:a5d:554a:: with SMTP id g10mr14195802wrw.334.1592743694715; Sun, 21 Jun 2020 05:48:14 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 04/15] hw/sh4: Extract timer definitions to 'hw/timer/tmu012.h' Date: Sun, 21 Jun 2020 14:47:56 +0200 Message-Id: <20200621124807.17226-5-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200621124807.17226-1-f4bug@amsat.org> References: <20200621124807.17226-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , Richard Henderson , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Extract timer definitions to 'hw/timer/tmu012.h'. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/sh4/sh.h | 9 --------- include/hw/timer/tmu012.h | 23 +++++++++++++++++++++++ hw/sh4/sh7750.c | 1 + hw/timer/sh_timer.c | 2 ++ 4 files changed, 26 insertions(+), 9 deletions(-) create mode 100644 include/hw/timer/tmu012.h diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index fe773cb01d..93f464bf4c 100644 --- a/include/hw/sh4/sh.h +++ b/include/hw/sh4/sh.h @@ -27,15 +27,6 @@ typedef struct { =20 int sh7750_register_io_device(struct SH7750State *s, sh7750_io_device * device); -/* sh_timer.c */ -#define TMU012_FEAT_TOCR (1 << 0) -#define TMU012_FEAT_3CHAN (1 << 1) -#define TMU012_FEAT_EXTCLK (1 << 2) -void tmu012_init(MemoryRegion *sysmem, hwaddr base, - int feat, uint32_t freq, - qemu_irq ch0_irq, qemu_irq ch1_irq, - qemu_irq ch2_irq0, qemu_irq ch2_irq1); - =20 /* sh_serial.c */ #define SH_SERIAL_FEAT_SCIF (1 << 0) diff --git a/include/hw/timer/tmu012.h b/include/hw/timer/tmu012.h new file mode 100644 index 0000000000..808ed8de1d --- /dev/null +++ b/include/hw/timer/tmu012.h @@ -0,0 +1,23 @@ +/* + * SuperH Timer + * + * Copyright (c) 2007 Magnus Damm + * + * This code is licensed under the GPL. + */ + +#ifndef HW_TIMER_TMU012_H +#define HW_TIMER_TMU012_H + +#include "exec/hwaddr.h" + +#define TMU012_FEAT_TOCR (1 << 0) +#define TMU012_FEAT_3CHAN (1 << 1) +#define TMU012_FEAT_EXTCLK (1 << 2) + +void tmu012_init(MemoryRegion *sysmem, hwaddr base, + int feat, uint32_t freq, + qemu_irq ch0_irq, qemu_irq ch1_irq, + qemu_irq ch2_irq0, qemu_irq ch2_irq1); + +#endif diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index d660714443..f8ac3ec6e3 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -30,6 +30,7 @@ #include "sh7750_regs.h" #include "sh7750_regnames.h" #include "hw/sh4/sh_intc.h" +#include "hw/timer/tmu012.h" #include "cpu.h" #include "exec/exec-all.h" =20 diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 13c4051808..b9cbacf5d0 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -9,10 +9,12 @@ */ =20 #include "qemu/osdep.h" +#include "exec/memory.h" #include "hw/hw.h" #include "hw/irq.h" #include "hw/sh4/sh.h" #include "qemu/timer.h" +#include "hw/timer/tmu012.h" #include "hw/ptimer.h" =20 //#define DEBUG_TIMER --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1592743917; cv=none; d=zohomail.com; s=zohoarc; b=Y8J/BoT/Kfnv3rE/ZBiwD0HBE5Ul4J+g69ZV8sy6fe969cwrdOKoCRfMYmTopyNm3nP79DzeF+LZHuv7lLDqvvIsN27470m4e2ADm5SCyAIzOYugnm43JyXbAG7c/jcZxonXFL7r2IAKax9C6xJiq65KDJba2NjUmP1mZCopHJs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592743917; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fCWXr6zHNQbQPJ8BLLwrAx76MymcZFD1NlfKOZXdkr4=; b=EtNUshI0b6pTlRGqtCQdZ6lZIdnRg2yCQatvGZVAqRC/elzKbT5Uh/BwNPW+6EOaQn3j1xaOp6o8L8aI63CAGZ6+kUICgXc+aruPDIyZ0GHl+Ms2lGkvNY6mekxeoOEqhz+hqaCKE1GfP+28XbldbW/itLrvVmIdyHhyLqTA9TI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592743917192457.035330960388; Sun, 21 Jun 2020 05:51:57 -0700 (PDT) Received: from localhost ([::1]:34058 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jmzRx-0002P4-3S for importer@patchew.org; Sun, 21 Jun 2020 08:51:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47464) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jmzOV-000584-Sc for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:19 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:42995) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jmzOT-0002pR-BV for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:18 -0400 Received: by mail-wr1-x441.google.com with SMTP id o11so6293227wrv.9 for ; Sun, 21 Jun 2020 05:48:16 -0700 (PDT) Received: from localhost.localdomain (1.red-83-51-162.dynamicip.rima-tde.net. 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That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , Richard Henderson , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Remove unused "qemu/timer.h" include. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/sh_timer.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index b9cbacf5d0..bb0e1c8ee5 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -13,7 +13,6 @@ #include "hw/hw.h" #include "hw/irq.h" #include "hw/sh4/sh.h" -#include "qemu/timer.h" #include "hw/timer/tmu012.h" #include "hw/ptimer.h" =20 --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1592743928; cv=none; d=zohomail.com; s=zohoarc; b=btX19rlWq+WYR2kf2vNoHjQsD/AqfxcLdUFgNhS6jLuAVhdF/9YoN/ltN9c+hwubRgU0ZYpTXiCmXMGCgyhTA9pFrKxSPro6YQnZUwUx3LtVJxyLRaESkRB643c55QZjIXoDxHPohYZfQeZV7AoCgDcXhfbIAEBoF8IH1VDPJV4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592743928; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RxiWSAurU0VXaBJTrV5wLkut3YrbIl6owWupFGOQzYg=; b=iPEUQRRgeki41AawS9K5TNw5gA1yE6+qAGz7PCT4VduzVX80X2m2C5fIA0RQVcuYdjmOaSSNJQEl2b61sJ1Z4dT2F/8QV9jS0pO/0c6ulqcIMDD+U784InONuSoggEv6L3FY4XatiMLJ0pUWpGuJYX0PCPecn4ASbSyZTamrmNU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159274392897781.66670061901357; Sun, 21 Jun 2020 05:52:08 -0700 (PDT) Received: from localhost ([::1]:34382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jmzSB-0002X8-Mf for importer@patchew.org; Sun, 21 Jun 2020 08:52:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47480) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jmzOY-0005Ci-E8 for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:22 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:38311) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jmzOW-0002pe-6z for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:22 -0400 Received: by mail-wr1-x436.google.com with SMTP id z13so2235611wrw.5 for ; Sun, 21 Jun 2020 05:48:18 -0700 (PDT) Received: from localhost.localdomain (1.red-83-51-162.dynamicip.rima-tde.net. [83.51.162.1]) by smtp.gmail.com with ESMTPSA id o10sm13779362wrj.37.2020.06.21.05.48.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 05:48:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RxiWSAurU0VXaBJTrV5wLkut3YrbIl6owWupFGOQzYg=; b=vURBBADe2DbbCdsxWTZvvCPR0S9m72W2ZMZO5N+ta86dMrqPJjavKNV07wkiwYJa9G kL7kck5WXceEUdQcllVQGpN0tv5p25UAjpmx9lGMslsMyI/kVe91yWWBHOIJUsRbUsLQ PUfxQ3u021oMbQkMpJyjwYLY8Scwv9R6mgLktJuaRwNBClYBmltlLLDEZ2yQk361d8fI A8z1hY+l8SC1WCWgqtVRfbCwF0K/73IQXPx1kJXU1zcY97MHs2wfyCkLQdp4GkmdJtr2 3o/or9dHRK6I4QHZD1j0basTqIlb3nNduHG7ectlXhVTvQXLIeNtY5ldpsWeqR3R68/4 Cx3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=RxiWSAurU0VXaBJTrV5wLkut3YrbIl6owWupFGOQzYg=; b=Io9BY+jr9zYIOVsYg8voXaqSuUxhnikzNUmcRHv9QmOK3xsSQCKFenrngOMznlF8HF cLujOK6lGwIfQ2jKonVAUr4ffdDa997rMYQpuF+N4z5/B36j50/8+uMRWg6c3/IZhhqH U9MxDuaqPKlkgFaGG5w2LUE/LLnJef5+eluAWZvFByyPs6zyB/IAiw3ofWz0u3iQD+9y I6tjJ/kj3F9KpkB7gmrsoCRtgrstHdRv4TLy6BcbqwBnOWGsYtl90ZM0pP2Kc69IXR22 ukgU/o291nnzTlkrRtxkHOXICNa3rVwa2629UXWVcU90RH1p9fpkpw8teAdsmSgcK3VP gjlQ== X-Gm-Message-State: AOAM530z5QxvjVxvW5nzOYh30ofV/6zhqLcDzh3wpreMjxDInt7V1mEf mCeqC/XUZOG0zYcXSFLrkb3KDoCE X-Google-Smtp-Source: ABdhPJyyPmfvr8fmCWUNv1HK9tcNjGui4/wnw+oKOLQ9mcIRjU7oWvB+vLqJfAYVVaD2QsiNJdSo5g== X-Received: by 2002:adf:f445:: with SMTP id f5mr5181177wrp.339.1592743697378; Sun, 21 Jun 2020 05:48:17 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 06/15] hw/intc: RX62N interrupt controller (ICUa) Date: Sun, 21 Jun 2020 14:47:58 +0200 Message-Id: <20200621124807.17226-7-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200621124807.17226-1-f4bug@amsat.org> References: <20200621124807.17226-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato This implementation supported only ICUa. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej= 0140_rx62n.pdf Signed-off-by: Yoshinori Sato Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-15-ysato@users.sourceforge.jp> [PMD: Fill VMStateField for migration, cover files in MAINTAINERS] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/intc/rx_icu.h | 76 ++++++++ hw/intc/rx_icu.c | 397 +++++++++++++++++++++++++++++++++++++++ MAINTAINERS | 6 + hw/intc/Kconfig | 3 + hw/intc/Makefile.objs | 1 + 5 files changed, 483 insertions(+) create mode 100644 include/hw/intc/rx_icu.h create mode 100644 hw/intc/rx_icu.c diff --git a/include/hw/intc/rx_icu.h b/include/hw/intc/rx_icu.h new file mode 100644 index 0000000000..7176015cd9 --- /dev/null +++ b/include/hw/intc/rx_icu.h @@ -0,0 +1,76 @@ +/* + * RX Interrupt Control Unit + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_INTC_RX_ICU_H +#define HW_INTC_RX_ICU_H + +#include "hw/sysbus.h" + +enum TRG_MODE { + TRG_LEVEL =3D 0, + TRG_NEDGE =3D 1, /* Falling */ + TRG_PEDGE =3D 2, /* Raising */ + TRG_BEDGE =3D 3, /* Both */ +}; + +struct IRQSource { + enum TRG_MODE sense; + int level; +}; + +enum { + /* Software interrupt request */ + SWI =3D 27, + NR_IRQS =3D 256 +}; + +struct RXICUState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion memory; + struct IRQSource src[NR_IRQS]; + uint32_t nr_irqs; + uint8_t *map; + uint32_t nr_sense; + uint8_t *init_sense; + + uint8_t ir[NR_IRQS]; + uint8_t dtcer[NR_IRQS]; + uint8_t ier[NR_IRQS / 8]; + uint8_t ipr[142]; + uint8_t dmasr[4]; + uint16_t fir; + uint8_t nmisr; + uint8_t nmier; + uint8_t nmiclr; + uint8_t nmicr; + int16_t req_irq; + qemu_irq _irq; + qemu_irq _fir; + qemu_irq _swi; +}; +typedef struct RXICUState RXICUState; + +#define TYPE_RX_ICU "rx-icu" +#define RX_ICU(obj) OBJECT_CHECK(RXICUState, (obj), TYPE_RX_ICU) + +#endif /* RX_ICU_H */ diff --git a/hw/intc/rx_icu.c b/hw/intc/rx_icu.c new file mode 100644 index 0000000000..df4b6a8d22 --- /dev/null +++ b/hw/intc/rx_icu.c @@ -0,0 +1,397 @@ +/* + * RX Interrupt Control Unit + * + * Warning: Only ICUa is supported. + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/qdev-properties.h" +#include "hw/intc/rx_icu.h" +#include "migration/vmstate.h" + +REG8(IR, 0) + FIELD(IR, IR, 0, 1) +REG8(DTCER, 0x100) + FIELD(DTCER, DTCE, 0, 1) +REG8(IER, 0x200) +REG8(SWINTR, 0x2e0) + FIELD(SWINTR, SWINT, 0, 1) +REG16(FIR, 0x2f0) + FIELD(FIR, FVCT, 0, 8) + FIELD(FIR, FIEN, 15, 1) +REG8(IPR, 0x300) + FIELD(IPR, IPR, 0, 4) +REG8(DMRSR, 0x400) +REG8(IRQCR, 0x500) + FIELD(IRQCR, IRQMD, 2, 2) +REG8(NMISR, 0x580) + FIELD(NMISR, NMIST, 0, 1) + FIELD(NMISR, LVDST, 1, 1) + FIELD(NMISR, OSTST, 2, 1) +REG8(NMIER, 0x581) + FIELD(NMIER, NMIEN, 0, 1) + FIELD(NMIER, LVDEN, 1, 1) + FIELD(NMIER, OSTEN, 2, 1) +REG8(NMICLR, 0x582) + FIELD(NMICLR, NMICLR, 0, 1) + FIELD(NMICLR, OSTCLR, 2, 1) +REG8(NMICR, 0x583) + FIELD(NMICR, NMIMD, 3, 1) + +static void set_irq(RXICUState *icu, int n_IRQ, int req) +{ + if ((icu->fir & R_FIR_FIEN_MASK) && + (icu->fir & R_FIR_FVCT_MASK) =3D=3D n_IRQ) { + qemu_set_irq(icu->_fir, req); + } else { + qemu_set_irq(icu->_irq, req); + } +} + +static uint16_t rxicu_level(RXICUState *icu, unsigned n) +{ + return (icu->ipr[icu->map[n]] << 8) | n; +} + +static void rxicu_request(RXICUState *icu, int n_IRQ) +{ + int enable; + + enable =3D icu->ier[n_IRQ / 8] & (1 << (n_IRQ & 7)); + if (n_IRQ > 0 && enable !=3D 0 && atomic_read(&icu->req_irq) < 0) { + atomic_set(&icu->req_irq, n_IRQ); + set_irq(icu, n_IRQ, rxicu_level(icu, n_IRQ)); + } +} + +static void rxicu_set_irq(void *opaque, int n_IRQ, int level) +{ + RXICUState *icu =3D opaque; + struct IRQSource *src; + int issue; + + if (n_IRQ >=3D NR_IRQS) { + error_report("%s: IRQ %d out of range", __func__, n_IRQ); + return; + } + + src =3D &icu->src[n_IRQ]; + + level =3D (level !=3D 0); + switch (src->sense) { + case TRG_LEVEL: + /* level-sensitive irq */ + issue =3D level; + src->level =3D level; + break; + case TRG_NEDGE: + issue =3D (level =3D=3D 0 && src->level =3D=3D 1); + src->level =3D level; + break; + case TRG_PEDGE: + issue =3D (level =3D=3D 1 && src->level =3D=3D 0); + src->level =3D level; + break; + case TRG_BEDGE: + issue =3D ((level ^ src->level) & 1); + src->level =3D level; + break; + default: + g_assert_not_reached(); + } + if (issue =3D=3D 0 && src->sense =3D=3D TRG_LEVEL) { + icu->ir[n_IRQ] =3D 0; + if (atomic_read(&icu->req_irq) =3D=3D n_IRQ) { + /* clear request */ + set_irq(icu, n_IRQ, 0); + atomic_set(&icu->req_irq, -1); + } + return; + } + if (issue) { + icu->ir[n_IRQ] =3D 1; + rxicu_request(icu, n_IRQ); + } +} + +static void rxicu_ack_irq(void *opaque, int no, int level) +{ + RXICUState *icu =3D opaque; + int i; + int n_IRQ; + int max_pri; + + n_IRQ =3D atomic_read(&icu->req_irq); + if (n_IRQ < 0) { + return; + } + atomic_set(&icu->req_irq, -1); + if (icu->src[n_IRQ].sense !=3D TRG_LEVEL) { + icu->ir[n_IRQ] =3D 0; + } + + max_pri =3D 0; + n_IRQ =3D -1; + for (i =3D 0; i < NR_IRQS; i++) { + if (icu->ir[i]) { + if (max_pri < icu->ipr[icu->map[i]]) { + n_IRQ =3D i; + max_pri =3D icu->ipr[icu->map[i]]; + } + } + } + + if (n_IRQ >=3D 0) { + rxicu_request(icu, n_IRQ); + } +} + +static uint64_t icu_read(void *opaque, hwaddr addr, unsigned size) +{ + RXICUState *icu =3D opaque; + int reg =3D addr & 0xff; + + if ((addr !=3D A_FIR && size !=3D 1) || + (addr =3D=3D A_FIR && size !=3D 2)) { + qemu_log_mask(LOG_GUEST_ERROR, "rx_icu: Invalid read size 0x%" + HWADDR_PRIX "\n", + addr); + return UINT64_MAX; + } + switch (addr) { + case A_IR ... A_IR + 0xff: + return icu->ir[reg] & R_IR_IR_MASK; + case A_DTCER ... A_DTCER + 0xff: + return icu->dtcer[reg] & R_DTCER_DTCE_MASK; + case A_IER ... A_IER + 0x1f: + return icu->ier[reg]; + case A_SWINTR: + return 0; + case A_FIR: + return icu->fir & (R_FIR_FIEN_MASK | R_FIR_FVCT_MASK); + case A_IPR ... A_IPR + 0x8f: + return icu->ipr[reg] & R_IPR_IPR_MASK; + case A_DMRSR: + case A_DMRSR + 4: + case A_DMRSR + 8: + case A_DMRSR + 12: + return icu->dmasr[reg >> 2]; + case A_IRQCR ... A_IRQCR + 0x1f: + return icu->src[64 + reg].sense << R_IRQCR_IRQMD_SHIFT; + case A_NMISR: + case A_NMICLR: + return 0; + case A_NMIER: + return icu->nmier; + case A_NMICR: + return icu->nmicr; + default: + qemu_log_mask(LOG_UNIMP, "rx_icu: Register 0x%" HWADDR_PRIX " " + "not implemented.\n", + addr); + break; + } + return UINT64_MAX; +} + +static void icu_write(void *opaque, hwaddr addr, uint64_t val, unsigned si= ze) +{ + RXICUState *icu =3D opaque; + int reg =3D addr & 0xff; + + if ((addr !=3D A_FIR && size !=3D 1) || + (addr =3D=3D A_FIR && size !=3D 2)) { + qemu_log_mask(LOG_GUEST_ERROR, "rx_icu: Invalid write size at " + "0x%" HWADDR_PRIX "\n", + addr); + return; + } + switch (addr) { + case A_IR ... A_IR + 0xff: + if (icu->src[reg].sense !=3D TRG_LEVEL && val =3D=3D 0) { + icu->ir[reg] =3D 0; + } + break; + case A_DTCER ... A_DTCER + 0xff: + icu->dtcer[reg] =3D val & R_DTCER_DTCE_MASK; + qemu_log_mask(LOG_UNIMP, "rx_icu: DTC not implemented\n"); + break; + case A_IER ... A_IER + 0x1f: + icu->ier[reg] =3D val; + break; + case A_SWINTR: + if (val & R_SWINTR_SWINT_MASK) { + qemu_irq_pulse(icu->_swi); + } + break; + case A_FIR: + icu->fir =3D val & (R_FIR_FIEN_MASK | R_FIR_FVCT_MASK); + break; + case A_IPR ... A_IPR + 0x8f: + icu->ipr[reg] =3D val & R_IPR_IPR_MASK; + break; + case A_DMRSR: + case A_DMRSR + 4: + case A_DMRSR + 8: + case A_DMRSR + 12: + icu->dmasr[reg >> 2] =3D val; + qemu_log_mask(LOG_UNIMP, "rx_icu: DMAC not implemented\n"); + break; + case A_IRQCR ... A_IRQCR + 0x1f: + icu->src[64 + reg].sense =3D val >> R_IRQCR_IRQMD_SHIFT; + break; + case A_NMICLR: + break; + case A_NMIER: + icu->nmier |=3D val & (R_NMIER_NMIEN_MASK | + R_NMIER_LVDEN_MASK | + R_NMIER_OSTEN_MASK); + break; + case A_NMICR: + if ((icu->nmier & R_NMIER_NMIEN_MASK) =3D=3D 0) { + icu->nmicr =3D val & R_NMICR_NMIMD_MASK; + } + break; + default: + qemu_log_mask(LOG_UNIMP, "rx_icu: Register 0x%" HWADDR_PRIX " " + "not implemented\n", + addr); + break; + } +} + +static const MemoryRegionOps icu_ops =3D { + .write =3D icu_write, + .read =3D icu_read, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 2, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 2, + }, +}; + +static void rxicu_realize(DeviceState *dev, Error **errp) +{ + RXICUState *icu =3D RX_ICU(dev); + int i, j; + + if (icu->init_sense =3D=3D NULL) { + qemu_log_mask(LOG_GUEST_ERROR, + "rx_icu: trigger-level property must be set."); + return; + } + for (i =3D j =3D 0; i < NR_IRQS; i++) { + if (icu->init_sense[j] =3D=3D i) { + icu->src[i].sense =3D TRG_LEVEL; + if (j < icu->nr_sense) { + j++; + } + } else { + icu->src[i].sense =3D TRG_PEDGE; + } + } + icu->req_irq =3D -1; +} + +static void rxicu_init(Object *obj) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(obj); + RXICUState *icu =3D RX_ICU(obj); + + memory_region_init_io(&icu->memory, OBJECT(icu), &icu_ops, + icu, "rx-icu", 0x600); + sysbus_init_mmio(d, &icu->memory); + + qdev_init_gpio_in(DEVICE(d), rxicu_set_irq, NR_IRQS); + qdev_init_gpio_in_named(DEVICE(d), rxicu_ack_irq, "ack", 1); + sysbus_init_irq(d, &icu->_irq); + sysbus_init_irq(d, &icu->_fir); + sysbus_init_irq(d, &icu->_swi); +} + +static void rxicu_fini(Object *obj) +{ + RXICUState *icu =3D RX_ICU(obj); + g_free(icu->map); + g_free(icu->init_sense); +} + +static const VMStateDescription vmstate_rxicu =3D { + .name =3D "rx-icu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8_ARRAY(ir, RXICUState, NR_IRQS), + VMSTATE_UINT8_ARRAY(dtcer, RXICUState, NR_IRQS), + VMSTATE_UINT8_ARRAY(ier, RXICUState, NR_IRQS / 8), + VMSTATE_UINT8_ARRAY(ipr, RXICUState, 142), + VMSTATE_UINT8_ARRAY(dmasr, RXICUState, 4), + VMSTATE_UINT16(fir, RXICUState), + VMSTATE_UINT8(nmisr, RXICUState), + VMSTATE_UINT8(nmier, RXICUState), + VMSTATE_UINT8(nmiclr, RXICUState), + VMSTATE_UINT8(nmicr, RXICUState), + VMSTATE_INT16(req_irq, RXICUState), + VMSTATE_END_OF_LIST() + } +}; + +static Property rxicu_properties[] =3D { + DEFINE_PROP_ARRAY("ipr-map", RXICUState, nr_irqs, map, + qdev_prop_uint8, uint8_t), + DEFINE_PROP_ARRAY("trigger-level", RXICUState, nr_sense, init_sense, + qdev_prop_uint8, uint8_t), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rxicu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D rxicu_realize; + dc->vmsd =3D &vmstate_rxicu; + device_class_set_props(dc, rxicu_properties); +} + +static const TypeInfo rxicu_info =3D { + .name =3D TYPE_RX_ICU, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RXICUState), + .instance_init =3D rxicu_init, + .instance_finalize =3D rxicu_fini, + .class_init =3D rxicu_class_init, +}; + +static void rxicu_register_types(void) +{ + type_register_static(&rxicu_info); +} + +type_init(rxicu_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index f1ae0775f4..dd0297a74e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1971,6 +1971,12 @@ F: hw/char/sh_serial.c F: hw/timer/sh_timer.c F: include/hw/sh4/sh.h =20 +Renesas RX peripherals +M: Yoshinori Sato +S: Maintained +F: hw/intc/rx_icu.c +F: include/hw/intc/rx_icu.h + Subsystems ---------- Audio diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index a189d6fedd..f562342bab 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -61,3 +61,6 @@ config S390_FLIC_KVM =20 config OMPIC bool + +config RX_ICU + bool diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index f726d87532..98a0b0f3bc 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -20,6 +20,7 @@ common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_dist.o common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_redist.o common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_its_common.o common-obj-$(CONFIG_OPENPIC) +=3D openpic.o +common-obj-$(CONFIG_RX_ICU) +=3D rx_icu.o common-obj-y +=3D intc.o =20 obj-$(CONFIG_APIC) +=3D apic.o apic_common.o --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[83.51.162.1]) by smtp.gmail.com with ESMTPSA id o10sm13779362wrj.37.2020.06.21.05.48.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 05:48:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PdH+OhSKTHotwgzPomJixLmJ0d9c3wgyyXnXH5sGHKo=; b=T1CkL35CusfSTrPVpCfFEWv4aknabBez3xfU7WYgxUO1GDkF3cE7AyIzspugjWzvtd WJXOPuVkITYws5enrDdqchRw/C70TdFijnIX0JPNOmsEyXSnQTLc61/yszrtZ37BjhZA VLhl4uT87w5VU6ytXl2LSta6I5Y/EFPlDluxwS1hhBnIv62vK2PA67RXxbbcwJMQD97L 1ofd+tCi4Ga045MKunv3eG3ZAQ2AJxCSwJBfCJzQb0nGm/WtOqQz1qqehn9BEsq2fz/O MMGT6TDwOKFEU0WHLe2rwdzx6xuviOoTg3Uka0+TsoiFBo/QERnnw/p4k8laiEA7kwlf uOJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=PdH+OhSKTHotwgzPomJixLmJ0d9c3wgyyXnXH5sGHKo=; b=SF6QlfFZlCOO1SHCfBQRqyIVk6VTuna+DIwvYQzwitTjGII8I2Oa5UWSdiKuzh567C LATCMtgVlDuJMPz0VB6s7ae7LAK4t7NluxD+iIzPmHg7eNAgpfb5vQM8fJV96CHgP+hp LJeDW1plyap1uoR9ibUZSTx8oo5gp4GDjAV/MgQa2Pf+ZnF8QchrRAVJPVwStSOpxoVD uvjEFk3uHRhyh6DzPwCEKCJ9324Uy8MeFpMuUNnbeNCx22EIZExPtujLZ0SWGtpB+x0L av2EQ5Sh6u1jiRfZXmt24ZWZPcBR/Bt3LeROnq5rn0FiNxc+CE++vhAhAqTCSLqjyKbx 51Kw== X-Gm-Message-State: AOAM5302pEfZyQCOnxuxtuAwmMk04niDZ2HV0CBj5nFtO5FmubCTDuFn CjhnkWCw73pvyj6ufS3K6r2d39ES X-Google-Smtp-Source: ABdhPJzQNtssfN57upHhQhLBDQCwNMVK0M/Nmi9eeD0bT2MJ090y4gGrVXVFQ5QZ1HpFEb7NglDS8w== X-Received: by 2002:a5d:4dd0:: with SMTP id f16mr14543586wru.117.1592743698729; Sun, 21 Jun 2020 05:48:18 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 07/15] hw/timer: RX62N 8-Bit timer (TMR) Date: Sun, 21 Jun 2020 14:47:59 +0200 Message-Id: <20200621124807.17226-8-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200621124807.17226-1-f4bug@amsat.org> References: <20200621124807.17226-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato renesas_tmr: 8bit timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej= 0140_rx62n.pdf Signed-off-by: Yoshinori Sato Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-16-ysato@users.sourceforge.jp> [PMD: Split from CMT, filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/renesas_tmr.h | 55 ++++ hw/timer/renesas_tmr.c | 477 +++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + hw/timer/Kconfig | 3 + hw/timer/Makefile.objs | 1 + 5 files changed, 538 insertions(+) create mode 100644 include/hw/timer/renesas_tmr.h create mode 100644 hw/timer/renesas_tmr.c diff --git a/include/hw/timer/renesas_tmr.h b/include/hw/timer/renesas_tmr.h new file mode 100644 index 0000000000..cf3baa7a28 --- /dev/null +++ b/include/hw/timer/renesas_tmr.h @@ -0,0 +1,55 @@ +/* + * Renesas 8bit timer Object + * + * Copyright (c) 2018 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_TIMER_RENESAS_TMR_H +#define HW_TIMER_RENESAS_TMR_H + +#include "qemu/timer.h" +#include "hw/sysbus.h" + +#define TYPE_RENESAS_TMR "renesas-tmr" +#define RTMR(obj) OBJECT_CHECK(RTMRState, (obj), TYPE_RENESAS_TMR) + +enum timer_event { + cmia =3D 0, + cmib =3D 1, + ovi =3D 2, + none =3D 3, + TMR_NR_EVENTS =3D 4 +}; + +enum { + TMR_CH =3D 2, + TMR_NR_IRQ =3D 3 * TMR_CH +}; + +typedef struct RTMRState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + uint64_t input_freq; + MemoryRegion memory; + + int64_t tick; + uint8_t tcnt[TMR_CH]; + uint8_t tcora[TMR_CH]; + uint8_t tcorb[TMR_CH]; + uint8_t tcr[TMR_CH]; + uint8_t tccr[TMR_CH]; + uint8_t tcor[TMR_CH]; + uint8_t tcsr[TMR_CH]; + int64_t div_round[TMR_CH]; + uint8_t next[TMR_CH]; + qemu_irq cmia[TMR_CH]; + qemu_irq cmib[TMR_CH]; + qemu_irq ovi[TMR_CH]; + QEMUTimer timer[TMR_CH]; +} RTMRState; + +#endif diff --git a/hw/timer/renesas_tmr.c b/hw/timer/renesas_tmr.c new file mode 100644 index 0000000000..446f2eacdd --- /dev/null +++ b/hw/timer/renesas_tmr.c @@ -0,0 +1,477 @@ +/* + * Renesas 8bit timer + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/qdev-properties.h" +#include "hw/timer/renesas_tmr.h" +#include "migration/vmstate.h" + +REG8(TCR, 0) + FIELD(TCR, CCLR, 3, 2) + FIELD(TCR, OVIE, 5, 1) + FIELD(TCR, CMIEA, 6, 1) + FIELD(TCR, CMIEB, 7, 1) +REG8(TCSR, 2) + FIELD(TCSR, OSA, 0, 2) + FIELD(TCSR, OSB, 2, 2) + FIELD(TCSR, ADTE, 4, 2) +REG8(TCORA, 4) +REG8(TCORB, 6) +REG8(TCNT, 8) +REG8(TCCR, 10) + FIELD(TCCR, CKS, 0, 3) + FIELD(TCCR, CSS, 3, 2) + FIELD(TCCR, TMRIS, 7, 1) + +#define INTERNAL 0x01 +#define CASCADING 0x03 +#define CCLR_A 0x01 +#define CCLR_B 0x02 + +static const int clkdiv[] =3D {0, 1, 2, 8, 32, 64, 1024, 8192}; + +static uint8_t concat_reg(uint8_t *reg) +{ + return (reg[0] << 8) | reg[1]; +} + +static void update_events(RTMRState *tmr, int ch) +{ + uint16_t diff[TMR_NR_EVENTS], min; + int64_t next_time; + int i, event; + + if (tmr->tccr[ch] =3D=3D 0) { + return ; + } + if (FIELD_EX8(tmr->tccr[ch], TCCR, CSS) =3D=3D 0) { + /* external clock mode */ + /* event not happened */ + return ; + } + if (FIELD_EX8(tmr->tccr[0], TCCR, CSS) =3D=3D CASCADING) { + /* cascading mode */ + if (ch =3D=3D 1) { + tmr->next[ch] =3D none; + return ; + } + diff[cmia] =3D concat_reg(tmr->tcora) - concat_reg(tmr->tcnt); + diff[cmib] =3D concat_reg(tmr->tcorb) - concat_reg(tmr->tcnt); + diff[ovi] =3D 0x10000 - concat_reg(tmr->tcnt); + } else { + /* separate mode */ + diff[cmia] =3D tmr->tcora[ch] - tmr->tcnt[ch]; + diff[cmib] =3D tmr->tcorb[ch] - tmr->tcnt[ch]; + diff[ovi] =3D 0x100 - tmr->tcnt[ch]; + } + /* Search for the most recently occurring event. */ + for (event =3D 0, min =3D diff[0], i =3D 1; i < none; i++) { + if (min > diff[i]) { + event =3D i; + min =3D diff[i]; + } + } + tmr->next[ch] =3D event; + next_time =3D diff[event]; + next_time *=3D clkdiv[FIELD_EX8(tmr->tccr[ch], TCCR, CKS)]; + next_time *=3D NANOSECONDS_PER_SECOND; + next_time /=3D tmr->input_freq; + next_time +=3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + timer_mod(&tmr->timer[ch], next_time); +} + +static int elapsed_time(RTMRState *tmr, int ch, int64_t delta) +{ + int divrate =3D clkdiv[FIELD_EX8(tmr->tccr[ch], TCCR, CKS)]; + int et; + + tmr->div_round[ch] +=3D delta; + if (divrate > 0) { + et =3D tmr->div_round[ch] / divrate; + tmr->div_round[ch] %=3D divrate; + } else { + /* disble clock. so no update */ + et =3D 0; + } + return et; +} + +static uint16_t read_tcnt(RTMRState *tmr, unsigned size, int ch) +{ + int64_t delta, now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + int elapsed, ovf =3D 0; + uint16_t tcnt[2]; + uint32_t ret; + + delta =3D (now - tmr->tick) * NANOSECONDS_PER_SECOND / tmr->input_freq; + if (delta > 0) { + tmr->tick =3D now; + + if (FIELD_EX8(tmr->tccr[1], TCCR, CSS) =3D=3D INTERNAL) { + /* timer1 count update */ + elapsed =3D elapsed_time(tmr, 1, delta); + if (elapsed >=3D 0x100) { + ovf =3D elapsed >> 8; + } + tcnt[1] =3D tmr->tcnt[1] + (elapsed & 0xff); + } + switch (FIELD_EX8(tmr->tccr[0], TCCR, CSS)) { + case INTERNAL: + elapsed =3D elapsed_time(tmr, 0, delta); + tcnt[0] =3D tmr->tcnt[0] + elapsed; + break; + case CASCADING: + if (ovf > 0) { + tcnt[0] =3D tmr->tcnt[0] + ovf; + } + break; + } + } else { + tcnt[0] =3D tmr->tcnt[0]; + tcnt[1] =3D tmr->tcnt[1]; + } + if (size =3D=3D 1) { + return tcnt[ch]; + } else { + ret =3D 0; + ret =3D deposit32(ret, 0, 8, tcnt[1]); + ret =3D deposit32(ret, 8, 8, tcnt[0]); + return ret; + } +} + +static uint8_t read_tccr(uint8_t r) +{ + uint8_t tccr =3D 0; + tccr =3D FIELD_DP8(tccr, TCCR, TMRIS, + FIELD_EX8(r, TCCR, TMRIS)); + tccr =3D FIELD_DP8(tccr, TCCR, CSS, + FIELD_EX8(r, TCCR, CSS)); + tccr =3D FIELD_DP8(tccr, TCCR, CKS, + FIELD_EX8(r, TCCR, CKS)); + return tccr; +} + +static uint64_t tmr_read(void *opaque, hwaddr addr, unsigned size) +{ + RTMRState *tmr =3D opaque; + int ch =3D addr & 1; + uint64_t ret; + + if (size =3D=3D 2 && (ch !=3D 0 || addr =3D=3D A_TCR || addr =3D=3D A_= TCSR)) { + qemu_log_mask(LOG_GUEST_ERROR, "renesas_tmr: Invalid read size 0x%" + HWADDR_PRIX "\n", + addr); + return UINT64_MAX; + } + switch (addr & 0x0e) { + case A_TCR: + ret =3D 0; + ret =3D FIELD_DP8(ret, TCR, CCLR, + FIELD_EX8(tmr->tcr[ch], TCR, CCLR)); + ret =3D FIELD_DP8(ret, TCR, OVIE, + FIELD_EX8(tmr->tcr[ch], TCR, OVIE)); + ret =3D FIELD_DP8(ret, TCR, CMIEA, + FIELD_EX8(tmr->tcr[ch], TCR, CMIEA)); + ret =3D FIELD_DP8(ret, TCR, CMIEB, + FIELD_EX8(tmr->tcr[ch], TCR, CMIEB)); + return ret; + case A_TCSR: + ret =3D 0; + ret =3D FIELD_DP8(ret, TCSR, OSA, + FIELD_EX8(tmr->tcsr[ch], TCSR, OSA)); + ret =3D FIELD_DP8(ret, TCSR, OSB, + FIELD_EX8(tmr->tcsr[ch], TCSR, OSB)); + switch (ch) { + case 0: + ret =3D FIELD_DP8(ret, TCSR, ADTE, + FIELD_EX8(tmr->tcsr[ch], TCSR, ADTE)); + break; + case 1: /* CH1 ADTE unimplement always 1 */ + ret =3D FIELD_DP8(ret, TCSR, ADTE, 1); + break; + } + return ret; + case A_TCORA: + if (size =3D=3D 1) { + return tmr->tcora[ch]; + } else if (ch =3D=3D 0) { + return concat_reg(tmr->tcora); + } + case A_TCORB: + if (size =3D=3D 1) { + return tmr->tcorb[ch]; + } else { + return concat_reg(tmr->tcorb); + } + case A_TCNT: + return read_tcnt(tmr, size, ch); + case A_TCCR: + if (size =3D=3D 1) { + return read_tccr(tmr->tccr[ch]); + } else { + return read_tccr(tmr->tccr[0]) << 8 | read_tccr(tmr->tccr[1]); + } + default: + qemu_log_mask(LOG_UNIMP, "renesas_tmr: Register 0x%" HWADDR_PRIX + " not implemented\n", + addr); + break; + } + return UINT64_MAX; +} + +static void tmr_write_count(RTMRState *tmr, int ch, unsigned size, + uint8_t *reg, uint64_t val) +{ + if (size =3D=3D 1) { + reg[ch] =3D val; + update_events(tmr, ch); + } else { + reg[0] =3D extract32(val, 8, 8); + reg[1] =3D extract32(val, 0, 8); + update_events(tmr, 0); + update_events(tmr, 1); + } +} + +static void tmr_write(void *opaque, hwaddr addr, uint64_t val, unsigned si= ze) +{ + RTMRState *tmr =3D opaque; + int ch =3D addr & 1; + + if (size =3D=3D 2 && (ch !=3D 0 || addr =3D=3D A_TCR || addr =3D=3D A_= TCSR)) { + qemu_log_mask(LOG_GUEST_ERROR, + "renesas_tmr: Invalid write size 0x%" HWADDR_PRIX "\= n", + addr); + return; + } + switch (addr & 0x0e) { + case A_TCR: + tmr->tcr[ch] =3D val; + break; + case A_TCSR: + tmr->tcsr[ch] =3D val; + break; + case A_TCORA: + tmr_write_count(tmr, ch, size, tmr->tcora, val); + break; + case A_TCORB: + tmr_write_count(tmr, ch, size, tmr->tcorb, val); + break; + case A_TCNT: + tmr_write_count(tmr, ch, size, tmr->tcnt, val); + break; + case A_TCCR: + tmr_write_count(tmr, ch, size, tmr->tccr, val); + break; + default: + qemu_log_mask(LOG_UNIMP, "renesas_tmr: Register 0x%" HWADDR_PRIX + " not implemented\n", + addr); + break; + } +} + +static const MemoryRegionOps tmr_ops =3D { + .write =3D tmr_write, + .read =3D tmr_read, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 2, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 2, + }, +}; + +static void timer_events(RTMRState *tmr, int ch); + +static uint16_t issue_event(RTMRState *tmr, int ch, int sz, + uint16_t tcnt, uint16_t tcora, uint16_t tcorb) +{ + uint16_t ret =3D tcnt; + + switch (tmr->next[ch]) { + case none: + break; + case cmia: + if (tcnt >=3D tcora) { + if (FIELD_EX8(tmr->tcr[ch], TCR, CCLR) =3D=3D CCLR_A) { + ret =3D tcnt - tcora; + } + if (FIELD_EX8(tmr->tcr[ch], TCR, CMIEA)) { + qemu_irq_pulse(tmr->cmia[ch]); + } + if (sz =3D=3D 8 && ch =3D=3D 0 && + FIELD_EX8(tmr->tccr[1], TCCR, CSS) =3D=3D CASCADING) { + tmr->tcnt[1]++; + timer_events(tmr, 1); + } + } + break; + case cmib: + if (tcnt >=3D tcorb) { + if (FIELD_EX8(tmr->tcr[ch], TCR, CCLR) =3D=3D CCLR_B) { + ret =3D tcnt - tcorb; + } + if (FIELD_EX8(tmr->tcr[ch], TCR, CMIEB)) { + qemu_irq_pulse(tmr->cmib[ch]); + } + } + break; + case ovi: + if ((tcnt >=3D (1 << sz)) && FIELD_EX8(tmr->tcr[ch], TCR, OVIE)) { + qemu_irq_pulse(tmr->ovi[ch]); + } + break; + default: + g_assert_not_reached(); + } + return ret; +} + +static void timer_events(RTMRState *tmr, int ch) +{ + uint16_t tcnt; + + tmr->tcnt[ch] =3D read_tcnt(tmr, 1, ch); + if (FIELD_EX8(tmr->tccr[0], TCCR, CSS) !=3D CASCADING) { + tmr->tcnt[ch] =3D issue_event(tmr, ch, 8, + tmr->tcnt[ch], + tmr->tcora[ch], + tmr->tcorb[ch]) & 0xff; + } else { + if (ch =3D=3D 1) { + return ; + } + tcnt =3D issue_event(tmr, ch, 16, + concat_reg(tmr->tcnt), + concat_reg(tmr->tcora), + concat_reg(tmr->tcorb)); + tmr->tcnt[0] =3D (tcnt >> 8) & 0xff; + tmr->tcnt[1] =3D tcnt & 0xff; + } + update_events(tmr, ch); +} + +static void timer_event0(void *opaque) +{ + RTMRState *tmr =3D opaque; + + timer_events(tmr, 0); +} + +static void timer_event1(void *opaque) +{ + RTMRState *tmr =3D opaque; + + timer_events(tmr, 1); +} + +static void rtmr_reset(DeviceState *dev) +{ + RTMRState *tmr =3D RTMR(dev); + tmr->tcr[0] =3D tmr->tcr[1] =3D 0x00; + tmr->tcsr[0] =3D 0x00; + tmr->tcsr[1] =3D 0x10; + tmr->tcnt[0] =3D tmr->tcnt[1] =3D 0x00; + tmr->tcora[0] =3D tmr->tcora[1] =3D 0xff; + tmr->tcorb[0] =3D tmr->tcorb[1] =3D 0xff; + tmr->tccr[0] =3D tmr->tccr[1] =3D 0x00; + tmr->next[0] =3D tmr->next[1] =3D none; + tmr->tick =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); +} + +static void rtmr_init(Object *obj) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(obj); + RTMRState *tmr =3D RTMR(obj); + int i; + + memory_region_init_io(&tmr->memory, OBJECT(tmr), &tmr_ops, + tmr, "renesas-tmr", 0x10); + sysbus_init_mmio(d, &tmr->memory); + + for (i =3D 0; i < ARRAY_SIZE(tmr->ovi); i++) { + sysbus_init_irq(d, &tmr->cmia[i]); + sysbus_init_irq(d, &tmr->cmib[i]); + sysbus_init_irq(d, &tmr->ovi[i]); + } + timer_init_ns(&tmr->timer[0], QEMU_CLOCK_VIRTUAL, timer_event0, tmr); + timer_init_ns(&tmr->timer[1], QEMU_CLOCK_VIRTUAL, timer_event1, tmr); +} + +static const VMStateDescription vmstate_rtmr =3D { + .name =3D "rx-tmr", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_INT64(tick, RTMRState), + VMSTATE_UINT8_ARRAY(tcnt, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(tcora, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(tcorb, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(tcr, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(tccr, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(tcor, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(tcsr, RTMRState, TMR_CH), + VMSTATE_INT64_ARRAY(div_round, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(next, RTMRState, TMR_CH), + VMSTATE_TIMER_ARRAY(timer, RTMRState, TMR_CH), + VMSTATE_END_OF_LIST() + } +}; + +static Property rtmr_properties[] =3D { + DEFINE_PROP_UINT64("input-freq", RTMRState, input_freq, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rtmr_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_rtmr; + dc->reset =3D rtmr_reset; + device_class_set_props(dc, rtmr_properties); +} + +static const TypeInfo rtmr_info =3D { + .name =3D TYPE_RENESAS_TMR, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RTMRState), + .instance_init =3D rtmr_init, + .class_init =3D rtmr_class_init, +}; + +static void rtmr_register_types(void) +{ + type_register_static(&rtmr_info); +} + +type_init(rtmr_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index dd0297a74e..4c84fb13ef 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1968,8 +1968,10 @@ M: Yoshinori Sato R: Magnus Damm S: Maintained F: hw/char/sh_serial.c +F: hw/timer/renesas_tmr.c F: hw/timer/sh_timer.c F: include/hw/sh4/sh.h +F: include/hw/timer/renesas_tmr.h =20 Renesas RX peripherals M: Yoshinori Sato diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig index 59b3f44d69..7039c2a686 100644 --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -35,3 +35,6 @@ config CMSDK_APB_TIMER config CMSDK_APB_DUALTIMER bool select PTIMER + +config RENESAS_TMR + bool diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index dece235fd7..44fb47a433 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -23,6 +23,7 @@ common-obj-$(CONFIG_OMAP) +=3D omap_gptimer.o common-obj-$(CONFIG_OMAP) +=3D omap_synctimer.o common-obj-$(CONFIG_PXA2XX) +=3D pxa2xx_timer.o common-obj-$(CONFIG_SH4) +=3D sh_timer.o +common-obj-$(CONFIG_RENESAS_TMR) +=3D renesas_tmr.o common-obj-$(CONFIG_DIGIC) +=3D digic-timer.o common-obj-$(CONFIG_MIPS_CPS) +=3D mips_gictimer.o =20 --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[83.51.162.1]) by smtp.gmail.com with ESMTPSA id o10sm13779362wrj.37.2020.06.21.05.48.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 05:48:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bcKld0eaekjaOavSgG+FcA8qhxJmWxkd64BI9BXaJ5g=; b=mtvZBekX+ZpvaowXv00oY7hwRcukXUv6IIMDIyRQoh0pFbMo6eWfteXf38NRmApO6T InQlekkPJ7jYyIAedw0WCBQWNxOPoVhFgOWq1S3596Rcn/VJd95pMfyo2NsgJSJksI1z jQTrfmrf34owhoafsl+cUmEOqfN6KBO1NW6Fy9i2bqwTo3MRdHRmkU6oGwe357GtjIpE kq0P7/k0Qnaf28rGI2mT9jooW5YzSKYkTs0WfmLSaTgz0Ave5eye5rP+J9zC6BuZwHDP y06rdI86wv99q+0OViCfniqFkZejMOW1iZDK1sR+PDvFou7Xu8PlGqQMbkkgleIYxdIc UzYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=bcKld0eaekjaOavSgG+FcA8qhxJmWxkd64BI9BXaJ5g=; b=oNA//ZSQtsIMWOmEcVbHGhvPLVE2p4QoPpKf+miHlrAEyUDQx3XBdFKGQB7oQ8OBGs oUnrugBxeCYOGeBBQK9cip9sb5CczllHPJ9houJfEeGa67PY76coiuVtzSQ8rjXJ9mxi 5wQKmVLX9Q/MxksX3GStNilwmlLVbmjITlGgU/GjmYt4KF1Bz35dvm2lgwZa+gO5arIu 4JjuuX8sblDl7cJojLpRWeFYrFRYfjTDkkn+PtQMqxN/rksDl/ow8axo0k06VUwcVu+w SlpjaeHWOCfAzMVDD1UPagiAK1+ILzcLOknHmOWfIuGVVrLLMDK0Iqx3SwnUoUWR8BEh d+mA== X-Gm-Message-State: AOAM5324iRdvDWtSqT5fU2KSPJQCqR5Eb/vNZeAJTNO0ZX/UnBiAKy+L pQ0Rl57iV0waFsNk8g0m7bHRjU/n X-Google-Smtp-Source: ABdhPJw3dbU9UCtk5NWz2Lay1UnxV8EKJ2st9L7BFKvqUAUFh1Cv9jqzPQkKmbtFpvsq+oLui8YzvA== X-Received: by 2002:adf:cc85:: with SMTP id p5mr10034105wrj.273.1592743700155; Sun, 21 Jun 2020 05:48:20 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 08/15] hw/timer: RX62N compare match timer (CMT) Date: Sun, 21 Jun 2020 14:48:00 +0200 Message-Id: <20200621124807.17226-9-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200621124807.17226-1-f4bug@amsat.org> References: <20200621124807.17226-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato renesas_cmt: 16bit compare match timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej= 0140_rx62n.pdf Signed-off-by: Yoshinori Sato Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-16-ysato@users.sourceforge.jp> [PMD: Split from TMR, filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/renesas_cmt.h | 40 +++++ hw/timer/renesas_cmt.c | 283 +++++++++++++++++++++++++++++++++ MAINTAINERS | 4 +- hw/timer/Kconfig | 3 + hw/timer/Makefile.objs | 1 + 5 files changed, 329 insertions(+), 2 deletions(-) create mode 100644 include/hw/timer/renesas_cmt.h create mode 100644 hw/timer/renesas_cmt.c diff --git a/include/hw/timer/renesas_cmt.h b/include/hw/timer/renesas_cmt.h new file mode 100644 index 0000000000..e28a15cb38 --- /dev/null +++ b/include/hw/timer/renesas_cmt.h @@ -0,0 +1,40 @@ +/* + * Renesas Compare-match timer Object + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_TIMER_RENESAS_CMT_H +#define HW_TIMER_RENESAS_CMT_H + +#include "qemu/timer.h" +#include "hw/sysbus.h" + +#define TYPE_RENESAS_CMT "renesas-cmt" +#define RCMT(obj) OBJECT_CHECK(RCMTState, (obj), TYPE_RENESAS_CMT) + +enum { + CMT_CH =3D 2, + CMT_NR_IRQ =3D 1 * CMT_CH +}; + +typedef struct RCMTState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + uint64_t input_freq; + MemoryRegion memory; + + uint16_t cmstr; + uint16_t cmcr[CMT_CH]; + uint16_t cmcnt[CMT_CH]; + uint16_t cmcor[CMT_CH]; + int64_t tick[CMT_CH]; + qemu_irq cmi[CMT_CH]; + QEMUTimer timer[CMT_CH]; +} RCMTState; + +#endif diff --git a/hw/timer/renesas_cmt.c b/hw/timer/renesas_cmt.c new file mode 100644 index 0000000000..2e0fd21a36 --- /dev/null +++ b/hw/timer/renesas_cmt.c @@ -0,0 +1,283 @@ +/* + * Renesas 16bit Compare-match timer + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/qdev-properties.h" +#include "hw/timer/renesas_cmt.h" +#include "migration/vmstate.h" + +/* + * +0 CMSTR - common control + * +2 CMCR - ch0 + * +4 CMCNT - ch0 + * +6 CMCOR - ch0 + * +8 CMCR - ch1 + * +10 CMCNT - ch1 + * +12 CMCOR - ch1 + * If we think that the address of CH 0 has an offset of +2, + * we can treat it with the same address as CH 1, so define it like that. + */ +REG16(CMSTR, 0) + FIELD(CMSTR, STR0, 0, 1) + FIELD(CMSTR, STR1, 1, 1) + FIELD(CMSTR, STR, 0, 2) +/* This addeess is channel offset */ +REG16(CMCR, 0) + FIELD(CMCR, CKS, 0, 2) + FIELD(CMCR, CMIE, 6, 1) +REG16(CMCNT, 2) +REG16(CMCOR, 4) + +static void update_events(RCMTState *cmt, int ch) +{ + int64_t next_time; + + if ((cmt->cmstr & (1 << ch)) =3D=3D 0) { + /* count disable, so not happened next event. */ + return ; + } + next_time =3D cmt->cmcor[ch] - cmt->cmcnt[ch]; + next_time *=3D NANOSECONDS_PER_SECOND; + next_time /=3D cmt->input_freq; + /* + * CKS -> div rate + * 0 -> 8 (1 << 3) + * 1 -> 32 (1 << 5) + * 2 -> 128 (1 << 7) + * 3 -> 512 (1 << 9) + */ + next_time *=3D 1 << (3 + FIELD_EX16(cmt->cmcr[ch], CMCR, CKS) * 2); + next_time +=3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + timer_mod(&cmt->timer[ch], next_time); +} + +static int64_t read_cmcnt(RCMTState *cmt, int ch) +{ + int64_t delta, now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + + if (cmt->cmstr & (1 << ch)) { + delta =3D (now - cmt->tick[ch]); + delta /=3D NANOSECONDS_PER_SECOND; + delta /=3D cmt->input_freq; + delta /=3D 1 << (3 + FIELD_EX16(cmt->cmcr[ch], CMCR, CKS) * 2); + cmt->tick[ch] =3D now; + return cmt->cmcnt[ch] + delta; + } else { + return cmt->cmcnt[ch]; + } +} + +static uint64_t cmt_read(void *opaque, hwaddr offset, unsigned size) +{ + RCMTState *cmt =3D opaque; + int ch =3D offset / 0x08; + uint64_t ret; + + if (offset =3D=3D A_CMSTR) { + ret =3D 0; + ret =3D FIELD_DP16(ret, CMSTR, STR, + FIELD_EX16(cmt->cmstr, CMSTR, STR)); + return ret; + } else { + offset &=3D 0x07; + if (ch =3D=3D 0) { + offset -=3D 0x02; + } + switch (offset) { + case A_CMCR: + ret =3D 0; + ret =3D FIELD_DP16(ret, CMCR, CKS, + FIELD_EX16(cmt->cmstr, CMCR, CKS)); + ret =3D FIELD_DP16(ret, CMCR, CMIE, + FIELD_EX16(cmt->cmstr, CMCR, CMIE)); + return ret; + case A_CMCNT: + return read_cmcnt(cmt, ch); + case A_CMCOR: + return cmt->cmcor[ch]; + } + } + qemu_log_mask(LOG_UNIMP, "renesas_cmt: Register 0x%" HWADDR_PRIX " " + "not implemented\n", + offset); + return UINT64_MAX; +} + +static void start_stop(RCMTState *cmt, int ch, int st) +{ + if (st) { + update_events(cmt, ch); + } else { + timer_del(&cmt->timer[ch]); + } +} + +static void cmt_write(void *opaque, hwaddr offset, uint64_t val, unsigned = size) +{ + RCMTState *cmt =3D opaque; + int ch =3D offset / 0x08; + + if (offset =3D=3D A_CMSTR) { + cmt->cmstr =3D FIELD_EX16(val, CMSTR, STR); + start_stop(cmt, 0, FIELD_EX16(cmt->cmstr, CMSTR, STR0)); + start_stop(cmt, 1, FIELD_EX16(cmt->cmstr, CMSTR, STR1)); + } else { + offset &=3D 0x07; + if (ch =3D=3D 0) { + offset -=3D 0x02; + } + switch (offset) { + case A_CMCR: + cmt->cmcr[ch] =3D FIELD_DP16(cmt->cmcr[ch], CMCR, CKS, + FIELD_EX16(val, CMCR, CKS)); + cmt->cmcr[ch] =3D FIELD_DP16(cmt->cmcr[ch], CMCR, CMIE, + FIELD_EX16(val, CMCR, CMIE)); + break; + case 2: + cmt->cmcnt[ch] =3D val; + break; + case 4: + cmt->cmcor[ch] =3D val; + break; + default: + qemu_log_mask(LOG_UNIMP, "renesas_cmt: Register 0x%" HWADDR_PR= IX " " + "not implemented\n", + offset); + return; + } + if (FIELD_EX16(cmt->cmstr, CMSTR, STR) & (1 << ch)) { + update_events(cmt, ch); + } + } +} + +static const MemoryRegionOps cmt_ops =3D { + .write =3D cmt_write, + .read =3D cmt_read, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 2, + .max_access_size =3D 2, + }, + .valid =3D { + .min_access_size =3D 2, + .max_access_size =3D 2, + }, +}; + +static void timer_events(RCMTState *cmt, int ch) +{ + cmt->cmcnt[ch] =3D 0; + cmt->tick[ch] =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + update_events(cmt, ch); + if (FIELD_EX16(cmt->cmcr[ch], CMCR, CMIE)) { + qemu_irq_pulse(cmt->cmi[ch]); + } +} + +static void timer_event0(void *opaque) +{ + RCMTState *cmt =3D opaque; + + timer_events(cmt, 0); +} + +static void timer_event1(void *opaque) +{ + RCMTState *cmt =3D opaque; + + timer_events(cmt, 1); +} + +static void rcmt_reset(DeviceState *dev) +{ + RCMTState *cmt =3D RCMT(dev); + cmt->cmstr =3D 0; + cmt->cmcr[0] =3D cmt->cmcr[1] =3D 0; + cmt->cmcnt[0] =3D cmt->cmcnt[1] =3D 0; + cmt->cmcor[0] =3D cmt->cmcor[1] =3D 0xffff; +} + +static void rcmt_init(Object *obj) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(obj); + RCMTState *cmt =3D RCMT(obj); + int i; + + memory_region_init_io(&cmt->memory, OBJECT(cmt), &cmt_ops, + cmt, "renesas-cmt", 0x10); + sysbus_init_mmio(d, &cmt->memory); + + for (i =3D 0; i < ARRAY_SIZE(cmt->cmi); i++) { + sysbus_init_irq(d, &cmt->cmi[i]); + } + timer_init_ns(&cmt->timer[0], QEMU_CLOCK_VIRTUAL, timer_event0, cmt); + timer_init_ns(&cmt->timer[1], QEMU_CLOCK_VIRTUAL, timer_event1, cmt); +} + +static const VMStateDescription vmstate_rcmt =3D { + .name =3D "rx-cmt", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT16(cmstr, RCMTState), + VMSTATE_UINT16_ARRAY(cmcr, RCMTState, CMT_CH), + VMSTATE_UINT16_ARRAY(cmcnt, RCMTState, CMT_CH), + VMSTATE_UINT16_ARRAY(cmcor, RCMTState, CMT_CH), + VMSTATE_INT64_ARRAY(tick, RCMTState, CMT_CH), + VMSTATE_TIMER_ARRAY(timer, RCMTState, CMT_CH), + VMSTATE_END_OF_LIST() + } +}; + +static Property rcmt_properties[] =3D { + DEFINE_PROP_UINT64("input-freq", RCMTState, input_freq, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rcmt_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_rcmt; + dc->reset =3D rcmt_reset; + device_class_set_props(dc, rcmt_properties); +} + +static const TypeInfo rcmt_info =3D { + .name =3D TYPE_RENESAS_CMT, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RCMTState), + .instance_init =3D rcmt_init, + .class_init =3D rcmt_class_init, +}; + +static void rcmt_register_types(void) +{ + type_register_static(&rcmt_info); +} + +type_init(rcmt_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 4c84fb13ef..b9eb14b27f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1968,10 +1968,10 @@ M: Yoshinori Sato R: Magnus Damm S: Maintained F: hw/char/sh_serial.c -F: hw/timer/renesas_tmr.c +F: hw/timer/renesas_*.c F: hw/timer/sh_timer.c F: include/hw/sh4/sh.h -F: include/hw/timer/renesas_tmr.h +F: include/hw/timer/renesas_*.h =20 Renesas RX peripherals M: Yoshinori Sato diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig index 7039c2a686..59a667c503 100644 --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -38,3 +38,6 @@ config CMSDK_APB_DUALTIMER =20 config RENESAS_TMR bool + +config RENESAS_CMT + bool diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 44fb47a433..a39f6ec0c2 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -24,6 +24,7 @@ common-obj-$(CONFIG_OMAP) +=3D omap_synctimer.o common-obj-$(CONFIG_PXA2XX) +=3D pxa2xx_timer.o common-obj-$(CONFIG_SH4) +=3D sh_timer.o common-obj-$(CONFIG_RENESAS_TMR) +=3D renesas_tmr.o +common-obj-$(CONFIG_RENESAS_CMT) +=3D renesas_cmt.o common-obj-$(CONFIG_DIGIC) +=3D digic-timer.o common-obj-$(CONFIG_MIPS_CPS) +=3D mips_gictimer.o =20 --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej= 0140_rx62n.pdf Signed-off-by: Yoshinori Sato Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-17-ysato@users.sourceforge.jp> [PMD: Filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/char/renesas_sci.h | 51 +++++ hw/char/renesas_sci.c | 350 ++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + hw/char/Kconfig | 3 + hw/char/Makefile.objs | 1 + 5 files changed, 407 insertions(+) create mode 100644 include/hw/char/renesas_sci.h create mode 100644 hw/char/renesas_sci.c diff --git a/include/hw/char/renesas_sci.h b/include/hw/char/renesas_sci.h new file mode 100644 index 0000000000..efdebc620a --- /dev/null +++ b/include/hw/char/renesas_sci.h @@ -0,0 +1,51 @@ +/* + * Renesas Serial Communication Interface + * + * Copyright (c) 2018 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_CHAR_RENESAS_SCI_H +#define HW_CHAR_RENESAS_SCI_H + +#include "chardev/char-fe.h" +#include "hw/sysbus.h" + +#define TYPE_RENESAS_SCI "renesas-sci" +#define RSCI(obj) OBJECT_CHECK(RSCIState, (obj), TYPE_RENESAS_SCI) + +enum { + ERI =3D 0, + RXI =3D 1, + TXI =3D 2, + TEI =3D 3, + SCI_NR_IRQ =3D 4 +}; + +typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion memory; + QEMUTimer timer; + CharBackend chr; + qemu_irq irq[SCI_NR_IRQ]; + + uint8_t smr; + uint8_t brr; + uint8_t scr; + uint8_t tdr; + uint8_t ssr; + uint8_t rdr; + uint8_t scmr; + uint8_t semr; + + uint8_t read_ssr; + int64_t trtime; + int64_t rx_next; + uint64_t input_freq; +} RSCIState; + +#endif diff --git a/hw/char/renesas_sci.c b/hw/char/renesas_sci.c new file mode 100644 index 0000000000..5d7c6e6523 --- /dev/null +++ b/hw/char/renesas_sci.c @@ -0,0 +1,350 @@ +/* + * Renesas Serial Communication Interface + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/qdev-properties.h" +#include "hw/char/renesas_sci.h" +#include "migration/vmstate.h" + +/* SCI register map */ +REG8(SMR, 0) + FIELD(SMR, CKS, 0, 2) + FIELD(SMR, MP, 2, 1) + FIELD(SMR, STOP, 3, 1) + FIELD(SMR, PM, 4, 1) + FIELD(SMR, PE, 5, 1) + FIELD(SMR, CHR, 6, 1) + FIELD(SMR, CM, 7, 1) +REG8(BRR, 1) +REG8(SCR, 2) + FIELD(SCR, CKE, 0, 2) + FIELD(SCR, TEIE, 2, 1) + FIELD(SCR, MPIE, 3, 1) + FIELD(SCR, RE, 4, 1) + FIELD(SCR, TE, 5, 1) + FIELD(SCR, RIE, 6, 1) + FIELD(SCR, TIE, 7, 1) +REG8(TDR, 3) +REG8(SSR, 4) + FIELD(SSR, MPBT, 0, 1) + FIELD(SSR, MPB, 1, 1) + FIELD(SSR, TEND, 2, 1) + FIELD(SSR, ERR, 3, 3) + FIELD(SSR, PER, 3, 1) + FIELD(SSR, FER, 4, 1) + FIELD(SSR, ORER, 5, 1) + FIELD(SSR, RDRF, 6, 1) + FIELD(SSR, TDRE, 7, 1) +REG8(RDR, 5) +REG8(SCMR, 6) + FIELD(SCMR, SMIF, 0, 1) + FIELD(SCMR, SINV, 2, 1) + FIELD(SCMR, SDIR, 3, 1) + FIELD(SCMR, BCP2, 7, 1) +REG8(SEMR, 7) + FIELD(SEMR, ACS0, 0, 1) + FIELD(SEMR, ABCS, 4, 1) + +static int can_receive(void *opaque) +{ + RSCIState *sci =3D RSCI(opaque); + if (sci->rx_next > qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { + return 0; + } else { + return FIELD_EX8(sci->scr, SCR, RE); + } +} + +static void receive(void *opaque, const uint8_t *buf, int size) +{ + RSCIState *sci =3D RSCI(opaque); + sci->rx_next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime; + if (FIELD_EX8(sci->ssr, SSR, RDRF) || size > 1) { + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, ORER, 1); + if (FIELD_EX8(sci->scr, SCR, RIE)) { + qemu_set_irq(sci->irq[ERI], 1); + } + } else { + sci->rdr =3D buf[0]; + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, RDRF, 1); + if (FIELD_EX8(sci->scr, SCR, RIE)) { + qemu_irq_pulse(sci->irq[RXI]); + } + } +} + +static void send_byte(RSCIState *sci) +{ + if (qemu_chr_fe_backend_connected(&sci->chr)) { + qemu_chr_fe_write_all(&sci->chr, &sci->tdr, 1); + } + timer_mod(&sci->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->tr= time); + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TEND, 0); + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TDRE, 1); + qemu_set_irq(sci->irq[TEI], 0); + if (FIELD_EX8(sci->scr, SCR, TIE)) { + qemu_irq_pulse(sci->irq[TXI]); + } +} + +static void txend(void *opaque) +{ + RSCIState *sci =3D RSCI(opaque); + if (!FIELD_EX8(sci->ssr, SSR, TDRE)) { + send_byte(sci); + } else { + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TEND, 1); + if (FIELD_EX8(sci->scr, SCR, TEIE)) { + qemu_set_irq(sci->irq[TEI], 1); + } + } +} + +static void update_trtime(RSCIState *sci) +{ + /* char per bits */ + sci->trtime =3D 8 - FIELD_EX8(sci->smr, SMR, CHR); + sci->trtime +=3D FIELD_EX8(sci->smr, SMR, PE); + sci->trtime +=3D FIELD_EX8(sci->smr, SMR, STOP) + 1; + /* x bit transmit time (32 * divrate * brr) / base freq */ + sci->trtime *=3D 32 * sci->brr; + sci->trtime *=3D 1 << (2 * FIELD_EX8(sci->smr, SMR, CKS)); + sci->trtime *=3D NANOSECONDS_PER_SECOND; + sci->trtime /=3D sci->input_freq; +} + +static bool sci_is_tr_enabled(RSCIState *sci) +{ + return FIELD_EX8(sci->scr, SCR, TE) || FIELD_EX8(sci->scr, SCR, RE); +} + +static void sci_write(void *opaque, hwaddr offset, uint64_t val, unsigned = size) +{ + RSCIState *sci =3D RSCI(opaque); + + switch (offset) { + case A_SMR: + if (!sci_is_tr_enabled(sci)) { + sci->smr =3D val; + update_trtime(sci); + } + break; + case A_BRR: + if (!sci_is_tr_enabled(sci)) { + sci->brr =3D val; + update_trtime(sci); + } + break; + case A_SCR: + sci->scr =3D val; + if (FIELD_EX8(sci->scr, SCR, TE)) { + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TDRE, 1); + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TEND, 1); + if (FIELD_EX8(sci->scr, SCR, TIE)) { + qemu_irq_pulse(sci->irq[TXI]); + } + } + if (!FIELD_EX8(sci->scr, SCR, TEIE)) { + qemu_set_irq(sci->irq[TEI], 0); + } + if (!FIELD_EX8(sci->scr, SCR, RIE)) { + qemu_set_irq(sci->irq[ERI], 0); + } + break; + case A_TDR: + sci->tdr =3D val; + if (FIELD_EX8(sci->ssr, SSR, TEND)) { + send_byte(sci); + } else { + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TDRE, 0); + } + break; + case A_SSR: + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, MPBT, + FIELD_EX8(val, SSR, MPBT)); + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, ERR, + FIELD_EX8(val, SSR, ERR) & 0x07); + if (FIELD_EX8(sci->read_ssr, SSR, ERR) && + FIELD_EX8(sci->ssr, SSR, ERR) =3D=3D 0) { + qemu_set_irq(sci->irq[ERI], 0); + } + break; + case A_RDR: + qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: RDR is read only.\n"); + break; + case A_SCMR: + sci->scmr =3D val; break; + case A_SEMR: /* SEMR */ + sci->semr =3D val; break; + default: + qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX "= " + "not implemented\n", + offset); + } +} + +static uint64_t sci_read(void *opaque, hwaddr offset, unsigned size) +{ + RSCIState *sci =3D RSCI(opaque); + + switch (offset) { + case A_SMR: + return sci->smr; + case A_BRR: + return sci->brr; + case A_SCR: + return sci->scr; + case A_TDR: + return sci->tdr; + case A_SSR: + sci->read_ssr =3D sci->ssr; + return sci->ssr; + case A_RDR: + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, RDRF, 0); + return sci->rdr; + case A_SCMR: + return sci->scmr; + case A_SEMR: + return sci->semr; + default: + qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX + " not implemented.\n", offset); + } + return UINT64_MAX; +} + +static const MemoryRegionOps sci_ops =3D { + .write =3D sci_write, + .read =3D sci_read, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl.max_access_size =3D 1, + .valid.max_access_size =3D 1, +}; + +static void rsci_reset(DeviceState *dev) +{ + RSCIState *sci =3D RSCI(dev); + sci->smr =3D sci->scr =3D 0x00; + sci->brr =3D 0xff; + sci->tdr =3D 0xff; + sci->rdr =3D 0x00; + sci->ssr =3D 0x84; + sci->scmr =3D 0x00; + sci->semr =3D 0x00; + sci->rx_next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); +} + +static void sci_event(void *opaque, QEMUChrEvent event) +{ + RSCIState *sci =3D RSCI(opaque); + if (event =3D=3D CHR_EVENT_BREAK) { + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, FER, 1); + if (FIELD_EX8(sci->scr, SCR, RIE)) { + qemu_set_irq(sci->irq[ERI], 1); + } + } +} + +static void rsci_realize(DeviceState *dev, Error **errp) +{ + RSCIState *sci =3D RSCI(dev); + + if (sci->input_freq =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "renesas_sci: input-freq property must be set."); + return; + } + qemu_chr_fe_set_handlers(&sci->chr, can_receive, receive, + sci_event, NULL, sci, NULL, true); +} + +static void rsci_init(Object *obj) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(obj); + RSCIState *sci =3D RSCI(obj); + int i; + + memory_region_init_io(&sci->memory, OBJECT(sci), &sci_ops, + sci, "renesas-sci", 0x8); + sysbus_init_mmio(d, &sci->memory); + + for (i =3D 0; i < SCI_NR_IRQ; i++) { + sysbus_init_irq(d, &sci->irq[i]); + } + timer_init_ns(&sci->timer, QEMU_CLOCK_VIRTUAL, txend, sci); +} + +static const VMStateDescription vmstate_rsci =3D { + .name =3D "renesas-sci", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_INT64(trtime, RSCIState), + VMSTATE_INT64(rx_next, RSCIState), + VMSTATE_UINT8(smr, RSCIState), + VMSTATE_UINT8(brr, RSCIState), + VMSTATE_UINT8(scr, RSCIState), + VMSTATE_UINT8(tdr, RSCIState), + VMSTATE_UINT8(ssr, RSCIState), + VMSTATE_UINT8(rdr, RSCIState), + VMSTATE_UINT8(scmr, RSCIState), + VMSTATE_UINT8(semr, RSCIState), + VMSTATE_UINT8(read_ssr, RSCIState), + VMSTATE_TIMER(timer, RSCIState), + VMSTATE_END_OF_LIST() + } +}; + +static Property rsci_properties[] =3D { + DEFINE_PROP_UINT64("input-freq", RSCIState, input_freq, 0), + DEFINE_PROP_CHR("chardev", RSCIState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rsci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D rsci_realize; + dc->vmsd =3D &vmstate_rsci; + dc->reset =3D rsci_reset; + device_class_set_props(dc, rsci_properties); +} + +static const TypeInfo rsci_info =3D { + .name =3D TYPE_RENESAS_SCI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RSCIState), + .instance_init =3D rsci_init, + .class_init =3D rsci_class_init, +}; + +static void rsci_register_types(void) +{ + type_register_static(&rsci_info); +} + +type_init(rsci_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index b9eb14b27f..dd829b300a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1967,9 +1967,11 @@ Renesas peripherals M: Yoshinori Sato R: Magnus Damm S: Maintained +F: hw/char/renesas_sci.c F: hw/char/sh_serial.c F: hw/timer/renesas_*.c F: hw/timer/sh_timer.c +F: include/hw/char/renesas_sci.h F: include/hw/sh4/sh.h F: include/hw/timer/renesas_*.h =20 diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 40e7a8b8bb..874627520c 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -46,3 +46,6 @@ config SCLPCONSOLE =20 config TERMINAL3270 bool + +config RENESAS_SCI + bool diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index 9e9a6c1aff..996c170750 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -20,6 +20,7 @@ common-obj-$(CONFIG_SH4) +=3D sh_serial.o common-obj-$(CONFIG_DIGIC) +=3D digic-uart.o common-obj-$(CONFIG_STM32F2XX_USART) +=3D stm32f2xx_usart.o common-obj-$(CONFIG_RASPI) +=3D bcm2835_aux.o +common-obj-$(CONFIG_RENESAS_SCI) +=3D renesas_sci.o =20 common-obj-$(CONFIG_CMSDK_APB_UART) +=3D cmsdk-apb-uart.o common-obj-$(CONFIG_ETRAXFS) +=3D etraxfs_ser.o --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[83.51.162.1]) by smtp.gmail.com with ESMTPSA id o10sm13779362wrj.37.2020.06.21.05.48.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 05:48:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vrcw+DmTS8CfHuCBOui+zn38OLxR/H6DISwkgtmUX1s=; b=Nw3M0IdNVJ20w6unVVX5396Sg5y5/2FO1Gv7UianPIblx6MTKLvJliBGJyEK8X38HF 9jeQmvW9Eo6Hq2uexNKjOUw4zjpi0fsGVKfi2cm52+TsG2jWv+Kg/W7TZXluWdP8aCXf 1KZfaJk8fO5gaSmqizK6HsaRbUIt4zBEsp/kMWtfrHUQBpBMeCb4x4UvqXdewVkDJ2+L lwnQpzE9DxPmDazjY5wNzXidI9aj7NDA4pI4dVVBQgGr8cpgdO0B8K8kAoLLU83XKnlI 7QuStnZNmPjK2HupdPAcyVysnI9OE01G+3BKjOKShM3alrEnNy93kazoKHBw5T9RqzJQ xzVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vrcw+DmTS8CfHuCBOui+zn38OLxR/H6DISwkgtmUX1s=; b=kd8ENg1ymmb1pxbVpW1h9CW3C9vqSFMOuTG7sEA8KFpQ/TvECEDTZ4I8fnYea3YOJM 8Cy+KQYikSgLIqC4MlG+70jf5icIEyEWjr5+9ZK5TiC+BCfnWsDhW3+luzn3Rak73EDu N1GSnmEQSIL7eBUlgnWs1sY9ZhoTIs1caIhO4IB0Sb8GQ4bKlTt9ls3tvfKDMoTbEyb4 pZDxxkhM7wTC0mvqp6rKJm7KekNyaomWQRal5717c49InUQCEI84ZrtPKsfM/8tYNaAx DqyGVDqyFEEPTfn0JQh164qJbGwOG6T0g8FySg18lPwfnb4YnJRZLpBaqts3CV7VFuZf LmkQ== X-Gm-Message-State: AOAM532YLSP7I/06YC68af4FzXKyZ2H2/Q/p+Zj35FNFc9fbhsBtXQhr joJLSahbF+5DKh8pUGeVB31KHSKn X-Google-Smtp-Source: ABdhPJzWuF4TqMWSb0bI5sNpHD0ZVBPdbu70Pxo/8rdY7sPGYt7aka4fvkEK32NI/VKQBc45puF62Q== X-Received: by 2002:a1c:1d93:: with SMTP id d141mr12870175wmd.14.1592743702781; Sun, 21 Jun 2020 05:48:22 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 10/15] hw/rx: RX62N microcontroller (MCU) Date: Sun, 21 Jun 2020 14:48:02 +0200 Message-Id: <20200621124807.17226-11-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200621124807.17226-1-f4bug@amsat.org> References: <20200621124807.17226-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x334.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , Richard Henderson , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato rx62n - RX62N cpu. Signed-off-by: Yoshinori Sato Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson [PMD: Use TYPE_RX62N_CPU, use #define for RX62N_NR_TMR/CMT/SCI, renamed CPU -> MCU, device -> microcontroller] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20200224141923.82118-18-ysato@users.sourceforge.jp> [PMD: Rebased on b77b5b3dc7, split of machine, use &error_abort] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/rx/rx62n.h | 75 +++++++++++++ hw/rx/rx62n.c | 254 ++++++++++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + hw/Kconfig | 1 + hw/rx/Kconfig | 6 + hw/rx/Makefile.objs | 1 + 6 files changed, 339 insertions(+) create mode 100644 include/hw/rx/rx62n.h create mode 100644 hw/rx/rx62n.c create mode 100644 hw/rx/Kconfig create mode 100644 hw/rx/Makefile.objs diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h new file mode 100644 index 0000000000..7c6023bcd6 --- /dev/null +++ b/include/hw/rx/rx62n.h @@ -0,0 +1,75 @@ +/* + * RX62N MCU Object + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_RX_RX62N_MCU_H +#define HW_RX_RX62N_MCU_H + +#include "target/rx/cpu.h" +#include "hw/intc/rx_icu.h" +#include "hw/timer/renesas_tmr.h" +#include "hw/timer/renesas_cmt.h" +#include "hw/char/renesas_sci.h" +#include "qemu/units.h" + +#define TYPE_RX62N_MCU "rx62n-mcu" +#define RX62N_MCU(obj) OBJECT_CHECK(RX62NState, (obj), TYPE_RX62N_MCU) + +#define RX62N_NR_TMR 2 +#define RX62N_NR_CMT 2 +#define RX62N_NR_SCI 6 + +typedef struct RX62NState { + /*< private >*/ + DeviceState parent_obj; + /*< public >*/ + + RXCPU cpu; + RXICUState icu; + RTMRState tmr[RX62N_NR_TMR]; + RCMTState cmt[RX62N_NR_CMT]; + RSCIState sci[RX62N_NR_SCI]; + + MemoryRegion *sysmem; + bool kernel; + + MemoryRegion iram; + MemoryRegion iomem1; + MemoryRegion d_flash; + MemoryRegion iomem2; + MemoryRegion iomem3; + MemoryRegion c_flash; + qemu_irq irq[NR_IRQS]; +} RX62NState; + +/* + * RX62N Internal Memory + * It is the value of R5F562N8. + * Please change the size for R5F562N7. + */ +#define RX62N_IRAM_SIZE (96 * KiB) +#define RX62N_DFLASH_SIZE (32 * KiB) +#define RX62N_CFLASH_SIZE (512 * KiB) + +#define RX62N_PCLK (48 * 1000 * 1000) + +#endif diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c new file mode 100644 index 0000000000..85b7770023 --- /dev/null +++ b/hw/rx/rx62n.c @@ -0,0 +1,254 @@ +/* + * RX62N Microcontroller + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/rx/rx62n.h" +#include "hw/loader.h" +#include "hw/sysbus.h" +#include "hw/qdev-properties.h" +#include "sysemu/sysemu.h" +#include "cpu.h" + +/* + * RX62N Internal Memory + */ +#define RX62N_IRAM_BASE 0x00000000 +#define RX62N_DFLASH_BASE 0x00100000 +#define RX62N_CFLASH_BASE 0xfff80000 + +/* + * RX62N Peripheral Address + * See users manual section 5 + */ +#define RX62N_ICU_BASE 0x00087000 +#define RX62N_TMR_BASE 0x00088200 +#define RX62N_CMT_BASE 0x00088000 +#define RX62N_SCI_BASE 0x00088240 + +/* + * RX62N Peripheral IRQ + * See users manual section 11 + */ +#define RX62N_TMR_IRQ 174 +#define RX62N_CMT_IRQ 28 +#define RX62N_SCI_IRQ 214 + +/* + * IRQ -> IPR mapping table + * 0x00 - 0x91: IPR no (IPR00 to IPR91) + * 0xff: IPR not assigned + * See "11.3.1 Interrupt Vector Table" in hardware manual. + */ +static const uint8_t ipr_table[NR_IRQS] =3D { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 15 */ + 0x00, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0x02, + 0xff, 0xff, 0xff, 0x03, 0x04, 0x05, 0x06, 0x07, /* 31 */ + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x14, 0x14, 0x14, /* 47 */ + 0x15, 0x15, 0x15, 0x15, 0xff, 0xff, 0xff, 0xff, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x1d, 0x1e, 0x1f, /* 63 */ + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, /* 79 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x3a, 0x3b, 0x3c, 0xff, 0xff, 0xff, /* 95 */ + 0x40, 0xff, 0x44, 0x45, 0xff, 0xff, 0x48, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 111 */ + 0xff, 0xff, 0x51, 0x51, 0x51, 0x51, 0x52, 0x52, + 0x52, 0x53, 0x53, 0x54, 0x54, 0x55, 0x55, 0x56, /* 127 */ + 0x56, 0x57, 0x57, 0x57, 0x57, 0x58, 0x59, 0x59, + 0x59, 0x59, 0x5a, 0x5b, 0x5b, 0x5b, 0x5c, 0x5c, /* 143 */ + 0x5c, 0x5c, 0x5d, 0x5d, 0x5d, 0x5e, 0x5e, 0x5f, + 0x5f, 0x60, 0x60, 0x61, 0x61, 0x62, 0x62, 0x62, /* 159 */ + 0x62, 0x63, 0x64, 0x64, 0x64, 0x64, 0x65, 0x66, + 0x66, 0x66, 0x67, 0x67, 0x67, 0x67, 0x68, 0x68, /* 175 */ + 0x68, 0x69, 0x69, 0x69, 0x6a, 0x6a, 0x6a, 0x6b, + 0x6b, 0x6b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 191 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x71, + 0x72, 0x73, 0x74, 0x75, 0xff, 0xff, 0xff, 0xff, /* 207 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x80, + 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x82, 0x82, /* 223 */ + 0x82, 0x82, 0x83, 0x83, 0x83, 0x83, 0xff, 0xff, + 0xff, 0xff, 0x85, 0x85, 0x85, 0x85, 0x86, 0x86, /* 239 */ + 0x86, 0x86, 0xff, 0xff, 0xff, 0xff, 0x88, 0x89, + 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, /* 255 */ +}; + +/* + * Level triggerd IRQ list + * Not listed IRQ is Edge trigger. + * See "11.3.1 Interrupt Vector Table" in hardware manual. + */ +static const uint8_t levelirq[] =3D { + 16, 21, 32, 44, 47, 48, 51, 64, 65, 66, + 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, + 77, 78, 79, 90, 91, 170, 171, 172, 173, 214, + 217, 218, 221, 222, 225, 226, 229, 234, 237, 238, + 241, 246, 249, 250, 253, +}; + +static void register_icu(RX62NState *s) +{ + int i; + SysBusDevice *icu; + + object_initialize_child(OBJECT(s), "icu", &s->icu, TYPE_RX_ICU); + icu =3D SYS_BUS_DEVICE(&s->icu); + qdev_prop_set_uint32(DEVICE(icu), "len-ipr-map", NR_IRQS); + for (i =3D 0; i < NR_IRQS; i++) { + char propname[32]; + snprintf(propname, sizeof(propname), "ipr-map[%d]", i); + qdev_prop_set_uint32(DEVICE(icu), propname, ipr_table[i]); + } + qdev_prop_set_uint32(DEVICE(icu), "len-trigger-level", + ARRAY_SIZE(levelirq)); + for (i =3D 0; i < ARRAY_SIZE(levelirq); i++) { + char propname[32]; + snprintf(propname, sizeof(propname), "trigger-level[%d]", i); + qdev_prop_set_uint32(DEVICE(icu), propname, levelirq[i]); + } + + for (i =3D 0; i < NR_IRQS; i++) { + s->irq[i] =3D qdev_get_gpio_in(DEVICE(icu), i); + } + sysbus_realize(icu, &error_abort); + sysbus_connect_irq(icu, 0, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_IR= Q)); + sysbus_connect_irq(icu, 1, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_FI= R)); + sysbus_connect_irq(icu, 2, s->irq[SWI]); + sysbus_mmio_map(SYS_BUS_DEVICE(icu), 0, RX62N_ICU_BASE); +} + +static void register_tmr(RX62NState *s, int unit) +{ + SysBusDevice *tmr; + int i, irqbase; + + object_initialize_child(OBJECT(s), "tmr[*]", + &s->tmr[unit], TYPE_RENESAS_TMR); + tmr =3D SYS_BUS_DEVICE(&s->tmr[unit]); + qdev_prop_set_uint64(DEVICE(tmr), "input-freq", RX62N_PCLK); + sysbus_realize(tmr, &error_abort); + + irqbase =3D RX62N_TMR_IRQ + TMR_NR_IRQ * unit; + for (i =3D 0; i < TMR_NR_IRQ; i++) { + sysbus_connect_irq(tmr, i, s->irq[irqbase + i]); + } + sysbus_mmio_map(tmr, 0, RX62N_TMR_BASE + unit * 0x10); +} + +static void register_cmt(RX62NState *s, int unit) +{ + SysBusDevice *cmt; + int i, irqbase; + + object_initialize_child(OBJECT(s), "cmt[*]", + &s->cmt[unit], TYPE_RENESAS_CMT); + cmt =3D SYS_BUS_DEVICE(&s->cmt[unit]); + qdev_prop_set_uint64(DEVICE(cmt), "input-freq", RX62N_PCLK); + sysbus_realize(cmt, &error_abort); + + irqbase =3D RX62N_CMT_IRQ + CMT_NR_IRQ * unit; + for (i =3D 0; i < CMT_NR_IRQ; i++) { + sysbus_connect_irq(cmt, i, s->irq[irqbase + i]); + } + sysbus_mmio_map(cmt, 0, RX62N_CMT_BASE + unit * 0x10); +} + +static void register_sci(RX62NState *s, int unit) +{ + SysBusDevice *sci; + int i, irqbase; + + object_initialize_child(OBJECT(s), "sci[*]", + &s->sci[unit], TYPE_RENESAS_SCI); + sci =3D SYS_BUS_DEVICE(&s->sci[unit]); + qdev_prop_set_chr(DEVICE(sci), "chardev", serial_hd(unit)); + qdev_prop_set_uint64(DEVICE(sci), "input-freq", RX62N_PCLK); + sysbus_realize(sci, &error_abort); + + irqbase =3D RX62N_SCI_IRQ + SCI_NR_IRQ * unit; + for (i =3D 0; i < SCI_NR_IRQ; i++) { + sysbus_connect_irq(sci, i, s->irq[irqbase + i]); + } + sysbus_mmio_map(sci, 0, RX62N_SCI_BASE + unit * 0x08); +} + +static void rx62n_realize(DeviceState *dev, Error **errp) +{ + RX62NState *s =3D RX62N_MCU(dev); + + memory_region_init_ram(&s->iram, OBJECT(dev), "iram", + RX62N_IRAM_SIZE, &error_abort); + memory_region_add_subregion(s->sysmem, RX62N_IRAM_BASE, &s->iram); + memory_region_init_rom(&s->d_flash, OBJECT(dev), "flash-data", + RX62N_DFLASH_SIZE, &error_abort); + memory_region_add_subregion(s->sysmem, RX62N_DFLASH_BASE, &s->d_flash); + memory_region_init_rom(&s->c_flash, OBJECT(dev), "flash-code", + RX62N_CFLASH_SIZE, &error_abort); + memory_region_add_subregion(s->sysmem, RX62N_CFLASH_BASE, &s->c_flash); + + if (!s->kernel) { + rom_add_file_fixed(bios_name, RX62N_CFLASH_BASE, 0); + } + + /* Initialize CPU */ + object_initialize_child(OBJECT(s), "cpu", &s->cpu, TYPE_RX62N_CPU); + qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); + + register_icu(s); + s->cpu.env.ack =3D qdev_get_gpio_in_named(DEVICE(&s->icu), "ack", 0); + register_tmr(s, 0); + register_tmr(s, 1); + register_cmt(s, 0); + register_cmt(s, 1); + register_sci(s, 0); +} + +static Property rx62n_properties[] =3D { + DEFINE_PROP_LINK("main-bus", RX62NState, sysmem, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_BOOL("load-kernel", RX62NState, kernel, false), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rx62n_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D rx62n_realize; + device_class_set_props(dc, rx62n_properties); +} + +static const TypeInfo rx62n_info =3D { + .name =3D TYPE_RX62N_MCU, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(RX62NState), + .class_init =3D rx62n_class_init, +}; + +static void rx62n_register_types(void) +{ + type_register_static(&rx62n_info); +} + +type_init(rx62n_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index dd829b300a..71308a485b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1979,7 +1979,9 @@ Renesas RX peripherals M: Yoshinori Sato S: Maintained F: hw/intc/rx_icu.c +F: hw/rx/ F: include/hw/intc/rx_icu.h +F: include/hw/rx/ =20 Subsystems ---------- diff --git a/hw/Kconfig b/hw/Kconfig index ecf491bf04..62f9ebdc22 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -55,6 +55,7 @@ source nios2/Kconfig source openrisc/Kconfig source ppc/Kconfig source riscv/Kconfig +source rx/Kconfig source s390x/Kconfig source sh4/Kconfig source sparc/Kconfig diff --git a/hw/rx/Kconfig b/hw/rx/Kconfig new file mode 100644 index 0000000000..e7b1c59516 --- /dev/null +++ b/hw/rx/Kconfig @@ -0,0 +1,6 @@ +config RX62N_MCU + bool + select RX_ICU + select RENESAS_TMR + select RENESAS_CMT + select RENESAS_SCI diff --git a/hw/rx/Makefile.objs b/hw/rx/Makefile.objs new file mode 100644 index 0000000000..fe19ee7984 --- /dev/null +++ b/hw/rx/Makefile.objs @@ -0,0 +1 @@ +obj-$(CONFIG_RX62N_MCU) +=3D rx62n.o --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[83.51.162.1]) by smtp.gmail.com with ESMTPSA id o10sm13779362wrj.37.2020.06.21.05.48.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 05:48:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nrmkQ/EOlQRnkklRoevO7IWC+EItEHCLWkyyjykQYg4=; b=rUbUvZQPRK6l8ahNcHix5CVlOp7Kg4tqkpKQU9wggMl/8GGaYlCj/phzi+DnehhOaV zbJcbjBXo4YKEQWRkqkCxZpjWmvaMSiV22+Pbj+Q7p8Hh07qEgInGrVqn1KaRpJCQW6P hoEKswRBKoX8XPLSMHi/jNXf4V36JitUTVesn3ZcPWJQTJlVd1WRbSO8L8fkLj1C2/l0 I9TT/blOSQo4DsjvfSW8F3j2MaWwHSzFg9jFaWdhk5lby4ezRUOv7ofnd7IQoG61Ect6 NKNj/IYuP4ElNBViH46q/ZhqpnRtqPto4GHw1J+vRmBO8LCq4XN2vXsOI2M+uLvYhvmT TQww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nrmkQ/EOlQRnkklRoevO7IWC+EItEHCLWkyyjykQYg4=; b=ugvVI3VSBvAhTCDKitC/xTys4M6chOMzrOks49cdxuosnRtFzaDZBFEPSjpQz5WKuR wXW4LRb24IYEMcINZ4m/1rMi+BASX3wAuc66kV0/Bx87xq6z9Ph4jnO7EZ0UYPWSKUcb GwanjmJqCU90pHpjv6SqTIciCRXs0NF6Ee3Fi95JhXgiouOIRbNTnSPCDw4HugkWpkcA IH0Ow8eFoZT7fn+PW/MS8U5Q22sLRnf89elVPk7YO0s49KNPKDxPI9aW5t/x2+h/LT4W nL5F33euGGsodJP5tU03fS9ZuWy9qS8/6cLDmKONpunWG4wfJGlAnFgFtfY0TB3Dyza9 mTgg== X-Gm-Message-State: AOAM532BavsmpCmzd6Rfn7G7xzBrWVem6lU5VgvT0LpCaYW+d22/d3OS DSunEGXJ6Y0YT1n9TSRpsgrYbR5G X-Google-Smtp-Source: ABdhPJygkObZExsXC4J7rxg9bU+HAguStLMr5Tj6vClRVrhx0lIBcbimmIkB6C4gNvrs/j5X6aA21w== X-Received: by 2002:a5d:5647:: with SMTP id j7mr5734779wrw.242.1592743703981; Sun, 21 Jun 2020 05:48:23 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 11/15] hw/rx: Honor -accel qtest Date: Sun, 21 Jun 2020 14:48:03 +0200 Message-Id: <20200621124807.17226-12-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200621124807.17226-1-f4bug@amsat.org> References: <20200621124807.17226-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , Magnus Damm , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Richard Henderson Issue an error if no kernel, no bios, and not qtest'ing. Fixes make check-qtest-rx: test/qom-test. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Yoshinori Sato Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20190531134315.4109-16-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/rx/rx62n.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index 85b7770023..d8f0fa4625 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -21,12 +21,14 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "hw/hw.h" #include "hw/rx/rx62n.h" #include "hw/loader.h" #include "hw/sysbus.h" #include "hw/qdev-properties.h" #include "sysemu/sysemu.h" +#include "sysemu/qtest.h" #include "cpu.h" =20 /* @@ -208,7 +210,12 @@ static void rx62n_realize(DeviceState *dev, Error **er= rp) memory_region_add_subregion(s->sysmem, RX62N_CFLASH_BASE, &s->c_flash); =20 if (!s->kernel) { - rom_add_file_fixed(bios_name, RX62N_CFLASH_BASE, 0); + if (bios_name) { + rom_add_file_fixed(bios_name, RX62N_CFLASH_BASE, 0); + } else if (!qtest_enabled()) { + error_report("No bios or kernel specified"); + exit(1); + } } =20 /* Initialize CPU */ --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1592744170; cv=none; d=zohomail.com; s=zohoarc; b=Cnr8PhH/icv04nRVOHxnDWoDU566pCAtakSV1KYWvA4BIpyprRoGv45NYHAeeJT2ictu+uqgjkoCMdhGZeCKVRbFPVbfmazFBdgzL5IwNdJE0Y1m5cIo+lZu9yjNFZ6FWTPDRHnOqWggzQbBxp4/fO2Bx2bi8KvMcJcSvsJgYpM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592744170; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8hvxw8zViwef4lvqYH+G0patKwDRHQfaUOaMCkfSQM4=; b=B3YO8g3cpTpy2zjNZFd99uXKinRfXDBlOoCHbEIRu9Zd4oYB9eJqnjLUso96iWPyWb9pIQvQcayeTWXXkAiN/sQTrk+TQfNU/3cNTgfXMtVeNhec52629vKLt8ejaT4Br4AoJpfCkOBC0N8vAV0guzVho1DXNLeQQCEhk838awE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592744170093433.0799728799575; Sun, 21 Jun 2020 05:56:10 -0700 (PDT) Received: from localhost ([::1]:48268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jmzW4-0000AO-QP for importer@patchew.org; Sun, 21 Jun 2020 08:56:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jmzOe-0005Mw-UK for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:28 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:44659) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jmzOc-0002rb-TG for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:28 -0400 Received: by mail-wr1-x42c.google.com with SMTP id b6so13977808wrs.11 for ; Sun, 21 Jun 2020 05:48:26 -0700 (PDT) Received: from localhost.localdomain (1.red-83-51-162.dynamicip.rima-tde.net. [83.51.162.1]) by smtp.gmail.com with ESMTPSA id o10sm13779362wrj.37.2020.06.21.05.48.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 05:48:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8hvxw8zViwef4lvqYH+G0patKwDRHQfaUOaMCkfSQM4=; b=kIUPm5yj6VuHBhMbjp52YB2IhCvLxW+UB9/4B6v/MpQ6UuKow3TZSy91zeeKrFpGOo X9ICYXZNehr8eZNUR1c2FUWf20Y8kOC+IIlNM9RMk+iTlbdKm+2yiJSxWPBBXlvUzJJJ WgFjpUXq33bYH/w8JAQR2YBvEwut5cIx/sv2sd3JmR/Ojmrd6rP/Z+y0XndIIyCdWRNO QwHM+2nruVvVEkB+qZtMaKXM1xG+6aMcy+2blhxKLXu4hGslz2962hPNlY0nX7JcAm5o r1iBDg5v8xDgmYuSyLbjVP3m7TnTjRb4YzRK323m/N7GcGAendFaM08Cwtw/D27nGio0 1bqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8hvxw8zViwef4lvqYH+G0patKwDRHQfaUOaMCkfSQM4=; b=MvFFF0SG/4hc5zCDlK35/S77Toks0gZhh6wEr6msCDeMwuRV+/pKuXPOyAsWMc9yzL HT09f4fQ7t8AypL6pr4+HDhtmTmh5ErdfYK176ZIdirmWQS8lKqHBWtlPwJMXO67ochI sQ8cyL3p3ZOBeEWSVu0H7/9UYYgBfR6//mf3b8H9mhsU6Z94OvdlJTE4mnE/Qm+QuRzu zhAITv8aXR74PBunjvyhJb1tuznCf/XXxDbMwBfuBGv80gTT65j69zgwAjbrTS3yBrlB 8Uema+g4MzWECbPA1/N6lDu9G0/K8o3fdMgWNZT7a8ZdArSLZShoa/qm0nPBMUCoJWv8 jMUQ== X-Gm-Message-State: AOAM533fvc5UMXiC46RXDHXYhtCJOeMHlN86mm6p++JbKx0wkAvTt8KZ aXemnahATOWBofJz06xjr/MAK7WG X-Google-Smtp-Source: ABdhPJxSNq77sBGkFF+NKveCZeE/r4TrwAsYqNf6fc1LEyS42Dbj4a6o84n+bBGuEF6dcnlphGrE2Q== X-Received: by 2002:a5d:4591:: with SMTP id p17mr5285548wrq.343.1592743705267; Sun, 21 Jun 2020 05:48:25 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 12/15] hw/rx: Register R5F562N7 and R5F562N8 MCUs Date: Sun, 21 Jun 2020 14:48:04 +0200 Message-Id: <20200621124807.17226-13-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200621124807.17226-1-f4bug@amsat.org> References: <20200621124807.17226-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , Richard Henderson , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Make the current TYPE_RX62N_MCU an abstract class, and generate TYPE_R5F562N7_MCU and TYPE_R5F562N8_MCU models. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/rx/rx62n.h | 19 ++++----- hw/rx/rx62n.c | 92 ++++++++++++++++++++++++++++++++++++------- 2 files changed, 85 insertions(+), 26 deletions(-) diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index 7c6023bcd6..1d3e6a5cad 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h @@ -34,6 +34,9 @@ #define TYPE_RX62N_MCU "rx62n-mcu" #define RX62N_MCU(obj) OBJECT_CHECK(RX62NState, (obj), TYPE_RX62N_MCU) =20 +#define TYPE_R5F562N7_MCU "r5f562n7-mcu" +#define TYPE_R5F562N8_MCU "r5f562n8-mcu" + #define RX62N_NR_TMR 2 #define RX62N_NR_CMT 2 #define RX62N_NR_SCI 6 @@ -59,17 +62,11 @@ typedef struct RX62NState { MemoryRegion iomem3; MemoryRegion c_flash; qemu_irq irq[NR_IRQS]; + + /* Input Clock (XTAL) frequency */ + uint32_t xtal_freq_hz; + /* Peripheral Module Clock frequency */ + uint32_t pclk_freq_hz; } RX62NState; =20 -/* - * RX62N Internal Memory - * It is the value of R5F562N8. - * Please change the size for R5F562N7. - */ -#define RX62N_IRAM_SIZE (96 * KiB) -#define RX62N_DFLASH_SIZE (32 * KiB) -#define RX62N_CFLASH_SIZE (512 * KiB) - -#define RX62N_PCLK (48 * 1000 * 1000) - #endif diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index d8f0fa4625..b9c217ebfa 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -5,6 +5,7 @@ * (Rev.1.40 R01UH0033EJ0140) * * Copyright (c) 2019 Yoshinori Sato + * Copyright (c) 2020 Philippe Mathieu-Daud=C3=A9 * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -55,6 +56,25 @@ #define RX62N_CMT_IRQ 28 #define RX62N_SCI_IRQ 214 =20 +#define RX62N_XTAL_MIN_HZ (8 * 1000 * 1000) +#define RX62N_XTAL_MAX_HZ (14 * 1000 * 1000) +#define RX62N_PCLK_MAX_HZ (50 * 1000 * 1000) + +typedef struct RX62NClass { + /*< private >*/ + DeviceClass parent_class; + /*< public >*/ + const char *name; + uint64_t ram_size; + uint64_t rom_flash_size; + uint64_t data_flash_size; +} RX62NClass; + +#define RX62N_MCU_CLASS(klass) \ + OBJECT_CLASS_CHECK(RX62NClass, (klass), TYPE_RX62N_MCU) +#define RX62N_MCU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(RX62NClass, (obj), TYPE_RX62N_MCU) + /* * IRQ -> IPR mapping table * 0x00 - 0x91: IPR no (IPR00 to IPR91) @@ -148,7 +168,7 @@ static void register_tmr(RX62NState *s, int unit) object_initialize_child(OBJECT(s), "tmr[*]", &s->tmr[unit], TYPE_RENESAS_TMR); tmr =3D SYS_BUS_DEVICE(&s->tmr[unit]); - qdev_prop_set_uint64(DEVICE(tmr), "input-freq", RX62N_PCLK); + qdev_prop_set_uint64(DEVICE(tmr), "input-freq", s->pclk_freq_hz); sysbus_realize(tmr, &error_abort); =20 irqbase =3D RX62N_TMR_IRQ + TMR_NR_IRQ * unit; @@ -166,7 +186,7 @@ static void register_cmt(RX62NState *s, int unit) object_initialize_child(OBJECT(s), "cmt[*]", &s->cmt[unit], TYPE_RENESAS_CMT); cmt =3D SYS_BUS_DEVICE(&s->cmt[unit]); - qdev_prop_set_uint64(DEVICE(cmt), "input-freq", RX62N_PCLK); + qdev_prop_set_uint64(DEVICE(cmt), "input-freq", s->pclk_freq_hz); sysbus_realize(cmt, &error_abort); =20 irqbase =3D RX62N_CMT_IRQ + CMT_NR_IRQ * unit; @@ -185,7 +205,7 @@ static void register_sci(RX62NState *s, int unit) &s->sci[unit], TYPE_RENESAS_SCI); sci =3D SYS_BUS_DEVICE(&s->sci[unit]); qdev_prop_set_chr(DEVICE(sci), "chardev", serial_hd(unit)); - qdev_prop_set_uint64(DEVICE(sci), "input-freq", RX62N_PCLK); + qdev_prop_set_uint64(DEVICE(sci), "input-freq", s->pclk_freq_hz); sysbus_realize(sci, &error_abort); =20 irqbase =3D RX62N_SCI_IRQ + SCI_NR_IRQ * unit; @@ -198,15 +218,31 @@ static void register_sci(RX62NState *s, int unit) static void rx62n_realize(DeviceState *dev, Error **errp) { RX62NState *s =3D RX62N_MCU(dev); + RX62NClass *rxc =3D RX62N_MCU_GET_CLASS(dev); + + if (s->xtal_freq_hz =3D=3D 0) { + error_setg(errp, "\"xtal-frequency-hz\" property must be provided.= "); + return; + } + /* XTAL range: 8-14 MHz */ + if (s->xtal_freq_hz < RX62N_XTAL_MIN_HZ + || s->xtal_freq_hz > RX62N_XTAL_MAX_HZ) { + error_setg(errp, "\"xtal-frequency-hz\" property in incorrect rang= e."); + return; + } + /* Use a 4x fixed multiplier */ + s->pclk_freq_hz =3D 4 * s->xtal_freq_hz; + /* PCLK range: 8-50 MHz */ + assert(s->pclk_freq_hz <=3D RX62N_PCLK_MAX_HZ); =20 memory_region_init_ram(&s->iram, OBJECT(dev), "iram", - RX62N_IRAM_SIZE, &error_abort); + rxc->ram_size, &error_abort); memory_region_add_subregion(s->sysmem, RX62N_IRAM_BASE, &s->iram); memory_region_init_rom(&s->d_flash, OBJECT(dev), "flash-data", - RX62N_DFLASH_SIZE, &error_abort); + rxc->data_flash_size, &error_abort); memory_region_add_subregion(s->sysmem, RX62N_DFLASH_BASE, &s->d_flash); memory_region_init_rom(&s->c_flash, OBJECT(dev), "flash-code", - RX62N_CFLASH_SIZE, &error_abort); + rxc->rom_flash_size, &error_abort); memory_region_add_subregion(s->sysmem, RX62N_CFLASH_BASE, &s->c_flash); =20 if (!s->kernel) { @@ -235,6 +271,7 @@ static Property rx62n_properties[] =3D { DEFINE_PROP_LINK("main-bus", RX62NState, sysmem, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_BOOL("load-kernel", RX62NState, kernel, false), + DEFINE_PROP_UINT32("xtal-frequency-hz", RX62NState, xtal_freq_hz, 0), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -246,16 +283,41 @@ static void rx62n_class_init(ObjectClass *klass, void= *data) device_class_set_props(dc, rx62n_properties); } =20 -static const TypeInfo rx62n_info =3D { - .name =3D TYPE_RX62N_MCU, - .parent =3D TYPE_DEVICE, - .instance_size =3D sizeof(RX62NState), - .class_init =3D rx62n_class_init, +static void r5f562n7_class_init(ObjectClass *oc, void *data) +{ + RX62NClass *rxc =3D RX62N_MCU_CLASS(oc); + + rxc->ram_size =3D 64 * KiB; + rxc->rom_flash_size =3D 384 * KiB; + rxc->data_flash_size =3D 32 * KiB; }; =20 -static void rx62n_register_types(void) +static void r5f562n8_class_init(ObjectClass *oc, void *data) { - type_register_static(&rx62n_info); -} + RX62NClass *rxc =3D RX62N_MCU_CLASS(oc); =20 -type_init(rx62n_register_types) + rxc->ram_size =3D 96 * KiB; + rxc->rom_flash_size =3D 512 * KiB; + rxc->data_flash_size =3D 32 * KiB; +}; + +static const TypeInfo rx62n_types[] =3D { + { + .name =3D TYPE_R5F562N7_MCU, + .parent =3D TYPE_RX62N_MCU, + .class_init =3D r5f562n7_class_init, + }, { + .name =3D TYPE_R5F562N8_MCU, + .parent =3D TYPE_RX62N_MCU, + .class_init =3D r5f562n8_class_init, + }, { + .name =3D TYPE_RX62N_MCU, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(RX62NState), + .class_size =3D sizeof(RX62NClass), + .class_init =3D rx62n_class_init, + .abstract =3D true, + } +}; + +DEFINE_TYPES(rx62n_types) --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; 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[83.51.162.1]) by smtp.gmail.com with ESMTPSA id o10sm13779362wrj.37.2020.06.21.05.48.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 05:48:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=if0y4BhSj2VUNFeFhpX00lUEZ4ua6tmVVgbzc+plJVY=; b=seHw8KwcZ1F1TlyeBHR+C/ZGBT8i2ReHrFXJSvqIrUuuW/8gNnzGj/TiaWaLdbRDKf jJDEUL9eU5mcL/e6GXoMSi87RmPih5xVxH+5bkfv3427OvsHPvC7eMbrBM9fJQm4I/zR XBkTGCTQf3sOp4uesYGUxZfHhCR6B2eynb5R7hy+MRNsKV4evjcjz6jr/OmCapIMUBe9 ZNr360KzXKBxG3j0KMnvCa4UmwfK+QsyCvY1QTNi9nRjRoGxj7G2aPs1OUYkxlG74tgK jyZsf8LRKu88zdRLFvPNlF5f2STLOmnU9s7vk7yfPX+J1jaUWvZZPdwDt9eZYBfFy12Z avHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=if0y4BhSj2VUNFeFhpX00lUEZ4ua6tmVVgbzc+plJVY=; b=oYSr4vtc2OxRa3SZOR4Ltv4mKzAsqQdfLb2XcvM3+d6qgNoPb6lMaQBqQg1GiUTgtd BCOORAWU+UScNGKjV7aDgB6qMnFc6gt/67pWonWf/cJiuUtkg3LY4WksI9T5O0Jdt2sY wxX7mvfhUmgsTj2NOoqQXsbtVFNMnZnmbyQCrPooSXkbPjX+7BdiC+ZC+kAc+q/sTeR7 uQNqPAtxmp6lh4OrBD1dK2crv67V7BETg9ledt117+MdWxwOSuBf6A0HTS3TMIQSNcEf sTy/Vw/lCmQ9qkCapsaZikS6DqzQndw6hBmkcxqgS6sOakwiT2LXfzMrHgUr174u7gmA b+OA== X-Gm-Message-State: AOAM531obl1qmvlKc2CHTL/3vODaz/okWtwCzVn8Srxna4IYwPPTowLw AFC4H00HmbAtQ8ZNOynrbP8/gVCC X-Google-Smtp-Source: ABdhPJwW7UuUFNpYbsMgiWlj6Vh8qF5pJurdE5MTHgwJoizWVC/lDClTWcAIfEsIwEWs5emWz8S7Bg== X-Received: by 2002:a5d:4446:: with SMTP id x6mr13340529wrr.119.1592743706550; Sun, 21 Jun 2020 05:48:26 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 13/15] hw/rx: Add RX GDB simulator Date: Sun, 21 Jun 2020 14:48:05 +0200 Message-Id: <20200621124807.17226-14-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200621124807.17226-1-f4bug@amsat.org> References: <20200621124807.17226-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , Richard Henderson , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato Add the RX machine internally simulated in GDB. Signed-off-by: Yoshinori Sato Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson [PMD: Use TYPE_RX62N_CPU, use #define for RX62N_NR_TMR/CMT/SCI, renamed CPU -> MCU, device -> microcontroller] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20200224141923.82118-18-ysato@users.sourceforge.jp> [PMD: Split of MCU, rename gdbsim, Add gdbsim-r5f562n7/r5f562n8] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- default-configs/rx-softmmu.mak | 1 + include/hw/rx/rx62n.h | 4 + hw/rx/rx-gdbsim.c | 196 +++++++++++++++++++++++++++++++++ MAINTAINERS | 7 ++ hw/rx/Kconfig | 4 + hw/rx/Makefile.objs | 1 + 6 files changed, 213 insertions(+) create mode 100644 hw/rx/rx-gdbsim.c diff --git a/default-configs/rx-softmmu.mak b/default-configs/rx-softmmu.mak index 7c4eb2c1a0..df2b4e4f42 100644 --- a/default-configs/rx-softmmu.mak +++ b/default-configs/rx-softmmu.mak @@ -1,2 +1,3 @@ # Default configuration for rx-softmmu =20 +CONFIG_RX_GDBSIM=3Dy diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index 1d3e6a5cad..aa94758c27 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h @@ -37,6 +37,10 @@ #define TYPE_R5F562N7_MCU "r5f562n7-mcu" #define TYPE_R5F562N8_MCU "r5f562n8-mcu" =20 +#define EXT_CS_BASE 0x01000000 +#define VECTOR_TABLE_BASE 0xffffff80 +#define RX62N_CFLASH_BASE 0xfff80000 + #define RX62N_NR_TMR 2 #define RX62N_NR_CMT 2 #define RX62N_NR_SCI 6 diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c new file mode 100644 index 0000000000..8cd7a438f2 --- /dev/null +++ b/hw/rx/rx-gdbsim.c @@ -0,0 +1,196 @@ +/* + * RX QEMU GDB simulator + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/loader.h" +#include "hw/rx/rx62n.h" +#include "sysemu/sysemu.h" +#include "sysemu/qtest.h" +#include "sysemu/device_tree.h" +#include "hw/boards.h" + +/* Same address of GDB integrated simulator */ +#define SDRAM_BASE EXT_CS_BASE + +typedef struct RxGdbSimMachineClass { + /*< private >*/ + MachineClass parent_class; + /*< public >*/ + const char *mcu_name; + uint32_t xtal_freq_hz; +} RxGdbSimMachineClass; + +typedef struct RxGdbSimMachineState { + /*< private >*/ + MachineState parent_obj; + /*< public >*/ + RX62NState mcu; +} RxGdbSimMachineState; + +#define TYPE_RX_GDBSIM_MACHINE MACHINE_TYPE_NAME("rx62n-common") + +#define RX_GDBSIM_MACHINE(obj) \ + OBJECT_CHECK(RxGdbSimMachineState, (obj), TYPE_RX_GDBSIM_MACHINE) + +#define RX_GDBSIM_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(RxGdbSimMachineClass, (klass), TYPE_RX_GDBSIM_MACHI= NE) +#define RX_GDBSIM_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(RxGdbSimMachineClass, (obj), TYPE_RX_GDBSIM_MACHINE) + +static void rx_load_image(RXCPU *cpu, const char *filename, + uint32_t start, uint32_t size) +{ + static uint32_t extable[32]; + long kernel_size; + int i; + + kernel_size =3D load_image_targphys(filename, start, size); + if (kernel_size < 0) { + fprintf(stderr, "qemu: could not load kernel '%s'\n", filename); + exit(1); + } + cpu->env.pc =3D start; + + /* setup exception trap trampoline */ + /* linux kernel only works little-endian mode */ + for (i =3D 0; i < ARRAY_SIZE(extable); i++) { + extable[i] =3D cpu_to_le32(0x10 + i * 4); + } + rom_add_blob_fixed("extable", extable, sizeof(extable), VECTOR_TABLE_B= ASE); +} + +static void rx_gdbsim_init(MachineState *machine) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + RxGdbSimMachineState *s =3D RX_GDBSIM_MACHINE(machine); + RxGdbSimMachineClass *rxc =3D RX_GDBSIM_MACHINE_GET_CLASS(machine); + MemoryRegion *sysmem =3D get_system_memory(); + const char *kernel_filename =3D machine->kernel_filename; + const char *dtb_filename =3D machine->dtb; + + if (machine->ram_size < mc->default_ram_size) { + error_report("Invalid RAM size, should be more than %" PRIi64 " By= tes", + mc->default_ram_size); + } + + /* Allocate memory space */ + memory_region_add_subregion(sysmem, SDRAM_BASE, machine->ram); + + /* Initialize MCU */ + object_initialize_child(OBJECT(machine), "mcu", &s->mcu, rxc->mcu_name= ); + object_property_set_link(OBJECT(&s->mcu), OBJECT(sysmem), + "main-bus", &error_abort); + object_property_set_uint(OBJECT(&s->mcu), rxc->xtal_freq_hz, + "xtal-frequency-hz", &error_abort); + object_property_set_bool(OBJECT(&s->mcu), kernel_filename !=3D NULL, + "load-kernel", &error_abort); + qdev_realize(DEVICE(&s->mcu), NULL, &error_abort); + + /* Load kernel and dtb */ + if (kernel_filename) { + ram_addr_t kernel_offset; + + /* + * The kernel image is loaded into + * the latter half of the SDRAM space. + */ + kernel_offset =3D machine->ram_size / 2; + rx_load_image(RXCPU(first_cpu), kernel_filename, + SDRAM_BASE + kernel_offset, kernel_offset); + if (dtb_filename) { + ram_addr_t dtb_offset; + int dtb_size; + void *dtb; + + dtb =3D load_device_tree(dtb_filename, &dtb_size); + if (dtb =3D=3D NULL) { + error_report("Couldn't open dtb file %s", dtb_filename); + exit(1); + } + if (machine->kernel_cmdline && + qemu_fdt_setprop_string(dtb, "/chosen", "bootargs", + machine->kernel_cmdline) < 0) { + error_report("Couldn't set /chosen/bootargs"); + exit(1); + } + /* DTB is located at the end of SDRAM space. */ + dtb_offset =3D machine->ram_size - dtb_size; + rom_add_blob_fixed("dtb", dtb, dtb_size, + SDRAM_BASE + dtb_offset); + /* Set dtb address to R1 */ + RXCPU(first_cpu)->env.regs[1] =3D SDRAM_BASE + dtb_offset; + } + } +} + +static void rx_gdbsim_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->init =3D rx_gdbsim_init; + mc->default_cpu_type =3D TYPE_RX62N_CPU; + mc->default_ram_size =3D 16 * MiB; + mc->default_ram_id =3D "ext-sdram"; +} + +static void rx62n7_class_init(ObjectClass *oc, void *data) +{ + RxGdbSimMachineClass *rxc =3D RX_GDBSIM_MACHINE_CLASS(oc); + MachineClass *mc =3D MACHINE_CLASS(oc); + + rxc->mcu_name =3D TYPE_R5F562N7_MCU; + rxc->xtal_freq_hz =3D 12 * 1000 * 1000; + mc->desc =3D "gdb simulator (R5F562N7 MCU and external RAM)"; +}; + +static void rx62n8_class_init(ObjectClass *oc, void *data) +{ + RxGdbSimMachineClass *rxc =3D RX_GDBSIM_MACHINE_CLASS(oc); + MachineClass *mc =3D MACHINE_CLASS(oc); + + rxc->mcu_name =3D TYPE_R5F562N8_MCU; + rxc->xtal_freq_hz =3D 12 * 1000 * 1000; + mc->desc =3D "gdb simulator (R5F562N8 MCU and external RAM)"; +}; + +static const TypeInfo rx_gdbsim_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("gdbsim-r5f562n7"), + .parent =3D TYPE_RX_GDBSIM_MACHINE, + .class_init =3D rx62n7_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("gdbsim-r5f562n8"), + .parent =3D TYPE_RX_GDBSIM_MACHINE, + .class_init =3D rx62n8_class_init, + }, { + .name =3D TYPE_RX_GDBSIM_MACHINE, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(RxGdbSimMachineState), + .class_size =3D sizeof(RxGdbSimMachineClass), + .class_init =3D rx_gdbsim_class_init, + .abstract =3D true, + } +}; + +DEFINE_TYPES(rx_gdbsim_types) diff --git a/MAINTAINERS b/MAINTAINERS index 71308a485b..a16e167721 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1252,6 +1252,13 @@ S: Supported F: hw/riscv/opentitan.c F: include/hw/riscv/opentitan.h =20 +RX Machines +----------- +rx-gdbsim +M: Yoshinori Sato +S: Maintained +F: hw/rx/rx-gdbsim.c + SH4 Machines ------------ R2D diff --git a/hw/rx/Kconfig b/hw/rx/Kconfig index e7b1c59516..2b297c5a6a 100644 --- a/hw/rx/Kconfig +++ b/hw/rx/Kconfig @@ -4,3 +4,7 @@ config RX62N_MCU select RENESAS_TMR select RENESAS_CMT select RENESAS_SCI + +config RX_GDBSIM + bool + select RX62N_MCU diff --git a/hw/rx/Makefile.objs b/hw/rx/Makefile.objs index fe19ee7984..4ef6b9e5b1 100644 --- a/hw/rx/Makefile.objs +++ b/hw/rx/Makefile.objs @@ -1 +1,2 @@ obj-$(CONFIG_RX62N_MCU) +=3D rx62n.o +obj-$(CONFIG_RX_GDBSIM) +=3D rx-gdbsim.o --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[83.51.162.1]) by smtp.gmail.com with ESMTPSA id o10sm13779362wrj.37.2020.06.21.05.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 05:48:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EoWHfagBj+px7QOt2jISTsysM/p7txdQCZQ0YKMDkTQ=; b=vccjz5ojLoeb70SENktPL1UJil2s5FwpdeFFK9KLSv1pP/t0USGNpydn7L+EOB09T/ jJ7OcustMbpOmqfJR8tT6LzwNKE+VB2yrbJbnV62pc8FS1HbafmE2yKX8V5Bbgn+JfzP WFmfSnpvhIOZjA0lZLN0H43ptegjMOK7Bp+llek5P6v0OTXHASM5961RQIfH9m1WIxJJ rm903sbuze8/eGA9KP4BifmN0t1dIxlaX0P7WlePTa3+bdIdcw+PRvVHNd8yyxHhorRh PTeDTuWki8OvopfAQbZVQrhqDhh+wQMxMXGXHtxVOgvMhU2p6syVRyPWw3NJrFASCh44 Ee3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=EoWHfagBj+px7QOt2jISTsysM/p7txdQCZQ0YKMDkTQ=; b=d9Xz+i75FoxN2LYTmlF3iD1qlmGsECTSZ2d2PT4IShQm7nuqTwJvkFNN1sreXg5wg5 mGcCyzl6k40G7OtfJJsFhBjpIP/Zl5ONfN8DkPzwGf0ptI6uVItQRd/QzXB4qabXXNck fAPriR2iw9XNQT5oU1Rmntxd5nUwGrKmkoazMKQ/NIpeK/DUl2alV5D28SDThBnrc9vB hvbYUANxMrFc90dK0iE+a+gxe+EYWUGJeMxZ8Fu8XNoC24wFS4lcDRCy8RbD0w6AuEua gg9aqOrrfV/0blWUIlDHJQek4sQ/uBA39K8GEmcWmSUNMzzmjx1h5apqXP7JNZx7XF7f a+gw== X-Gm-Message-State: AOAM531ON12QqVkS5OAfoqOYnJeb1mj+rS1spGav7d67PH7rxS+2VpGw bLlQJpXrLIJzydPJ+Ywtwkeaue67 X-Google-Smtp-Source: ABdhPJwmXtVfSIxcO2KAKR4gHDhvgHCB/FnvWirgvBe1/9QWw5uI/ED5YCPjT+fepUHajslPXqmOew== X-Received: by 2002:a05:600c:210:: with SMTP id 16mr14167611wmi.185.1592743707866; Sun, 21 Jun 2020 05:48:27 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 14/15] BootLinuxConsoleTest: Test the RX GDB simulator Date: Sun, 21 Jun 2020 14:48:06 +0200 Message-Id: <20200621124807.17226-15-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200621124807.17226-1-f4bug@amsat.org> References: <20200621124807.17226-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , Richard Henderson , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Add two tests for the rx-gdbsim machine, based on the recommended test setup from Yoshinori Sato: https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg03586.html - U-Boot prompt - Linux kernel with Sash shell These are very quick tests: $ avocado run -t arch:rx tests/acceptance/machine_rx_gdbsim.py JOB ID : 84a6ef01c0b87975ecbfcb31a920afd735753ace JOB LOG : /home/phil/avocado/job-results/job-2019-05-24T05.02-84a6ef0/= job.log (1/2) tests/acceptance/machine_rx_gdbsim.py:RxGdbSimMachine.test_uboot: = PASS (0.11 s) (2/2) tests/acceptance/machine_rx_gdbsim.py:RxGdbSimMachine.test_linux_s= ash: PASS (0.45 s) RESULTS : PASS 2 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | = CANCEL 0 Tests can also be run with: $ avocado --show=3Dconsole run -t arch:rx tests/acceptance/machine_rx_gdb= sim.py console: U-Boot 2016.05-rc3-23705-ga1ef3c71cb-dirty (Feb 05 2019 - 21:56:= 06 +0900) console: Linux version 4.19.0+ (yo-satoh@yo-satoh-debian) (gcc version 9.= 0.0 20181105 (experimental) (GCC)) #137 Wed Feb 20 23:20:02 JST 2019 console: Built 1 zonelists, mobility grouping on. Total pages: 8128 ... console: SuperH (H)SCI(F) driver initialized console: 88240.serial: ttySC0 at MMIO 0x88240 (irq =3D 215, base_baud =3D= 0) is a sci console: console [ttySC0] enabled console: 88248.serial: ttySC1 at MMIO 0x88248 (irq =3D 219, base_baud =3D= 0) is a sci Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Yoshinori Sato Message-Id: <20200224141923.82118-22-ysato@users.sourceforge.jp> [PMD: Replace obsolete set_machine() by machine tag, and rename as gdbsim] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- MAINTAINERS | 1 + tests/acceptance/machine_rx_gdbsim.py | 68 +++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 tests/acceptance/machine_rx_gdbsim.py diff --git a/MAINTAINERS b/MAINTAINERS index a16e167721..1c9b4bc8e7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1258,6 +1258,7 @@ rx-gdbsim M: Yoshinori Sato S: Maintained F: hw/rx/rx-gdbsim.c +F: tests/acceptance/machine_rx_gdbsim.py =20 SH4 Machines ------------ diff --git a/tests/acceptance/machine_rx_gdbsim.py b/tests/acceptance/machi= ne_rx_gdbsim.py new file mode 100644 index 0000000000..a44f2c87da --- /dev/null +++ b/tests/acceptance/machine_rx_gdbsim.py @@ -0,0 +1,68 @@ +# Functional test that boots a Linux kernel and checks the console +# +# Copyright (c) 2018 Red Hat, Inc. +# +# Author: +# Cleber Rosa +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +from avocado_qemu import Test +from avocado_qemu import exec_command_and_wait_for_pattern +from avocado_qemu import wait_for_console_pattern +from avocado.utils import archive + + +class RxGdbSimMachine(Test): + + timeout =3D 30 + KERNEL_COMMON_COMMAND_LINE =3D 'printk.time=3D0 ' + + def test_uboot(self): + """ + U-Boot and checks that the console is operational. + + :avocado: tags=3Darch:rx + :avocado: tags=3Dmachine:gdbsim-r5f562n8 + :avocado: tags=3Dendian:little + """ + uboot_url =3D ('https://acc.dl.osdn.jp/users/23/23888/u-boot.bin.g= z') + uboot_hash =3D '9b78dbd43b40b2526848c0b1ce9de02c24f4dcdb' + uboot_path =3D self.fetch_asset(uboot_url, asset_hash=3Duboot_hash) + uboot_path =3D archive.uncompress(uboot_path, self.workdir) + + self.vm.set_console() + self.vm.add_args('-bios', uboot_path, + '-no-reboot') + self.vm.launch() + uboot_version =3D 'U-Boot 2016.05-rc3-23705-ga1ef3c71cb-dirty' + wait_for_console_pattern(self, uboot_version) + gcc_version =3D 'rx-unknown-linux-gcc (GCC) 9.0.0 20181105 (experi= mental)' + # FIXME limit baudrate on chardev, else we type too fast + #exec_command_and_wait_for_pattern(self, 'version', gcc_version) + + def test_linux_sash(self): + """ + Boots a Linux kernel and checks that the console is operational. + + :avocado: tags=3Darch:rx + :avocado: tags=3Dmachine:gdbsim-r5f562n7 + :avocado: tags=3Dendian:little + """ + dtb_url =3D ('https://acc.dl.osdn.jp/users/23/23887/rx-qemu.dtb') + dtb_hash =3D '7b4e4e2c71905da44e86ce47adee2210b026ac18' + dtb_path =3D self.fetch_asset(dtb_url, asset_hash=3Ddtb_hash) + kernel_url =3D ('http://acc.dl.osdn.jp/users/23/23845/zImage') + kernel_hash =3D '39a81067f8d72faad90866ddfefa19165d68fc99' + kernel_path =3D self.fetch_asset(kernel_url, asset_hash=3Dkernel_h= ash) + + self.vm.set_console() + kernel_command_line =3D self.KERNEL_COMMON_COMMAND_LINE + 'earlyco= n' + self.vm.add_args('-kernel', kernel_path, + '-dtb', dtb_path, + '-no-reboot') + self.vm.launch() + wait_for_console_pattern(self, 'Sash command shell (version 1.1.1)= ', + failure_message=3D'Kernel panic - not syn= cing') + exec_command_and_wait_for_pattern(self, 'printenv', 'TERM=3Dlinux') --=20 2.21.3 From nobody Fri Nov 1 00:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1592744250; cv=none; d=zohomail.com; s=zohoarc; b=ZJgX6fTpXtE2TNHHW/X2Pvt7ekAdSjh9HTxuaiDtrA4cfdTaAolSCiykOUX/SI87S9TmVQO/ShNyAJZoIXkxDWouhNWC8oPNA5mZAGAibZ0CJGzSfPx6YyB2AB/San/1hnRIch6/0TWwzT2hmDWjkCX6GMC1218xW+Cuec3W7zo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592744250; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sH5Z7PRdVohuoItYDl5pz8xjGsZcdn/4T0aCVreGxQE=; b=IFHZ3VVDfPMHb6pik9QxZ+np7Lqa7SBEW1I5sp634HB0BrAlvpkTdBQCHkVPWDzJ3GC3NbZwD8tFG4Sj/hGJNx6VzKemQHVuW4q1CkBSqJzM5+7pLHLuaJNCt8ExQ0LI3UlQpCRB6vQzXDyhKamnG1f7Wj9/zk0mywoe3drzTjI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592744250654904.3071926437224; Sun, 21 Jun 2020 05:57:30 -0700 (PDT) Received: from localhost ([::1]:54692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jmzXN-0003LS-Fy for importer@patchew.org; Sun, 21 Jun 2020 08:57:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47610) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jmzOi-0005Wa-F7 for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:32 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:40418) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jmzOg-0002sB-OC for qemu-devel@nongnu.org; Sun, 21 Jun 2020 08:48:32 -0400 Received: by mail-wr1-x444.google.com with SMTP id h5so14017792wrc.7 for ; Sun, 21 Jun 2020 05:48:30 -0700 (PDT) Received: from localhost.localdomain (1.red-83-51-162.dynamicip.rima-tde.net. [83.51.162.1]) by smtp.gmail.com with ESMTPSA id o10sm13779362wrj.37.2020.06.21.05.48.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 05:48:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sH5Z7PRdVohuoItYDl5pz8xjGsZcdn/4T0aCVreGxQE=; b=VNUhS0qwVHBPqs/7BDhN4Shxzj0oR2USE/DL7xqrIrfo6rg1W3Lk5MKZHgn0LidjdK pBus3MqJJ2M0q4DrYQKNJyCcHi1LdKwCIB9YsWx8HfOf8flMN032jVudKnauP1gtidId GFXMnQwVzQ0VO6LoFm++RXVXAU/fAV9lzD5QfWnOBjrCkyeawCG17AqxhBddtbK3c0mx CapzmqhwXSZUIn9099zfhj0p0RFi7w6PQMidXxYZ7I3KVS6RjlMYdOT6Cw7tilCU+LRH WLlTuFB+oRKQWseQy5PDoWVlDxMcdxg6Y59kYnQOr/xLxb/suFzNcn7UEZjHzOd/U4wh fzvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sH5Z7PRdVohuoItYDl5pz8xjGsZcdn/4T0aCVreGxQE=; b=S+PBy9H0Ii6ADvzZSvf3AO4spdq4RK7RvxLXaXypDZafgsSCfY0LXX7iG5Fiotzjiu /wnWmR9SKMkDfPO5WxUg16fLwGFQ19sMqOCCzwnG3H5lTPk89ZJt810LuvjSxmLaflbA rbG/9BYR3jg06nht/A4tSxbqKUUO0f43DdVmWokIwdBb7TUvVYqkqrkK5b1TzwcOfg5s OGvm/8/aWJtyVF8h7Qhyn6YecVbhnVb8H/3BrjlHxdT6809RnOBe2kE1A0uX/kd1Z2Hn 0r76nh2svuVNQueAlNZGkyVt9os/U+/DC6B/I/SJ7VwkYrQfJx6+qHZD4rp7JzpI3V2O Zf8Q== X-Gm-Message-State: AOAM533+IFujB8rfB5uZjbR6a9hZ4C/jUck35RWmchdBczi8E4STlIOL eEbgaibey1wffkJvDbbKUE07vIrL X-Google-Smtp-Source: ABdhPJzxaQQBUfqKw3Ek3zqe/pQS6NGe6YbJ2IwZhN4H+GwgH/fThLJsZNxPd7gmtc1Kqcg6VHOWsQ== X-Received: by 2002:adf:edd0:: with SMTP id v16mr494022wro.214.1592743708998; Sun, 21 Jun 2020 05:48:28 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 15/15] docs: Document the RX target Date: Sun, 21 Jun 2020 14:48:07 +0200 Message-Id: <20200621124807.17226-16-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200621124807.17226-1-f4bug@amsat.org> References: <20200621124807.17226-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , Richard Henderson , Magnus Damm , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato Add rx-virt target specification document. Signed-off-by: Yoshinori Sato Message-Id: <20200308130637.37651-1-ysato@users.sourceforge.jp> [PMD: Cover in MAINTAINERS, rename as gdbsim, use machine argument] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- docs/system/target-rx.rst | 36 ++++++++++++++++++++++++++++++++++++ docs/system/targets.rst | 1 + MAINTAINERS | 1 + 3 files changed, 38 insertions(+) create mode 100644 docs/system/target-rx.rst diff --git a/docs/system/target-rx.rst b/docs/system/target-rx.rst new file mode 100644 index 0000000000..4a20a89a06 --- /dev/null +++ b/docs/system/target-rx.rst @@ -0,0 +1,36 @@ +.. _RX-System-emulator: + +RX System emulator +-------------------- + +Use the executable ``qemu-system-rx`` to simulate RX target (GDB simulator= ). +This target emulated following devices. + +- R5F562N8 MCU + + - On-chip memory (ROM 512KB, RAM 96KB) + - Interrupt Control Unit (ICUa) + - 8Bit Timer x 1CH (TMR0,1) + - Compare Match Timer x 2CH (CMT0,1) + - Serial Communication Interface x 1CH (SCI0) + +- External memory 16MByte + +Example of ``qemu-system-rx`` usage for RX is shown below: + +Download ```` from +https://osdn.net/users/ysato/pf/qemu/dl/u-boot.bin.gz + +Start emulation of rx-virt:: + qemu-system-rx -M gdbsim-r5f562n8 -bios + +Download ``kernel_image_file`` from +https://osdn.net/users/ysato/pf/qemu/dl/zImage + +Download ``device_tree_blob`` from +https://osdn.net/users/ysato/pf/qemu/dl/rx-virt.dtb + +Start emulation of rx-virt:: + qemu-system-rx -M gdbsim-r5f562n8 \ + -kernel -dtb \ + -append "earlycon" diff --git a/docs/system/targets.rst b/docs/system/targets.rst index 0d8f91580a..99435a3eba 100644 --- a/docs/system/targets.rst +++ b/docs/system/targets.rst @@ -18,3 +18,4 @@ Contents: target-m68k target-xtensa target-s390x + target-rx diff --git a/MAINTAINERS b/MAINTAINERS index 1c9b4bc8e7..5a46536d86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1257,6 +1257,7 @@ RX Machines rx-gdbsim M: Yoshinori Sato S: Maintained +F: docs/system/target-rx.rst F: hw/rx/rx-gdbsim.c F: tests/acceptance/machine_rx_gdbsim.py =20 --=20 2.21.3