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IronPort-SDR: D3SzsxhkntV8jQMxiKGY2xwPVcc147raH2PNC3Oig7cLD1QsNi50/Zc56xaUk5WYLL/y1xXttO l1IMx6DtEABAeLVQm/2rFPxxOBPDu6dnOrWUMUtau0ygmtQ+sV/Zyz/OdES+HQiR/NCML2MOzp I+N5wjgrvXNT5cyF9nySHRyLzgxnVw/6cRvZMR86BvVqrXWykXiARcZ7HzTz/1bkTAwZlTlciO HDdg4gdKexaTgkaUKYH5cTmR27wBiF0tc7EA8x/RbtomHFAR+t6KB8BJPZn3fp+g1/FyodSqN1 3Mo= X-IronPort-AV: E=Sophos;i="5.75,256,1589212800"; d="scan'208";a="243417012" IronPort-SDR: Gbdt2w1RBiaEWpwP1wFdrJG1TL9g74AE4viYJsDnMh42xm3odZ6vSmiFvwG0J6cB/7WKJvhPqg eDF8VhNTYUUFOGCNFKsQHp1D59HuwbUfM= IronPort-SDR: bWhma3ycjeD7EZVFJguWugMJAPaMigYkcXp1FcLRv74xmyzecFlKIC/Jt7BbdQ8qUTCc+v2/cj iGEo1SbJY/bA== WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL v2 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Date: Fri, 19 Jun 2020 09:58:09 -0700 Message-Id: <20200619165817.4144200-25-alistair.francis@wdc.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200619165817.4144200-1-alistair.francis@wdc.com> References: <20200619165817.4144200-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=4324eb4de=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/19 13:07:24 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Bin Meng At present the GPIO output IRQs are triggered each time any GPIO register is written. However this is not correct. We should only trigger the output IRQ when the pin is configured as output enable. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 1591625864-31494-9-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-9-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- hw/riscv/sifive_gpio.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c index 0d0fd2ba5e..aac6b44cac 100644 --- a/hw/riscv/sifive_gpio.c +++ b/hw/riscv/sifive_gpio.c @@ -76,7 +76,9 @@ static void update_state(SIFIVEGPIOState *s) actual_value =3D pull; } =20 - qemu_set_irq(s->output[i], actual_value); + if (output_en) { + qemu_set_irq(s->output[i], actual_value); + } =20 /* Input value */ ival =3D input_en && actual_value; --=20 2.27.0