From nobody Tue Feb 10 12:45:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1592587280; cv=none; d=zohomail.com; s=zohoarc; b=bsgx8+uIuQCes9teUidsASQzPic6XAJT8pv9xpiHDNhXLDqeSjnnvxJwMIJOP2uuJWqBdn/rjvBTANxQUSgHv05iD4Da9PGapo9dihiRxN4WXs5hBo8fqFeYBRQevrMsP0x9zYv52Gm8AKVhVPbhRYETYCuHf72zXDJVtnm734o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592587280; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=c1CZTaF6JHcZKsdtyUdmB1bOhLoZwEjYE0yVCM/Yk78=; b=BvAnvGIo5irG5tU40HCuCJWM+W8rt6UHpo/KhcFsnqiHVf4pnjexX2mKbuNB8ZHGdDUS/9q0uILs5CUpd2c8RGNDQQl0IGyZ7WH3ttfcYKSxH/JOY/jYLjDd0+cnar3iCJwB+i3lyMpSsyhIQFZflcOubZki1qreTQ2grrgGmeo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592587280212979.7143226298407; Fri, 19 Jun 2020 10:21:20 -0700 (PDT) Received: from localhost ([::1]:58660 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jmKha-00060f-NM for importer@patchew.org; Fri, 19 Jun 2020 13:21:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58310) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jmKUO-0000rg-4E for qemu-devel@nongnu.org; Fri, 19 Jun 2020 13:07:41 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:24436) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jmKUG-0004Q3-LY for qemu-devel@nongnu.org; Fri, 19 Jun 2020 13:07:39 -0400 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 20 Jun 2020 01:07:28 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jun 2020 09:56:03 -0700 Received: from unknown (HELO risc6-mainframe.hgst.com) ([10.86.58.142]) by uls-op-cesaip02.wdc.com with ESMTP; 19 Jun 2020 10:07:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1592586457; x=1624122457; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4Ag3dG3gO5iJShtsvDkPTUJzzzPAJlVfRVRDsoWCqx0=; b=o2Iur9HPwTx3NLtSqBxYLv36RtWuF03Zdow6BwiBQvIRBXaO6OsXMFPd Us9S2rZ8D5XptPK7FzNk2p44ApWQl5DOicJBeD2a6gXClI1zpdItMWWte KcWTm2aVX18ukhfkrULgQtsdg2PwToWDP5nuIiJA8IH3LNBcxXUMGrFAD muaVIAHkVCyO7X0cyrpZJBRY8CP0NdrUtZ3h98RRzystYxbi8aktFTUUk 6H4EgvEcGPRN2405VBBOsah6dHCz3r9BoGitMF1KqdNYxdLZO+WJPEywr eAvP9tAvMI0tw1INU7S1CaaaIKb92t6appwcbM6MhNJLMgzN55ht21m3J Q==; IronPort-SDR: 2wbGMnErFY+zQZSHyMbkR+Z1PxetB0QEK00+3NcSWqzwCrbismtUcniUn4k4qK9uUngG9r1h5O AV63LpgSxjXrO5eL4mcuLZxDbyFClyFF70X6NyP+e2lL+3r1AA8wTGtZDgaQVcfO+YSvyIwlTy 6JVRxgcUyzZZr61mlgMTQrWVKqoX+we+f8B6EEHPFJvyseywPlmAUs8A/1ivnkJOEpinU8s41Z jOW19rvsCthxYmY2FfijUKJ8yJXfY9LYrinBBVvLIhHTyJMFTi7ZAbVldYHR/FzB9RDHED/vvO 6ZY= X-IronPort-AV: E=Sophos;i="5.75,256,1589212800"; d="scan'208";a="243417005" IronPort-SDR: qDC0zaLiwgNKKviT3xufOVTbF+WPMvVIfPMJ1uyNIbNhvKW0LZjpqgoEKbFo8D/6vRXVIE4OF7 Ml+kSQv1+ciN6z5vu+GmlPnfDhGTYh6/w= IronPort-SDR: hQnxKYaYSn3YmJsSWkuJgVikTNj0fyt72a8/9DSKuONaPINRdMsMSGRr2lwdi0DAV3yxb32ViS AjWaeLYvpwkw== WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL v2 21/32] hw/riscv: sifive_gpio: Clean up the codes Date: Fri, 19 Jun 2020 09:58:06 -0700 Message-Id: <20200619165817.4144200-22-alistair.francis@wdc.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200619165817.4144200-1-alistair.francis@wdc.com> References: <20200619165817.4144200-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=4324eb4de=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/19 13:07:24 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Bin Meng Do various minor clean-ups to the exisiting codes for: - coding convention conformance - remove unnecessary blank lines - spell SiFive correctly Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 1591625864-31494-6-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- include/hw/riscv/sifive_gpio.h | 7 ++++--- hw/riscv/sifive_gpio.c | 13 +++++-------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h index fce03d6c41..ad915b26d6 100644 --- a/include/hw/riscv/sifive_gpio.h +++ b/include/hw/riscv/sifive_gpio.h @@ -1,5 +1,5 @@ /* - * sifive System-on-Chip general purpose input/output register definition + * SiFive System-on-Chip general purpose input/output register definition * * Copyright 2019 AdaCore * @@ -10,10 +10,12 @@ * This code is licensed under the GPL version 2 or later. See * the COPYING file in the top-level directory. */ + #ifndef SIFIVE_GPIO_H #define SIFIVE_GPIO_H =20 #include "hw/sysbus.h" + #define TYPE_SIFIVE_GPIO "sifive_soc.gpio" #define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_= GPIO) =20 @@ -66,7 +68,6 @@ typedef struct SIFIVEGPIOState { uint32_t out_xor; uint32_t in; uint32_t in_mask; - } SIFIVEGPIOState; =20 -#endif +#endif /* SIFIVE_GPIO_H */ diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c index 5c7c596e6b..c9cffa2eba 100644 --- a/hw/riscv/sifive_gpio.c +++ b/hw/riscv/sifive_gpio.c @@ -1,5 +1,5 @@ /* - * sifive System-on-Chip general purpose input/output register definition + * SiFive System-on-Chip general purpose input/output register definition * * Copyright 2019 AdaCore * @@ -20,7 +20,6 @@ =20 static void update_output_irq(SIFIVEGPIOState *s) { - uint32_t pending; uint32_t pin; =20 @@ -186,7 +185,7 @@ static uint64_t sifive_gpio_read(void *opaque, hwaddr o= ffset, unsigned int size) } =20 static void sifive_gpio_write(void *opaque, hwaddr offset, - uint64_t value, unsigned int size) + uint64_t value, unsigned int size) { SIFIVEGPIOState *s =3D SIFIVE_GPIO(opaque); =20 @@ -318,7 +317,6 @@ static void sifive_gpio_reset(DeviceState *dev) s->out_xor =3D 0; s->in =3D 0; s->in_mask =3D 0; - } =20 static const VMStateDescription vmstate_sifive_gpio =3D { @@ -342,8 +340,8 @@ static const VMStateDescription vmstate_sifive_gpio =3D= { VMSTATE_UINT32(iof_en, SIFIVEGPIOState), VMSTATE_UINT32(iof_sel, SIFIVEGPIOState), VMSTATE_UINT32(out_xor, SIFIVEGPIOState), - VMSTATE_UINT32(in, SIFIVEGPIOState), - VMSTATE_UINT32(in_mask, SIFIVEGPIOState), + VMSTATE_UINT32(in, SIFIVEGPIOState), + VMSTATE_UINT32(in_mask, SIFIVEGPIOState), VMSTATE_END_OF_LIST() } }; @@ -356,7 +354,6 @@ static void sifive_gpio_init(Object *obj) TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); =20 - for (int i =3D 0; i < SIFIVE_GPIO_PINS; i++) { sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); } @@ -371,7 +368,7 @@ static void sifive_gpio_class_init(ObjectClass *klass, = void *data) =20 dc->vmsd =3D &vmstate_sifive_gpio; dc->reset =3D sifive_gpio_reset; - dc->desc =3D "sifive GPIO"; + dc->desc =3D "SiFive GPIO"; } =20 static const TypeInfo sifive_gpio_info =3D { --=20 2.27.0