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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=4324eb4de=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/19 13:07:24 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Bin Meng This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- hw/riscv/opentitan.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 675ce900bd..19223e4c29 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -53,7 +53,7 @@ static const struct MemmapEntry { [IBEX_PADCTRL] =3D { 0x40160000, 0x10000 } }; =20 -static void riscv_opentitan_init(MachineState *machine) +static void opentitan_board_init(MachineState *machine) { const struct MemmapEntry *memmap =3D ibex_memmap; OpenTitanState *s =3D g_new0(OpenTitanState, 1); @@ -70,7 +70,6 @@ static void riscv_opentitan_init(MachineState *machine) memory_region_add_subregion(sys_mem, memmap[IBEX_RAM].base, main_mem); =20 - if (machine->firmware) { riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL= ); } @@ -80,17 +79,17 @@ static void riscv_opentitan_init(MachineState *machine) } } =20 -static void riscv_opentitan_machine_init(MachineClass *mc) +static void opentitan_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Board compatible with OpenTitan"; - mc->init =3D riscv_opentitan_init; + mc->init =3D opentitan_board_init; mc->max_cpus =3D 1; mc->default_cpu_type =3D TYPE_RISCV_CPU_IBEX; } =20 -DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init) +DEFINE_MACHINE("opentitan", opentitan_machine_init) =20 -static void riscv_lowrisc_ibex_soc_init(Object *obj) +static void lowrisc_ibex_soc_init(Object *obj) { LowRISCIbexSoCState *s =3D RISCV_IBEX_SOC(obj); =20 @@ -101,7 +100,7 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj) object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); } =20 -static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **e= rrp) +static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) { const struct MemmapEntry *memmap =3D ibex_memmap; MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -186,26 +185,26 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceStat= e *dev_soc, Error **errp) memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size); } =20 -static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) +static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - dc->realize =3D riscv_lowrisc_ibex_soc_realize; + dc->realize =3D lowrisc_ibex_soc_realize; /* Reason: Uses serial_hds in realize function, thus can't be used twi= ce */ dc->user_creatable =3D false; } =20 -static const TypeInfo riscv_lowrisc_ibex_soc_type_info =3D { +static const TypeInfo lowrisc_ibex_soc_type_info =3D { .name =3D TYPE_RISCV_IBEX_SOC, .parent =3D TYPE_DEVICE, .instance_size =3D sizeof(LowRISCIbexSoCState), - .instance_init =3D riscv_lowrisc_ibex_soc_init, - .class_init =3D riscv_lowrisc_ibex_soc_class_init, + .instance_init =3D lowrisc_ibex_soc_init, + .class_init =3D lowrisc_ibex_soc_class_init, }; =20 -static void riscv_lowrisc_ibex_soc_register_types(void) +static void lowrisc_ibex_soc_register_types(void) { - type_register_static(&riscv_lowrisc_ibex_soc_type_info); + type_register_static(&lowrisc_ibex_soc_type_info); } =20 -type_init(riscv_lowrisc_ibex_soc_register_types) +type_init(lowrisc_ibex_soc_register_types) --=20 2.27.0