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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" For SVE, we potentially have a 4th argument coming from the movprfx instruction. Currently we do not optimize movprfx, so the problem is not visible. Signed-off-by: Richard Henderson --- target/arm/helper.h | 20 ++++++------- target/arm/translate-a64.c | 27 ++++++++++++++---- target/arm/translate-neon.inc.c | 10 ++++--- target/arm/translate-sve.c | 5 ++-- target/arm/vec_helper.c | 50 +++++++++++++-------------------- 5 files changed, 61 insertions(+), 51 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index dd32a11b9d..331f77c908 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -595,16 +595,16 @@ DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 -DEF_HELPER_FLAGS_5(gvec_fcmlah, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_fcmlah_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_fcmlas, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(gvec_fcmlah, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(gvec_fcmlah_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(gvec_fcmlas, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(gvec_fcmlas_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(gvec_fcmlad, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7366553f8d..341b11f98d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -616,6 +616,22 @@ static void gen_gvec_op4_ool(DisasContext *s, bool is_= q, int rd, int rn, is_q ? 16 : 8, vec_full_reg_size(s), data, fn); } =20 +/* Expand a 4-operand + fpstatus pointer + simd data value operation using + * an out-of-line helper. + */ +static void gen_gvec_op4_fpst(DisasContext *s, bool is_q, int rd, int rn, + int rm, int ra, bool is_fp16, int data, + gen_helper_gvec_4_ptr *fn) +{ + TCGv_ptr fpst =3D get_fpstatus_ptr(is_fp16); + tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + vec_full_reg_offset(s, ra), fpst, + is_q ? 16 : 8, vec_full_reg_size(s), data, fn); + tcg_temp_free_ptr(fpst); +} + /* Set ZF and NF based on a 64 bit result. This is alas fiddlier * than the 32 bit equivalent. */ @@ -11732,15 +11748,15 @@ static void disas_simd_three_reg_same_extra(Disas= Context *s, uint32_t insn) rot =3D extract32(opcode, 0, 2); switch (size) { case 1: - gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot, + gen_gvec_op4_fpst(s, is_q, rd, rn, rm, rd, true, rot, gen_helper_gvec_fcmlah); break; case 2: - gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, + gen_gvec_op4_fpst(s, is_q, rd, rn, rm, rd, false, rot, gen_helper_gvec_fcmlas); break; case 3: - gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, + gen_gvec_op4_fpst(s, is_q, rd, rn, rm, rd, false, rot, gen_helper_gvec_fcmlad); break; default: @@ -12994,9 +13010,10 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) { int rot =3D extract32(insn, 13, 2); int data =3D (index << 2) | rot; - tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), - vec_full_reg_offset(s, rm), fpst, + vec_full_reg_offset(s, rm), + vec_full_reg_offset(s, rd), fpst, is_q ? 16 : 8, vec_full_reg_size(s), data, size =3D=3D MO_64 ? gen_helper_gvec_fcmlas_idx diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index d4556dfb4e..f79995cf50 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -58,7 +58,7 @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) { int opr_sz; TCGv_ptr fpst; - gen_helper_gvec_3_ptr *fn_gvec_ptr; + gen_helper_gvec_4_ptr *fn_gvec_ptr; =20 if (!dc_isar_feature(aa32_vcma, s) || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) { @@ -82,9 +82,10 @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) opr_sz =3D (1 + a->q) * 8; fpst =3D get_fpstatus_ptr(1); fn_gvec_ptr =3D a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcm= lah; - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), + tcg_gen_gvec_4_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vm), + vfp_reg_offset(1, a->vd), fpst, opr_sz, opr_sz, a->rot, fn_gvec_ptr); tcg_temp_free_ptr(fpst); @@ -194,7 +195,7 @@ static bool trans_VFML(DisasContext *s, arg_VFML *a) =20 static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a) { - gen_helper_gvec_3_ptr *fn_gvec_ptr; + gen_helper_gvec_4_ptr *fn_gvec_ptr; int opr_sz; TCGv_ptr fpst; =20 @@ -223,9 +224,10 @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VC= MLA_scalar *a) : gen_helper_gvec_fcmlah_idx); opr_sz =3D (1 + a->q) * 8; fpst =3D get_fpstatus_ptr(1); - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), + tcg_gen_gvec_4_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vm), + vfp_reg_offset(1, a->vd), fpst, opr_sz, opr_sz, (a->index << 2) | a->rot, fn_gvec_ptr); tcg_temp_free_ptr(fpst); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 835ccc0cee..26497f0a6d 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4391,7 +4391,7 @@ static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FC= MLA_zpzzz *a) =20 static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a) { - static gen_helper_gvec_3_ptr * const fns[2] =3D { + static gen_helper_gvec_4_ptr * const fns[2] =3D { gen_helper_gvec_fcmlah_idx, gen_helper_gvec_fcmlas_idx, }; @@ -4401,9 +4401,10 @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FC= MLA_zzxz *a) if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); - tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), + tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), + vec_full_reg_offset(s, a->ra), status, vsz, vsz, a->index * 4 + a->rot, fns[a->esz - 1]); diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 5a8de167f3..5c0760de05 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -609,13 +609,11 @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, clear_tail(d, opr_sz, simd_maxsz(desc)); } =20 -void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, +void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, void *va, void *vfpst, uint32_t desc) { uintptr_t opr_sz =3D simd_oprsz(desc); - float16 *d =3D vd; - float16 *n =3D vn; - float16 *m =3D vm; + float16 *d =3D vd, *n =3D vn, *m =3D vm, *a =3D va; float_status *fpst =3D vfpst; intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); @@ -632,19 +630,17 @@ void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, float16 e4 =3D e2; float16 e3 =3D m[H2(i + 1 - flip)] ^ neg_imag; =20 - d[H2(i)] =3D float16_muladd(e2, e1, d[H2(i)], 0, fpst); - d[H2(i + 1)] =3D float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); + d[H2(i)] =3D float16_muladd(e2, e1, a[H2(i)], 0, fpst); + d[H2(i + 1)] =3D float16_muladd(e4, e3, a[H2(i + 1)], 0, fpst); } clear_tail(d, opr_sz, simd_maxsz(desc)); } =20 -void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, +void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, void *va, void *vfpst, uint32_t desc) { uintptr_t opr_sz =3D simd_oprsz(desc); - float16 *d =3D vd; - float16 *n =3D vn; - float16 *m =3D vm; + float16 *d =3D vd, *n =3D vn, *m =3D vm, *a =3D va; float_status *fpst =3D vfpst; intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); @@ -668,20 +664,18 @@ void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void= *vm, float16 e2 =3D n[H2(j + flip)]; float16 e4 =3D e2; =20 - d[H2(j)] =3D float16_muladd(e2, e1, d[H2(j)], 0, fpst); - d[H2(j + 1)] =3D float16_muladd(e4, e3, d[H2(j + 1)], 0, fpst); + d[H2(j)] =3D float16_muladd(e2, e1, a[H2(j)], 0, fpst); + d[H2(j + 1)] =3D float16_muladd(e4, e3, a[H2(j + 1)], 0, fpst); } } clear_tail(d, opr_sz, simd_maxsz(desc)); } =20 -void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, +void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, void *va, void *vfpst, uint32_t desc) { uintptr_t opr_sz =3D simd_oprsz(desc); - float32 *d =3D vd; - float32 *n =3D vn; - float32 *m =3D vm; + float32 *d =3D vd, *n =3D vn, *m =3D vm, *a =3D va; float_status *fpst =3D vfpst; intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); @@ -698,19 +692,17 @@ void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, float32 e4 =3D e2; float32 e3 =3D m[H4(i + 1 - flip)] ^ neg_imag; =20 - d[H4(i)] =3D float32_muladd(e2, e1, d[H4(i)], 0, fpst); - d[H4(i + 1)] =3D float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); + d[H4(i)] =3D float32_muladd(e2, e1, a[H4(i)], 0, fpst); + d[H4(i + 1)] =3D float32_muladd(e4, e3, a[H4(i + 1)], 0, fpst); } clear_tail(d, opr_sz, simd_maxsz(desc)); } =20 -void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, +void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, void *va, void *vfpst, uint32_t desc) { uintptr_t opr_sz =3D simd_oprsz(desc); - float32 *d =3D vd; - float32 *n =3D vn; - float32 *m =3D vm; + float32 *d =3D vd, *n =3D vn, *m =3D vm, *a =3D va; float_status *fpst =3D vfpst; intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); @@ -734,20 +726,18 @@ void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void= *vm, float32 e2 =3D n[H4(j + flip)]; float32 e4 =3D e2; =20 - d[H4(j)] =3D float32_muladd(e2, e1, d[H4(j)], 0, fpst); - d[H4(j + 1)] =3D float32_muladd(e4, e3, d[H4(j + 1)], 0, fpst); + d[H4(j)] =3D float32_muladd(e2, e1, a[H4(j)], 0, fpst); + d[H4(j + 1)] =3D float32_muladd(e4, e3, a[H4(j + 1)], 0, fpst); } } clear_tail(d, opr_sz, simd_maxsz(desc)); } =20 -void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, +void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, void *va, void *vfpst, uint32_t desc) { uintptr_t opr_sz =3D simd_oprsz(desc); - float64 *d =3D vd; - float64 *n =3D vn; - float64 *m =3D vm; + float64 *d =3D vd, *n =3D vn, *m =3D vm, *a =3D va; float_status *fpst =3D vfpst; intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); uint64_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); @@ -764,8 +754,8 @@ void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, float64 e4 =3D e2; float64 e3 =3D m[i + 1 - flip] ^ neg_imag; =20 - d[i] =3D float64_muladd(e2, e1, d[i], 0, fpst); - d[i + 1] =3D float64_muladd(e4, e3, d[i + 1], 0, fpst); + d[i] =3D float64_muladd(e2, e1, a[i], 0, fpst); + d[i + 1] =3D float64_muladd(e4, e3, a[i + 1], 0, fpst); } clear_tail(d, opr_sz, simd_maxsz(desc)); } --=20 2.25.1