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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200416173109.8856-1-steplong@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix overlap between output and input vectors. --- target/arm/helper-sve.h | 7 +++ target/arm/sve.decode | 6 ++ target/arm/sve_helper.c | 124 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 19 ++++++ 4 files changed, 156 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index c47dea5920..1d5d272c5c 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -2063,6 +2063,13 @@ DEF_HELPER_FLAGS_5(sve2_nmatch_ppzz_b, TCG_CALL_NO_R= WG, DEF_HELPER_FLAGS_5(sve2_nmatch_ppzz_h, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(sve2_histcnt_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_histcnt_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_histseg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_s, TCG_CALL_NO_RWG, diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 3121eabbf8..0edb72d4fb 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -146,6 +146,7 @@ &rprrr_esz rn=3D%reg_movprfx @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \ &rprrr_esz rn=3D%reg_movprfx +@rd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 &rprr_esz =20 # One register operand, with governing predicate, vector element size @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz @@ -1336,6 +1337,11 @@ RSUBHNT 01000101 .. 1 ..... 011 111 ..... ..= ... @rd_rn_rm MATCH 01000101 .. 1 ..... 100 ... ..... 0 .... @pd_pg_rn_rm NMATCH 01000101 .. 1 ..... 100 ... ..... 1 .... @pd_pg_rn_rm =20 +### SVE2 Histogram Computation + +HISTCNT 01000101 .. 1 ..... 110 ... ..... ..... @rd_pg_rn_rm +HISTSEG 01000101 .. 1 ..... 101 000 ..... ..... @rd_rn_rm + ## SVE2 floating-point pairwise operations =20 FADDP 01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 4464c9af52..bc1c3ce1f0 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -6660,3 +6660,127 @@ DO_PPZZ_MATCH(sve2_nmatch_ppzz_b, MO_8, true) DO_PPZZ_MATCH(sve2_nmatch_ppzz_h, MO_16, true) =20 #undef DO_PPZZ_MATCH + +void HELPER(sve2_histcnt_s)(void *vd, void *vn, void *vm, void *vg, + uint32_t desc) +{ + ARMVectorReg scratch; + intptr_t i, j; + intptr_t opr_sz =3D simd_oprsz(desc); + uint32_t *d =3D vd, *n =3D vn, *m =3D vm; + uint8_t *pg =3D vg; + + if (d =3D=3D n) { + n =3D memcpy(&scratch, n, opr_sz); + if (d =3D=3D m) { + m =3D n; + } + } else if (d =3D=3D m) { + m =3D memcpy(&scratch, m, opr_sz); + } + + for (i =3D 0; i < opr_sz; i +=3D 4) { + uint64_t count =3D 0; + uint8_t pred; + + pred =3D pg[H1(i >> 3)] >> (i & 7); + if (pred & 1) { + uint32_t nn =3D n[H4(i >> 2)]; + + for (j =3D 0; j <=3D i; j +=3D 4) { + pred =3D pg[H1(j >> 3)] >> (j & 7); + if ((pred & 1) && nn =3D=3D m[H4(j >> 2)]) { + ++count; + } + } + } + d[H4(i >> 2)] =3D count; + } +} + +void HELPER(sve2_histcnt_d)(void *vd, void *vn, void *vm, void *vg, + uint32_t desc) +{ + ARMVectorReg scratch; + intptr_t i, j; + intptr_t opr_sz =3D simd_oprsz(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + uint8_t *pg =3D vg; + + if (d =3D=3D n) { + n =3D memcpy(&scratch, n, opr_sz); + if (d =3D=3D m) { + m =3D n; + } + } else if (d =3D=3D m) { + m =3D memcpy(&scratch, m, opr_sz); + } + + for (i =3D 0; i < opr_sz / 8; ++i) { + uint64_t count =3D 0; + if (pg[H1(i)] & 1) { + uint64_t nn =3D n[i]; + for (j =3D 0; j <=3D i; ++j) { + if ((pg[H1(j)] & 1) && nn =3D=3D m[j]) { + ++count; + } + } + } + d[i] =3D count; + } +} + +/* + * Returns the number of bytes in m0 and m1 that match n. + * See comment for do_match2(). + * */ +static inline uint64_t do_histseg_cnt(uint8_t n, uint64_t m0, uint64_t m1) +{ + int esz =3D MO_8; + int bits =3D 8 << esz; + uint64_t ones =3D dup_const(esz, 1); + uint64_t signs =3D ones << (bits - 1); + uint64_t cmp0, cmp1; + + cmp1 =3D dup_const(esz, n); + cmp0 =3D cmp1 ^ m0; + cmp1 =3D cmp1 ^ m1; + cmp0 =3D (cmp0 - ones) & ~cmp0 & signs; + cmp1 =3D (cmp1 - ones) & ~cmp1 & signs; + + /* + * Combine the two compares in a way that the bits do + * not overlap, and so preserves the count of set bits. + * If the host has an efficient instruction for ctpop, + * then ctpop(x) + ctpop(y) has the same number of + * operations as ctpop(x | (y >> 1)). If the host does + * not have an efficient ctpop, then we only want to + * use it once. + */ + return ctpop64(cmp0 | (cmp1 >> 1)); +} + +void HELPER(sve2_histseg)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, j; + intptr_t opr_sz =3D simd_oprsz(desc); + + for (i =3D 0; i < opr_sz; i +=3D 16) { + uint64_t n0 =3D *(uint64_t *)(vn + i); + uint64_t m0 =3D *(uint64_t *)(vm + i); + uint64_t n1 =3D *(uint64_t *)(vn + i + 8); + uint64_t m1 =3D *(uint64_t *)(vm + i + 8); + uint64_t out0 =3D 0; + uint64_t out1 =3D 0; + + for (j =3D 0; j < 64; j +=3D 8) { + uint64_t cnt0 =3D do_histseg_cnt(n0 >> j, m0, m1); + uint64_t cnt1 =3D do_histseg_cnt(n1 >> j, m0, m1); + out0 |=3D cnt0 << j; + out1 |=3D cnt1 << j; + } + + *(uint64_t *)(vd + i) =3D out0; + *(uint64_t *)(vd + i + 8) =3D out1; + } +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index c8c4822d9e..559250e0d6 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7065,6 +7065,25 @@ static bool trans_##NAME(DisasContext *s, arg_rprr_e= sz *a) \ DO_SVE2_PPZZ_MATCH(MATCH, match) DO_SVE2_PPZZ_MATCH(NMATCH, nmatch) =20 +static bool trans_HISTCNT(DisasContext *s, arg_rprr_esz *a) +{ + static gen_helper_gvec_4 * const fns[2] =3D { + gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d + }; + if (a->esz < 2) { + return false; + } + return do_sve2_zpzz_ool(s, a, fns[a->esz - 2]); +} + +static bool trans_HISTSEG(DisasContext *s, arg_rrr_esz *a) +{ + if (a->esz !=3D 0) { + return false; + } + return do_sve2_zzz_ool(s, a, gen_helper_sve2_histseg); +} + static bool do_sve2_zpzz_fp(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4_ptr *fn) { --=20 2.25.1