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bh=6mwRQvaPxwp78gZwlfE2uirgWSBqcSQCzBEF2uyFkyI=; b=Yz28+0n86qMDVmWltDc7RVxgFNUs26O+/ij2804l/KLYhgvOfvnWm4V1I9+ybD6ul3ZzE4 MD/c6y3HqLZNpod2iKle2LBndSgLlXB0RaLX7r4uo7IOM8cOP0wBnKN9picW7x5qeRCHz1 KbOPtsSCj3OW34XBU70WaGn9urDDP10= X-MC-Unique: CGipXDDZOw6LWXyBs5X5Cw-1 From: P J P To: Peter Maydell Subject: [PATCH 2/6] pci-host: add pcie-msi read method Date: Wed, 17 Jun 2020 11:09:29 +0530 Message-Id: <20200617053934.122642-3-ppandit@redhat.com> In-Reply-To: <20200617053934.122642-1-ppandit@redhat.com> References: <20200617053934.122642-1-ppandit@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=207.211.31.120; envelope-from=ppandit@redhat.com; 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charset="utf-8" From: Prasad J Pandit Add pcie-msi mmio read method to avoid NULL pointer dereference issue. Reported-by: Lei Sun Signed-off-by: Prasad J Pandit --- hw/pci-host/designware.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index dd245516dd..c34c366f36 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/log.h" #include "hw/pci/msi.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_host.h" @@ -63,6 +64,13 @@ designware_pcie_root_to_host(DesignwarePCIERoot *root) return DESIGNWARE_PCIE_HOST(bus->parent); } =20 +static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr, + unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); + return 0; +} + static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { @@ -77,6 +85,7 @@ static void designware_pcie_root_msi_write(void *opaque, = hwaddr addr, } =20 static const MemoryRegionOps designware_pci_host_msi_ops =3D { + .read =3D designware_pcie_root_msi_read, .write =3D designware_pcie_root_msi_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { --=20 2.26.2