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charset="utf-8" From: Prasad J Pandit Add pci-intack mmio write method to avoid NULL pointer dereference issue. Reported-by: Lei Sun Signed-off-by: Prasad J Pandit --- hw/pci-host/prep.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 1a02e9a670..41befee203 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -27,6 +27,7 @@ #include "qemu-common.h" #include "qemu/units.h" #include "qapi/error.h" +#include "qemu/log.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_host.h" @@ -119,8 +120,15 @@ static uint64_t raven_intack_read(void *opaque, hwaddr= addr, return pic_read_irq(isa_pic); } =20 +static void raven_intack_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); +} + static const MemoryRegionOps raven_intack_ops =3D { .read =3D raven_intack_read, + .write =3D raven_intack_write, .valid =3D { .max_access_size =3D 1, }, --=20 2.26.2 From nobody Sun Feb 8 22:22:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Prasad J Pandit Add pcie-msi mmio read method to avoid NULL pointer dereference issue. Reported-by: Lei Sun Signed-off-by: Prasad J Pandit --- hw/pci-host/designware.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index dd245516dd..c34c366f36 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/log.h" #include "hw/pci/msi.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_host.h" @@ -63,6 +64,13 @@ designware_pcie_root_to_host(DesignwarePCIERoot *root) return DESIGNWARE_PCIE_HOST(bus->parent); } =20 +static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr, + unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); + return 0; +} + static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { @@ -77,6 +85,7 @@ static void designware_pcie_root_msi_write(void *opaque, = hwaddr addr, } =20 static const MemoryRegionOps designware_pci_host_msi_ops =3D { + .read =3D designware_pcie_root_msi_read, .write =3D designware_pcie_root_msi_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { --=20 2.26.2 From nobody Sun Feb 8 22:22:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Prasad J Pandit Add vfio quirk device mmio write method to avoid NULL pointer dereference issue. Reported-by: Lei Sun Signed-off-by: Prasad J Pandit --- hw/vfio/pci-quirks.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index f2155ddb1d..5bd98885d5 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -13,6 +13,7 @@ #include "qemu/osdep.h" #include "exec/memop.h" #include "qemu/units.h" +#include "qemu/log.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qemu/module.h" @@ -263,8 +264,15 @@ static uint64_t vfio_ati_3c3_quirk_read(void *opaque, return data; } =20 +static void vfio_ati_3c3_quirk_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); +} + static const MemoryRegionOps vfio_ati_3c3_quirk =3D { .read =3D vfio_ati_3c3_quirk_read, + .write =3D vfio_ati_3c3_quirk_write, .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 --=20 2.26.2 From nobody Sun Feb 8 22:22:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Prasad J Pandit Add ppc-parity mmio write method to avoid NULL pointer dereference issue. Reported-by: Lei Sun Signed-off-by: Prasad J Pandit --- hw/ppc/prep_systemio.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c index bbc51b6e9a..aacd7831fd 100644 --- a/hw/ppc/prep_systemio.c +++ b/hw/ppc/prep_systemio.c @@ -23,6 +23,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" #include "hw/irq.h" #include "hw/isa/isa.h" #include "hw/qdev-properties.h" @@ -235,8 +236,15 @@ static uint64_t ppc_parity_error_readl(void *opaque, h= waddr addr, return val; } =20 +static void ppc_parity_error_writel(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); +} + static const MemoryRegionOps ppc_parity_error_ops =3D { .read =3D ppc_parity_error_readl, + .write =3D ppc_parity_error_writel, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, --=20 2.26.2 From nobody Sun Feb 8 22:22:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Prasad J Pandit Add nrf51_soc mmio read method to avoid NULL pointer dereference issue. Reported-by: Lei Sun Signed-off-by: Prasad J Pandit --- hw/nvram/nrf51_nvm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/nvram/nrf51_nvm.c b/hw/nvram/nrf51_nvm.c index f2283c1a8d..e813c7ec72 100644 --- a/hw/nvram/nrf51_nvm.c +++ b/hw/nvram/nrf51_nvm.c @@ -274,6 +274,12 @@ static const MemoryRegionOps io_ops =3D { }; =20 =20 +static uint64_t flash_read(void *opaque, hwaddr addr, unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); + return 0; +} + static void flash_write(void *opaque, hwaddr offset, uint64_t value, unsigned int size) { @@ -300,6 +306,7 @@ static void flash_write(void *opaque, hwaddr offset, ui= nt64_t value, =20 =20 static const MemoryRegionOps flash_ops =3D { + .read =3D flash_read, .write =3D flash_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, --=20 2.26.2 From nobody Sun Feb 8 22:22:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Prasad J Pandit Add spapr msi mmio read method to avoid NULL pointer dereference issue. Reported-by: Lei Sun Signed-off-by: Prasad J Pandit --- hw/ppc/spapr_pci.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 83f1453096..d4193be205 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -52,6 +52,7 @@ #include "sysemu/kvm.h" #include "sysemu/hostmem.h" #include "sysemu/numa.h" +#include "qemu/log.h" =20 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ #define RTAS_QUERY_FN 0 @@ -738,6 +739,12 @@ static PCIINTxRoute spapr_route_intx_pin_to_irq(void *= opaque, int pin) return route; } =20 +static uint64_t spapr_msi_read(void *opaque, hwaddr addr, unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); + return 0; +} + /* * MSI/MSIX memory region implementation. * The handler handles both MSI and MSIX. @@ -756,7 +763,7 @@ static void spapr_msi_write(void *opaque, hwaddr addr, =20 static const MemoryRegionOps spapr_msi_ops =3D { /* There is no .read as the read result is undefined by PCI spec */ - .read =3D NULL, + .read =3D spapr_msi_read, .write =3D spapr_msi_write, .endianness =3D DEVICE_LITTLE_ENDIAN }; --=20 2.26.2