From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592327499; cv=none; d=zohomail.com; s=zohoarc; b=h+eCgtMsO2+hjDTkztLwv/mzzYKuxIMuKdjb2pgfkkIf0TkOBFaXwL8k5xRZK3q1bGSKIe5mS3uZ3Q5iuM+DXHLQ1AQVFz1sxgPHit0I+V7X/CsGPDEOZcN+Y0CeXjoPDOj8Kmguk+AgrBIjtJ1vVSPz6kEVxowtxjDuucpjeRU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592327499; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xWDTix/EFrDbpFYcthSvvgWszuD0YBkrPi92WsJkrek=; b=M2AGpwQubATnptZNQbN55VUKQIWNZWVelxyc7vkSS/V34LUHmL6wVgcpkMlHj/JO9JjsoHIjSlA4QuM9nVYRMDibMKmKOSNrZaBNgrPvS5iGLXV04TuzN/iFU4MbBmSmb6tbzruYpBBbDGWtAGNXdSlvDEqenteEx5qg0nO+9lo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592327499692591.4669716790717; Tue, 16 Jun 2020 10:11:39 -0700 (PDT) Received: from localhost ([::1]:41486 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlF7a-0006so-Dq for importer@patchew.org; Tue, 16 Jun 2020 13:11:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF4u-0000zI-A1 for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:08:52 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:52877) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF4s-0007QT-Il for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:08:52 -0400 Received: by mail-wm1-x343.google.com with SMTP id r9so3583884wmh.2 for ; Tue, 16 Jun 2020 10:08:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y80sm5263216wmc.34.2020.06.16.10.08.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 10:08:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xWDTix/EFrDbpFYcthSvvgWszuD0YBkrPi92WsJkrek=; b=B+oIK/0UaCUu8kjSV1lidcxOl9ORLboEDGyaNq6SiX+YIWndub5PlD5ki+csGnIk+q T5PMaNZMOubupQ9hvo/HYGFfEW267BZhJIPC1nL090d2/utWXcJrcaW4SSD49aw8+mCF L3d+wJkuAGbj3tHtvx0bGNY8d770vw1FR21hP7RBtxXdBEw1k0lAmEiMVMnanKq7t9R+ qoiklSoGdAjyr1rgCev7OY7y/anUyaA0eVbeEqMXd+cpFWLANQht+LJjBznvD0GPQh3z G7Ml+zb9v8OeAJxaj4wZhdwr4mtlYwPH28HlLWQbajMHq/fvXxAWwNhRK+6TxLzM/ymh jbng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xWDTix/EFrDbpFYcthSvvgWszuD0YBkrPi92WsJkrek=; b=WJ0IMx7Xe3+KMY8Tq0vqDo0FbYty8j/VxNyjILlENR3aIydSihmJ1r8futBxIgUT/r XvTQ813lwI14TvGWrX+YKST4HHnqemM2Qyv9CGuVi9Dl+0cBEysXF+Nomwj7bHLtpIB3 kau36iOYacb08Zl0JIitAYLGuY28yBJNx4SHiVaetwkPScu4EISEiihIjqeabMYLxv7h B5adT/MAffu7L+4E0Av5pehGBuXrL6n7bvnd+riO1EXUj3aHyGR8yW9u/eDANBbTuzf5 5SlpmjCerulVKvSCN7F04VtJU5/F81ofK+oUSvqVnOaLfEkgjbg0+5jxHP7Tyn8fYlJ7 Sstg== X-Gm-Message-State: AOAM533epIRUsISufdwBVv477u6gCa7ptJDLuFXBbhxa3e/kac63b57K s9fHvVufsm5cFu8MoU5RBlVtJ63lsbdP3Q== X-Google-Smtp-Source: ABdhPJy6/DUOc7a7VNYQHK080uHCs0jcKB17ju9diR0UjJjv71M0YGBk1xQ8h5JgNPSWesKmBfngsw== X-Received: by 2002:a1c:2b01:: with SMTP id r1mr4463121wmr.26.1592327329086; Tue, 16 Jun 2020 10:08:49 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/21] target/arm: Convert Neon 2-reg-misc VREV64 to decodetree Date: Tue, 16 Jun 2020 18:08:24 +0100 Message-Id: <20200616170844.13318-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200616170844.13318-1-peter.maydell@linaro.org> References: <20200616170844.13318-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon VREV64 insn from the 2-reg-misc grouping to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 12 ++++++++ target/arm/translate-neon.inc.c | 50 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 24 ++-------------- 3 files changed, 64 insertions(+), 22 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 6d890b2161f..e12fdf30957 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -429,6 +429,18 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0= . op:1 1 .... @1reg_imm vm=3D%vm_dp vd=3D%vd_dp size=3D1 VDUP_scalar 1111 001 1 1 . 11 index:1 100 .... 11 000 q:1 . 0 .... \ vm=3D%vm_dp vd=3D%vd_dp size=3D2 + + ################################################################## + # 2-reg-misc grouping: + # 1111 001 11 D 11 size:2 opc1:2 Vd:4 0 opc2:4 q:1 M 0 Vm:4 + ################################################################## + + &2misc vd vm q size + + @2misc .... ... .. . .. size:2 .. .... . .... q:1 . . .... \ + &2misc vm=3D%vm_dp vd=3D%vd_dp + + VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc ] =20 # Subgroup for size !=3D 0b11 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index a5aa56bbdeb..90431a5383f 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -2970,3 +2970,53 @@ static bool trans_VDUP_scalar(DisasContext *s, arg_V= DUP_scalar *a) a->q ? 16 : 8, a->q ? 16 : 8); return true; } + +static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) +{ + int pass, half; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (a->size =3D=3D 3) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + for (pass =3D 0; pass < (a->q ? 2 : 1); pass++) { + TCGv_i32 tmp[2]; + + for (half =3D 0; half < 2; half++) { + tmp[half] =3D neon_load_reg(a->vm, pass * 2 + half); + switch (a->size) { + case 0: + tcg_gen_bswap32_i32(tmp[half], tmp[half]); + break; + case 1: + gen_swap_half(tmp[half]); + break; + case 2: + break; + default: + g_assert_not_reached(); + } + } + neon_store_reg(a->vd, pass * 2, tmp[1]); + neon_store_reg(a->vd, pass * 2 + 1, tmp[0]); + } + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 6d18892adee..5fca38b5fae 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5092,28 +5092,8 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) } switch (op) { case NEON_2RM_VREV64: - for (pass =3D 0; pass < (q ? 2 : 1); pass++) { - tmp =3D neon_load_reg(rm, pass * 2); - tmp2 =3D neon_load_reg(rm, pass * 2 + 1); - switch (size) { - case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_swap_half(tmp); break; - case 2: /* no-op */ break; - default: abort(); - } - neon_store_reg(rd, pass * 2 + 1, tmp); - if (size =3D=3D 2) { - neon_store_reg(rd, pass * 2, tmp2); - } else { - switch (size) { - case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break; - case 1: gen_swap_half(tmp2); break; - default: abort(); - } - neon_store_reg(rd, pass * 2, tmp2); - } - } - break; + /* handled by decodetree */ + return 1; case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U: case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U: for (pass =3D 0; pass < q + 1; pass++) { --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592327396; cv=none; d=zohomail.com; s=zohoarc; b=J4GiIZTYRVh+mm9Nkr0SotqSPeFlOesUoHv5ME/9p31sYjWZQAnwm1yrsaCjUNuRpvB/qXfXSEdzVKP0D0TJWRJT9wE02wxV5uR8PSL8jdZO9F3s0o+rcOSgXJa3DubdftxxIYy8sojnSZtx74nMdWA8APn09WB/y/sRsaClPiI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592327396; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=J9rY0KgHARtmNDmyguZ1hMN7+xt6+4WGmPZIRF6AfUg=; b=EdlBrNbuqbaFjDuso61kQadUr6eWXTqej1eRw1EMDLZJNHI4Td3Oj0FXbLOKSHNCmxtDnAsuQidrW9o/8BqnrDYKSf6bIa9ppYDGN0KqKQqqbIDsD/eLMRuPfvJpWiIX4tElGh0gZ0TRGuuWs2+PUBol8Zxwjd+VmJonSclwlUE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592327396603890.4712820156689; Tue, 16 Jun 2020 10:09:56 -0700 (PDT) Received: from localhost ([::1]:33230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlF5v-0002yZ-Ay for importer@patchew.org; Tue, 16 Jun 2020 13:09:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF4w-00010g-JB for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:08:54 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:54277) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF4u-0007R7-GE for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:08:54 -0400 Received: by mail-wm1-x344.google.com with SMTP id g10so3581366wmh.4 for ; Tue, 16 Jun 2020 10:08:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y80sm5263216wmc.34.2020.06.16.10.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 10:08:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J9rY0KgHARtmNDmyguZ1hMN7+xt6+4WGmPZIRF6AfUg=; b=WjdJ2bCcj5bT81TCIz8SHurcRW+FqARvWWycUCTyqoBjNON1nnt2eSV6M0xw9rT3r5 lNk7H/S2UPnxNCdEBog5quz4+QugHPreOL6j89jQyIUnsxDmKeHUuAtIodsEsjGkVGlq tIaq4uReGo96HHFWuJ7TntzmUsNhK4Or2whISRCQVRXTAsxRDoRcoi1Xm2AESFqpAzh1 PB4gVhkVnEYDvWN7OL1YtkJej1G7VTKSKsdLurEH5JB3CMync2L+/9WkKbxC40A+mwXy jZR0AutaVE+9qbeGKhTggZ6fbhijTDdK/Ow8pSVsvDtTIKGuNPIEtJoVBJryDNDHKWEf 4V9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J9rY0KgHARtmNDmyguZ1hMN7+xt6+4WGmPZIRF6AfUg=; b=oYpdSb1RxkKsOFwimbP2yUqQ0A/vJ3i1O2AQxPhPLtECZLzIUom/teWZLKR5idYG0Y 0MN4Ar1TfXOnpD0TMJfgM/2M1O2j70fPLrrY+av5qNzGHvHtcEVKLVicjz6z31haQgjB gckeem4L1RKMGOyFn8Fp9mmIxRxYndNsyUmkBMhUO/cjgDKFvDk3mjyMVKxv6dTczKZe LCVB1nCsdrunuXYmkEefWtdao7zSTYU16Kg2fspD3F2SpSDEj25nUclijrXZ3MCQ+fH0 Hwk0LZdvFYgzS46k6siDVwGcwzHUoOtWZyp43A17LDssuDSNC8aR2U6BSPS78uBsLDgU sQNQ== X-Gm-Message-State: AOAM533ga0OO3/BCjFJ6lG/T/otpDXi/JOQCIEVxpKBu3S9vFjaXCs5+ EgvU7ZYvqxIbPBvJ8L+xkgNPrw== X-Google-Smtp-Source: ABdhPJx+EPHWyEB0ZT1gQkd0SMwd1znghGpwZNa/olfk4pyd42P1YxXas5BNNgo8hbeGhYnotWTpSg== X-Received: by 2002:a1c:bb05:: with SMTP id l5mr4103347wmf.141.1592327331031; Tue, 16 Jun 2020 10:08:51 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/21] target/arm: Convert Neon 2-reg-misc pairwise ops to decodetree Date: Tue, 16 Jun 2020 18:08:25 +0100 Message-Id: <20200616170844.13318-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200616170844.13318-1-peter.maydell@linaro.org> References: <20200616170844.13318-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the pairwise ops VPADDL and VPADAL in the 2-reg-misc grouping to decodetree. At this point we can get rid of the weird CPU_V001 #define that was used to avoid having to explicitly list all the arguments being passed to some TCG gen/helper functions. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 6 ++ target/arm/translate-neon.inc.c | 149 ++++++++++++++++++++++++++++++++ target/arm/translate.c | 35 +------- 3 files changed, 157 insertions(+), 33 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index e12fdf30957..dd521baa07d 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -441,6 +441,12 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0= . op:1 1 .... @1reg_imm &2misc vm=3D%vm_dp vd=3D%vd_dp =20 VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc + + VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc + VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc + + VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc + VPADAL_U 1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc ] =20 # Subgroup for size !=3D 0b11 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 90431a5383f..2f7bd0d556f 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3020,3 +3020,152 @@ static bool trans_VREV64(DisasContext *s, arg_VREV6= 4 *a) } return true; } + +static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a, + NeonGenWidenFn *widenfn, + NeonGenTwo64OpFn *opfn, + NeonGenTwo64OpFn *accfn) +{ + /* + * Pairwise long operations: widen both halves of the pair, + * combine the pairs with the opfn, and then possibly accumulate + * into the destination with the accfn. + */ + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!widenfn) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + for (pass =3D 0; pass < a->q + 1; pass++) { + TCGv_i32 tmp; + TCGv_i64 rm0_64, rm1_64, rd_64; + + rm0_64 =3D tcg_temp_new_i64(); + rm1_64 =3D tcg_temp_new_i64(); + rd_64 =3D tcg_temp_new_i64(); + tmp =3D neon_load_reg(a->vm, pass * 2); + widenfn(rm0_64, tmp); + tcg_temp_free_i32(tmp); + tmp =3D neon_load_reg(a->vm, pass * 2 + 1); + widenfn(rm1_64, tmp); + tcg_temp_free_i32(tmp); + opfn(rd_64, rm0_64, rm1_64); + tcg_temp_free_i64(rm0_64); + tcg_temp_free_i64(rm1_64); + + if (accfn) { + TCGv_i64 tmp64 =3D tcg_temp_new_i64(); + neon_load_reg64(tmp64, a->vd + pass); + accfn(rd_64, tmp64, rd_64); + tcg_temp_free_i64(tmp64); + } + neon_store_reg64(rd_64, a->vd + pass); + tcg_temp_free_i64(rd_64); + } + return true; +} + +static bool trans_VPADDL_S(DisasContext *s, arg_2misc *a) +{ + static NeonGenWidenFn * const widenfn[] =3D { + gen_helper_neon_widen_s8, + gen_helper_neon_widen_s16, + tcg_gen_ext_i32_i64, + NULL, + }; + static NeonGenTwo64OpFn * const opfn[] =3D { + gen_helper_neon_paddl_u16, + gen_helper_neon_paddl_u32, + tcg_gen_add_i64, + NULL, + }; + + return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL); +} + +static bool trans_VPADDL_U(DisasContext *s, arg_2misc *a) +{ + static NeonGenWidenFn * const widenfn[] =3D { + gen_helper_neon_widen_u8, + gen_helper_neon_widen_u16, + tcg_gen_extu_i32_i64, + NULL, + }; + static NeonGenTwo64OpFn * const opfn[] =3D { + gen_helper_neon_paddl_u16, + gen_helper_neon_paddl_u32, + tcg_gen_add_i64, + NULL, + }; + + return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL); +} + +static bool trans_VPADAL_S(DisasContext *s, arg_2misc *a) +{ + static NeonGenWidenFn * const widenfn[] =3D { + gen_helper_neon_widen_s8, + gen_helper_neon_widen_s16, + tcg_gen_ext_i32_i64, + NULL, + }; + static NeonGenTwo64OpFn * const opfn[] =3D { + gen_helper_neon_paddl_u16, + gen_helper_neon_paddl_u32, + tcg_gen_add_i64, + NULL, + }; + static NeonGenTwo64OpFn * const accfn[] =3D { + gen_helper_neon_addl_u16, + gen_helper_neon_addl_u32, + tcg_gen_add_i64, + NULL, + }; + + return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], + accfn[a->size]); +} + +static bool trans_VPADAL_U(DisasContext *s, arg_2misc *a) +{ + static NeonGenWidenFn * const widenfn[] =3D { + gen_helper_neon_widen_u8, + gen_helper_neon_widen_u16, + tcg_gen_extu_i32_i64, + NULL, + }; + static NeonGenTwo64OpFn * const opfn[] =3D { + gen_helper_neon_paddl_u16, + gen_helper_neon_paddl_u32, + tcg_gen_add_i64, + NULL, + }; + static NeonGenTwo64OpFn * const accfn[] =3D { + gen_helper_neon_addl_u16, + gen_helper_neon_addl_u32, + tcg_gen_add_i64, + NULL, + }; + + return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], + accfn[a->size]); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 5fca38b5fae..4405b034f77 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2934,8 +2934,6 @@ static void gen_exception_return(DisasContext *s, TCG= v_i32 pc) gen_rfe(s, pc, load_cpu_field(spsr)); } =20 -#define CPU_V001 cpu_V0, cpu_V0, cpu_V1 - static int gen_neon_unzip(int rd, int rm, int size, int q) { TCGv_ptr pd, pm; @@ -3117,16 +3115,6 @@ static inline void gen_neon_widen(TCGv_i64 dest, TCG= v_i32 src, int size, int u) tcg_temp_free_i32(src); } =20 -static inline void gen_neon_addl(int size) -{ - switch (size) { - case 0: gen_helper_neon_addl_u16(CPU_V001); break; - case 1: gen_helper_neon_addl_u32(CPU_V001); break; - case 2: tcg_gen_add_i64(CPU_V001); break; - default: abort(); - } -} - static void gen_neon_narrow_op(int op, int u, int size, TCGv_i32 dest, TCGv_i64 src) { @@ -5092,29 +5080,10 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) } switch (op) { case NEON_2RM_VREV64: - /* handled by decodetree */ - return 1; case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U: case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U: - for (pass =3D 0; pass < q + 1; pass++) { - tmp =3D neon_load_reg(rm, pass * 2); - gen_neon_widen(cpu_V0, tmp, size, op & 1); - tmp =3D neon_load_reg(rm, pass * 2 + 1); - gen_neon_widen(cpu_V1, tmp, size, op & 1); - switch (size) { - case 0: gen_helper_neon_paddl_u16(CPU_V001); break; - case 1: gen_helper_neon_paddl_u32(CPU_V001); break; - case 2: tcg_gen_add_i64(CPU_V001); break; - default: abort(); - } - if (op >=3D NEON_2RM_VPADAL) { - /* Accumulate. */ - neon_load_reg64(cpu_V1, rd + pass); - gen_neon_addl(size); - } - neon_store_reg64(cpu_V0, rd + pass); - } - break; + /* handled by decodetree */ + return 1; case NEON_2RM_VTRN: if (size =3D=3D 2) { int n; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon VZIP and VUZP insns in the 2-reg-misc group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 3 ++ target/arm/translate-neon.inc.c | 74 ++++++++++++++++++++++++++ target/arm/translate.c | 92 +-------------------------------- 3 files changed, 79 insertions(+), 90 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index dd521baa07d..ad9e17fd737 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -447,6 +447,9 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm =20 VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc VPADAL_U 1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc + + VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc + VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc ] =20 # Subgroup for size !=3D 0b11 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 2f7bd0d556f..f4799dd9770 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3169,3 +3169,77 @@ static bool trans_VPADAL_U(DisasContext *s, arg_2mis= c *a) return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], accfn[a->size]); } + +typedef void ZipFn(TCGv_ptr, TCGv_ptr); + +static bool do_zip_uzp(DisasContext *s, arg_2misc *a, + ZipFn *fn) +{ + TCGv_ptr pd, pm; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!fn) { + /* Bad size or size/q combination */ + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + pd =3D vfp_reg_ptr(true, a->vd); + pm =3D vfp_reg_ptr(true, a->vm); + fn(pd, pm); + tcg_temp_free_ptr(pd); + tcg_temp_free_ptr(pm); + return true; +} + +static bool trans_VUZP(DisasContext *s, arg_2misc *a) +{ + static ZipFn * const fn[2][4] =3D { + { + gen_helper_neon_unzip8, + gen_helper_neon_unzip16, + NULL, + NULL, + }, { + gen_helper_neon_qunzip8, + gen_helper_neon_qunzip16, + gen_helper_neon_qunzip32, + NULL, + } + }; + return do_zip_uzp(s, a, fn[a->q][a->size]); +} + +static bool trans_VZIP(DisasContext *s, arg_2misc *a) +{ + static ZipFn * const fn[2][4] =3D { + { + gen_helper_neon_zip8, + gen_helper_neon_zip16, + NULL, + NULL, + }, { + gen_helper_neon_qzip8, + gen_helper_neon_qzip16, + gen_helper_neon_qzip32, + NULL, + } + }; + return do_zip_uzp(s, a, fn[a->q][a->size]); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 4405b034f77..442f287d861 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2934,86 +2934,6 @@ static void gen_exception_return(DisasContext *s, TC= Gv_i32 pc) gen_rfe(s, pc, load_cpu_field(spsr)); } =20 -static int gen_neon_unzip(int rd, int rm, int size, int q) -{ - TCGv_ptr pd, pm; - =20 - if (!q && size =3D=3D 2) { - return 1; - } - pd =3D vfp_reg_ptr(true, rd); - pm =3D vfp_reg_ptr(true, rm); - if (q) { - switch (size) { - case 0: - gen_helper_neon_qunzip8(pd, pm); - break; - case 1: - gen_helper_neon_qunzip16(pd, pm); - break; - case 2: - gen_helper_neon_qunzip32(pd, pm); - break; - default: - abort(); - } - } else { - switch (size) { - case 0: - gen_helper_neon_unzip8(pd, pm); - break; - case 1: - gen_helper_neon_unzip16(pd, pm); - break; - default: - abort(); - } - } - tcg_temp_free_ptr(pd); - tcg_temp_free_ptr(pm); - return 0; -} - -static int gen_neon_zip(int rd, int rm, int size, int q) -{ - TCGv_ptr pd, pm; - - if (!q && size =3D=3D 2) { - return 1; - } - pd =3D vfp_reg_ptr(true, rd); - pm =3D vfp_reg_ptr(true, rm); - if (q) { - switch (size) { - case 0: - gen_helper_neon_qzip8(pd, pm); - break; - case 1: - gen_helper_neon_qzip16(pd, pm); - break; - case 2: - gen_helper_neon_qzip32(pd, pm); - break; - default: - abort(); - } - } else { - switch (size) { - case 0: - gen_helper_neon_zip8(pd, pm); - break; - case 1: - gen_helper_neon_zip16(pd, pm); - break; - default: - abort(); - } - } - tcg_temp_free_ptr(pd); - tcg_temp_free_ptr(pm); - return 0; -} - static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1) { TCGv_i32 rd, tmp; @@ -5082,6 +5002,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_2RM_VREV64: case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U: case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U: + case NEON_2RM_VUZP: + case NEON_2RM_VZIP: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -5097,16 +5019,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) goto elementwise; } break; - case NEON_2RM_VUZP: - if (gen_neon_unzip(rd, rm, size, q)) { - return 1; - } - break; - case NEON_2RM_VZIP: - if (gen_neon_zip(rd, rm, size, q)) { - return 1; - } - break; case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: /* also VQMOVUN; op field and mnemonics don't line up = */ if (rm & 1) { --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592327502; cv=none; d=zohomail.com; s=zohoarc; b=B5v20a78qqqXZUMWyWv3C0/eRxqF5Q3WTYaXrhCMfULCNLilCHeteozZMOjBWYoPhk6zugwVwgvwC8ijGsXiDnr2OGTznFkj+vCgEk1qUy3T1MyXqAgW+nunQxcDEgogcjz0xLFfJzT2+PnATEDX1S8mIXMdvNsrXEPGnMf+BLo= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y80sm5263216wmc.34.2020.06.16.10.08.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 10:08:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v6P61HLrEGFwATqpE9ZgpSDARdlQ3liQ+Dl/YATMb3A=; b=B7NtDCKXz7UDIf765cw1aRFTpUM7F2Do82M1zuHF85oNF8rlerS3LBu1sr9TTY8PXu 99kc3cycko6R0EPcWYre+5z4XcwNrIb5/z4nA1b+2k7mukV/kNtxuV6yA1+0Gwa1Dq6a tS/GEfO3u9b4sr4SDiU8C7R5llY0hwTcQGclwVjnGa+iAImrbk5ctX5eszQHgknay9UO +/jnv7RUQjOfxYDKRskaBmhBAIKrxVShqYii0puJgrFEax9uXgHzzn6iqGRXigZXWlLn 1UOv8iRdgyxoxORHHncf7MInpONn6OtfR2CEpNuOLq75Y+0+VePcDieaBoCKlc2kUkFw TYOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v6P61HLrEGFwATqpE9ZgpSDARdlQ3liQ+Dl/YATMb3A=; b=GX9E4iDi3SYQEy6qwfQh9WpdxvrCNiufdEneT1d97WJoISsoky7khRJ8h6pV2X2rjO xu/9wnRDo11DTgr+fy7nwWKOfgTcf/kT2Hk4v/NDIOZ1Y1Z+7EThcQA8gMd2l6il/eWl N/FOUbUWwDLr2cSeZQsvo/+jSz3lZ66DO92djCoImpEQj3513EVpd2vd4d3yNRSVj6uM CGeTYFh25e85JqbR9MOHU+kz4aWn3OvK3GEAWBRsYpvkMS0L3Le8W9smZ/uD8md/FRLk /8E2VXZFtSS8F4XXAj+ibsmrhnlQ9GIJPekQxc/NIjSliPIwXfleIYjAbEVdyGp9gxc8 K8ng== X-Gm-Message-State: AOAM531d9ugcY+wk/PYh/SP8lb6np29OcnhYnscEdw5IRjd49RQ9wLXX 2K5IwfhWaF9/znlDR4TeOZh4uA== X-Google-Smtp-Source: ABdhPJxs0iGnHhHT4iYFZ+qDp7WzpuGZRKOZ4u+g0GHLwzAWA9aBvaSTxTspQPSpAOv2lsyMzCRPpw== X-Received: by 2002:a5d:500c:: with SMTP id e12mr4101929wrt.359.1592327333725; Tue, 16 Jun 2020 10:08:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/21] target/arm: Convert Neon narrowing moves to decodetree Date: Tue, 16 Jun 2020 18:08:27 +0100 Message-Id: <20200616170844.13318-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200616170844.13318-1-peter.maydell@linaro.org> References: <20200616170844.13318-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon narrowing moves VMQNV, VQMOVN, VQMOVUN in the 2-reg-misc group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 9 ++++ target/arm/translate-neon.inc.c | 59 ++++++++++++++++++++++++ target/arm/translate.c | 81 +-------------------------------- 3 files changed, 70 insertions(+), 79 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index ad9e17fd737..2277b4c7b51 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -439,6 +439,8 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm =20 @2misc .... ... .. . .. size:2 .. .... . .... q:1 . . .... \ &2misc vm=3D%vm_dp vd=3D%vd_dp + @2misc_q0 .... ... .. . .. size:2 .. .... . .... . . . .... \ + &2misc vm=3D%vm_dp vd=3D%vd_dp q=3D0 =20 VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc =20 @@ -450,6 +452,13 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0= . op:1 1 .... @1reg_imm =20 VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc + + VMOVN 1111 001 11 . 11 .. 10 .... 0 0100 0 . 0 .... @2misc_q0 + # VQMOVUN: unsigned result (source is always signed) + VQMOVUN 1111 001 11 . 11 .. 10 .... 0 0100 1 . 0 .... @2misc_q0 + # VQMOVN: signed result, source may be signed (_S) or unsigned (_U) + VQMOVN_S 1111 001 11 . 11 .. 10 .... 0 0101 0 . 0 .... @2misc_q0 + VQMOVN_U 1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0 ] =20 # Subgroup for size !=3D 0b11 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index f4799dd9770..b0620972854 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3243,3 +3243,62 @@ static bool trans_VZIP(DisasContext *s, arg_2misc *a) }; return do_zip_uzp(s, a, fn[a->q][a->size]); } + +static bool do_vmovn(DisasContext *s, arg_2misc *a, + NeonGenNarrowEnvFn *narrowfn) +{ + TCGv_i64 rm; + TCGv_i32 rd0, rd1; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vm & 1) { + return false; + } + + if (!narrowfn) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + rm =3D tcg_temp_new_i64(); + rd0 =3D tcg_temp_new_i32(); + rd1 =3D tcg_temp_new_i32(); + + neon_load_reg64(rm, a->vm); + narrowfn(rd0, cpu_env, rm); + neon_load_reg64(rm, a->vm + 1); + narrowfn(rd1, cpu_env, rm); + neon_store_reg(a->vd, 0, rd0); + neon_store_reg(a->vd, 1, rd1); + tcg_temp_free_i64(rm); + return true; +} + +#define DO_VMOVN(INSN, FUNC) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + static NeonGenNarrowEnvFn * const narrowfn[] =3D { \ + FUNC##8, \ + FUNC##16, \ + FUNC##32, \ + NULL, \ + }; \ + return do_vmovn(s, a, narrowfn[a->size]); \ + } + +DO_VMOVN(VMOVN, gen_neon_narrow_u) +DO_VMOVN(VQMOVUN, gen_helper_neon_unarrow_sat) +DO_VMOVN(VQMOVN_S, gen_helper_neon_narrow_sat_s) +DO_VMOVN(VQMOVN_U, gen_helper_neon_narrow_sat_u) diff --git a/target/arm/translate.c b/target/arm/translate.c index 442f287d861..8ecae264e15 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2975,46 +2975,6 @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t= 1) tcg_temp_free_i32(rd); } =20 -static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src) -{ - switch (size) { - case 0: gen_helper_neon_narrow_u8(dest, src); break; - case 1: gen_helper_neon_narrow_u16(dest, src); break; - case 2: tcg_gen_extrl_i64_i32(dest, src); break; - default: abort(); - } -} - -static inline void gen_neon_narrow_sats(int size, TCGv_i32 dest, TCGv_i64 = src) -{ - switch (size) { - case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break; - case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break; - case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break; - default: abort(); - } -} - -static inline void gen_neon_narrow_satu(int size, TCGv_i32 dest, TCGv_i64 = src) -{ - switch (size) { - case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break; - case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break; - case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break; - default: abort(); - } -} - -static inline void gen_neon_unarrow_sats(int size, TCGv_i32 dest, TCGv_i64= src) -{ - switch (size) { - case 0: gen_helper_neon_unarrow_sat8(dest, cpu_env, src); break; - case 1: gen_helper_neon_unarrow_sat16(dest, cpu_env, src); break; - case 2: gen_helper_neon_unarrow_sat32(dest, cpu_env, src); break; - default: abort(); - } -} - static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, i= nt u) { if (u) { @@ -3035,24 +2995,6 @@ static inline void gen_neon_widen(TCGv_i64 dest, TCG= v_i32 src, int size, int u) tcg_temp_free_i32(src); } =20 -static void gen_neon_narrow_op(int op, int u, int size, - TCGv_i32 dest, TCGv_i64 src) -{ - if (op) { - if (u) { - gen_neon_unarrow_sats(size, dest, src); - } else { - gen_neon_narrow(size, dest, src); - } - } else { - if (u) { - gen_neon_narrow_satu(size, dest, src); - } else { - gen_neon_narrow_sats(size, dest, src); - } - } -} - /* Symbolic constants for op fields for Neon 2-register miscellaneous. * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B * table A7-13. @@ -4994,8 +4936,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) !arm_dc_feature(s, ARM_FEATURE_V8)) { return 1; } - if ((op !=3D NEON_2RM_VMOVN && op !=3D NEON_2RM_VQMOVN) && - q && ((rm | rd) & 1)) { + if (q && ((rm | rd) & 1)) { return 1; } switch (op) { @@ -5004,6 +4945,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U: case NEON_2RM_VUZP: case NEON_2RM_VZIP: + case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -5019,25 +4961,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) goto elementwise; } break; - case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: - /* also VQMOVUN; op field and mnemonics don't line up = */ - if (rm & 1) { - return 1; - } - tmp2 =3D NULL; - for (pass =3D 0; pass < 2; pass++) { - neon_load_reg64(cpu_V0, rm + pass); - tmp =3D tcg_temp_new_i32(); - gen_neon_narrow_op(op =3D=3D NEON_2RM_VMOVN, q, si= ze, - tmp, cpu_V0); - if (pass =3D=3D 0) { - tmp2 =3D tmp; - } else { - neon_store_reg(rd, 0, tmp2); - neon_store_reg(rd, 1, tmp); - } - } - break; case NEON_2RM_VSHLL: if (q || (rd & 1)) { return 1; --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VSHLL insn in the 2-reg-misc Neon group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 2 ++ target/arm/translate-neon.inc.c | 52 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 35 +--------------------- 3 files changed, 55 insertions(+), 34 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 2277b4c7b51..0102aa7254b 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -459,6 +459,8 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm # VQMOVN: signed result, source may be signed (_S) or unsigned (_U) VQMOVN_S 1111 001 11 . 11 .. 10 .... 0 0101 0 . 0 .... @2misc_q0 VQMOVN_U 1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0 + + VSHLL 1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0 ] =20 # Subgroup for size !=3D 0b11 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index b0620972854..78239ec1c1b 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3302,3 +3302,55 @@ DO_VMOVN(VMOVN, gen_neon_narrow_u) DO_VMOVN(VQMOVUN, gen_helper_neon_unarrow_sat) DO_VMOVN(VQMOVN_S, gen_helper_neon_narrow_sat_s) DO_VMOVN(VQMOVN_U, gen_helper_neon_narrow_sat_u) + +static bool trans_VSHLL(DisasContext *s, arg_2misc *a) +{ + TCGv_i32 rm0, rm1; + TCGv_i64 rd; + static NeonGenWidenFn * const widenfns[] =3D { + gen_helper_neon_widen_u8, + gen_helper_neon_widen_u16, + tcg_gen_extu_i32_i64, + NULL, + }; + NeonGenWidenFn *widenfn =3D widenfns[a->size]; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vd & 1) { + return false; + } + + if (!widenfn) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + rd =3D tcg_temp_new_i64(); + + rm0 =3D neon_load_reg(a->vm, 0); + rm1 =3D neon_load_reg(a->vm, 1); + + widenfn(rd, rm0); + tcg_gen_shli_i64(rd, rd, 8 << a->size); + neon_store_reg64(rd, a->vd); + widenfn(rd, rm1); + tcg_gen_shli_i64(rd, rd, 8 << a->size); + neon_store_reg64(rd, a->vd + 1); + + tcg_temp_free_i64(rd); + tcg_temp_free_i32(rm0); + tcg_temp_free_i32(rm1); + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 8ecae264e15..94d5e34fff4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2975,26 +2975,6 @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t= 1) tcg_temp_free_i32(rd); } =20 -static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, i= nt u) -{ - if (u) { - switch (size) { - case 0: gen_helper_neon_widen_u8(dest, src); break; - case 1: gen_helper_neon_widen_u16(dest, src); break; - case 2: tcg_gen_extu_i32_i64(dest, src); break; - default: abort(); - } - } else { - switch (size) { - case 0: gen_helper_neon_widen_s8(dest, src); break; - case 1: gen_helper_neon_widen_s16(dest, src); break; - case 2: tcg_gen_ext_i32_i64(dest, src); break; - default: abort(); - } - } - tcg_temp_free_i32(src); -} - /* Symbolic constants for op fields for Neon 2-register miscellaneous. * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B * table A7-13. @@ -4946,6 +4926,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_2RM_VUZP: case NEON_2RM_VZIP: case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: + case NEON_2RM_VSHLL: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -4961,20 +4942,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) goto elementwise; } break; - case NEON_2RM_VSHLL: - if (q || (rd & 1)) { - return 1; - } - tmp =3D neon_load_reg(rm, 0); - tmp2 =3D neon_load_reg(rm, 1); - for (pass =3D 0; pass < 2; pass++) { - if (pass =3D=3D 1) - tmp =3D tmp2; - gen_neon_widen(cpu_V0, tmp, size, 1); - tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size); - neon_store_reg64(cpu_V0, rd + pass); - } - break; case NEON_2RM_VCVT_F16_F32: { TCGv_ptr fpst; --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592327521; cv=none; d=zohomail.com; s=zohoarc; b=bdnU4RzKSYGEnD1vydvaJDBSMEN0xFV2MCrFJN/kbAjALc60z3UOCroy2me5XdK2zsWt+zIbiRM+K8AC+gPPaMvTa2Lvv2cLGXV6P3KGhUJ2uwR6wVyc75ymyHAvykDoiveCeukzf3lQxrp/dky3FQU3rYniqg/9fDh9Jjs5OFk= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y80sm5263216wmc.34.2020.06.16.10.08.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 10:08:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9Sp05zSviKK/vex9tstJEZpczFuX6qw9ndOqIxUFQRg=; b=gCbxYBdAGWZ+mXkZAWZFO3kyxY2u0IO+FMn/5EZoKKIgUXRU0V7qgFP0MJpox7XOJq BkXqe8e8FPzapEQVnVJGoujWwPVr7FkEXIpSqY8vuFB9zUxi4a9oU5MEUH3EcOYeX5df xyHPWipBAvYaWKfdplxJwIoxZOjfmPAdonZEh6ku20/EMs6uXWbGe8J4dkNKz+Ce9J0Y Tlm/5+WJ+eFhM/AQfJASZDoxPTENIFDStdZlC30D80tz+kERRjuVotJm1JtkXOLTchoA PsQS5LVjYuRh7mtIlDaKshKaCSLr7RMcjePz1ZOWy8c+ivhaIMXXMgjjKT8lbZ9hcVJV sXKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9Sp05zSviKK/vex9tstJEZpczFuX6qw9ndOqIxUFQRg=; b=c/EWtSzXsDx7kYwOrjeCnCyh3lK3iESLim/ZqOJPDt+Bm+RzpFeA1CC713d9D2O6od gm0R5VumuKHE+Ld6a0itBU4IN4kgTNxPcO/KDMrPDe64wdVwJpovxBi3EsDshhpdg3Os cw3Kb8SAo/cvEgDjzY+7dZaIVV/k47akgzc3hwSnKPEAhJKAefkLpxazHKjvVlyx2ovX 9qd3IBCYgs4/oetFfRWtqRl4gRdSbwhOD+p0V7BSSevBbfjyvCjjqZM5ZwhnYy8KAaOw lobTPnHQkL5cAZYRTt15FUn1F97o4KYD2rQhs07H5n/DI8sZ5eCAV3CNOKaTZiwX4bcT 4K0w== X-Gm-Message-State: AOAM530GBbHQ8B+op9T+UDXw6T1Rnw6vphcrbIW+1saEU+YHOXfaS4+k gpa6xa9OebZDL+i7c4UMFj4eO5EAhqStvQ== X-Google-Smtp-Source: ABdhPJzg/tqdIjApk9oeRvJ2zGNr6ihY/bxf0jIntTNO7vMhGM46ohLuQ8s0zhmHWR6SZZgHd39RHQ== X-Received: by 2002:a5d:5449:: with SMTP id w9mr4147375wrv.106.1592327336310; Tue, 16 Jun 2020 10:08:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/21] target/arm: Convert Neon VCVT f16/f32 insns to decodetree Date: Tue, 16 Jun 2020 18:08:29 +0100 Message-Id: <20200616170844.13318-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200616170844.13318-1-peter.maydell@linaro.org> References: <20200616170844.13318-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon insns in the 2-reg-misc group which are VCVT between f32 and f16 to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 3 ++ target/arm/translate-neon.inc.c | 96 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 65 ++-------------------- 3 files changed, 102 insertions(+), 62 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 0102aa7254b..8174f2f92f4 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -461,6 +461,9 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm VQMOVN_U 1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0 =20 VSHLL 1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0 + + VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0 + VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0 ] =20 # Subgroup for size !=3D 0b11 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 78239ec1c1b..d37be597cf4 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3354,3 +3354,99 @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *= a) tcg_temp_free_i32(rm1); return true; } + +static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a) +{ + TCGv_ptr fpst; + TCGv_i32 ahp, tmp, tmp2, tmp3; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || + !dc_isar_feature(aa32_fp16_spconv, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm & 1) || (a->size !=3D 1)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(true); + ahp =3D get_ahp_flag(); + tmp =3D neon_load_reg(a->vm, 0); + gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); + tmp2 =3D neon_load_reg(a->vm, 1); + gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); + tcg_gen_shli_i32(tmp2, tmp2, 16); + tcg_gen_or_i32(tmp2, tmp2, tmp); + tcg_temp_free_i32(tmp); + tmp =3D neon_load_reg(a->vm, 2); + gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); + tmp3 =3D neon_load_reg(a->vm, 3); + neon_store_reg(a->vd, 0, tmp2); + gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); + tcg_gen_shli_i32(tmp3, tmp3, 16); + tcg_gen_or_i32(tmp3, tmp3, tmp); + neon_store_reg(a->vd, 1, tmp3); + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); + + return true; +} + +static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) +{ + TCGv_ptr fpst; + TCGv_i32 ahp, tmp, tmp2, tmp3; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || + !dc_isar_feature(aa32_fp16_spconv, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vd & 1) || (a->size !=3D 1)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(true); + ahp =3D get_ahp_flag(); + tmp3 =3D tcg_temp_new_i32(); + tmp =3D neon_load_reg(a->vm, 0); + tmp2 =3D neon_load_reg(a->vm, 1); + tcg_gen_ext16u_i32(tmp3, tmp); + gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); + neon_store_reg(a->vd, 0, tmp3); + tcg_gen_shri_i32(tmp, tmp, 16); + gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); + neon_store_reg(a->vd, 1, tmp); + tmp3 =3D tcg_temp_new_i32(); + tcg_gen_ext16u_i32(tmp3, tmp2); + gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); + neon_store_reg(a->vd, 2, tmp3); + tcg_gen_shri_i32(tmp2, tmp2, 16); + gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); + neon_store_reg(a->vd, 3, tmp2); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); + + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 94d5e34fff4..1ea09695546 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4860,7 +4860,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) int pass; int u; int vec_size; - TCGv_i32 tmp, tmp2, tmp3; + TCGv_i32 tmp, tmp2; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return 1; @@ -4927,6 +4927,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_2RM_VZIP: case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: case NEON_2RM_VSHLL: + case NEON_2RM_VCVT_F16_F32: + case NEON_2RM_VCVT_F32_F16: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -4942,67 +4944,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) goto elementwise; } break; - case NEON_2RM_VCVT_F16_F32: - { - TCGv_ptr fpst; - TCGv_i32 ahp; - - if (!dc_isar_feature(aa32_fp16_spconv, s) || - q || (rm & 1)) { - return 1; - } - fpst =3D get_fpstatus_ptr(true); - ahp =3D get_ahp_flag(); - tmp =3D neon_load_reg(rm, 0); - gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); - tmp2 =3D neon_load_reg(rm, 1); - gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); - tcg_gen_shli_i32(tmp2, tmp2, 16); - tcg_gen_or_i32(tmp2, tmp2, tmp); - tcg_temp_free_i32(tmp); - tmp =3D neon_load_reg(rm, 2); - gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); - tmp3 =3D neon_load_reg(rm, 3); - neon_store_reg(rd, 0, tmp2); - gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); - tcg_gen_shli_i32(tmp3, tmp3, 16); - tcg_gen_or_i32(tmp3, tmp3, tmp); - neon_store_reg(rd, 1, tmp3); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(ahp); - tcg_temp_free_ptr(fpst); - break; - } - case NEON_2RM_VCVT_F32_F16: - { - TCGv_ptr fpst; - TCGv_i32 ahp; - if (!dc_isar_feature(aa32_fp16_spconv, s) || - q || (rd & 1)) { - return 1; - } - fpst =3D get_fpstatus_ptr(true); - ahp =3D get_ahp_flag(); - tmp3 =3D tcg_temp_new_i32(); - tmp =3D neon_load_reg(rm, 0); - tmp2 =3D neon_load_reg(rm, 1); - tcg_gen_ext16u_i32(tmp3, tmp); - gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); - neon_store_reg(rd, 0, tmp3); - tcg_gen_shri_i32(tmp, tmp, 16); - gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); - neon_store_reg(rd, 1, tmp); - tmp3 =3D tcg_temp_new_i32(); - tcg_gen_ext16u_i32(tmp3, tmp2); - gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); - neon_store_reg(rd, 2, tmp3); - tcg_gen_shri_i32(tmp2, tmp2, 16); - gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); - neon_store_reg(rd, 3, tmp2); - tcg_temp_free_i32(ahp); - tcg_temp_free_ptr(fpst); - break; - } case NEON_2RM_AESE: case NEON_2RM_AESMC: if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) { return 1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert to decodetree the insns in the Neon 2-reg-misc grouping which we implement using gvec. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 11 +++++++ target/arm/translate-neon.inc.c | 55 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 35 +++++---------------- 3 files changed, 74 insertions(+), 27 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 8174f2f92f4..b5692070d62 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -447,9 +447,20 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0= . op:1 1 .... @1reg_imm VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc =20 + VMVN 1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc + VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc VPADAL_U 1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc =20 + VCGT0 1111 001 11 . 11 .. 01 .... 0 0000 . . 0 .... @2misc + VCGE0 1111 001 11 . 11 .. 01 .... 0 0001 . . 0 .... @2misc + VCEQ0 1111 001 11 . 11 .. 01 .... 0 0010 . . 0 .... @2misc + VCLE0 1111 001 11 . 11 .. 01 .... 0 0011 . . 0 .... @2misc + VCLT0 1111 001 11 . 11 .. 01 .... 0 0100 . . 0 .... @2misc + + VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc + VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc + VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc =20 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index d37be597cf4..d80123514c2 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3450,3 +3450,58 @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_= 2misc *a) =20 return true; } + +static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn) +{ + int vec_size =3D a->q ? 16 : 8; + int rd_ofs =3D neon_reg_offset(a->vd, 0); + int rm_ofs =3D neon_reg_offset(a->vm, 0); + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->size =3D=3D 3) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fn(a->size, rd_ofs, rm_ofs, vec_size, vec_size); + + return true; +} + +#define DO_2MISC_VEC(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + return do_2misc_vec(s, a, FN); \ + } + +DO_2MISC_VEC(VNEG, tcg_gen_gvec_neg) +DO_2MISC_VEC(VABS, tcg_gen_gvec_abs) +DO_2MISC_VEC(VCEQ0, gen_gvec_ceq0) +DO_2MISC_VEC(VCGT0, gen_gvec_cgt0) +DO_2MISC_VEC(VCLE0, gen_gvec_cle0) +DO_2MISC_VEC(VCGE0, gen_gvec_cge0) +DO_2MISC_VEC(VCLT0, gen_gvec_clt0) + +static bool trans_VMVN(DisasContext *s, arg_2misc *a) +{ + if (a->size !=3D 0) { + return false; + } + return do_2misc_vec(s, a, tcg_gen_gvec_not); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 1ea09695546..0f0741a37bc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4859,7 +4859,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) int size; int pass; int u; - int vec_size; TCGv_i32 tmp, tmp2; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -4883,7 +4882,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) VFP_DREG_D(rd, insn); VFP_DREG_M(rm, insn); size =3D (insn >> 20) & 3; - vec_size =3D q ? 16 : 8; rd_ofs =3D neon_reg_offset(rd, 0); rm_ofs =3D neon_reg_offset(rm, 0); =20 @@ -4929,6 +4927,14 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) case NEON_2RM_VSHLL: case NEON_2RM_VCVT_F16_F32: case NEON_2RM_VCVT_F32_F16: + case NEON_2RM_VMVN: + case NEON_2RM_VNEG: + case NEON_2RM_VABS: + case NEON_2RM_VCEQ0: + case NEON_2RM_VCGT0: + case NEON_2RM_VCLE0: + case NEON_2RM_VCGE0: + case NEON_2RM_VCLT0: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -4989,31 +4995,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) q ? gen_helper_crypto_sha256su0 : gen_helper_crypto_sha1su1); break; - case NEON_2RM_VMVN: - tcg_gen_gvec_not(0, rd_ofs, rm_ofs, vec_size, vec_size= ); - break; - case NEON_2RM_VNEG: - tcg_gen_gvec_neg(size, rd_ofs, rm_ofs, vec_size, vec_s= ize); - break; - case NEON_2RM_VABS: - tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_s= ize); - break; - - case NEON_2RM_VCEQ0: - gen_gvec_ceq0(size, rd_ofs, rm_ofs, vec_size, vec_size= ); - break; - case NEON_2RM_VCGT0: - gen_gvec_cgt0(size, rd_ofs, rm_ofs, vec_size, vec_size= ); - break; - case NEON_2RM_VCLE0: - gen_gvec_cle0(size, rd_ofs, rm_ofs, vec_size, vec_size= ); - break; - case NEON_2RM_VCGE0: - gen_gvec_cge0(size, rd_ofs, rm_ofs, vec_size, vec_size= ); - break; - case NEON_2RM_VCLT0: - gen_gvec_clt0(size, rd_ofs, rm_ofs, vec_size, vec_size= ); - break; =20 default: elementwise: --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592327728; cv=none; d=zohomail.com; s=zohoarc; b=PBy/sjIMxZCS2UkJaVKQ81Q6S1wjU2ygMxCl2sh/RQi19Z6KRMLeByfBw/8AWb2d8+6kXPCjO9hJkZF/q2L+HlXtN/iu7KKEXSonn5JmWGtyjVoUxjiwERSGYGxzMA13QoC9zuT/dV0G8wp22BS/bJjdDDeaJQxtAVkCvAiAwzM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592327728; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kP44X+T+Jfw2C1rlZJnvqC8xIudFDMP5KRrffXuNTsw=; b=i+VS0bRV2gZyiMiHjkkZ688DWN8AgB5gOBJ6aPCxMmwgbyAaQEeTPgaKi0aumRn59damOQS4MEzMJKdhBuHntPZVAGfjBijUGCTMgzg2CH4Q8UzNmsLhQoQiOe91bJ5JpEDk+EfHqTUhxoUf0XEPfJmCmlCEvqnGz6iwNcqhaJU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592327728917806.6309223005321; Tue, 16 Jun 2020 10:15:28 -0700 (PDT) Received: from localhost ([::1]:60248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlFBH-0000Kb-HW for importer@patchew.org; Tue, 16 Jun 2020 13:15:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF54-0001K3-Dp for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:02 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:39566) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF52-0007TL-8I for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:02 -0400 Received: by mail-wr1-x442.google.com with SMTP id t18so21579170wru.6 for ; Tue, 16 Jun 2020 10:08:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon-2-reg misc crypto ops (AESE, AESMC, SHA1H, SHA1SU1) to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 12 ++++++++ target/arm/translate-neon.inc.c | 42 ++++++++++++++++++++++++++ target/arm/translate.c | 52 +++------------------------------ 3 files changed, 58 insertions(+), 48 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index b5692070d62..86b1b9e34bf 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -441,12 +441,19 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 = 0 . op:1 1 .... @1reg_imm &2misc vm=3D%vm_dp vd=3D%vd_dp @2misc_q0 .... ... .. . .. size:2 .. .... . .... . . . .... \ &2misc vm=3D%vm_dp vd=3D%vd_dp q=3D0 + @2misc_q1 .... ... .. . .. size:2 .. .... . .... . . . .... \ + &2misc vm=3D%vm_dp vd=3D%vd_dp q=3D1 =20 VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc =20 VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc =20 + AESE 1111 001 11 . 11 .. 00 .... 0 0110 0 . 0 .... @2misc_q1 + AESD 1111 001 11 . 11 .. 00 .... 0 0110 1 . 0 .... @2misc_q1 + AESMC 1111 001 11 . 11 .. 00 .... 0 0111 0 . 0 .... @2misc_q1 + AESIMC 1111 001 11 . 11 .. 00 .... 0 0111 1 . 0 .... @2misc_q1 + VMVN 1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc =20 VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc @@ -458,6 +465,8 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm VCLE0 1111 001 11 . 11 .. 01 .... 0 0011 . . 0 .... @2misc VCLT0 1111 001 11 . 11 .. 01 .... 0 0100 . . 0 .... @2misc =20 + SHA1H 1111 001 11 . 11 .. 01 .... 0 0101 1 . 0 .... @2misc_q1 + VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc =20 @@ -473,6 +482,9 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm =20 VSHLL 1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0 =20 + SHA1SU1 1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1 + SHA256SU0 1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1 + VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0 VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0 ] diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index d80123514c2..5e2cd18bf71 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3505,3 +3505,45 @@ static bool trans_VMVN(DisasContext *s, arg_2misc *a) } return do_2misc_vec(s, a, tcg_gen_gvec_not); } + +#define WRAP_2M_3_OOL_FN(WRAPNAME, FUNC, DATA) \ + static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \ + uint32_t rm_ofs, uint32_t oprsz, \ + uint32_t maxsz) \ + { \ + tcg_gen_gvec_3_ool(rd_ofs, rd_ofs, rm_ofs, oprsz, maxsz, \ + DATA, FUNC); \ + } + +#define WRAP_2M_2_OOL_FN(WRAPNAME, FUNC, DATA) \ + static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \ + uint32_t rm_ofs, uint32_t oprsz, \ + uint32_t maxsz) \ + { \ + tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, oprsz, maxsz, DATA, FUNC); \ + } + +WRAP_2M_3_OOL_FN(gen_AESE, gen_helper_crypto_aese, 0) +WRAP_2M_3_OOL_FN(gen_AESD, gen_helper_crypto_aese, 1) +WRAP_2M_2_OOL_FN(gen_AESMC, gen_helper_crypto_aesmc, 0) +WRAP_2M_2_OOL_FN(gen_AESIMC, gen_helper_crypto_aesmc, 1) +WRAP_2M_2_OOL_FN(gen_SHA1H, gen_helper_crypto_sha1h, 0) +WRAP_2M_2_OOL_FN(gen_SHA1SU1, gen_helper_crypto_sha1su1, 0) +WRAP_2M_2_OOL_FN(gen_SHA256SU0, gen_helper_crypto_sha256su0, 0) + +#define DO_2M_CRYPTO(INSN, FEATURE, SIZE) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + if (!dc_isar_feature(FEATURE, s) || a->size !=3D SIZE) { \ + return false; \ + } \ + return do_2misc_vec(s, a, gen_##INSN); \ + } + +DO_2M_CRYPTO(AESE, aa32_aes, 0) +DO_2M_CRYPTO(AESD, aa32_aes, 0) +DO_2M_CRYPTO(AESMC, aa32_aes, 0) +DO_2M_CRYPTO(AESIMC, aa32_aes, 0) +DO_2M_CRYPTO(SHA1H, aa32_sha1, 2) +DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2) +DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0f0741a37bc..38644995ab2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4855,7 +4855,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) { int op; int q; - int rd, rm, rd_ofs, rm_ofs; + int rd, rm; int size; int pass; int u; @@ -4882,8 +4882,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) VFP_DREG_D(rd, insn); VFP_DREG_M(rm, insn); size =3D (insn >> 20) & 3; - rd_ofs =3D neon_reg_offset(rd, 0); - rm_ofs =3D neon_reg_offset(rm, 0); =20 if ((insn & (1 << 23)) =3D=3D 0) { /* Three register same length: handled by decodetree */ @@ -4935,6 +4933,9 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_2RM_VCLE0: case NEON_2RM_VCGE0: case NEON_2RM_VCLT0: + case NEON_2RM_AESE: case NEON_2RM_AESMC: + case NEON_2RM_SHA1H: + case NEON_2RM_SHA1SU1: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -4950,51 +4951,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) goto elementwise; } break; - case NEON_2RM_AESE: case NEON_2RM_AESMC: - if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) { - return 1; - } - /* - * Bit 6 is the lowest opcode bit; it distinguishes - * between encryption (AESE/AESMC) and decryption - * (AESD/AESIMC). - */ - if (op =3D=3D NEON_2RM_AESE) { - tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd), - vfp_reg_offset(true, rd), - vfp_reg_offset(true, rm), - 16, 16, extract32(insn, 6, 1), - gen_helper_crypto_aese); - } else { - tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd), - vfp_reg_offset(true, rm), - 16, 16, extract32(insn, 6, 1), - gen_helper_crypto_aesmc); - } - break; - case NEON_2RM_SHA1H: - if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1))= { - return 1; - } - tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0, - gen_helper_crypto_sha1h); - break; - case NEON_2RM_SHA1SU1: - if ((rm | rd) & 1) { - return 1; - } - /* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */ - if (q) { - if (!dc_isar_feature(aa32_sha2, s)) { - return 1; - } - } else if (!dc_isar_feature(aa32_sha1, s)) { - return 1; - } - tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0, - q ? gen_helper_crypto_sha256su0 - : gen_helper_crypto_sha1su1); - break; =20 default: elementwise: --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592327872; cv=none; d=zohomail.com; s=zohoarc; b=iRqLeal4iEXG+61bS2tRkg+3vD6lVwDDYAcK6ZSJ7xYi6Spj6p/MU35jLhOEloAfn0q3VkYj2e+80XldD7Cly4Xpf/fBJKMQD7RwJs0F+87Z+eV2RgYhH1I2dkF8FOtJ90Tuay5qQWkt3T9l7OCEUSP4v41Z6vSTnfI6tRlQAd4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592327872; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y80sm5263216wmc.34.2020.06.16.10.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 10:08:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AhFkiGFNXdst6Xbi7nbMnw/kboTQarT4OU0u4/cvDkU=; b=YX2/l1yY+lY0w6SdYempW6wtkUJVCVhyvNDxltxec/OgDv83sra5Au5Y8+q3WJ728J sX7erYahfTsS8J1Gt5faQfL7dk9WH8YIlrHyMJNlR2rohySaQQgx8Ozodck8NRU55dn4 XtfqASHTD5pnfagh8f2wkLu2V7F1jS2vJ8JLRKkAEUSi73QCOHD8xFhSzest6bi6suyQ yuXqp/sVeK03G2Cko+eJ5QS2+JUBOhXY6uDkVUgVH6vV01KU2kXVJFkgPNxMybvkdUW0 82UU3W/f2a+TWXwo5nyfGaq2CLk3sRlrAq6IJj1qk7QEK6Zyvk3p8Lusw6MhY1ZFACcp isyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AhFkiGFNXdst6Xbi7nbMnw/kboTQarT4OU0u4/cvDkU=; b=CKPrbtKQMiA0/XXWL9uSj7punQQZR0GsOPxXsYwCi2z8/uOQtA1qd22JPKj/fq9ymq GuQ5neEyJl84cl/6GrOkMtrFTvAdYU3FFiM36LqkrrOBrbGhFGRydvTvORSWLDNZ279e +cpLgoDgkc/kAzZCQx4D92Ja/2vzf2RtYdiW8T42lF406rvWgji9w8cnxBeuMKiU6EnB e3K9R2OIyyY/3zPdPLqpkfYGgYvqn8WYZ5KEJ8P36vEwZ8S6KzOY+xjFclLHMaECbB4Z D2ju/KutK5p9OoCozlITKgqmhZJP1pmhI0wPxBJBOU8QNJAd6TnrKHVT6+77Dm1DCUi5 qkPg== X-Gm-Message-State: AOAM533Soiywv6txiZyBWRXtBAFnPVcPK1XZsEXXr/2e1tJjdY3qxNr2 cr4CCQd3enI3N9CtJ3lUAfTO/Q== X-Google-Smtp-Source: ABdhPJwcYSj4iucJavVtSz4BkIXpldWL6WnRCdfVnqfeNKiDuX4Zrfu51PKon9hu2938J7xBoHMbwA== X-Received: by 2002:a1c:60d6:: with SMTP id u205mr4462949wmb.163.1592327339742; Tue, 16 Jun 2020 10:08:59 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/21] target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFn Date: Tue, 16 Jun 2020 18:08:32 +0100 Message-Id: <20200616170844.13318-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200616170844.13318-1-peter.maydell@linaro.org> References: <20200616170844.13318-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The NeonGenOneOpFn typedef breaks with the pattern of the other NeonGen*Fn typedefs, because it is a TCGv_i64 -> TCGv_i64 operation but it does not have '64' in its name. Rename it to NeonGenOne64OpFn, so that the old name is available for a TCGv_i32 -> TCGv_i32 operation (which we will need in a subsequent commit). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.h | 2 +- target/arm/translate-a64.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 62ed5c4780c..35218b3fdf1 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -374,7 +374,7 @@ typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); -typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); +typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64); typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a0e72ad6942..7cb5fbfba80 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11917,8 +11917,8 @@ static void handle_2misc_pairwise(DisasContext *s, = int opcode, bool u, } else { for (pass =3D 0; pass < maxpass; pass++) { TCGv_i64 tcg_op =3D tcg_temp_new_i64(); - NeonGenOneOpFn *genfn; - static NeonGenOneOpFn * const fns[2][2] =3D { + NeonGenOne64OpFn *genfn; + static NeonGenOne64OpFn * const fns[2][2] =3D { { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 }, { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 }, }; --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592327633; cv=none; d=zohomail.com; s=zohoarc; b=bwf8u16dDAjFFWILtaSrI+mD4dQa+H+Kb8WqjQ6jMEdtIvYOAkHXxsMtV4vmd1MkcyAh0fhsfbex0/Wccc6IzdgXrWs32xLZEn72JBnBhSQ1ImF676R8A1TYoS303Mz3HxyPEiuUHWGm/BmwubARoDCNc4VyDouH5L+ykrKCk+w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592327633; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h9ltt+F4LrKZIkRTSNT6mJTq1A3I28QBdjW3sTZLEvk=; b=cW0VhgZe8N27z+YTyo2mWPOm5/eA1eWvn72JE/o7B5XlC5LNB9XUpcKZy9FAYQJos5EC6+UEqdcnCOEQoT6sxZwnVC+Fw4UB4q0SFzaxcfpRacFEFJ8MnTxXzei6til4hKdOXnhCGibkfwnjufj9PDRIRW/8dF0Ct/MFisDyucw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592327633319316.6703537132379; Tue, 16 Jun 2020 10:13:53 -0700 (PDT) Received: from localhost ([::1]:53372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlF9k-0004CT-1S for importer@patchew.org; Tue, 16 Jun 2020 13:13:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47018) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF56-0001P3-Cc for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:04 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:56191) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF54-0007UK-Dl for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:03 -0400 Received: by mail-wm1-x344.google.com with SMTP id c71so3576678wmd.5 for ; Tue, 16 Jun 2020 10:09:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y80sm5263216wmc.34.2020.06.16.10.08.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 10:09:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h9ltt+F4LrKZIkRTSNT6mJTq1A3I28QBdjW3sTZLEvk=; b=p9qwFqvqdF4EuWaXu52rQ/2ZxpI6yMZX7WlO4H3HlSTKuoP5JzwS+VfEt2KC2AyLEy /6XLQwMly4t6JfyuN2v48ChaRzKSx4qy8HvhmEDl+PNxYy1HEZgIIuGcv+td5nMwPiwm Ni3bZQugLqQFYFqwb4BaxRgKCYW64So4ip6R/+xzcAFj92gFyDH50X9AvLhRnZtUD96b XH1o9jZZQPfzi/EKhEaIwbJXwy6N+gSnMRknlFfzQ0R5JUYWLVFhxOxA02v/XgfhRxc7 wIMXj0x3DV7OFwEuOm2Z8tNkrpQlRFwntWy/UH5yEqO0U+pHEeN7EeoVq9nM73Q0BluL lyKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h9ltt+F4LrKZIkRTSNT6mJTq1A3I28QBdjW3sTZLEvk=; b=Ddc+3NOWXeSI35W4xJ7Ee/oIcu1r4Hb49RYz+RGRSlrT9A5PFQFooBtsMkBAg/9diq qZc5ujx2VblmnP92M8xFbzlFHhtqPN1FrRAz0e3s4YjN/+c/i85lt/nHX9c5s/svjWnL aRzro3wQ7OoHJP8jNQvRFX2MTGHeoYA3TSI7jEam1UgPNsepjTsY+q0N4E2JAT3QQgRc 47giur7t/kmxS30rXld8DwzTlAbq3Ndty/Qiiy+uYYiaLTMNxDXLuYt7OaL+HCFmlyf0 VOruXIPSuGPGZ6S5MpI3HApU6+K11szuz6WfQBamG32sN9zgU7oq/FuG7qxDzf9I+RRb X3dQ== X-Gm-Message-State: AOAM533cChhqH7dPVZbujiNGzf6oYj2ZXWaJ07d2RNucjcBmqFQfdl4h K1u6jkNXYLFroV7lb0e+yQX+mw== X-Google-Smtp-Source: ABdhPJxQREB7/zxRhmsRFlaXtyN/5AYK1szEwzmhHOdBQYzcmc7eL3QLy3pLEhrrMWNjM7ZcwyTnmA== X-Received: by 2002:a05:600c:4410:: with SMTP id u16mr4205349wmn.88.1592327340993; Tue, 16 Jun 2020 10:09:00 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/21] target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefs Date: Tue, 16 Jun 2020 18:08:33 +0100 Message-Id: <20200616170844.13318-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200616170844.13318-1-peter.maydell@linaro.org> References: <20200616170844.13318-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" All the other typedefs like these spell "Op" with a lowercase 'p'; remane the NeonGenTwoSingleOPFn and NeonGenTwoDoubleOPFn typedefs to match. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.h | 4 ++-- target/arm/translate-a64.c | 4 ++-- target/arm/translate-neon.inc.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 35218b3fdf1..467c5291101 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -372,8 +372,8 @@ typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); -typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); -typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); +typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); +typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64); typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7cb5fbfba80..12040984981 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9534,7 +9534,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, i= nt opcode, TCGv_i64 tcg_op =3D tcg_temp_new_i64(); TCGv_i64 tcg_zero =3D tcg_const_i64(0); TCGv_i64 tcg_res =3D tcg_temp_new_i64(); - NeonGenTwoDoubleOPFn *genfn; + NeonGenTwoDoubleOpFn *genfn; bool swap =3D false; int pass; =20 @@ -9576,7 +9576,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, i= nt opcode, TCGv_i32 tcg_op =3D tcg_temp_new_i32(); TCGv_i32 tcg_zero =3D tcg_const_i32(0); TCGv_i32 tcg_res =3D tcg_temp_new_i32(); - NeonGenTwoSingleOPFn *genfn; + NeonGenTwoSingleOpFn *genfn; bool swap =3D false; int pass, maxpasses; =20 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 5e2cd18bf71..c39443c8cae 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1664,7 +1664,7 @@ static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2r= eg_shift *a) } =20 static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, - NeonGenTwoSingleOPFn *fn) + NeonGenTwoSingleOpFn *fn) { /* FP operations in 2-reg-and-shift group */ TCGv_i32 tmp, shiftv; --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592328004; cv=none; d=zohomail.com; s=zohoarc; b=OvB6uzXMfN62b4OLbzj0V0EYIDcmLCF9sD2OPWcVqCmpXSeijIObGDSm50gdcrZDWrOemQLI4FL8UFtK6jkX53nSiONAVbJokcy0idXRRaa2UKSMOxhfeObgl8alao14RCnVfrjjnT7e4YKCHy3db43kqnVESTPIs+pnryRcy7A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592328004; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7LajX6MigHB41GQ8EUoLxZbQvXk12YJJTXi7/b1pm8I=; b=bvfc5zVn6/iTqESC2R7no7tYaR7bXLqH8J6VBuE//CsfBUFVF7LAhKNa0VbbD8BM9cfdlA1I/BDPrClgPWKCbHxKLHJsBT/jQNPqsfYveFAZdTKk8Esuzfs29+tRw5VmMdKk8OsOnkRimeSb2fhVPxI4r2dox1ZE0WTNmHQJpjg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592328004103688.0627097693354; Tue, 16 Jun 2020 10:20:04 -0700 (PDT) Received: from localhost ([::1]:51188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlFFi-0008TB-Gy for importer@patchew.org; Tue, 16 Jun 2020 13:20:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF57-0001S3-B4 for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:05 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:33610) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF55-0007Uh-Dd for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:04 -0400 Received: by mail-wr1-x441.google.com with SMTP id l11so21577827wru.0 for ; Tue, 16 Jun 2020 10:09:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y80sm5263216wmc.34.2020.06.16.10.09.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 10:09:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7LajX6MigHB41GQ8EUoLxZbQvXk12YJJTXi7/b1pm8I=; b=IG8cbs/tjzQOL7NuXNYgazP4L0BqzXhTAGCSn26mxKUwoTfxPsX4k0wGgTkQfzimfS tf6ScVYyYbevZPvQ0cLW52Cd+T/GdKtDjCn4le/7G/WL9eNgnosOWBZ4EdsfaU77Okan vcQ+dj43pjhOImPJjquB24P1LCjBiOU6lrDj7+idrCBd2nMJzfNkVUdsD6A0TcNtehNQ EbukkZ0cE/Cl5FjV7cQoEFvIPz198wDd7OEKmnhNt1AdwZoZv6xDL3k3ViB9XSRQTUV8 cUSyaOR06ZDCZ0b+sBoPn81ppU4YtWyazGqSLZ3JfjcoSIrBuSPKVxc/gz7oQgOiRHIw bOvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7LajX6MigHB41GQ8EUoLxZbQvXk12YJJTXi7/b1pm8I=; b=M+UVFbG+KZyQP2FhyTZ16mlwhTtQLd+TEVDjxrPtwsuaPvzjLhdrnJke/oJUy/t14H Jh90hETz5n6Zv7pMIUdJj5X6RueVXIktxoLzj3XoDwjj/blRlV/d3vF1QK9vqu6w3Ybe 7I5bVQ6rIhA5T2jX8JKbSkLmiACD3att28mRWmDJ5fiPOFVi+PolRFOgMNqvKnY2q7AE qB+xep/JqzYIA3JiBCZt2KlTM33bgWE7PwyCp6lVZj2k9WK544A/Vvki8uzacy1v/ipm AR97bOnpfkw3gUYRxx23wVzHMTs/C4QZlFdYjKYxJyDVsne7kVpQEI/D3mU9k/WTcjZv vImw== X-Gm-Message-State: AOAM533T5cEac5xiTJ9zdOIzFANI5sy7+VA94cdpNcvex+KV5ggm14j5 8kr9imfBsrqqj1rXVYokN4pesg== X-Google-Smtp-Source: ABdhPJyHcAIWSOnAmjBIqCBz8xN65TKkCD29RzerGPYBIxO1/KrkzgNl4X32whF5dxvfCe+UWM0wqQ== X-Received: by 2002:a05:6000:7:: with SMTP id h7mr4368917wrx.55.1592327341941; Tue, 16 Jun 2020 10:09:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/21] target/arm: Make gen_swap_half() take separate src and dest Date: Tue, 16 Jun 2020 18:08:34 +0100 Message-Id: <20200616170844.13318-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200616170844.13318-1-peter.maydell@linaro.org> References: <20200616170844.13318-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Make gen_swap_half() take a source and destination TCGv_i32 rather than modifying the input TCGv_i32; we're going to want to be able to use it with the more flexible function signature, and this also brings it into line with other functions like gen_rev16() and gen_revsh(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-neon.inc.c | 2 +- target/arm/translate.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index c39443c8cae..4967e974386 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3007,7 +3007,7 @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 = *a) tcg_gen_bswap32_i32(tmp[half], tmp[half]); break; case 1: - gen_swap_half(tmp[half]); + gen_swap_half(tmp[half], tmp[half]); break; case 2: break; diff --git a/target/arm/translate.c b/target/arm/translate.c index 38644995ab2..64b18a95b64 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -378,9 +378,9 @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) } =20 /* Swap low and high halfwords. */ -static void gen_swap_half(TCGv_i32 var) +static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var) { - tcg_gen_rotri_i32(var, var, 16); + tcg_gen_rotri_i32(dest, var, 16); } =20 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. @@ -4960,7 +4960,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_2RM_VREV32: switch (size) { case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_swap_half(tmp); break; + case 1: gen_swap_half(tmp, tmp); break; default: abort(); } break; @@ -8046,7 +8046,7 @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bo= ol m_swap, bool sub) t1 =3D load_reg(s, a->rn); t2 =3D load_reg(s, a->rm); if (m_swap) { - gen_swap_half(t2); + gen_swap_half(t2, t2); } gen_smul_dual(t1, t2); =20 @@ -8104,7 +8104,7 @@ static bool op_smlald(DisasContext *s, arg_rrrr *a, b= ool m_swap, bool sub) t1 =3D load_reg(s, a->rn); t2 =3D load_reg(s, a->rm); if (m_swap) { - gen_swap_half(t2); + gen_swap_half(t2, t2); } gen_smul_dual(t1, t2); =20 --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592327745; cv=none; d=zohomail.com; s=zohoarc; b=nUFvZps62U1M1lpaO+0iIwwGptehjjDSmFz90SDMd1voAcgCCuqDhRPQzNHSpPIXM7bPmmWIYcGzbYMskndsWm/w7Ce0YrSCm0nivUWYkVu0jv602tXH/oPizADDserXR7lTnRxPAHBUYkiJrSN8co8ojNyZFSRbxUjIzsBknLs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592327745; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MMCxjLv+7WRojX6ZDXGB9ezsqw5NM5e5KUtfRRuMaFY=; b=RL9gFpyqRdw/l/K+BFuT9Chb9EVNt5jnFCm0pxX86pKQPhgFYr295w6Jt7lhF3O26N/EJDFwyWBADsUu/moJobe/rTVEYCinw9IqrXqMjO+e1UybJgf1VFnPKXVEXioAlVzD4OwI8OGFvRwzg1r4qzaWpHlcG3yGSoP7GBS1bFc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592327745871692.1065755249666; Tue, 16 Jun 2020 10:15:45 -0700 (PDT) Received: from localhost ([::1]:33554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlFBY-00010b-7S for importer@patchew.org; Tue, 16 Jun 2020 13:15:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47088) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF58-0001Ur-Ar for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:06 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:39566) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF56-0007V7-Cp for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:06 -0400 Received: by mail-wr1-x441.google.com with SMTP id t18so21579375wru.6 for ; Tue, 16 Jun 2020 10:09:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VREV32 and VREV16 insns in the Neon 2-reg-misc group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.h | 1 + target/arm/neon-dp.decode | 2 ++ target/arm/translate-neon.inc.c | 55 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 12 ++----- 4 files changed, 60 insertions(+), 10 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 467c5291101..4dbeee4c89f 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -363,6 +363,7 @@ typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, u= int32_t, uint32_t, uint32_t, uint32_t); =20 /* Function prototype for gen_ functions for calling Neon helpers */ +typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32); typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 86b1b9e34bf..0a791af46c8 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -445,6 +445,8 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm &2misc vm=3D%vm_dp vd=3D%vd_dp q=3D1 =20 VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc + VREV32 1111 001 11 . 11 .. 00 .... 0 0001 . . 0 .... @2misc + VREV16 1111 001 11 . 11 .. 00 .... 0 0010 . . 0 .... @2misc =20 VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 4967e974386..0a779980d01 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3547,3 +3547,58 @@ DO_2M_CRYPTO(AESIMC, aa32_aes, 0) DO_2M_CRYPTO(SHA1H, aa32_sha1, 2) DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2) DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2) + +static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) +{ + int pass; + + /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (!fn) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { + TCGv_i32 tmp =3D neon_load_reg(a->vm, pass); + fn(tmp, tmp); + neon_store_reg(a->vd, pass, tmp); + } + + return true; +} + +static bool trans_VREV32(DisasContext *s, arg_2misc *a) +{ + static NeonGenOneOpFn * const fn[] =3D { + tcg_gen_bswap32_i32, + gen_swap_half, + NULL, + NULL, + }; + return do_2misc(s, a, fn[a->size]); +} + +static bool trans_VREV16(DisasContext *s, arg_2misc *a) +{ + if (a->size !=3D 0) { + return false; + } + return do_2misc(s, a, gen_rev16); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 64b18a95b64..5b50eddd111 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4936,6 +4936,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_2RM_AESE: case NEON_2RM_AESMC: case NEON_2RM_SHA1H: case NEON_2RM_SHA1SU1: + case NEON_2RM_VREV32: + case NEON_2RM_VREV16: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -4957,16 +4959,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) for (pass =3D 0; pass < (q ? 4 : 2); pass++) { tmp =3D neon_load_reg(rm, pass); switch (op) { - case NEON_2RM_VREV32: - switch (size) { - case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_swap_half(tmp, tmp); break; - default: abort(); - } - break; - case NEON_2RM_VREV16: - gen_rev16(tmp, tmp); - break; case NEON_2RM_VCLS: switch (size) { case 0: gen_helper_neon_cls_s8(tmp, tmp); brea= k; --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592327633; cv=none; d=zohomail.com; s=zohoarc; b=RwCAJc18XVFyNkKOgBAAWlCKDhyiIt+wn7V2+PLKxfC06sCMsoVTHCjWeTQMhI3Yy1os2UL4UnjiZZY1kFMz2Gci3vEqmJkivl9j40T93kzezUftV33du9OqbMQGBgqxKn2x7j6HQ4EHDTHK+MoyqaQjt75vWbG7p1w25sK6MuQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592327633; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8XDNy5i8wbkQg//M5D1t/pjF6TQt81ktgOCgLPl1lf0=; b=drMfKoPh5ERqplh4oXod2cCtRUtJYGWO/n0ak+okwzpuzsbSoJXru1kzMHUAv59q/KkFnUscbLVZ6VrdelZEhy+t37SsftP3hTSngruQ3MJiq1LTByE5hrIldoFJrtq4d6m3SX49KzSngZksn1lHnh7S5GYHEB/v5eYInmbyAsc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592327633700416.21820705174116; Tue, 16 Jun 2020 10:13:53 -0700 (PDT) Received: from localhost ([::1]:53336 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlF9k-0004AR-D1 for importer@patchew.org; Tue, 16 Jun 2020 13:13:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47132) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF59-0001Yt-PY for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:07 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:38624) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF57-0007VZ-Gr for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:07 -0400 Received: by mail-wm1-x343.google.com with SMTP id f185so3870951wmf.3 for ; Tue, 16 Jun 2020 10:09:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y80sm5263216wmc.34.2020.06.16.10.09.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 10:09:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8XDNy5i8wbkQg//M5D1t/pjF6TQt81ktgOCgLPl1lf0=; b=Zsnf2wvsUL0ndcXwl4QKpWumgeoZ+jdzcdfrYKh9jNN+r86q32I/KRoLD+lyS6F3hq vRugjdK3Cf8Jk9Hjphr2KXKqQJWOwfu9LHXgGkg5CVd0IFhVvUwQ+k6jlkStlJdpTGGA iYkTPif00YYwfRaQMvUXDze5DxGCYjTw/zIhh9qFHia3PdSLoubyus2fFEoES102skZ2 FpO7LD2RPX8ytXTsBX7e6eqS1OPsktai3Iyb+/CV9pI6YKe57YMRKthn7turMDn0yFMB ax3q0mPRABqCm1TbIwAZI7HW3Rm2A5l7L0JkEe8LcMeAtAm+2MdlrKG8gYNm06IPhOi6 vStw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8XDNy5i8wbkQg//M5D1t/pjF6TQt81ktgOCgLPl1lf0=; b=HF3bD6yEN/jD7RmYIcxLanJuIDMHTc9SIUresOrfLVB94+AY/W114LCVyqXAewD69w SIjUCHC+L+YIGoLHEsNSAtIj8qualEV7fzr8r+ucUMGEjZSUy8uLGMwJ2hyOEEsAFCFo KnfZLF0Jn3oWNZnV0Ql2sLFS6zZ5eqJUKVDVNTPFteloD7VxJ8ni6V11CEk/eOadqJyC mc6YrAEjOEYpPfD7udqupi0I1+0Pam6EZt7rdY2/7zFidsT5JehEuOKqUDZ6Xr9IqqlT 6CdRSWaEpH5W+A7cJwjh+rgicahXrHAdL1MXfbd62/7MoA+jXMaz/mvPwxGXNS7+Z7sw IHxg== X-Gm-Message-State: AOAM532CW6KLl3qb2QPK9xwVa+y6Q1HEY0lxNfFy88nJ2FaVTxOKdJyw wH25YCGbzFLN6cpdPP85IbWa1Mxcv+j9Hw== X-Google-Smtp-Source: ABdhPJy9akmWc6qGJuzf59wYQZv3l4ghUM8uB62e8VPEHV1TBLjMXYSp4C0thwV737qMCKm0c+eBMQ== X-Received: by 2002:a05:600c:4146:: with SMTP id h6mr4400459wmm.170.1592327344098; Tue, 16 Jun 2020 10:09:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 13/21] target/arm: Convert remaining simple 2-reg-misc Neon ops Date: Tue, 16 Jun 2020 18:08:36 +0100 Message-Id: <20200616170844.13318-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200616170844.13318-1-peter.maydell@linaro.org> References: <20200616170844.13318-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the remaining ops in the Neon 2-reg-misc group which can be implemented simply with our do_2misc() helper. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 10 +++++ target/arm/translate-neon.inc.c | 69 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 38 ++++-------------- 3 files changed, 86 insertions(+), 31 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 0a791af46c8..f947f7d09f0 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -456,6 +456,10 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0= . op:1 1 .... @1reg_imm AESMC 1111 001 11 . 11 .. 00 .... 0 0111 0 . 0 .... @2misc_q1 AESIMC 1111 001 11 . 11 .. 00 .... 0 0111 1 . 0 .... @2misc_q1 =20 + VCLS 1111 001 11 . 11 .. 00 .... 0 1000 . . 0 .... @2misc + VCLZ 1111 001 11 . 11 .. 00 .... 0 1001 . . 0 .... @2misc + VCNT 1111 001 11 . 11 .. 00 .... 0 1010 . . 0 .... @2misc + VMVN 1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc =20 VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc @@ -472,6 +476,9 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc =20 + VABS_F 1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc + VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc + VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc =20 @@ -489,6 +496,9 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm =20 VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0 VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0 + + VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc + VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc ] =20 # Subgroup for size !=3D 0b11 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 0a779980d01..336c2b312eb 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3602,3 +3602,72 @@ static bool trans_VREV16(DisasContext *s, arg_2misc = *a) } return do_2misc(s, a, gen_rev16); } + +static bool trans_VCLS(DisasContext *s, arg_2misc *a) +{ + static NeonGenOneOpFn * const fn[] =3D { + gen_helper_neon_cls_s8, + gen_helper_neon_cls_s16, + gen_helper_neon_cls_s32, + NULL, + }; + return do_2misc(s, a, fn[a->size]); +} + +static void do_VCLZ_32(TCGv_i32 rd, TCGv_i32 rm) +{ + tcg_gen_clzi_i32(rd, rm, 32); +} + +static bool trans_VCLZ(DisasContext *s, arg_2misc *a) +{ + static NeonGenOneOpFn * const fn[] =3D { + gen_helper_neon_clz_u8, + gen_helper_neon_clz_u16, + do_VCLZ_32, + NULL, + }; + return do_2misc(s, a, fn[a->size]); +} + +static bool trans_VCNT(DisasContext *s, arg_2misc *a) +{ + if (a->size !=3D 0) { + return false; + } + return do_2misc(s, a, gen_helper_neon_cnt_u8); +} + +static bool trans_VABS_F(DisasContext *s, arg_2misc *a) +{ + if (a->size !=3D 2) { + return false; + } + /* TODO: FP16 : size =3D=3D 1 */ + return do_2misc(s, a, gen_helper_vfp_abss); +} + +static bool trans_VNEG_F(DisasContext *s, arg_2misc *a) +{ + if (a->size !=3D 2) { + return false; + } + /* TODO: FP16 : size =3D=3D 1 */ + return do_2misc(s, a, gen_helper_vfp_negs); +} + +static bool trans_VRECPE(DisasContext *s, arg_2misc *a) +{ + if (a->size !=3D 2) { + return false; + } + return do_2misc(s, a, gen_helper_recpe_u32); +} + +static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a) +{ + if (a->size !=3D 2) { + return false; + } + return do_2misc(s, a, gen_helper_rsqrte_u32); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 5b50eddd111..17373743889 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4938,6 +4938,13 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) case NEON_2RM_SHA1SU1: case NEON_2RM_VREV32: case NEON_2RM_VREV16: + case NEON_2RM_VCLS: + case NEON_2RM_VCLZ: + case NEON_2RM_VCNT: + case NEON_2RM_VABS_F: + case NEON_2RM_VNEG_F: + case NEON_2RM_VRECPE: + case NEON_2RM_VRSQRTE: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -4959,25 +4966,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) for (pass =3D 0; pass < (q ? 4 : 2); pass++) { tmp =3D neon_load_reg(rm, pass); switch (op) { - case NEON_2RM_VCLS: - switch (size) { - case 0: gen_helper_neon_cls_s8(tmp, tmp); brea= k; - case 1: gen_helper_neon_cls_s16(tmp, tmp); bre= ak; - case 2: gen_helper_neon_cls_s32(tmp, tmp); bre= ak; - default: abort(); - } - break; - case NEON_2RM_VCLZ: - switch (size) { - case 0: gen_helper_neon_clz_u8(tmp, tmp); brea= k; - case 1: gen_helper_neon_clz_u16(tmp, tmp); bre= ak; - case 2: tcg_gen_clzi_i32(tmp, tmp, 32); break; - default: abort(); - } - break; - case NEON_2RM_VCNT: - gen_helper_neon_cnt_u8(tmp, tmp); - break; case NEON_2RM_VQABS: switch (size) { case 0: @@ -5051,12 +5039,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tcg_temp_free_ptr(fpstatus); break; } - case NEON_2RM_VABS_F: - gen_helper_vfp_abss(tmp, tmp); - break; - case NEON_2RM_VNEG_F: - gen_helper_vfp_negs(tmp, tmp); - break; case NEON_2RM_VSWP: tmp2 =3D neon_load_reg(rd, pass); neon_store_reg(rm, pass, tmp2); @@ -5137,12 +5119,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tcg_temp_free_ptr(fpst); break; } - case NEON_2RM_VRECPE: - gen_helper_recpe_u32(tmp, tmp); - break; - case NEON_2RM_VRSQRTE: - gen_helper_rsqrte_u32(tmp, tmp); - break; case NEON_2RM_VRECPE_F: { TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592328100; cv=none; d=zohomail.com; s=zohoarc; b=En+gjyAw/vOZtZDmr17SRDRJ7WWmWXpHPDI4YYJN3jnjw0lF3C24uo7o/uYXr+nH7l2acKng+kM02xkWBst8A+R6bNqif8VapYWbg3FB08aqY3ySAbyOF8kmoQyNF1TPqwLbvw7L77RRoJq76GsstF0pgRmTzaN1lPjAgOlv/z4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592328100; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q+0uZHHdicr4FHXDVL/N22V2qnJh66s6U25qsKc1zpA=; b=go1kLBqry45324b6Z8LaiFG0d3L8uD1dABlFMxjfgCP1ZPmUy4rrAr+P4zPlVIw9SUHktj/mhr4QBHXjoQCXbl6/JAH/XJWDu/cAbSKWsisRjbC+Pe9ud1q9U7KCXwjpwh9sbd1nfTfgzFbRf8s8pAQqKFSsWBPKjrbLwnHgPIM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592328100733995.5013168148321; Tue, 16 Jun 2020 10:21:40 -0700 (PDT) Received: from localhost ([::1]:57242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlFHG-0002eF-Eh for importer@patchew.org; Tue, 16 Jun 2020 13:21:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF5A-0001bc-Qk for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:08 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:41074) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF58-0007Vy-R9 for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:08 -0400 Received: by mail-wr1-x444.google.com with SMTP id j10so21555893wrw.8 for ; Tue, 16 Jun 2020 10:09:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y80sm5263216wmc.34.2020.06.16.10.09.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 10:09:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q+0uZHHdicr4FHXDVL/N22V2qnJh66s6U25qsKc1zpA=; b=P4//LCdpdE9XCKe56D5wKz06ioLvBJCQMZNlJg6Ac1VLLt7iLP7jGbEqovNw44Zi0L QCfZaemXs8gYIU4IBAuxtig5RTyIdJKoAoBzxsoqCb38pBlRjAGYgqbuUivDJ9b/5lWw ytmLfcVptE5Xk2PmIOvoFxJG7VRxJklD+zGGOme26i1CuP95gQJhaaRk1UX6GA2KYNKH C2Bzx2dsC3vJ1xSjqjMqNnk9hkBt1T0mC9W8PLgLIXMgNxouc8uLeSnR0u0+v9mlhwXy Eyi9i4BthXf50oiL/9y3YtyAPjQBfCkCQZtrcyRPLuWcdSfrLdyX8CfH5Bl6NyIDcSME RPGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q+0uZHHdicr4FHXDVL/N22V2qnJh66s6U25qsKc1zpA=; b=tErdQdvRi65RsTqG39vBB5Ko9txfy1Ov656TVy7jVCJHIJTAT5m5r3MVh7CCtbqLWg BYhprAiD9ovjq9Wcj3RNIn13BOgurnv/1T0O7jYfrbZ2UIj4v4qGzPQUyR/SI0TG1ojE nHWl3aiDHzLSNSJ8Vt8dzTTjRa5WThHU5VlXx1cVs+/Q3dRBWFFKVG2z0FDtvI/fSu/c 8MyfP2yQkVQ61nfVNpSWnynA2DZBz/JH9Fba6CJbEARTyAEHXW3OLesfZGS1+WjkTijv yYmSoD/75XLYQj7eKFFO308HJH/upOTx6/VL48MQyuBWMHWefF4kkCtyLC+HJSnzWHQG CFXw== X-Gm-Message-State: AOAM530ZbjDXFXML54aCtJ2ZOKQZDqqVkNl2FEjhi330hGaaubUVYts6 wEqo89lrdK+PxcqOOtLQZ6WXIQ== X-Google-Smtp-Source: ABdhPJwkBb0rKqoP9zU5qygAGrKvCGNx49KPaIhw9ZXER17JrbXAuE+i/VCboA3o8vbheD9NpTtw/Q== X-Received: by 2002:adf:a18b:: with SMTP id u11mr4046191wru.102.1592327345499; Tue, 16 Jun 2020 10:09:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 14/21] target/arm: Convert Neon VQABS, VQNEG to decodetree Date: Tue, 16 Jun 2020 18:08:37 +0100 Message-Id: <20200616170844.13318-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200616170844.13318-1-peter.maydell@linaro.org> References: <20200616170844.13318-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon VQABS and VQNEG insns to decodetree. Since these are the only ones which need cpu_env passing to the helper, we wrap the helper rather than creating a whole new do_2misc_env() function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 3 +++ target/arm/translate-neon.inc.c | 35 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 30 ++-------------------------- 3 files changed, 40 insertions(+), 28 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index f947f7d09f0..f0bb34a49eb 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -465,6 +465,9 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc VPADAL_U 1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc =20 + VQABS 1111 001 11 . 11 .. 00 .... 0 1110 . . 0 .... @2misc + VQNEG 1111 001 11 . 11 .. 00 .... 0 1111 . . 0 .... @2misc + VCGT0 1111 001 11 . 11 .. 01 .... 0 0000 . . 0 .... @2misc VCGE0 1111 001 11 . 11 .. 01 .... 0 0001 . . 0 .... @2misc VCEQ0 1111 001 11 . 11 .. 01 .... 0 0010 . . 0 .... @2misc diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 336c2b312eb..2b5dc86f628 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3671,3 +3671,38 @@ static bool trans_VRSQRTE(DisasContext *s, arg_2misc= *a) } return do_2misc(s, a, gen_helper_rsqrte_u32); } + +#define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \ + static void WRAPNAME(TCGv_i32 d, TCGv_i32 m) \ + { \ + FUNC(d, cpu_env, m); \ + } + +WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8) +WRAP_1OP_ENV_FN(gen_VQABS_s16, gen_helper_neon_qabs_s16) +WRAP_1OP_ENV_FN(gen_VQABS_s32, gen_helper_neon_qabs_s32) +WRAP_1OP_ENV_FN(gen_VQNEG_s8, gen_helper_neon_qneg_s8) +WRAP_1OP_ENV_FN(gen_VQNEG_s16, gen_helper_neon_qneg_s16) +WRAP_1OP_ENV_FN(gen_VQNEG_s32, gen_helper_neon_qneg_s32) + +static bool trans_VQABS(DisasContext *s, arg_2misc *a) +{ + static NeonGenOneOpFn * const fn[] =3D { + gen_VQABS_s8, + gen_VQABS_s16, + gen_VQABS_s32, + NULL, + }; + return do_2misc(s, a, fn[a->size]); +} + +static bool trans_VQNEG(DisasContext *s, arg_2misc *a) +{ + static NeonGenOneOpFn * const fn[] =3D { + gen_VQNEG_s8, + gen_VQNEG_s16, + gen_VQNEG_s32, + NULL, + }; + return do_2misc(s, a, fn[a->size]); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 17373743889..3cbd2ab0c96 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4945,6 +4945,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_2RM_VNEG_F: case NEON_2RM_VRECPE: case NEON_2RM_VRSQRTE: + case NEON_2RM_VQABS: + case NEON_2RM_VQNEG: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -4966,34 +4968,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) for (pass =3D 0; pass < (q ? 4 : 2); pass++) { tmp =3D neon_load_reg(rm, pass); switch (op) { - case NEON_2RM_VQABS: - switch (size) { - case 0: - gen_helper_neon_qabs_s8(tmp, cpu_env, tmp); - break; - case 1: - gen_helper_neon_qabs_s16(tmp, cpu_env, tmp= ); - break; - case 2: - gen_helper_neon_qabs_s32(tmp, cpu_env, tmp= ); - break; - default: abort(); - } - break; - case NEON_2RM_VQNEG: - switch (size) { - case 0: - gen_helper_neon_qneg_s8(tmp, cpu_env, tmp); - break; - case 1: - gen_helper_neon_qneg_s16(tmp, cpu_env, tmp= ); - break; - case 2: - gen_helper_neon_qneg_s32(tmp, cpu_env, tmp= ); - break; - default: abort(); - } - break; case NEON_2RM_VCGT0_F: { TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592327550; cv=none; d=zohomail.com; s=zohoarc; b=J/aPkaxuKkQy1600KvgygHQeiOebpN1UvuGxK/2myyyvwoE/5WyWDwJrlRJ/9tNJ0TGlOz0Rdc4bC3n6/heLU2AerY7xGV8E+BZPBOY2cO73YFUYeUyreYuHX09inXJrPgykXQrMfPE1+VvcNbowFFhIDRJ0DZTorjHyvWPgH9w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592327550; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3ljny7kzY5+YovQYIFcaKIcwx9fioEhuEMYRzUduLVQ=; b=nIfg8AzLqixHRmakOr/fGZJ9AF8H83vdMtkyKvjLdnP1T3Znc3HDkh47c0ztKMD/mca9vT7ATviMMsxoObLY4w7KySqNxiBgv5hnHIR8J4NOcEnW9ZqsgkHY8wCYmfNVdZEgYXou9h6xJZyRxYpOc+lk/3YieCoelU88bXihI94= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592327550830491.090220127153; Tue, 16 Jun 2020 10:12:30 -0700 (PDT) Received: from localhost ([::1]:46394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlF8P-0000WR-Ct for importer@patchew.org; Tue, 16 Jun 2020 13:12:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47190) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF5C-0001fI-8Z for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:10 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:38845) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF5A-0007WN-3T for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:09 -0400 Received: by mail-wr1-x442.google.com with SMTP id e1so21601532wrt.5 for ; Tue, 16 Jun 2020 10:09:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y80sm5263216wmc.34.2020.06.16.10.09.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 10:09:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3ljny7kzY5+YovQYIFcaKIcwx9fioEhuEMYRzUduLVQ=; b=E9h7OuHP3xwxQw3+24QWfnLj09s1OSr0wfLf7NZmWcv7YnZhKML8bxljocuN2YSkCy mU+5ym0qoKs3OawUJHrd25oiIIublERjKW1UzdZos5ZFvm3f8U6DBlt5U+fJWFyZHsWm 2FyKly86SiFLp0psT8vPAB4VFn/iXoIS/rTh3aVxVHks4JcoJTegfLfjq+nwb9bUUpcJ LaletovLZBg03qEZE1GNm5sU6cKYNUYk9U3FpAXoYW3FSDGZEcjPRa0An7jjW+QJBkDr enwvhD9ecCuLjyPSEkCnoUMrOGv8iXHDaBNWoRT/PjvI07MNE6c7B+OkbzC+uEXW7pUk rO2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3ljny7kzY5+YovQYIFcaKIcwx9fioEhuEMYRzUduLVQ=; b=rrYBueFEqyjVifPnpRgIrL+PnIhvijQm/P+sTrC0bSaH0JiiYtksdQybMrpvqAIMW9 ZV+GxcCUrsntnRZCkE6axL1ZMVPqsCbvEXlaph/geyxGvKiuy7oTNs4y20yKPdOw+Kgg h9TveusiGqMj4hQONk0Ayc9vTyKXCJuIlHju8zFrIZm55SIKqlMiJpso9g6LwAuD+n9x MCUOrvi4G+u2h2DlzzadbnREFMBpMS7nX8m2DK/9bwV0XDROMfy4xb6dMv+CgfABWuZw PaJpomjFL/vfSWUWYGrp/dX2WT1Xu2uePJ7zFa35boPpkOl+qEPVSUrvZ4L+W6A0QT/a xGPA== X-Gm-Message-State: AOAM531c0rsCLAnMgF0b0dzGmXzadSe/qMhrnDViWQdAFt3Fculz4oZ3 5aX7LNdcjx4VEYkeND3pRs7oV2yuA8kp7A== X-Google-Smtp-Source: ABdhPJwl7y+DFeJT4nuuMOrakKAvvJTBpfd+L4IhYWB/ZVAQPmCbTEUrG9KMDYNQ5YE89p1KKdJUjA== X-Received: by 2002:adf:9404:: with SMTP id 4mr3952334wrq.367.1592327346680; Tue, 16 Jun 2020 10:09:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 15/21] target/arm: Convert simple fp Neon 2-reg-misc insns Date: Tue, 16 Jun 2020 18:08:38 +0100 Message-Id: <20200616170844.13318-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200616170844.13318-1-peter.maydell@linaro.org> References: <20200616170844.13318-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon 2-reg-misc insns which are implemented with simple calls to functions that take the input, output and fpstatus pointer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.h | 1 + target/arm/neon-dp.decode | 8 +++++ target/arm/translate-neon.inc.c | 62 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 56 ++++------------------------- 4 files changed, 78 insertions(+), 49 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 4dbeee4c89f..19650a9e2d7 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -373,6 +373,7 @@ typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); +typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr); typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64); diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index f0bb34a49eb..ea8d5fd99c3 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -497,11 +497,19 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 = 0 . op:1 1 .... @1reg_imm SHA1SU1 1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1 SHA256SU0 1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1 =20 + VRINTX 1111 001 11 . 11 .. 10 .... 0 1001 . . 0 .... @2misc + VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0 VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0 =20 VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc + VRECPE_F 1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc + VRSQRTE_F 1111 001 11 . 11 .. 11 .... 0 1011 . . 0 .... @2misc + VCVT_FS 1111 001 11 . 11 .. 11 .... 0 1100 . . 0 .... @2misc + VCVT_FU 1111 001 11 . 11 .. 11 .... 0 1101 . . 0 .... @2misc + VCVT_SF 1111 001 11 . 11 .. 11 .... 0 1110 . . 0 .... @2misc + VCVT_UF 1111 001 11 . 11 .. 11 .... 0 1111 . . 0 .... @2misc ] =20 # Subgroup for size !=3D 0b11 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 2b5dc86f628..ab183e47d7d 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3706,3 +3706,65 @@ static bool trans_VQNEG(DisasContext *s, arg_2misc *= a) }; return do_2misc(s, a, fn[a->size]); } + +static bool do_2misc_fp(DisasContext *s, arg_2misc *a, + NeonGenOneSingleOpFn *fn) +{ + int pass; + TCGv_ptr fpst; + + /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->size !=3D 2) { + /* TODO: FP16 will be the size =3D=3D 1 case */ + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(1); + for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { + TCGv_i32 tmp =3D neon_load_reg(a->vm, pass); + fn(tmp, tmp, fpst); + neon_store_reg(a->vd, pass, tmp); + } + tcg_temp_free_ptr(fpst); + + return true; +} + +#define DO_2MISC_FP(INSN, FUNC) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + return do_2misc_fp(s, a, FUNC); \ + } + +DO_2MISC_FP(VRECPE_F, gen_helper_recpe_f32) +DO_2MISC_FP(VRSQRTE_F, gen_helper_rsqrte_f32) +DO_2MISC_FP(VCVT_FS, gen_helper_vfp_sitos) +DO_2MISC_FP(VCVT_FU, gen_helper_vfp_uitos) +DO_2MISC_FP(VCVT_SF, gen_helper_vfp_tosizs) +DO_2MISC_FP(VCVT_UF, gen_helper_vfp_touizs) + +static bool trans_VRINTX(DisasContext *s, arg_2misc *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + return do_2misc_fp(s, a, gen_helper_rints_exact); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 3cbd2ab0c96..48377860c75 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4947,6 +4947,13 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) case NEON_2RM_VRSQRTE: case NEON_2RM_VQABS: case NEON_2RM_VQNEG: + case NEON_2RM_VRECPE_F: + case NEON_2RM_VRSQRTE_F: + case NEON_2RM_VCVT_FS: + case NEON_2RM_VCVT_FU: + case NEON_2RM_VCVT_SF: + case NEON_2RM_VCVT_UF: + case NEON_2RM_VRINTX: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -5052,13 +5059,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tcg_temp_free_i32(tcg_rmode); break; } - case NEON_2RM_VRINTX: - { - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); - gen_helper_rints_exact(tmp, tmp, fpstatus); - tcg_temp_free_ptr(fpstatus); - break; - } case NEON_2RM_VCVTAU: case NEON_2RM_VCVTAS: case NEON_2RM_VCVTNU: @@ -5093,48 +5093,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tcg_temp_free_ptr(fpst); break; } - case NEON_2RM_VRECPE_F: - { - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); - gen_helper_recpe_f32(tmp, tmp, fpstatus); - tcg_temp_free_ptr(fpstatus); - break; - } - case NEON_2RM_VRSQRTE_F: - { - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); - gen_helper_rsqrte_f32(tmp, tmp, fpstatus); - tcg_temp_free_ptr(fpstatus); - break; - } - case NEON_2RM_VCVT_FS: /* VCVT.F32.S32 */ - { - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); - gen_helper_vfp_sitos(tmp, tmp, fpstatus); - tcg_temp_free_ptr(fpstatus); - break; - } - case NEON_2RM_VCVT_FU: /* VCVT.F32.U32 */ - { - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); - gen_helper_vfp_uitos(tmp, tmp, fpstatus); - tcg_temp_free_ptr(fpstatus); - break; - } - case NEON_2RM_VCVT_SF: /* VCVT.S32.F32 */ - { - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); - gen_helper_vfp_tosizs(tmp, tmp, fpstatus); - tcg_temp_free_ptr(fpstatus); - break; - } - case NEON_2RM_VCVT_UF: /* VCVT.U32.F32 */ - { - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); - gen_helper_vfp_touizs(tmp, tmp, fpstatus); - tcg_temp_free_ptr(fpstatus); - break; - } default: /* Reserved op values were caught by the * neon_2rm_sizes[] check earlier. --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592327666; cv=none; d=zohomail.com; s=zohoarc; b=BfSjz9FK5nEU146kTlYfMWs4BXpW1bHXL9c1wpqhcCEs7vnf37X3ZNVyQx98IsbOWruBYyivyGTPjvbR53Ti6BQTDuMb1oaXXYL2RxLR2v5WXTbqqKjR2zol6S/JSnNyQXESaBgW4LpFGeFt3PBerxRuzjQ89M6vx5OTeuFRUTs= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y80sm5263216wmc.34.2020.06.16.10.09.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 10:09:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vc9v4JyqM1J6J25K3IQzcyGCo39vD/Fqu6L0fttjfbs=; b=vk+F375cu6vxXYfkqADK6clbUJIeHvYlvuhzxt8zcEUTdd4wbzeOu2lWPN9WsUHG10 m7ElLOUbS84FhRAJ6fPsxTir2eJphk/f0FSkuRNYtAgSbTTfeG/bgZbYkMIvUa+BhG58 LA7Fl2P39q0+wQ6cXPcbBqqS0/clrG/6LA+ywQbDvN1Rb2k3nlztzRMYOjV+D0q8f2DK Qrq0N1dPi/at3GdXdJDnQiS/MR1bNMYukvHYyVimD26bloKJMseBDGfUHJyyCYnqGWHS 14srSKxxVSgqYBlZTSLm7Q6r4/kBH3dSthxoLl4AWQC+S+WNypWzC2oV9CC0LmSnZ7UI ZukA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vc9v4JyqM1J6J25K3IQzcyGCo39vD/Fqu6L0fttjfbs=; b=d9xx5Olk/fDf9NL0lSGtemlMsy9AVn09WxmdnEIVKjY9ZeVgSFQYcP7jP7LK2vQVjc LhutB5C70SKkXTFs/Jq1xq/XEzNbmiw5uKkKDHRo6LO1Hx67/e8FXqJMul3TBzD4bN8y gvE0owO1BLXjvowecAZZY1TEynsBCHyq8MwJf/jUqHo2xNgNZ3iWn16e6zwBml7JoI/Z K17CZKt8Hw1FEmj1Gtn/trqPPjpvgtZfwhjsSZnKXEl4Ri+8LBHRWXV2bG8MkLUhk1SX WwqjlB6z6DtMI7VgShTFCGgTjCulspqhzBSJmGAUiVrxwLq2/tCmWLDktqzMiXjjqYOv 9a+w== X-Gm-Message-State: AOAM533pcWHJDa0eK/Mzq6MKag0yV+LnNeJQm2KGrqOyIaK+8PH6HDHZ GbOioemTGYWLDPY1WiJhbWc3+w== X-Google-Smtp-Source: ABdhPJxQnwM2I2wYv1NOEySTTB59bg54jCqEGru20aCk8zMcVEJh0bQIrJ4QNwvWzJne0MbbFPu0SA== X-Received: by 2002:adf:e387:: with SMTP id e7mr4035291wrm.70.1592327347854; Tue, 16 Jun 2020 10:09:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 16/21] target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetree Date: Tue, 16 Jun 2020 18:08:39 +0100 Message-Id: <20200616170844.13318-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200616170844.13318-1-peter.maydell@linaro.org> References: <20200616170844.13318-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the fp-compare-with-zero insns in the Neon 2-reg-misc group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 6 ++++ target/arm/translate-neon.inc.c | 28 ++++++++++++++++++ target/arm/translate.c | 50 ++++----------------------------- 3 files changed, 39 insertions(+), 45 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index ea8d5fd99c3..c9acd00f1e8 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -479,6 +479,12 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0= . op:1 1 .... @1reg_imm VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc =20 + VCGT0_F 1111 001 11 . 11 .. 01 .... 0 1000 . . 0 .... @2misc + VCGE0_F 1111 001 11 . 11 .. 01 .... 0 1001 . . 0 .... @2misc + VCEQ0_F 1111 001 11 . 11 .. 01 .... 0 1010 . . 0 .... @2misc + VCLE0_F 1111 001 11 . 11 .. 01 .... 0 1011 . . 0 .... @2misc + VCLT0_F 1111 001 11 . 11 .. 01 .... 0 1100 . . 0 .... @2misc + VABS_F 1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc =20 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index ab183e47d7d..a62da21b152 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3768,3 +3768,31 @@ static bool trans_VRINTX(DisasContext *s, arg_2misc = *a) } return do_2misc_fp(s, a, gen_helper_rints_exact); } + +#define WRAP_FP_CMP0_FWD(WRAPNAME, FUNC) \ + static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \ + { \ + TCGv_i32 zero =3D tcg_const_i32(0); \ + FUNC(d, m, zero, fpst); \ + tcg_temp_free_i32(zero); \ + } +#define WRAP_FP_CMP0_REV(WRAPNAME, FUNC) \ + static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \ + { \ + TCGv_i32 zero =3D tcg_const_i32(0); \ + FUNC(d, zero, m, fpst); \ + tcg_temp_free_i32(zero); \ + } + +#define DO_FP_CMP0(INSN, FUNC, REV) \ + WRAP_FP_CMP0_##REV(gen_##INSN, FUNC) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + return do_2misc_fp(s, a, gen_##INSN); \ + } + +DO_FP_CMP0(VCGT0_F, gen_helper_neon_cgt_f32, FWD) +DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD) +DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD) +DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV) +DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV) diff --git a/target/arm/translate.c b/target/arm/translate.c index 48377860c75..dc98928856d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4954,6 +4954,11 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) case NEON_2RM_VCVT_SF: case NEON_2RM_VCVT_UF: case NEON_2RM_VRINTX: + case NEON_2RM_VCGT0_F: + case NEON_2RM_VCGE0_F: + case NEON_2RM_VCEQ0_F: + case NEON_2RM_VCLE0_F: + case NEON_2RM_VCLT0_F: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -4975,51 +4980,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) for (pass =3D 0; pass < (q ? 4 : 2); pass++) { tmp =3D neon_load_reg(rm, pass); switch (op) { - case NEON_2RM_VCGT0_F: - { - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); - tmp2 =3D tcg_const_i32(0); - gen_helper_neon_cgt_f32(tmp, tmp, tmp2, fpstat= us); - tcg_temp_free_i32(tmp2); - tcg_temp_free_ptr(fpstatus); - break; - } - case NEON_2RM_VCGE0_F: - { - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); - tmp2 =3D tcg_const_i32(0); - gen_helper_neon_cge_f32(tmp, tmp, tmp2, fpstat= us); - tcg_temp_free_i32(tmp2); - tcg_temp_free_ptr(fpstatus); - break; - } - case NEON_2RM_VCEQ0_F: - { - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); - tmp2 =3D tcg_const_i32(0); - gen_helper_neon_ceq_f32(tmp, tmp, tmp2, fpstat= us); - tcg_temp_free_i32(tmp2); - tcg_temp_free_ptr(fpstatus); - break; - } - case NEON_2RM_VCLE0_F: - { - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); - tmp2 =3D tcg_const_i32(0); - gen_helper_neon_cge_f32(tmp, tmp2, tmp, fpstat= us); - tcg_temp_free_i32(tmp2); - tcg_temp_free_ptr(fpstatus); - break; - } - case NEON_2RM_VCLT0_F: - { - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); - tmp2 =3D tcg_const_i32(0); - gen_helper_neon_cgt_f32(tmp, tmp2, tmp, fpstat= us); - tcg_temp_free_i32(tmp2); - tcg_temp_free_ptr(fpstatus); - break; - } case NEON_2RM_VSWP: tmp2 =3D neon_load_reg(rd, pass); neon_store_reg(rm, pass, tmp2); --=20 2.20.1 From nobody Sat Feb 7 05:53:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592328195; cv=none; d=zohomail.com; s=zohoarc; b=aoZNZKqkjPGDgkdglQUYzL32F4HcRQ85or71mYUqD2PahSuRP77RfCjqy3yul7m03oB7Qz1H7BlHBiCYOHuKBrWO3oqDQwD3GAPqzu01i0zQcDN3NI35iHjanb7xBREi9EIGFCc1oYSpdkszNzOzIGYr/D0RgVs3enoh0d8LG20= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592328195; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=t+BSTJ1xzvQLWxMKa/LhLilHEVnIMMztSbawWPlpCgs=; b=Kq/TQSbq9AXdbPEHDfIlkDrfQQg3Pg4SmPFg1e8Ss5wKewHRA6kOlsFm7cjv86X7ZT7pM1xHmHxSf16jeQXBvoNVySohl6nvushYZNjDODxucct1C8a2RToKmLC/adO+oVTJAbymSw5CmbOUBrxqiExQmFd2DhssvuVx8Jh0cG8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592328195323623.1500914626922; Tue, 16 Jun 2020 10:23:15 -0700 (PDT) Received: from localhost ([::1]:33786 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlFIo-0004cR-0b for importer@patchew.org; Tue, 16 Jun 2020 13:23:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF5E-0001nT-Td for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:12 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:34274) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF5C-0007YI-Pt for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:12 -0400 Received: by mail-wr1-x42a.google.com with SMTP id r7so21590613wro.1 for ; Tue, 16 Jun 2020 10:09:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y80sm5263216wmc.34.2020.06.16.10.09.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 10:09:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t+BSTJ1xzvQLWxMKa/LhLilHEVnIMMztSbawWPlpCgs=; b=et62m1m26kp0dyOIDiKiZeCePqla2FuE0M13lVM7RbLKf4ck3durjiDKzesfpFDSux 42RO2AxcKugZu0AquvvXH+PHzOTJJYkiQZ+0DhZuJYFFQAMTgstcE19U5YgACjUFGP6K 5cMKE6lCAH9BUErsCaXE8bZiCciPvVbPoHKUgXc7GcLTGUSyfhgiKy4vfhy2fQc53q7N cFO8E6oMrbJ0dfZpJtAYtVHvUeMHIj6obpQ5wLE53fCmEXlza9jOzlODkp1GKUcLBVw/ eGCkTqDVtnkDzFoNmZf5ukPhnHnAAz3vc9bzel028DaS/0QCqB5dBWUUteSmTReC/qfQ Bt8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t+BSTJ1xzvQLWxMKa/LhLilHEVnIMMztSbawWPlpCgs=; b=c38lbAL0vXaTSKfze2tA2E6UdqcYO3zwhOuHHlaka3RNQhGJgjySceb7HRX6zzDqm2 WVTTtpmhjI5dtyJu6LTQ1KYscfVbdMAoeK+OPHevBAB5yDzmcrBQSWjYGm3KxPigqJg6 AZiPm1wNkjegEmO9Gj3ifxi3veyRLJczO+0ORVai3kE+p+nRYfTVuHvlpkMaoYvQuYKX 1ZmzDzRDwaJ/IL3bSfMbDQTua/VnqahP4q3TpCDfEBcvZmC1mwO4RJKydeK6TLh4mGgz WAeqrbdOfrStQ4I9XSFlPzXixPGQ8UXyEhzJkueJEObfVMZq0+yIFjVxEgLgjJs28yUo xMyQ== X-Gm-Message-State: AOAM532viJZBqKed/0jfBBDQ8VzHpsmMLdk+8BQjilTek/Tfx0iBMmO1 vOqxyeB5YclBa0fNmoJpgpSq7A== X-Google-Smtp-Source: ABdhPJwl8nNcwIs89jzHmD155nKbC4QCOAJ+Wa/CIw0LFfpvBDejdiR95tEyqsid7tcd0M1rm5AjEg== X-Received: by 2002:a5d:4d89:: with SMTP id b9mr4354008wru.210.1592327349224; Tue, 16 Jun 2020 10:09:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 17/21] target/arm: Convert Neon 2-reg-misc VRINT insns to decodetree Date: Tue, 16 Jun 2020 18:08:40 +0100 Message-Id: <20200616170844.13318-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200616170844.13318-1-peter.maydell@linaro.org> References: <20200616170844.13318-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon 2-reg-misc VRINT insns to decodetree. Giving these insns their own do_vrint() function allows us to change the rounding mode just once at the start and end rather than doing it for every element in the vector. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 8 +++++ target/arm/translate-neon.inc.c | 61 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 31 +++-------------- 3 files changed, 74 insertions(+), 26 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index c9acd00f1e8..e0717c7e4a6 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -503,11 +503,19 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 = 0 . op:1 1 .... @1reg_imm SHA1SU1 1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1 SHA256SU0 1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1 =20 + VRINTN 1111 001 11 . 11 .. 10 .... 0 1000 . . 0 .... @2misc VRINTX 1111 001 11 . 11 .. 10 .... 0 1001 . . 0 .... @2misc + VRINTA 1111 001 11 . 11 .. 10 .... 0 1010 . . 0 .... @2misc + VRINTZ 1111 001 11 . 11 .. 10 .... 0 1011 . . 0 .... @2misc =20 VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0 + + VRINTM 1111 001 11 . 11 .. 10 .... 0 1101 . . 0 .... @2misc + VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0 =20 + VRINTP 1111 001 11 . 11 .. 10 .... 0 1111 . . 0 .... @2misc + VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc VRECPE_F 1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index a62da21b152..0e7f86ad156 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3796,3 +3796,64 @@ DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD) DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD) DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV) DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV) + +static bool do_vrint(DisasContext *s, arg_2misc *a, int rmode) +{ + /* + * Handle a VRINT* operation by iterating 32 bits at a time, + * with a specified rounding mode in operation. + */ + int pass; + TCGv_ptr fpst; + TCGv_i32 tcg_rmode; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->size !=3D 2) { + /* TODO: FP16 will be the size =3D=3D 1 case */ + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(1); + tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); + for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { + TCGv_i32 tmp =3D neon_load_reg(a->vm, pass); + gen_helper_rints(tmp, tmp, fpst); + neon_store_reg(a->vd, pass, tmp); + } + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_temp_free_i32(tcg_rmode); + tcg_temp_free_ptr(fpst); + + return true; +} + +#define DO_VRINT(INSN, RMODE) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + return do_vrint(s, a, RMODE); \ + } + +DO_VRINT(VRINTN, FPROUNDING_TIEEVEN) +DO_VRINT(VRINTA, FPROUNDING_TIEAWAY) +DO_VRINT(VRINTZ, FPROUNDING_ZERO) +DO_VRINT(VRINTM, FPROUNDING_NEGINF) +DO_VRINT(VRINTP, FPROUNDING_POSINF) diff --git a/target/arm/translate.c b/target/arm/translate.c index dc98928856d..61dfc3ae7af 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4959,6 +4959,11 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) case NEON_2RM_VCEQ0_F: case NEON_2RM_VCLE0_F: case NEON_2RM_VCLT0_F: + case NEON_2RM_VRINTN: + case NEON_2RM_VRINTA: + case NEON_2RM_VRINTM: + case NEON_2RM_VRINTP: + case NEON_2RM_VRINTZ: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -4993,32 +4998,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) } neon_store_reg(rm, pass, tmp2); break; - case NEON_2RM_VRINTN: - case NEON_2RM_VRINTA: - case NEON_2RM_VRINTM: - case NEON_2RM_VRINTP: - case NEON_2RM_VRINTZ: - { - TCGv_i32 tcg_rmode; - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); - int rmode; - - if (op =3D=3D NEON_2RM_VRINTZ) { - rmode =3D FPROUNDING_ZERO; - } else { - rmode =3D fp_decode_rm[((op & 0x6) >> 1) ^= 1]; - } - - tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rm= ode)); - gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, - cpu_env); - gen_helper_rints(tmp, tmp, fpstatus); - gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, - cpu_env); - tcg_temp_free_ptr(fpstatus); - tcg_temp_free_i32(tcg_rmode); - break; - } case NEON_2RM_VCVTAU: case NEON_2RM_VCVTAS: case NEON_2RM_VCVTNU: --=20 2.20.1 From nobody Sat Feb 7 05:53:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592327890; cv=none; d=zohomail.com; s=zohoarc; b=Qs2qDcziM1fCHVMtBxpMRp2+g0esKY+boiarVMbO6Mn5QAr537OuJe3F5S6nihkijGpYhmf8XLINohd/tMY8eqgBEfxLFhRB4YyPGP5d7lZbyEEoT1nT/FgmbXLmtIf8VxJPsxL/wSUhitsDqbcsXq1D/3goKqnVVeqLAIRIemM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592327890; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FPydNdOU0w28Pvpu0fq6kbDJFKInbAdeM0gPvhKG/v4=; b=B1eJzZ6HgzAxEpECWqBClQNSkN85w5GH7IEDlCMjoLiBfHDmtOzsiU4YNJV2yeJtOdv4zPXoQxzoIDDvx0vuUCmdOFn2AkEYwIeh3VyhmebeEAG4z/nZTYuISlqod0LDVn99XQzpHY+l/hlQ9+o/2xi7mvu5u6ua2ls/FAbZl+g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592327890501239.1185029978169; Tue, 16 Jun 2020 10:18:10 -0700 (PDT) Received: from localhost ([::1]:43342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlFDs-0005Ef-OF for importer@patchew.org; Tue, 16 Jun 2020 13:18:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47296) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF5H-0001rf-92 for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:15 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:39226) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF5E-0007Yk-13 for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:14 -0400 Received: by mail-wr1-x42d.google.com with SMTP id t18so21579719wru.6 for ; Tue, 16 Jun 2020 10:09:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VCVT instructions in the 2-reg-misc grouping to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 9 +++++ target/arm/translate-neon.inc.c | 70 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 70 ++++----------------------------- 3 files changed, 87 insertions(+), 62 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index e0717c7e4a6..5507c3e4623 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -516,6 +516,15 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0= . op:1 1 .... @1reg_imm =20 VRINTP 1111 001 11 . 11 .. 10 .... 0 1111 . . 0 .... @2misc =20 + VCVTAS 1111 001 11 . 11 .. 11 .... 0 0000 . . 0 .... @2misc + VCVTAU 1111 001 11 . 11 .. 11 .... 0 0001 . . 0 .... @2misc + VCVTNS 1111 001 11 . 11 .. 11 .... 0 0010 . . 0 .... @2misc + VCVTNU 1111 001 11 . 11 .. 11 .... 0 0011 . . 0 .... @2misc + VCVTPS 1111 001 11 . 11 .. 11 .... 0 0100 . . 0 .... @2misc + VCVTPU 1111 001 11 . 11 .. 11 .... 0 0101 . . 0 .... @2misc + VCVTMS 1111 001 11 . 11 .. 11 .... 0 0110 . . 0 .... @2misc + VCVTMU 1111 001 11 . 11 .. 11 .... 0 0111 . . 0 .... @2misc + VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc VRECPE_F 1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 0e7f86ad156..29bc161f36a 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3857,3 +3857,73 @@ DO_VRINT(VRINTA, FPROUNDING_TIEAWAY) DO_VRINT(VRINTZ, FPROUNDING_ZERO) DO_VRINT(VRINTM, FPROUNDING_NEGINF) DO_VRINT(VRINTP, FPROUNDING_POSINF) + +static bool do_vcvt(DisasContext *s, arg_2misc *a, int rmode, bool is_sign= ed) +{ + /* + * Handle a VCVT* operation by iterating 32 bits at a time, + * with a specified rounding mode in operation. + */ + int pass; + TCGv_ptr fpst; + TCGv_i32 tcg_rmode, tcg_shift; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->size !=3D 2) { + /* TODO: FP16 will be the size =3D=3D 1 case */ + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(1); + tcg_shift =3D tcg_const_i32(0); + tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); + for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { + TCGv_i32 tmp =3D neon_load_reg(a->vm, pass); + if (is_signed) { + gen_helper_vfp_tosls(tmp, tmp, tcg_shift, fpst); + } else { + gen_helper_vfp_touls(tmp, tmp, tcg_shift, fpst); + } + neon_store_reg(a->vd, pass, tmp); + } + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_temp_free_i32(tcg_rmode); + tcg_temp_free_i32(tcg_shift); + tcg_temp_free_ptr(fpst); + + return true; +} + +#define DO_VCVT(INSN, RMODE, SIGNED) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + return do_vcvt(s, a, RMODE, SIGNED); \ + } + +DO_VCVT(VCVTAU, FPROUNDING_TIEAWAY, false) +DO_VCVT(VCVTAS, FPROUNDING_TIEAWAY, true) +DO_VCVT(VCVTNU, FPROUNDING_TIEEVEN, false) +DO_VCVT(VCVTNS, FPROUNDING_TIEEVEN, true) +DO_VCVT(VCVTPU, FPROUNDING_POSINF, false) +DO_VCVT(VCVTPS, FPROUNDING_POSINF, true) +DO_VCVT(VCVTMU, FPROUNDING_NEGINF, false) +DO_VCVT(VCVTMS, FPROUNDING_NEGINF, true) diff --git a/target/arm/translate.c b/target/arm/translate.c index 61dfc3ae7af..b0181062020 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3042,30 +3042,6 @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t= 1) #define NEON_2RM_VCVT_SF 62 #define NEON_2RM_VCVT_UF 63 =20 -static bool neon_2rm_is_v8_op(int op) -{ - /* Return true if this neon 2reg-misc op is ARMv8 and up */ - switch (op) { - case NEON_2RM_VRINTN: - case NEON_2RM_VRINTA: - case NEON_2RM_VRINTM: - case NEON_2RM_VRINTP: - case NEON_2RM_VRINTZ: - case NEON_2RM_VRINTX: - case NEON_2RM_VCVTAU: - case NEON_2RM_VCVTAS: - case NEON_2RM_VCVTNU: - case NEON_2RM_VCVTNS: - case NEON_2RM_VCVTPU: - case NEON_2RM_VCVTPS: - case NEON_2RM_VCVTMU: - case NEON_2RM_VCVTMS: - return true; - default: - return false; - } -} - /* Each entry in this array has bit n set if the insn allows * size value n (otherwise it will UNDEF). Since unallocated * op values will have no bits set they always UNDEF. @@ -4908,10 +4884,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) if ((neon_2rm_sizes[op] & (1 << size)) =3D=3D 0) { return 1; } - if (neon_2rm_is_v8_op(op) && - !arm_dc_feature(s, ARM_FEATURE_V8)) { - return 1; - } if (q && ((rm | rd) & 1)) { return 1; } @@ -4964,6 +4936,14 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) case NEON_2RM_VRINTM: case NEON_2RM_VRINTP: case NEON_2RM_VRINTZ: + case NEON_2RM_VCVTAU: + case NEON_2RM_VCVTAS: + case NEON_2RM_VCVTNU: + case NEON_2RM_VCVTNS: + case NEON_2RM_VCVTPU: + case NEON_2RM_VCVTPS: + case NEON_2RM_VCVTMU: + case NEON_2RM_VCVTMS: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -4998,40 +4978,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) } neon_store_reg(rm, pass, tmp2); break; - case NEON_2RM_VCVTAU: - case NEON_2RM_VCVTAS: - case NEON_2RM_VCVTNU: - case NEON_2RM_VCVTNS: - case NEON_2RM_VCVTPU: - case NEON_2RM_VCVTPS: - case NEON_2RM_VCVTMU: - case NEON_2RM_VCVTMS: - { - bool is_signed =3D !extract32(insn, 7, 1); - TCGv_ptr fpst =3D get_fpstatus_ptr(1); - TCGv_i32 tcg_rmode, tcg_shift; - int rmode =3D fp_decode_rm[extract32(insn, 8, = 2)]; - - tcg_shift =3D tcg_const_i32(0); - tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rm= ode)); - gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, - cpu_env); - - if (is_signed) { - gen_helper_vfp_tosls(tmp, tmp, - tcg_shift, fpst); - } else { - gen_helper_vfp_touls(tmp, tmp, - tcg_shift, fpst); - } - - gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, - cpu_env); - tcg_temp_free_i32(tcg_rmode); - tcg_temp_free_i32(tcg_shift); - tcg_temp_free_ptr(fpst); - break; - } default: /* Reserved op values were caught by the * neon_2rm_sizes[] check earlier. --=20 2.20.1 From nobody Sat Feb 7 05:53:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592328314; cv=none; d=zohomail.com; s=zohoarc; b=i3tCFbKWmtlK3xWCYSQbZOn7K/kqRCFeTr5bdSU7zgu1N3/N88A0OyKWhhF2jzF2ZRu4yspIQtj+1ll7Q0qm4oDF1ghvCwRK4HDANC1mykanMigmipaGket+9kKOAALPWkCBQ6zBvv0jXJZOE5yDn6MVf5+O0FTGiml4p+aUS+A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592328314; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CA/am0GygyJkpXmDs56auXtZMrbcHbWGBURQkVmFBWU=; b=EP3Dp0kyJ3vHGK7z5tm6lXsfCzoPTGJtPVbYo0XRqJyYOE8JtJKuDDmTC2aE7zu8UwioCbfnT9L0oqH4++GAJBsyyz/r8Bsu3Bb0Uu1dylKOs9aL7fBDy/FcevX17nv1PcXFc10cXhBuI9fonBsS2Rel3fEesSipHIxTWq/ZlUA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159232831431272.3372838833833; Tue, 16 Jun 2020 10:25:14 -0700 (PDT) Received: from localhost ([::1]:42272 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlFKj-00087w-5V for importer@patchew.org; Tue, 16 Jun 2020 13:25:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47318) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF5I-0001uJ-7E for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:16 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:38846) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF5G-0007Z7-9t for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:15 -0400 Received: by mail-wr1-x442.google.com with SMTP id e1so21601784wrt.5 for ; Tue, 16 Jun 2020 10:09:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon VSWP insn to decodetree. Since the new implementation doesn't have to share a pass-loop with the other 2-reg-misc operations we can implement the swap with 64-bit accesses rather than 32-bits (which brings us into line with the pseudocode and is more efficient). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 2 ++ target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 5 +--- 3 files changed, 44 insertions(+), 4 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 5507c3e4623..2f64841de52 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -488,6 +488,8 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm VABS_F 1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc =20 + VSWP 1111 001 11 . 11 .. 10 .... 0 0000 . . 0 .... @2misc + VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc =20 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 29bc161f36a..01da7fad462 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3927,3 +3927,44 @@ DO_VCVT(VCVTPU, FPROUNDING_POSINF, false) DO_VCVT(VCVTPS, FPROUNDING_POSINF, true) DO_VCVT(VCVTMU, FPROUNDING_NEGINF, false) DO_VCVT(VCVTMS, FPROUNDING_NEGINF, true) + +static bool trans_VSWP(DisasContext *s, arg_2misc *a) +{ + TCGv_i64 rm, rd; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->size !=3D 0) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + rm =3D tcg_temp_new_i64(); + rd =3D tcg_temp_new_i64(); + for (pass =3D 0; pass < (a->q ? 2 : 1); pass++) { + neon_load_reg64(rm, a->vm + pass); + neon_load_reg64(rd, a->vd + pass); + neon_store_reg64(rm, a->vd + pass); + neon_store_reg64(rd, a->vm + pass); + } + tcg_temp_free_i64(rm); + tcg_temp_free_i64(rd); + + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index b0181062020..e8cd4a9c61f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4944,6 +4944,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_2RM_VCVTPS: case NEON_2RM_VCVTMU: case NEON_2RM_VCVTMS: + case NEON_2RM_VSWP: /* handled by decodetree */ return 1; case NEON_2RM_VTRN: @@ -4965,10 +4966,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) for (pass =3D 0; pass < (q ? 4 : 2); pass++) { tmp =3D neon_load_reg(rm, pass); switch (op) { - case NEON_2RM_VSWP: - tmp2 =3D neon_load_reg(rd, pass); - neon_store_reg(rm, pass, tmp2); - break; case NEON_2RM_VTRN: tmp2 =3D neon_load_reg(rd, pass); switch (size) { --=20 2.20.1 From nobody Sat Feb 7 05:53:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592328380; cv=none; d=zohomail.com; s=zohoarc; b=Ji2tFRIN6vyCZLB1Z6ArOL4QxIcAJQvDQlteqdBUqA6XyhvyxIeTA1JnTSkQMdBJxZr/dJ1hy/V9OUXqBBpadVATin2DFbfs1m8gJS9LYKHrIC/eJcSaCb8aOYTAb/fWyULHTZhZclixBYbIAzX4xhDlGnY5Zc9fLS5np4lD3w0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592328380; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=L7g+XpEeGGZVzbSRirQO8Y0StVZDY7uk47N2neXf45k=; b=PAiCionOfjDtlwWUHaMDFTxmuYIt786ucS70FuvpufJXj3I3/26fLv8QNArXRHp0MoFBqZZOM2Bt79aLiHyb4DQeaoozzIFc0cfnGKKwTJ0Tf6ucEsFvVq+163uDK4sUF/WDQrbq5ot/wu9mpK1n68HDcwNDVAKaLOEQ7wwE/bU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592328379985846.5607683899328; Tue, 16 Jun 2020 10:26:19 -0700 (PDT) Received: from localhost ([::1]:45924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlFLm-0001KK-MA for importer@patchew.org; Tue, 16 Jun 2020 13:26:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47356) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF5J-0001xl-FV for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:17 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:39570) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF5G-0007ZO-VM for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:17 -0400 Received: by mail-wr1-x444.google.com with SMTP id t18so21579876wru.6 for ; Tue, 16 Jun 2020 10:09:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon VTRN insn to decodetree. This is the last insn in the Neon data-processing group, so we can remove all the now-unused old decoder framework. It's possible that there's a more efficient implementation of VTRN, but for this conversion we just copy the existing approach. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 2 +- target/arm/translate-neon.inc.c | 90 ++++++++ target/arm/translate.c | 363 +------------------------------- 3 files changed, 93 insertions(+), 362 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 2f64841de52..686f9fbf46a 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -489,7 +489,7 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc =20 VSWP 1111 001 11 . 11 .. 10 .... 0 0000 . . 0 .... @2misc - + VTRN 1111 001 11 . 11 .. 10 .... 0 0001 . . 0 .... @2misc VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc =20 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 01da7fad462..8cc7f5db544 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -3968,3 +3968,93 @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a) =20 return true; } +static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1) +{ + TCGv_i32 rd, tmp; + + rd =3D tcg_temp_new_i32(); + tmp =3D tcg_temp_new_i32(); + + tcg_gen_shli_i32(rd, t0, 8); + tcg_gen_andi_i32(rd, rd, 0xff00ff00); + tcg_gen_andi_i32(tmp, t1, 0x00ff00ff); + tcg_gen_or_i32(rd, rd, tmp); + + tcg_gen_shri_i32(t1, t1, 8); + tcg_gen_andi_i32(t1, t1, 0x00ff00ff); + tcg_gen_andi_i32(tmp, t0, 0xff00ff00); + tcg_gen_or_i32(t1, t1, tmp); + tcg_gen_mov_i32(t0, rd); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(rd); +} + +static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) +{ + TCGv_i32 rd, tmp; + + rd =3D tcg_temp_new_i32(); + tmp =3D tcg_temp_new_i32(); + + tcg_gen_shli_i32(rd, t0, 16); + tcg_gen_andi_i32(tmp, t1, 0xffff); + tcg_gen_or_i32(rd, rd, tmp); + tcg_gen_shri_i32(t1, t1, 16); + tcg_gen_andi_i32(tmp, t0, 0xffff0000); + tcg_gen_or_i32(t1, t1, tmp); + tcg_gen_mov_i32(t0, rd); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(rd); +} + +static bool trans_VTRN(DisasContext *s, arg_2misc *a) +{ + TCGv_i32 tmp, tmp2; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (a->size =3D=3D 3) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (a->size =3D=3D 2) { + for (pass =3D 0; pass < (a->q ? 4 : 2); pass +=3D 2) { + tmp =3D neon_load_reg(a->vm, pass); + tmp2 =3D neon_load_reg(a->vd, pass + 1); + neon_store_reg(a->vm, pass, tmp2); + neon_store_reg(a->vd, pass + 1, tmp); + } + } else { + for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { + tmp =3D neon_load_reg(a->vm, pass); + tmp2 =3D neon_load_reg(a->vd, pass); + if (a->size =3D=3D 0) { + gen_neon_trn_u8(tmp, tmp2); + } else { + gen_neon_trn_u16(tmp, tmp2); + } + neon_store_reg(a->vm, pass, tmp2); + neon_store_reg(a->vd, pass, tmp); + } + } + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index e8cd4a9c61f..581b0b5cde4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2934,183 +2934,6 @@ static void gen_exception_return(DisasContext *s, T= CGv_i32 pc) gen_rfe(s, pc, load_cpu_field(spsr)); } =20 -static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1) -{ - TCGv_i32 rd, tmp; - - rd =3D tcg_temp_new_i32(); - tmp =3D tcg_temp_new_i32(); - - tcg_gen_shli_i32(rd, t0, 8); - tcg_gen_andi_i32(rd, rd, 0xff00ff00); - tcg_gen_andi_i32(tmp, t1, 0x00ff00ff); - tcg_gen_or_i32(rd, rd, tmp); - - tcg_gen_shri_i32(t1, t1, 8); - tcg_gen_andi_i32(t1, t1, 0x00ff00ff); - tcg_gen_andi_i32(tmp, t0, 0xff00ff00); - tcg_gen_or_i32(t1, t1, tmp); - tcg_gen_mov_i32(t0, rd); - - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(rd); -} - -static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) -{ - TCGv_i32 rd, tmp; - - rd =3D tcg_temp_new_i32(); - tmp =3D tcg_temp_new_i32(); - - tcg_gen_shli_i32(rd, t0, 16); - tcg_gen_andi_i32(tmp, t1, 0xffff); - tcg_gen_or_i32(rd, rd, tmp); - tcg_gen_shri_i32(t1, t1, 16); - tcg_gen_andi_i32(tmp, t0, 0xffff0000); - tcg_gen_or_i32(t1, t1, tmp); - tcg_gen_mov_i32(t0, rd); - - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(rd); -} - -/* Symbolic constants for op fields for Neon 2-register miscellaneous. - * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B - * table A7-13. - */ -#define NEON_2RM_VREV64 0 -#define NEON_2RM_VREV32 1 -#define NEON_2RM_VREV16 2 -#define NEON_2RM_VPADDL 4 -#define NEON_2RM_VPADDL_U 5 -#define NEON_2RM_AESE 6 /* Includes AESD */ -#define NEON_2RM_AESMC 7 /* Includes AESIMC */ -#define NEON_2RM_VCLS 8 -#define NEON_2RM_VCLZ 9 -#define NEON_2RM_VCNT 10 -#define NEON_2RM_VMVN 11 -#define NEON_2RM_VPADAL 12 -#define NEON_2RM_VPADAL_U 13 -#define NEON_2RM_VQABS 14 -#define NEON_2RM_VQNEG 15 -#define NEON_2RM_VCGT0 16 -#define NEON_2RM_VCGE0 17 -#define NEON_2RM_VCEQ0 18 -#define NEON_2RM_VCLE0 19 -#define NEON_2RM_VCLT0 20 -#define NEON_2RM_SHA1H 21 -#define NEON_2RM_VABS 22 -#define NEON_2RM_VNEG 23 -#define NEON_2RM_VCGT0_F 24 -#define NEON_2RM_VCGE0_F 25 -#define NEON_2RM_VCEQ0_F 26 -#define NEON_2RM_VCLE0_F 27 -#define NEON_2RM_VCLT0_F 28 -#define NEON_2RM_VABS_F 30 -#define NEON_2RM_VNEG_F 31 -#define NEON_2RM_VSWP 32 -#define NEON_2RM_VTRN 33 -#define NEON_2RM_VUZP 34 -#define NEON_2RM_VZIP 35 -#define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */ -#define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */ -#define NEON_2RM_VSHLL 38 -#define NEON_2RM_SHA1SU1 39 /* Includes SHA256SU0 */ -#define NEON_2RM_VRINTN 40 -#define NEON_2RM_VRINTX 41 -#define NEON_2RM_VRINTA 42 -#define NEON_2RM_VRINTZ 43 -#define NEON_2RM_VCVT_F16_F32 44 -#define NEON_2RM_VRINTM 45 -#define NEON_2RM_VCVT_F32_F16 46 -#define NEON_2RM_VRINTP 47 -#define NEON_2RM_VCVTAU 48 -#define NEON_2RM_VCVTAS 49 -#define NEON_2RM_VCVTNU 50 -#define NEON_2RM_VCVTNS 51 -#define NEON_2RM_VCVTPU 52 -#define NEON_2RM_VCVTPS 53 -#define NEON_2RM_VCVTMU 54 -#define NEON_2RM_VCVTMS 55 -#define NEON_2RM_VRECPE 56 -#define NEON_2RM_VRSQRTE 57 -#define NEON_2RM_VRECPE_F 58 -#define NEON_2RM_VRSQRTE_F 59 -#define NEON_2RM_VCVT_FS 60 -#define NEON_2RM_VCVT_FU 61 -#define NEON_2RM_VCVT_SF 62 -#define NEON_2RM_VCVT_UF 63 - -/* Each entry in this array has bit n set if the insn allows - * size value n (otherwise it will UNDEF). Since unallocated - * op values will have no bits set they always UNDEF. - */ -static const uint8_t neon_2rm_sizes[] =3D { - [NEON_2RM_VREV64] =3D 0x7, - [NEON_2RM_VREV32] =3D 0x3, - [NEON_2RM_VREV16] =3D 0x1, - [NEON_2RM_VPADDL] =3D 0x7, - [NEON_2RM_VPADDL_U] =3D 0x7, - [NEON_2RM_AESE] =3D 0x1, - [NEON_2RM_AESMC] =3D 0x1, - [NEON_2RM_VCLS] =3D 0x7, - [NEON_2RM_VCLZ] =3D 0x7, - [NEON_2RM_VCNT] =3D 0x1, - [NEON_2RM_VMVN] =3D 0x1, - [NEON_2RM_VPADAL] =3D 0x7, - [NEON_2RM_VPADAL_U] =3D 0x7, - [NEON_2RM_VQABS] =3D 0x7, - [NEON_2RM_VQNEG] =3D 0x7, - [NEON_2RM_VCGT0] =3D 0x7, - [NEON_2RM_VCGE0] =3D 0x7, - [NEON_2RM_VCEQ0] =3D 0x7, - [NEON_2RM_VCLE0] =3D 0x7, - [NEON_2RM_VCLT0] =3D 0x7, - [NEON_2RM_SHA1H] =3D 0x4, - [NEON_2RM_VABS] =3D 0x7, - [NEON_2RM_VNEG] =3D 0x7, - [NEON_2RM_VCGT0_F] =3D 0x4, - [NEON_2RM_VCGE0_F] =3D 0x4, - [NEON_2RM_VCEQ0_F] =3D 0x4, - [NEON_2RM_VCLE0_F] =3D 0x4, - [NEON_2RM_VCLT0_F] =3D 0x4, - [NEON_2RM_VABS_F] =3D 0x4, - [NEON_2RM_VNEG_F] =3D 0x4, - [NEON_2RM_VSWP] =3D 0x1, - [NEON_2RM_VTRN] =3D 0x7, - [NEON_2RM_VUZP] =3D 0x7, - [NEON_2RM_VZIP] =3D 0x7, - [NEON_2RM_VMOVN] =3D 0x7, - [NEON_2RM_VQMOVN] =3D 0x7, - [NEON_2RM_VSHLL] =3D 0x7, - [NEON_2RM_SHA1SU1] =3D 0x4, - [NEON_2RM_VRINTN] =3D 0x4, - [NEON_2RM_VRINTX] =3D 0x4, - [NEON_2RM_VRINTA] =3D 0x4, - [NEON_2RM_VRINTZ] =3D 0x4, - [NEON_2RM_VCVT_F16_F32] =3D 0x2, - [NEON_2RM_VRINTM] =3D 0x4, - [NEON_2RM_VCVT_F32_F16] =3D 0x2, - [NEON_2RM_VRINTP] =3D 0x4, - [NEON_2RM_VCVTAU] =3D 0x4, - [NEON_2RM_VCVTAS] =3D 0x4, - [NEON_2RM_VCVTNU] =3D 0x4, - [NEON_2RM_VCVTNS] =3D 0x4, - [NEON_2RM_VCVTPU] =3D 0x4, - [NEON_2RM_VCVTPS] =3D 0x4, - [NEON_2RM_VCVTMU] =3D 0x4, - [NEON_2RM_VCVTMS] =3D 0x4, - [NEON_2RM_VRECPE] =3D 0x4, - [NEON_2RM_VRSQRTE] =3D 0x4, - [NEON_2RM_VRECPE_F] =3D 0x4, - [NEON_2RM_VRSQRTE_F] =3D 0x4, - [NEON_2RM_VCVT_FS] =3D 0x4, - [NEON_2RM_VCVT_FU] =3D 0x4, - [NEON_2RM_VCVT_SF] =3D 0x4, - [NEON_2RM_VCVT_UF] =3D 0x4, -}; - static void gen_gvec_fn3_qc(uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_= ofs, uint32_t opr_sz, uint32_t max_sz, gen_helper_gvec_3_ptr *fn) @@ -4822,178 +4645,6 @@ void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, = uint32_t rn_ofs, tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]); } =20 -/* Translate a NEON data processing instruction. Return nonzero if the - instruction is invalid. - We process data in a mixture of 32-bit and 64-bit chunks. - Mostly we use 32-bit chunks so we can use normal scalar instructions. = */ - -static int disas_neon_data_insn(DisasContext *s, uint32_t insn) -{ - int op; - int q; - int rd, rm; - int size; - int pass; - int u; - TCGv_i32 tmp, tmp2; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return 1; - } - - /* FIXME: this access check should not take precedence over UNDEF - * for invalid encodings; we will generate incorrect syndrome informat= ion - * for attempts to execute invalid vfp/neon encodings with FP disabled. - */ - if (s->fp_excp_el) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_simd_access_trap(1, 0xe, false), s->fp_excp= _el); - return 0; - } - - if (!s->vfp_enabled) - return 1; - q =3D (insn & (1 << 6)) !=3D 0; - u =3D (insn >> 24) & 1; - VFP_DREG_D(rd, insn); - VFP_DREG_M(rm, insn); - size =3D (insn >> 20) & 3; - - if ((insn & (1 << 23)) =3D=3D 0) { - /* Three register same length: handled by decodetree */ - return 1; - } else if (insn & (1 << 4)) { - /* Two registers and shift or reg and imm: handled by decodetree */ - return 1; - } else { /* (insn & 0x00800010 =3D=3D 0x00800000) */ - if (size !=3D 3) { - /* - * Three registers of different lengths, or two registers and - * a scalar: handled by decodetree - */ - return 1; - } else { /* size =3D=3D 3 */ - if (!u) { - /* Extract: handled by decodetree */ - return 1; - } else if ((insn & (1 << 11)) =3D=3D 0) { - /* Two register misc. */ - op =3D ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf); - size =3D (insn >> 18) & 3; - /* UNDEF for unknown op values and bad op-size combination= s */ - if ((neon_2rm_sizes[op] & (1 << size)) =3D=3D 0) { - return 1; - } - if (q && ((rm | rd) & 1)) { - return 1; - } - switch (op) { - case NEON_2RM_VREV64: - case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U: - case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U: - case NEON_2RM_VUZP: - case NEON_2RM_VZIP: - case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: - case NEON_2RM_VSHLL: - case NEON_2RM_VCVT_F16_F32: - case NEON_2RM_VCVT_F32_F16: - case NEON_2RM_VMVN: - case NEON_2RM_VNEG: - case NEON_2RM_VABS: - case NEON_2RM_VCEQ0: - case NEON_2RM_VCGT0: - case NEON_2RM_VCLE0: - case NEON_2RM_VCGE0: - case NEON_2RM_VCLT0: - case NEON_2RM_AESE: case NEON_2RM_AESMC: - case NEON_2RM_SHA1H: - case NEON_2RM_SHA1SU1: - case NEON_2RM_VREV32: - case NEON_2RM_VREV16: - case NEON_2RM_VCLS: - case NEON_2RM_VCLZ: - case NEON_2RM_VCNT: - case NEON_2RM_VABS_F: - case NEON_2RM_VNEG_F: - case NEON_2RM_VRECPE: - case NEON_2RM_VRSQRTE: - case NEON_2RM_VQABS: - case NEON_2RM_VQNEG: - case NEON_2RM_VRECPE_F: - case NEON_2RM_VRSQRTE_F: - case NEON_2RM_VCVT_FS: - case NEON_2RM_VCVT_FU: - case NEON_2RM_VCVT_SF: - case NEON_2RM_VCVT_UF: - case NEON_2RM_VRINTX: - case NEON_2RM_VCGT0_F: - case NEON_2RM_VCGE0_F: - case NEON_2RM_VCEQ0_F: - case NEON_2RM_VCLE0_F: - case NEON_2RM_VCLT0_F: - case NEON_2RM_VRINTN: - case NEON_2RM_VRINTA: - case NEON_2RM_VRINTM: - case NEON_2RM_VRINTP: - case NEON_2RM_VRINTZ: - case NEON_2RM_VCVTAU: - case NEON_2RM_VCVTAS: - case NEON_2RM_VCVTNU: - case NEON_2RM_VCVTNS: - case NEON_2RM_VCVTPU: - case NEON_2RM_VCVTPS: - case NEON_2RM_VCVTMU: - case NEON_2RM_VCVTMS: - case NEON_2RM_VSWP: - /* handled by decodetree */ - return 1; - case NEON_2RM_VTRN: - if (size =3D=3D 2) { - int n; - for (n =3D 0; n < (q ? 4 : 2); n +=3D 2) { - tmp =3D neon_load_reg(rm, n); - tmp2 =3D neon_load_reg(rd, n + 1); - neon_store_reg(rm, n, tmp2); - neon_store_reg(rd, n + 1, tmp); - } - } else { - goto elementwise; - } - break; - - default: - elementwise: - for (pass =3D 0; pass < (q ? 4 : 2); pass++) { - tmp =3D neon_load_reg(rm, pass); - switch (op) { - case NEON_2RM_VTRN: - tmp2 =3D neon_load_reg(rd, pass); - switch (size) { - case 0: gen_neon_trn_u8(tmp, tmp2); break; - case 1: gen_neon_trn_u16(tmp, tmp2); break; - default: abort(); - } - neon_store_reg(rm, pass, tmp2); - break; - default: - /* Reserved op values were caught by the - * neon_2rm_sizes[] check earlier. - */ - abort(); - } - neon_store_reg(rd, pass, tmp); - } - break; - } - } else { - /* VTBL, VTBX, VDUP: handled by decodetree */ - return 1; - } - } - } - return 0; -} - static int disas_coproc_insn(DisasContext *s, uint32_t insn) { int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; @@ -8694,13 +8345,6 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) } /* fall back to legacy decoder */ =20 - if (((insn >> 25) & 7) =3D=3D 1) { - /* NEON Data processing. */ - if (disas_neon_data_insn(s, insn)) { - goto illegal_op; - } - return; - } if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -8888,11 +8532,8 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) break; } if (((insn >> 24) & 3) =3D=3D 3) { - /* Translate into the equivalent ARM encoding. */ - insn =3D (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 = << 28); - if (disas_neon_data_insn(s, insn)) { - goto illegal_op; - } + /* Neon DP, but failed disas_neon_dp() */ + goto illegal_op; } else if (((insn >> 8) & 0xe) =3D=3D 10) { /* VFP, but failed disas_vfp. */ goto illegal_op; --=20 2.20.1 From nobody Sat Feb 7 05:53:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1592327859; cv=none; d=zohomail.com; s=zohoarc; b=Yhq4PWQ18f+sfJUtcKoutt4Sx23Hde740xmCqZY2r+UB5wUMjIqcnO/EZqOJgJolfg5BmUiQfhh0hrQ0XAP2DJESZCbL6QI2+T6qH27uq1T0Fms6mxtelEUtQ/hKlHVmOijiQnB7o7mblSwtwVpqK7LtHerN4LIJuKOtFTV7VbI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592327859; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ewe6RYNvrMPtXGvRt+OIItTfxTHNlzfYc6x9hP/Letk=; b=CKNvcFpnHGSe//+HHs/C0YdJPZcJmPfGIW8KozOExZq2h/mZFEhiPQkVGWLF3ER9tgOLmAG+27dyzmv7y2vFGuJz6yygD+s1Te7VbbBppoJ6WAUNShnJjivvEY7i/JasG3+nxL/D42N/XA8+NRRYgXsHm8loGKk0oBbjEvXvZgg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1592327858991294.9911787499086; Tue, 16 Jun 2020 10:17:38 -0700 (PDT) Received: from localhost ([::1]:40242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jlFDN-0003yx-Hi for importer@patchew.org; Tue, 16 Jun 2020 13:17:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47360) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jlF5K-0001zC-04 for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:18 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:41074) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jlF5H-0007ZY-Sw for qemu-devel@nongnu.org; Tue, 16 Jun 2020 13:09:17 -0400 Received: by mail-wr1-x441.google.com with SMTP id j10so21556315wrw.8 for ; Tue, 16 Jun 2020 10:09:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y80sm5263216wmc.34.2020.06.16.10.09.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 10:09:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ewe6RYNvrMPtXGvRt+OIItTfxTHNlzfYc6x9hP/Letk=; b=KDPPrj8kGdB40oU2FH+gCimGrkRl01AUQvVJMJbXNoVZkllYDvzpumAY66Hxe/RHpI UYKTlqs7x2quDFVCUetyDslh7lY07mYXvXn2M6HJsAwS2Fyxti37H74A5NJ2nLNEotn9 IYUtKxzhFTMMKsDgbM9aRQqcLInyt0catja1uW/GMRC8YbNkDRzWqNrmwgw29mLs5Xxt j1TxY3zblnObbGQJsj9aKfWVUJg5viO7UvGh57lN0AptJep9CuaNpBzC8We2tur3jckx chIVl/kO8LWKVS/NZG9E1D36vS3D3MLQ2rX+RsxWFqPfZMx2DyMdiBgqzGUhRwDkX/Go odPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ewe6RYNvrMPtXGvRt+OIItTfxTHNlzfYc6x9hP/Letk=; b=eSAwtVPCclnjQF6MEsOTiqxJSVVlUWuX2nrFj82LQwsvt9D/DwPr2938ThYVsG5z7E m17Yiv9i+vTw6gfzFkw5CvXove2y3QTPPfotjH9cPYm/f69QGBu5OQXQE2oNL7OP5MJv 6XQmv/nn6vcEDrALjouVu81uJ8jxnoKCfOiTG6i3LbGb06KKPzf+1BHo90at6q2tlfSk Pzqg2pBHH87BX2463CpXm0YpGJsV+rldULRzJ1cXjlOOFm0GxOVHQDj3q8rbiNoVdb3w 5tZklpJ9sUZu8hiJW6cDVPtnp07GPyWugyhUMXIMN00R4UAiqKgYNbzXBu5BtLb9yFjn tY6w== X-Gm-Message-State: AOAM533urVn3Bcfqli6w2wyKs24kHC0dMPYWJdcBSr15KNjrqjY3bNOm 3kE41S7fooac4W4A9gB7PwzAqVP6BYRHSw== X-Google-Smtp-Source: ABdhPJwPiZF1SyXWTZo5y1BwHCSpRAcwuO+UT1vKAcnDajRQeo/cqD523vqqz/kMeAMtSIL11/LDgg== X-Received: by 2002:adf:f990:: with SMTP id f16mr3958793wrr.311.1592327354387; Tue, 16 Jun 2020 10:09:14 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 21/21] target/arm: Move some functions used only in translate-neon.inc.c to that file Date: Tue, 16 Jun 2020 18:08:44 +0100 Message-Id: <20200616170844.13318-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200616170844.13318-1-peter.maydell@linaro.org> References: <20200616170844.13318-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The functions neon_element_offset(), neon_load_element(), neon_load_element64(), neon_store_element() and neon_store_element64() are used only in the translate-neon.inc.c file, so move their definitions there. Since the .inc.c file is #included in translate.c this doesn't make much difference currently, but it's a more logical place to put the functions and it might be helpful if we ever decide to try to make the .inc.c files genuinely separate compilation units. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-neon.inc.c | 101 ++++++++++++++++++++++++++++++++ target/arm/translate.c | 101 -------------------------------- 2 files changed, 101 insertions(+), 101 deletions(-) diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 8cc7f5db544..f6cb9215739 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -54,6 +54,107 @@ static inline int rsub_8(DisasContext *s, int x) #include "decode-neon-ls.inc.c" #include "decode-neon-shared.inc.c" =20 +/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, + * where 0 is the least significant end of the register. + */ +static inline long +neon_element_offset(int reg, int element, MemOp size) +{ + int element_size =3D 1 << size; + int ofs =3D element * element_size; +#ifdef HOST_WORDS_BIGENDIAN + /* Calculate the offset assuming fully little-endian, + * then XOR to account for the order of the 8-byte units. + */ + if (element_size < 8) { + ofs ^=3D 8 - element_size; + } +#endif + return neon_reg_offset(reg, 0) + ofs; +} + +static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) +{ + long offset =3D neon_element_offset(reg, ele, mop & MO_SIZE); + + switch (mop) { + case MO_UB: + tcg_gen_ld8u_i32(var, cpu_env, offset); + break; + case MO_UW: + tcg_gen_ld16u_i32(var, cpu_env, offset); + break; + case MO_UL: + tcg_gen_ld_i32(var, cpu_env, offset); + break; + default: + g_assert_not_reached(); + } +} + +static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop) +{ + long offset =3D neon_element_offset(reg, ele, mop & MO_SIZE); + + switch (mop) { + case MO_UB: + tcg_gen_ld8u_i64(var, cpu_env, offset); + break; + case MO_UW: + tcg_gen_ld16u_i64(var, cpu_env, offset); + break; + case MO_UL: + tcg_gen_ld32u_i64(var, cpu_env, offset); + break; + case MO_Q: + tcg_gen_ld_i64(var, cpu_env, offset); + break; + default: + g_assert_not_reached(); + } +} + +static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var) +{ + long offset =3D neon_element_offset(reg, ele, size); + + switch (size) { + case MO_8: + tcg_gen_st8_i32(var, cpu_env, offset); + break; + case MO_16: + tcg_gen_st16_i32(var, cpu_env, offset); + break; + case MO_32: + tcg_gen_st_i32(var, cpu_env, offset); + break; + default: + g_assert_not_reached(); + } +} + +static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 va= r) +{ + long offset =3D neon_element_offset(reg, ele, size); + + switch (size) { + case MO_8: + tcg_gen_st8_i64(var, cpu_env, offset); + break; + case MO_16: + tcg_gen_st16_i64(var, cpu_env, offset); + break; + case MO_32: + tcg_gen_st32_i64(var, cpu_env, offset); + break; + case MO_64: + tcg_gen_st_i64(var, cpu_env, offset); + break; + default: + g_assert_not_reached(); + } +} + static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) { int opr_sz; diff --git a/target/arm/translate.c b/target/arm/translate.c index 581b0b5cde4..408fb7a492f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1133,25 +1133,6 @@ neon_reg_offset (int reg, int n) return vfp_reg_offset(0, sreg); } =20 -/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, - * where 0 is the least significant end of the register. - */ -static inline long -neon_element_offset(int reg, int element, MemOp size) -{ - int element_size =3D 1 << size; - int ofs =3D element * element_size; -#ifdef HOST_WORDS_BIGENDIAN - /* Calculate the offset assuming fully little-endian, - * then XOR to account for the order of the 8-byte units. - */ - if (element_size < 8) { - ofs ^=3D 8 - element_size; - } -#endif - return neon_reg_offset(reg, 0) + ofs; -} - static TCGv_i32 neon_load_reg(int reg, int pass) { TCGv_i32 tmp =3D tcg_temp_new_i32(); @@ -1159,94 +1140,12 @@ static TCGv_i32 neon_load_reg(int reg, int pass) return tmp; } =20 -static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) -{ - long offset =3D neon_element_offset(reg, ele, mop & MO_SIZE); - - switch (mop) { - case MO_UB: - tcg_gen_ld8u_i32(var, cpu_env, offset); - break; - case MO_UW: - tcg_gen_ld16u_i32(var, cpu_env, offset); - break; - case MO_UL: - tcg_gen_ld_i32(var, cpu_env, offset); - break; - default: - g_assert_not_reached(); - } -} - -static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop) -{ - long offset =3D neon_element_offset(reg, ele, mop & MO_SIZE); - - switch (mop) { - case MO_UB: - tcg_gen_ld8u_i64(var, cpu_env, offset); - break; - case MO_UW: - tcg_gen_ld16u_i64(var, cpu_env, offset); - break; - case MO_UL: - tcg_gen_ld32u_i64(var, cpu_env, offset); - break; - case MO_Q: - tcg_gen_ld_i64(var, cpu_env, offset); - break; - default: - g_assert_not_reached(); - } -} - static void neon_store_reg(int reg, int pass, TCGv_i32 var) { tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); tcg_temp_free_i32(var); } =20 -static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var) -{ - long offset =3D neon_element_offset(reg, ele, size); - - switch (size) { - case MO_8: - tcg_gen_st8_i32(var, cpu_env, offset); - break; - case MO_16: - tcg_gen_st16_i32(var, cpu_env, offset); - break; - case MO_32: - tcg_gen_st_i32(var, cpu_env, offset); - break; - default: - g_assert_not_reached(); - } -} - -static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 va= r) -{ - long offset =3D neon_element_offset(reg, ele, size); - - switch (size) { - case MO_8: - tcg_gen_st8_i64(var, cpu_env, offset); - break; - case MO_16: - tcg_gen_st16_i64(var, cpu_env, offset); - break; - case MO_32: - tcg_gen_st32_i64(var, cpu_env, offset); - break; - case MO_64: - tcg_gen_st_i64(var, cpu_env, offset); - break; - default: - g_assert_not_reached(); - } -} - static inline void neon_load_reg64(TCGv_i64 var, int reg) { tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); --=20 2.20.1