From nobody Mon Feb 9 10:49:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1591718969; cv=none; d=zohomail.com; s=zohoarc; b=Nu8hv1tXa3K9euGjLygf0xTEykv4EMJSnAV4YVY0nScZe0Vqh/70lF+RmRuvEMZaS5k2QGqDvDPd+ErZ3a8aPCb0swjXT9vHQApYPhlCtGoj72kJpPJ8vxrusxkkYX8arYdhL1/UETL3M0csRTfX/JgdNiOKa8vwxZXruLUs/WI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591718969; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6Po3TGUgc62Sm+OROEr5qzIKDQbHx7K4FmJnkx1dhO0=; b=b6LKOPsGwuUNG6NhIHzKt15zP1mXsJ5poVk7fDA+l8iBAGqgkxTmwbJe/oVcXhGJFZwFW29KHvZslOayAfJ/2SJW4RNJQza4o+NyRMtmxEdhHYgH8c060mk331n7gx1vRXVPRbwWjoRv9FVrk8GZn68TmfOBcYZPieXMZ4DobfI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591718969052322.661983474566; Tue, 9 Jun 2020 09:09:29 -0700 (PDT) Received: from localhost ([::1]:47408 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jigoZ-0003io-N6 for importer@patchew.org; Tue, 09 Jun 2020 12:09:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42716) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jighi-0003MV-Fj for qemu-devel@nongnu.org; Tue, 09 Jun 2020 12:02:22 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:53212) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jighd-0003QA-9T for qemu-devel@nongnu.org; Tue, 09 Jun 2020 12:02:21 -0400 Received: by mail-wm1-x344.google.com with SMTP id r9so3357722wmh.2 for ; Tue, 09 Jun 2020 09:02:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b81sm3699867wmc.5.2020.06.09.09.02.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 09:02:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6Po3TGUgc62Sm+OROEr5qzIKDQbHx7K4FmJnkx1dhO0=; b=TMdPaoOVc06Hcuvb444JBkpYSOXZoYIIgGmcsB6k8J70qDFAdYz4I+YnsfdBeQQcWu 7kWoGGbjxbeJKuWdHXfYU4h5sMgkCjSePRUDQ8MgSdRbWkeI5nFZQ7yI6degLsH/FTSo 2qpRYYWS5ifcx9t4R2fUrTvEkepWOO4M4jyS72ie6uN/8i8HtH+wU25XtXHpVn5TGu5p dVJjChSxteORd+VkuVaDNIZGSWcvFnoqI3kRW+YWxhApP7vlqbLzxu69EC1ZdB1hEguA /bmuJTaZkOh09zXF09vrgov/e53ucycEM4zi8/VfiphMXnvvSpxFP3YL534PV47VZY6Z pePQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6Po3TGUgc62Sm+OROEr5qzIKDQbHx7K4FmJnkx1dhO0=; b=h8Y+crN8qGVFpj9WdQvXbT6l4QJ9EDZRKdL6LOMPsIpiOYtpZ8ebuW2dczidoviCmS dHZeOnHKgCeqiokwKqOq2ncT2S9+poo6R32eJNEhnAuCiQVFjs/tokhjw/4waL6yTp9s 2VGUDFL6hiEhGXIYUWVgtoSVm9qvEqYqLTrifUtRI31uJUvEFccG/7Qkm7E0i6WeW/mf r30t77rabUEfI3llMfjAXzkKlLyMZRRkPvpcZvaY7/mW6SLGJjkaMzqBtaVMiVarMuGK PChAHXmcYQqKDsURIAiV4IC/nm6FLQ8+JnH2+VXsHB2VXLxIJyHFOQ6vgNnsFKZ9Xb4p tuWw== X-Gm-Message-State: AOAM5302gwdv5lN4/61LdOgPQ/hUU+5th9VKTqsiLxnNJ+LzMLqph6wR pYC5atS2zFLh4LjdSB5jNJi9DQ== X-Google-Smtp-Source: ABdhPJxuSZcpHq/4Qg5JzeeIiuX7XIuehQlX36A0ed2JArfbRVJ2mimu5wCWd7CrAB2ZGrHNgGSuXg== X-Received: by 2002:a1c:3bc2:: with SMTP id i185mr4887468wma.33.1591718533812; Tue, 09 Jun 2020 09:02:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/7] target/arm: Fix missing temp frees in do_vshll_2sh Date: Tue, 9 Jun 2020 17:02:03 +0100 Message-Id: <20200609160209.29960-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200609160209.29960-1-peter.maydell@linaro.org> References: <20200609160209.29960-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The widenfn() in do_vshll_2sh() does not free the input 32-bit TCGv, so we need to do this in the calling code. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/translate-neon.inc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 664d3612607..299a61f067b 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1624,6 +1624,7 @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_sh= ift *a, tmp =3D tcg_temp_new_i64(); =20 widenfn(tmp, rm0); + tcg_temp_free_i32(rm0); if (a->shift !=3D 0) { tcg_gen_shli_i64(tmp, tmp, a->shift); tcg_gen_andi_i64(tmp, tmp, ~widen_mask); @@ -1631,6 +1632,7 @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_sh= ift *a, neon_store_reg64(tmp, a->vd); =20 widenfn(tmp, rm1); + tcg_temp_free_i32(rm1); if (a->shift !=3D 0) { tcg_gen_shli_i64(tmp, tmp, a->shift); tcg_gen_andi_i64(tmp, tmp, ~widen_mask); --=20 2.20.1 From nobody Mon Feb 9 10:49:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1591718854; cv=none; d=zohomail.com; s=zohoarc; b=SQtVRMwj5HL9J8CHCw9i53T6NR1bfAMnOSCZTmOHxPKBc0WWycf1lI5Gud8r0fD3F1zjfK6mkW18iLIVKV7ZUsg8Jw3WgBtf9X/03Tpg0s0hj76xOTNgE4Mi28r95fh1XglR9XpapbIb3RM0wnM1hJyEAJtGxtbAR5HwzRRndLI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591718854; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8uhbH3R8ttA4y5SJ7ktopOo31UwAu136Rzv9dXmwq14=; b=EyowDzb+LEzX80JYKBr+n9p9mU0iLpHeFFYiPpB3XNKYB9Jz0M5uQf0alrNvW0qP19J5ONB61+EIOFHzHLoY33D+Jf6d/V89F9WDK0ePBXGKnV5PqcdXH1VUSTAOEXjYPjPobEXRcmeiWSo8TRzDtXjT9AQmiUmv7hdQWPgzSMk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591718854715262.03786945250476; Tue, 9 Jun 2020 09:07:34 -0700 (PDT) Received: from localhost ([::1]:40444 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jigmj-0000l6-9L for importer@patchew.org; Tue, 09 Jun 2020 12:07:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jighh-0003Ld-M7 for qemu-devel@nongnu.org; Tue, 09 Jun 2020 12:02:21 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:45812) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jighd-0003QO-C1 for qemu-devel@nongnu.org; Tue, 09 Jun 2020 12:02:21 -0400 Received: by mail-wr1-x430.google.com with SMTP id c3so21894310wru.12 for ; Tue, 09 Jun 2020 09:02:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b81sm3699867wmc.5.2020.06.09.09.02.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 09:02:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8uhbH3R8ttA4y5SJ7ktopOo31UwAu136Rzv9dXmwq14=; b=Di5tjZLrOvFmYYA7v0V6R8YENuHksKXXYIalyPW3T5LHtkQw+a2phw8yYWsQKIh+ty RcXjsJLG2npTGSKMMIDNWtZA3t1hIS8XO9Fz6GBVClIJe7p1m3QUmspb0ysdHhY92Clu b7W0zDRzRdw/Xi6mRajwTMfUzfq6LzqVnW6YuXfFAGnQBE2K0kUXUHsoWu/pIcJJWIDA sTZpuDeVPh7tzSfyJPOu1ij1f9Oak9uZfRPoWiSxXc/IcmDl8r8e8cKbGx2AzMvgkRUa S80Qe6TclGQZobzf/qRW7zNOexBec3GMyhN27J7HbZVorgn3BrENfDBXuwxk2pX25mxi QkBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8uhbH3R8ttA4y5SJ7ktopOo31UwAu136Rzv9dXmwq14=; b=mXbHTnaVyNIQ/00fXThZAyNHn59GeLO71kSRU28iJkhfW3CH/XDXR3LlAuCqt3QSAV m4m+0pNdZBMSV9/fPKhe7KDgb34V4hm5k5BrhOqC0Ozh3jbYmwHyi/5DYzEKfcUPXLci c4+JnK+DFMiagUlW3fjGHbE1HXDgjWvfavovvJg910nvbFEWmlKSgz7Bq23Idb+4/8GO yvjBNOl0TDydea7NUT9EeHGI/au15U0I8Zg5ruQr/5sOs56h+fSaKqfaEdEy13tKdRGN t7sqx8gS83g8wKVSwBp/jC2im4OllpY7mOYyoel+0TFDdNjOwt4m0e1MKMa953ufvbMR HXNg== X-Gm-Message-State: AOAM5310ucT9/ZvP94bh7jlYJWP2E7Flm1Zmu3tr2OlHr813GJ2dGuk+ e2S2Z3xwhsT8MXYPL0uyUk3wXEqaKF7qzg== X-Google-Smtp-Source: ABdhPJxUzbXkubiEr0Y5kEQaepcBR0/VnH8NzkUF85PmQbDFtKLWj+nweYb1F1z1cbhRoEMgC7VeRw== X-Received: by 2002:adf:d0d0:: with SMTP id z16mr5408891wrh.308.1591718535121; Tue, 09 Jun 2020 09:02:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/7] target/arm: Convert Neon 3-reg-diff prewidening ops to decodetree Date: Tue, 9 Jun 2020 17:02:04 +0100 Message-Id: <20200609160209.29960-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200609160209.29960-1-peter.maydell@linaro.org> References: <20200609160209.29960-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the "pre-widening" insns VADDL, VSUBL, VADDW and VSUBW in the Neon 3-registers-different-lengths group to decodetree. These insns work by widening one or both inputs to double their size, performing an add or subtract at the doubled size and then storing the double-size result. As usual, rather than copying the loop of the original decoder (which needs awkward code to avoid problems when source and destination registers overlap) we just unroll the two passes. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 43 +++++++++++++ target/arm/translate-neon.inc.c | 104 ++++++++++++++++++++++++++++++++ target/arm/translate.c | 16 ++--- 3 files changed, 151 insertions(+), 12 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index bd1b0e13f7d..144a527ee65 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -397,3 +397,46 @@ VCVT_FU_2sh 1111 001 1 1 . ...... .... 1111 0 . .= 1 .... @2reg_vcvt # So we have a single decode line and check the cmode/op in the # trans function. Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg= _imm + +###################################################################### +# Within the "two registers, or three registers of different lengths" +# grouping ([23,4]=3D0b10), bits [21:20] are either part of the opcode +# decode: 0b11 for VEXT, two-reg-misc, VTBL, and duplicate-scalar; +# or they are a size field for the three-reg-different-lengths and +# two-reg-and-scalar insn groups (where size cannot be 0b11). This +# is slightly awkward for decodetree: we handle it with this +# non-exclusive group which contains within it two exclusive groups: +# one for the size=3D0b11 patterns, and one for the size-not-0b11 +# patterns. This allows us to check that none of the insns within +# each subgroup accidentally overlap each other. Note that all the +# trans functions for the size-not-0b11 patterns must check and +# return false for size=3D=3D3. +###################################################################### +{ + # 0b11 subgroup will go here + + # Subgroup for size !=3D 0b11 + [ + ################################################################## + # 3-reg-different-length grouping: + # 1111 001 U 1 D sz!=3D11 Vn:4 Vd:4 opc:4 N 0 M 0 Vm:4 + ################################################################## + + &3diff vm vn vd size + + @3diff .... ... . . . size:2 .... .... .... . . . . .... \ + &3diff vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp + + VADDL_S_3d 1111 001 0 1 . .. .... .... 0000 . 0 . 0 .... @3diff + VADDL_U_3d 1111 001 1 1 . .. .... .... 0000 . 0 . 0 .... @3diff + + VADDW_S_3d 1111 001 0 1 . .. .... .... 0001 . 0 . 0 .... @3diff + VADDW_U_3d 1111 001 1 1 . .. .... .... 0001 . 0 . 0 .... @3diff + + VSUBL_S_3d 1111 001 0 1 . .. .... .... 0010 . 0 . 0 .... @3diff + VSUBL_U_3d 1111 001 1 1 . .. .... .... 0010 . 0 . 0 .... @3diff + + VSUBW_S_3d 1111 001 0 1 . .. .... .... 0011 . 0 . 0 .... @3diff + VSUBW_U_3d 1111 001 1 1 . .. .... .... 0011 . 0 . 0 .... @3diff + ] +} diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 299a61f067b..f0ec13e5a91 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1828,3 +1828,107 @@ static bool trans_Vimm_1r(DisasContext *s, arg_1reg= _imm *a) } return do_1reg_imm(s, a, fn); } + +static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, + NeonGenWidenFn *widenfn, + NeonGenTwo64OpFn *opfn, + bool src1_wide) +{ + /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW= ) */ + TCGv_i64 rn0_64, rn1_64, rm_64; + TCGv_i32 rm; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (!widenfn || !opfn) { + /* size =3D=3D 3 case, which is an entirely different insn group */ + return false; + } + + if ((a->vd & 1) || (src1_wide && (a->vn & 1))) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + rn0_64 =3D tcg_temp_new_i64(); + rn1_64 =3D tcg_temp_new_i64(); + rm_64 =3D tcg_temp_new_i64(); + + if (src1_wide) { + neon_load_reg64(rn0_64, a->vn); + } else { + TCGv_i32 tmp =3D neon_load_reg(a->vn, 0); + widenfn(rn0_64, tmp); + tcg_temp_free_i32(tmp); + } + rm =3D neon_load_reg(a->vm, 0); + + widenfn(rm_64, rm); + tcg_temp_free_i32(rm); + opfn(rn0_64, rn0_64, rm_64); + + /* + * Load second pass inputs before storing the first pass result, to + * avoid incorrect results if a narrow input overlaps with the result. + */ + if (src1_wide) { + neon_load_reg64(rn1_64, a->vn + 1); + } else { + TCGv_i32 tmp =3D neon_load_reg(a->vn, 1); + widenfn(rn1_64, tmp); + tcg_temp_free_i32(tmp); + } + rm =3D neon_load_reg(a->vm, 1); + + neon_store_reg64(rn0_64, a->vd); + + widenfn(rm_64, rm); + tcg_temp_free_i32(rm); + opfn(rn1_64, rn1_64, rm_64); + neon_store_reg64(rn1_64, a->vd + 1); + + tcg_temp_free_i64(rn0_64); + tcg_temp_free_i64(rn1_64); + tcg_temp_free_i64(rm_64); + + return true; +} + +#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \ + static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ + { \ + NeonGenWidenFn *widenfn[] =3D { \ + gen_helper_neon_widen_##S##8, \ + gen_helper_neon_widen_##S##16, \ + tcg_gen_##EXT##_i32_i64, \ + NULL, \ + }; \ + NeonGenTwo64OpFn *addfn[] =3D { \ + gen_helper_neon_##OP##l_u16, \ + gen_helper_neon_##OP##l_u32, \ + tcg_gen_##OP##_i64, \ + NULL, \ + }; \ + return do_prewiden_3d(s, a, widenfn[a->size], \ + addfn[a->size], SRC1WIDE); \ + } + +DO_PREWIDEN(VADDL_S, s, ext, add, false) +DO_PREWIDEN(VADDL_U, u, extu, add, false) +DO_PREWIDEN(VSUBL_S, s, ext, sub, false) +DO_PREWIDEN(VSUBL_U, u, extu, sub, false) +DO_PREWIDEN(VADDW_S, s, ext, add, true) +DO_PREWIDEN(VADDW_U, u, extu, add, true) +DO_PREWIDEN(VSUBW_S, s, ext, sub, true) +DO_PREWIDEN(VSUBW_U, u, extu, sub, true) diff --git a/target/arm/translate.c b/target/arm/translate.c index bcdfec34d28..93765344414 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5241,7 +5241,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) /* Three registers of different lengths. */ int src1_wide; int src2_wide; - int prewiden; /* undefreq: bit 0 : UNDEF if size =3D=3D 0 * bit 1 : UNDEF if size =3D=3D 1 * bit 2 : UNDEF if size =3D=3D 2 @@ -5251,10 +5250,10 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) int undefreq; /* prewiden, src1_wide, src2_wide, undefreq */ static const int neon_3reg_wide[16][4] =3D { - {1, 0, 0, 0}, /* VADDL */ - {1, 1, 0, 0}, /* VADDW */ - {1, 0, 0, 0}, /* VSUBL */ - {1, 1, 0, 0}, /* VSUBW */ + {0, 0, 0, 7}, /* VADDL: handled by decodetree */ + {0, 0, 0, 7}, /* VADDW: handled by decodetree */ + {0, 0, 0, 7}, /* VSUBL: handled by decodetree */ + {0, 0, 0, 7}, /* VSUBW: handled by decodetree */ {0, 1, 1, 0}, /* VADDHN */ {0, 0, 0, 0}, /* VABAL */ {0, 1, 1, 0}, /* VSUBHN */ @@ -5269,7 +5268,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) {0, 0, 0, 7}, /* Reserved: always UNDEF */ }; =20 - prewiden =3D neon_3reg_wide[op][0]; src1_wide =3D neon_3reg_wide[op][1]; src2_wide =3D neon_3reg_wide[op][2]; undefreq =3D neon_3reg_wide[op][3]; @@ -5322,9 +5320,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } else { tmp =3D neon_load_reg(rn, pass); } - if (prewiden) { - gen_neon_widen(cpu_V0, tmp, size, u); - } } if (src2_wide) { neon_load_reg64(cpu_V1, rm + pass); @@ -5335,9 +5330,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } else { tmp2 =3D neon_load_reg(rm, pass); } - if (prewiden) { - gen_neon_widen(cpu_V1, tmp2, size, u); - } } switch (op) { case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADD= HN */ --=20 2.20.1 From nobody Mon Feb 9 10:49:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b81sm3699867wmc.5.2020.06.09.09.02.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 09:02:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TFWTbg10WhHmc79yRA1SVMCWJi4UtxxtU8KvpJ5j2+U=; b=X7kM/e7tbbHb21/aYYwhhV3BYbOBVAVD/octas32dCl7wSy4ZG9og/YkvxLo9Yg8RD 6bfLx8ICiw2GD4U5l0mC1/A/6wV4mLYTceGCtVbG9KijuJrFk/jE2JEtu+hu8+zbk5cP V8osyZ+40nutYE/4qOqI7L5DtpAC7ku3aGc+zww3LcK3ANzhbivKSmcXCEJEFHVTMkuJ 60xDg6y1sK3qmKEN6HWWkm4SWfJmdocd5DIlrCOKawiuQzQQRiREMFOlbQ/6Kg9U8PNT GgvDPNz5VZALOlS07zE94DV8W+wfefKAFnRHITwOmt7TA2TMPFjAbqHd+qqHYKqWl2Qe 3s6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TFWTbg10WhHmc79yRA1SVMCWJi4UtxxtU8KvpJ5j2+U=; b=HdNA2VSXRjJDFUrWaedd2f0YHje/e6Wz35u4FexqAmvQauYH1D4m5R5jYv5Q8Ji6qe N0vUIxXCID40sXLRV8ZQvslsOacGDvVhiLrqxGLIIxiZDnKSvAhC77+U5xfRag0dgycZ GnxWd5kzXgBvtqJXDuQBD7ozib9KfMXU5XkgYFSxtz/idsRj1WiApm4j2IfoFXzhAVcd Gl2Wpt94gl0aU+9ioMlBkV7DHfvdWEsgghh3SWp3fWTWFh0kW0k+QAUuFzYPmOJsUlYC 2I/ZzDey0XJZF+28xGoUyxVj0/pk7g4WRv+2imZzPZrC1xLpNCi7lBVpQ9r3bUUCJBIk r7+Q== X-Gm-Message-State: AOAM531jpGQL7rWG9yU2bhLUuT8UClsUjFacTilTz8h0ijr/cbRbLoZk xWuv7zwey5M3q9prNfsX5s0Q0g== X-Google-Smtp-Source: ABdhPJxCQ/3x6OGfNYPDzf1EUKRaUrz/7esafLIeWu+2q7eWgpTgaWNFPiuhuLKCr2n+9gz+nsZJKQ== X-Received: by 2002:adf:9286:: with SMTP id 6mr5295006wrn.361.1591718536611; Tue, 09 Jun 2020 09:02:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/7] target/arm: Convert Neon 3-reg-diff narrowing ops to decodetree Date: Tue, 9 Jun 2020 17:02:05 +0100 Message-Id: <20200609160209.29960-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200609160209.29960-1-peter.maydell@linaro.org> References: <20200609160209.29960-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the narrow-to-high-half insns VADDHN, VSUBHN, VRADDHN, VRSUBHN in the Neon 3-registers-different-lengths group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 6 +++ target/arm/translate-neon.inc.c | 87 +++++++++++++++++++++++++++++++ target/arm/translate.c | 91 ++++----------------------------- 3 files changed, 104 insertions(+), 80 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 144a527ee65..a2234dfa4f3 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -438,5 +438,11 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0= . op:1 1 .... @1reg_imm =20 VSUBW_S_3d 1111 001 0 1 . .. .... .... 0011 . 0 . 0 .... @3diff VSUBW_U_3d 1111 001 1 1 . .. .... .... 0011 . 0 . 0 .... @3diff + + VADDHN_3d 1111 001 0 1 . .. .... .... 0100 . 0 . 0 .... @3diff + VRADDHN_3d 1111 001 1 1 . .. .... .... 0100 . 0 . 0 .... @3diff + + VSUBHN_3d 1111 001 0 1 . .. .... .... 0110 . 0 . 0 .... @3diff + VRSUBHN_3d 1111 001 1 1 . .. .... .... 0110 . 0 . 0 .... @3diff ] } diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index f0ec13e5a91..0033cb7eb25 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1932,3 +1932,90 @@ DO_PREWIDEN(VADDW_S, s, ext, add, true) DO_PREWIDEN(VADDW_U, u, extu, add, true) DO_PREWIDEN(VSUBW_S, s, ext, sub, true) DO_PREWIDEN(VSUBW_U, u, extu, sub, true) + +static bool do_narrow_3d(DisasContext *s, arg_3diff *a, + NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn) +{ + /* 3-regs different lengths, narrowing (VADDHN/VSUBHN/VRADDHN/VRSUBHN)= */ + TCGv_i64 rn_64, rm_64; + TCGv_i32 rd0, rd1; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (!opfn || !narrowfn) { + /* size =3D=3D 3 case, which is an entirely different insn group */ + return false; + } + + if ((a->vn | a->vm) & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + rn_64 =3D tcg_temp_new_i64(); + rm_64 =3D tcg_temp_new_i64(); + rd0 =3D tcg_temp_new_i32(); + rd1 =3D tcg_temp_new_i32(); + + neon_load_reg64(rn_64, a->vn); + neon_load_reg64(rm_64, a->vm); + + opfn(rn_64, rn_64, rm_64); + + narrowfn(rd0, rn_64); + + neon_load_reg64(rn_64, a->vn + 1); + neon_load_reg64(rm_64, a->vm + 1); + + opfn(rn_64, rn_64, rm_64); + + narrowfn(rd1, rn_64); + + neon_store_reg(a->vd, 0, rd0); + neon_store_reg(a->vd, 1, rd1); + + tcg_temp_free_i64(rn_64); + tcg_temp_free_i64(rm_64); + + return true; +} + +#define DO_NARROW_3D(INSN, OP, NARROWTYPE, EXTOP) \ + static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ + { \ + NeonGenTwo64OpFn *addfn[] =3D { \ + gen_helper_neon_##OP##l_u16, \ + gen_helper_neon_##OP##l_u32, \ + tcg_gen_##OP##_i64, \ + NULL, \ + }; \ + NeonGenNarrowFn *narrowfn[] =3D { \ + gen_helper_neon_##NARROWTYPE##_high_u8, \ + gen_helper_neon_##NARROWTYPE##_high_u16, \ + EXTOP, \ + NULL, \ + }; \ + return do_narrow_3d(s, a, addfn[a->size], narrowfn[a->size]); \ + } + +static void gen_narrow_round_high_u32(TCGv_i32 rd, TCGv_i64 rn) +{ + tcg_gen_addi_i64(rn, rn, 1u << 31); + tcg_gen_extrh_i64_i32(rd, rn); +} + +DO_NARROW_3D(VADDHN, add, narrow, tcg_gen_extrh_i64_i32) +DO_NARROW_3D(VSUBHN, sub, narrow, tcg_gen_extrh_i64_i32) +DO_NARROW_3D(VRADDHN, add, narrow_round, gen_narrow_round_high_u32) +DO_NARROW_3D(VRSUBHN, sub, narrow_round, gen_narrow_round_high_u32) diff --git a/target/arm/translate.c b/target/arm/translate.c index 93765344414..3fe39cd4f49 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3231,16 +3231,6 @@ static inline void gen_neon_addl(int size) } } =20 -static inline void gen_neon_subl(int size) -{ - switch (size) { - case 0: gen_helper_neon_subl_u16(CPU_V001); break; - case 1: gen_helper_neon_subl_u32(CPU_V001); break; - case 2: tcg_gen_sub_i64(CPU_V001); break; - default: abort(); - } -} - static inline void gen_neon_negl(TCGv_i64 var, int size) { switch (size) { @@ -5239,8 +5229,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) op =3D (insn >> 8) & 0xf; if ((insn & (1 << 6)) =3D=3D 0) { /* Three registers of different lengths. */ - int src1_wide; - int src2_wide; /* undefreq: bit 0 : UNDEF if size =3D=3D 0 * bit 1 : UNDEF if size =3D=3D 1 * bit 2 : UNDEF if size =3D=3D 2 @@ -5254,9 +5242,9 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) {0, 0, 0, 7}, /* VADDW: handled by decodetree */ {0, 0, 0, 7}, /* VSUBL: handled by decodetree */ {0, 0, 0, 7}, /* VSUBW: handled by decodetree */ - {0, 1, 1, 0}, /* VADDHN */ + {0, 0, 0, 7}, /* VADDHN: handled by decodetree */ {0, 0, 0, 0}, /* VABAL */ - {0, 1, 1, 0}, /* VSUBHN */ + {0, 0, 0, 7}, /* VSUBHN: handled by decodetree */ {0, 0, 0, 0}, /* VABDL */ {0, 0, 0, 0}, /* VMLAL */ {0, 0, 0, 9}, /* VQDMLAL */ @@ -5268,17 +5256,13 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) {0, 0, 0, 7}, /* Reserved: always UNDEF */ }; =20 - src1_wide =3D neon_3reg_wide[op][1]; - src2_wide =3D neon_3reg_wide[op][2]; undefreq =3D neon_3reg_wide[op][3]; =20 if ((undefreq & (1 << size)) || ((undefreq & 8) && u)) { return 1; } - if ((src1_wide && (rn & 1)) || - (src2_wide && (rm & 1)) || - (!src2_wide && (rd & 1))) { + if (rd & 1) { return 1; } =20 @@ -5302,42 +5286,26 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) /* Avoid overlapping operands. Wide source operands are always aligned so will never overlap with wide destinations in problematic ways. */ - if (rd =3D=3D rm && !src2_wide) { + if (rd =3D=3D rm) { tmp =3D neon_load_reg(rm, 1); neon_store_scratch(2, tmp); - } else if (rd =3D=3D rn && !src1_wide) { + } else if (rd =3D=3D rn) { tmp =3D neon_load_reg(rn, 1); neon_store_scratch(2, tmp); } tmp3 =3D NULL; for (pass =3D 0; pass < 2; pass++) { - if (src1_wide) { - neon_load_reg64(cpu_V0, rn + pass); - tmp =3D NULL; + if (pass =3D=3D 1 && rd =3D=3D rn) { + tmp =3D neon_load_scratch(2); } else { - if (pass =3D=3D 1 && rd =3D=3D rn) { - tmp =3D neon_load_scratch(2); - } else { - tmp =3D neon_load_reg(rn, pass); - } + tmp =3D neon_load_reg(rn, pass); } - if (src2_wide) { - neon_load_reg64(cpu_V1, rm + pass); - tmp2 =3D NULL; + if (pass =3D=3D 1 && rd =3D=3D rm) { + tmp2 =3D neon_load_scratch(2); } else { - if (pass =3D=3D 1 && rd =3D=3D rm) { - tmp2 =3D neon_load_scratch(2); - } else { - tmp2 =3D neon_load_reg(rm, pass); - } + tmp2 =3D neon_load_reg(rm, pass); } switch (op) { - case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADD= HN */ - gen_neon_addl(size); - break; - case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUB= HN */ - gen_neon_subl(size); - break; case 5: case 7: /* VABAL, VABDL */ switch ((size << 1) | u) { case 0: @@ -5395,43 +5363,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) abort(); } neon_store_reg64(cpu_V0, rd + pass); - } else if (op =3D=3D 4 || op =3D=3D 6) { - /* Narrowing operation. */ - tmp =3D tcg_temp_new_i32(); - if (!u) { - switch (size) { - case 0: - gen_helper_neon_narrow_high_u8(tmp, cpu_V0= ); - break; - case 1: - gen_helper_neon_narrow_high_u16(tmp, cpu_V= 0); - break; - case 2: - tcg_gen_extrh_i64_i32(tmp, cpu_V0); - break; - default: abort(); - } - } else { - switch (size) { - case 0: - gen_helper_neon_narrow_round_high_u8(tmp, = cpu_V0); - break; - case 1: - gen_helper_neon_narrow_round_high_u16(tmp,= cpu_V0); - break; - case 2: - tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31); - tcg_gen_extrh_i64_i32(tmp, cpu_V0); - break; - default: abort(); - } - } - if (pass =3D=3D 0) { - tmp3 =3D tmp; - } else { - neon_store_reg(rd, 0, tmp3); - neon_store_reg(rd, 1, tmp); - } } else { /* Write back the result. */ neon_store_reg64(cpu_V0, rd + pass); --=20 2.20.1 From nobody Mon Feb 9 10:49:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1591718995; cv=none; d=zohomail.com; s=zohoarc; b=UL14Ef6IpUjfeVPQVsLGf20jb962VqYVX9yPeBwuIV7IRgLsZbtU4roHGT1f1WmIZnA1yDfZAPTZZssEmqTNvH715dS4T/melJFK2hFcCCZztBSqdDwn3BFbj65H7HZV24gw5xo4tAdOl2t3X97tgUpJng33UR0zvoyVHV7iTHQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591718995; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yD3aBUk/yUeo1kZA43j/pO6AQgeHZtAwzYiFa/0q35M=; b=OLfIh2mu0q8pAZWtidumVeVq/9UE53ZfM1ifDXwN/OnDD/wJ7dSPt4nz7ZJhRdO/l/Xm7Jhl060Wh6tdY17gq1g5FkN36hvHydVWvk4555APoxl2jaMhISH+uFcjChBVselXotucTKFyG/NDmsCSAvPgZ73V17Odo/9rEGC8G8E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591718995424787.8301690089659; Tue, 9 Jun 2020 09:09:55 -0700 (PDT) Received: from localhost ([::1]:49422 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jigoz-0004YV-UO for importer@patchew.org; Tue, 09 Jun 2020 12:09:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42732) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jighj-0003O3-Gg for qemu-devel@nongnu.org; Tue, 09 Jun 2020 12:02:23 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:45368) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jighh-0003R5-7e for qemu-devel@nongnu.org; Tue, 09 Jun 2020 12:02:22 -0400 Received: by mail-wr1-x442.google.com with SMTP id c3so21894488wru.12 for ; Tue, 09 Jun 2020 09:02:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b81sm3699867wmc.5.2020.06.09.09.02.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 09:02:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yD3aBUk/yUeo1kZA43j/pO6AQgeHZtAwzYiFa/0q35M=; b=nz2w1SWQWHqYskpdJnxuaKFNq/XM9UEfBvJSk+evtr8QUe3UZl8YIhoeUv4zKjVIaN NmFFyrkKhL38gqjlJ4Yq/dkbzaY6ki+QJA0p69QVNs8cZMMbBrVr12olEHy/kIO7lgth 0dwzF/QHa9eNcbdwS6tVsR1voSM9dOXYGh5t3WjIVGcZuZ7gzPb1mrry8urNMNC1Vv2j jzu2ng6LwQ8meSCijok+s4IyVCUMppE9wooRgI+OMCiFhmdTghaGJiEruqi3ATzgpjCq 1HiyDmG7tQYQZGOJWWg81LboY2cutQnbgH3Tu1NvL16bzhO2S91n4aJUCw+Z09huktUY wt3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yD3aBUk/yUeo1kZA43j/pO6AQgeHZtAwzYiFa/0q35M=; b=KyPa33FL5cCx3F/SuWNUvSDtchIDZCVL6JBDTlxDzFjYxYSe5BvQSMVPwRhklLEbFZ M8p+QdIT8VBsuGj5C5yM0/OG5nYoWQ0dWg/gCdw/y224DMbsvOGrW6JUxbglRpClObq3 uAz/bU89fBkPvh1wPNQ9XUsbNTzj+NZ+aiFNJY2AzpDgJrQVPpBEJKvjz6XjhZZzAHsG EzzOybOomyqgWnrVMKkDihynI8ZqqVCEOXBu8CtP55Hjd7sh7Wel6Rc8ddITcdDmvHUp deWSktg85YAHyjP+p5CwYzy+N4pw4CzEZgdKJOgd+3zuRzJdOBuZcWCd2Tygxcx/+yhf eJfA== X-Gm-Message-State: AOAM530X4m291C1AVqtve6QnPY/EIfNWiLV7Nehcu9hqNwunb+Bhek6h InX0ChWjcJ9vcHST7l++/mUBUw== X-Google-Smtp-Source: ABdhPJxrg+e3DW2UpXAp8n+izM4KdVheBOMGF8JzLI2IDw8QKJC3sj+gU94uOZoYWMQpfgjLXnMxYg== X-Received: by 2002:adf:e587:: with SMTP id l7mr5302455wrm.352.1591718538041; Tue, 09 Jun 2020 09:02:18 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/7] target/arm: Convert Neon 3-reg-diff VABAL, VABDL to decodetree Date: Tue, 9 Jun 2020 17:02:06 +0100 Message-Id: <20200609160209.29960-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200609160209.29960-1-peter.maydell@linaro.org> References: <20200609160209.29960-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon 3-reg-diff insns VABAL and VABDL to decodetree. Like almost all the remaining insns in this group, these are a combination of a two-input operation which returns a double width result and then a possible accumulation of that double width result into the destination. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.h | 1 + target/arm/neon-dp.decode | 6 ++ target/arm/translate-neon.inc.c | 132 ++++++++++++++++++++++++++++++++ target/arm/translate.c | 31 +------- 4 files changed, 142 insertions(+), 28 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index c937dfe9bf0..62ed5c4780c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -371,6 +371,7 @@ typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TC= Gv_i64, TCGv_i64); typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); +typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index a2234dfa4f3..4f0aaaf6bb2 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -442,7 +442,13 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0= . op:1 1 .... @1reg_imm VADDHN_3d 1111 001 0 1 . .. .... .... 0100 . 0 . 0 .... @3diff VRADDHN_3d 1111 001 1 1 . .. .... .... 0100 . 0 . 0 .... @3diff =20 + VABAL_S_3d 1111 001 0 1 . .. .... .... 0101 . 0 . 0 .... @3diff + VABAL_U_3d 1111 001 1 1 . .. .... .... 0101 . 0 . 0 .... @3diff + VSUBHN_3d 1111 001 0 1 . .. .... .... 0110 . 0 . 0 .... @3diff VRSUBHN_3d 1111 001 1 1 . .. .... .... 0110 . 0 . 0 .... @3diff + + VABDL_S_3d 1111 001 0 1 . .. .... .... 0111 . 0 . 0 .... @3diff + VABDL_U_3d 1111 001 1 1 . .. .... .... 0111 . 0 . 0 .... @3diff ] } diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 0033cb7eb25..fd85ff5ea50 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -2019,3 +2019,135 @@ DO_NARROW_3D(VADDHN, add, narrow, tcg_gen_extrh_i64= _i32) DO_NARROW_3D(VSUBHN, sub, narrow, tcg_gen_extrh_i64_i32) DO_NARROW_3D(VRADDHN, add, narrow_round, gen_narrow_round_high_u32) DO_NARROW_3D(VRSUBHN, sub, narrow_round, gen_narrow_round_high_u32) + +static bool do_long_3d(DisasContext *s, arg_3diff *a, + NeonGenTwoOpWidenFn *opfn, + NeonGenTwo64OpFn *accfn) +{ + /* + * 3-regs different lengths, long operations. + * These perform an operation on two inputs that returns a double-width + * result, and then possibly perform an accumulation operation of + * that result into the double-width destination. + */ + TCGv_i64 rd0, rd1, tmp; + TCGv_i32 rn, rm; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (!opfn) { + /* size =3D=3D 3 case, which is an entirely different insn group */ + return false; + } + + if (a->vd & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + rd0 =3D tcg_temp_new_i64(); + rd1 =3D tcg_temp_new_i64(); + + rn =3D neon_load_reg(a->vn, 0); + rm =3D neon_load_reg(a->vm, 0); + opfn(rd0, rn, rm); + tcg_temp_free_i32(rn); + tcg_temp_free_i32(rm); + + rn =3D neon_load_reg(a->vn, 1); + rm =3D neon_load_reg(a->vm, 1); + opfn(rd1, rn, rm); + tcg_temp_free_i32(rn); + tcg_temp_free_i32(rm); + + /* Don't store results until after all loads: they might overlap */ + if (accfn) { + tmp =3D tcg_temp_new_i64(); + neon_load_reg64(tmp, a->vd); + accfn(tmp, tmp, rd0); + neon_store_reg64(tmp, a->vd); + neon_load_reg64(tmp, a->vd + 1); + accfn(tmp, tmp, rd1); + neon_store_reg64(tmp, a->vd + 1); + tcg_temp_free_i64(tmp); + } else { + neon_store_reg64(rd0, a->vd); + neon_store_reg64(rd1, a->vd + 1); + } + + tcg_temp_free_i64(rd0); + tcg_temp_free_i64(rd1); + + return true; +} + +static bool trans_VABDL_S_3d(DisasContext *s, arg_3diff *a) +{ + NeonGenTwoOpWidenFn *opfn[] =3D { + gen_helper_neon_abdl_s16, + gen_helper_neon_abdl_s32, + gen_helper_neon_abdl_s64, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], NULL); +} + +static bool trans_VABDL_U_3d(DisasContext *s, arg_3diff *a) +{ + NeonGenTwoOpWidenFn *opfn[] =3D { + gen_helper_neon_abdl_u16, + gen_helper_neon_abdl_u32, + gen_helper_neon_abdl_u64, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], NULL); +} + +static bool trans_VABAL_S_3d(DisasContext *s, arg_3diff *a) +{ + NeonGenTwoOpWidenFn *opfn[] =3D { + gen_helper_neon_abdl_s16, + gen_helper_neon_abdl_s32, + gen_helper_neon_abdl_s64, + NULL, + }; + NeonGenTwo64OpFn *addfn[] =3D { + gen_helper_neon_addl_u16, + gen_helper_neon_addl_u32, + tcg_gen_add_i64, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], addfn[a->size]); +} + +static bool trans_VABAL_U_3d(DisasContext *s, arg_3diff *a) +{ + NeonGenTwoOpWidenFn *opfn[] =3D { + gen_helper_neon_abdl_u16, + gen_helper_neon_abdl_u32, + gen_helper_neon_abdl_u64, + NULL, + }; + NeonGenTwo64OpFn *addfn[] =3D { + gen_helper_neon_addl_u16, + gen_helper_neon_addl_u32, + tcg_gen_add_i64, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], addfn[a->size]); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 3fe39cd4f49..37fe9d46e0b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5243,9 +5243,9 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) {0, 0, 0, 7}, /* VSUBL: handled by decodetree */ {0, 0, 0, 7}, /* VSUBW: handled by decodetree */ {0, 0, 0, 7}, /* VADDHN: handled by decodetree */ - {0, 0, 0, 0}, /* VABAL */ + {0, 0, 0, 7}, /* VABAL */ {0, 0, 0, 7}, /* VSUBHN: handled by decodetree */ - {0, 0, 0, 0}, /* VABDL */ + {0, 0, 0, 7}, /* VABDL */ {0, 0, 0, 0}, /* VMLAL */ {0, 0, 0, 9}, /* VQDMLAL */ {0, 0, 0, 0}, /* VMLSL */ @@ -5306,31 +5306,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tmp2 =3D neon_load_reg(rm, pass); } switch (op) { - case 5: case 7: /* VABAL, VABDL */ - switch ((size << 1) | u) { - case 0: - gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2); - break; - case 1: - gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2); - break; - case 2: - gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2); - break; - case 3: - gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2); - break; - case 4: - gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2); - break; - case 5: - gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2); - break; - default: abort(); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - break; case 8: case 9: case 10: case 11: case 12: case 13: /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL = */ gen_neon_mull(cpu_V0, tmp, tmp2, size, u); @@ -5349,7 +5324,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case 10: /* VMLSL */ gen_neon_negl(cpu_V0, size); /* Fall through */ - case 5: case 8: /* VABAL, VMLAL */ + case 8: /* VABAL, VMLAL */ gen_neon_addl(size); break; case 9: case 11: /* VQDMLAL, VQDMLSL */ --=20 2.20.1 From nobody Mon Feb 9 10:49:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b81sm3699867wmc.5.2020.06.09.09.02.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 09:02:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dFdsf0awDgnbeOkGxCbfVxPQlEMuI1Pc0StnYKQsJXk=; b=plqyZ/e/j8vvVISc9MRbUHnO3fEOPdZJAGOUPm1tHiKt7qBZthaswMskYZ46g71KW7 9DRH1UqQA+BZ+pXc1EiY0kczgX3belM+1gR/sOKYO1cn1AxgEkEI5IBeCN0pa5dhbTRA Fb5ksXAOs695+9/mDpneAOtU05AyF062hIRcTkBd6FTDnqAeFkVYQFRB09pymjQLzU90 f02HOAF/847889wDg6ZXB7KDDGBiNn6nnI54dtn2iH0BoWFjibgDDFjc2tcIqrylRZc/ BZs6DcqUAVzyOFOzdtn+0w70P8sGEHd4PsZvEt4l9yf2UMIIjUrBMuASHX/YfmxSHEYl 3Ncg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dFdsf0awDgnbeOkGxCbfVxPQlEMuI1Pc0StnYKQsJXk=; b=KBGkMD1BjRM6kBAkgKBVMS3iAGSXT9a+ncBxHnQ6vsaGaUq8xJMkxlT10dh1ieHPvG bmOwPQBw7LLAH34ADiFsM77mKGfoV/f8iU0VZmIS9gvfJ+qLNZOQwndnHGrXFeqRRnK0 iWGK2jOjVAaOYrLPKp3FMcOi08vRFxN10T0uT2hgcA8JqMkkHhaClLdcqugAUTzWCajT KsKqamv/JjN5njb36xdldmOS43as69NlDciKQMTV47TKzcLMTC0Mn2t/cELxrtSWS1Po /Nmf41/KuQBVgqu/kCrryJ6H8n09Zf5NinnKeXjhAg+Cr40Fz3kJdaiW9St4ydRAS9Y6 JhNA== X-Gm-Message-State: AOAM532cJf1EsakxbDuNLWRcWrKG0Fah56ArvbX8n8VxBrHcUWv5S7gk iQk3dGeHQIWeFtUm7Z0JyqSX9A== X-Google-Smtp-Source: ABdhPJzbM/H5/OcfIe4DhDUQ6J+Ez9QrasSyusRi9/HBZsuJfeKHaTM39AyNTEyzxRW8KqQmaIfBOg== X-Received: by 2002:a05:600c:2110:: with SMTP id u16mr4694096wml.26.1591718539489; Tue, 09 Jun 2020 09:02:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/7] target/arm: Convert Neon 3-reg-diff long multiplies Date: Tue, 9 Jun 2020 17:02:07 +0100 Message-Id: <20200609160209.29960-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200609160209.29960-1-peter.maydell@linaro.org> References: <20200609160209.29960-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon 3-reg-diff insns VMULL, VMLAL and VMLSL; these perform a 32x32->64 multiply with possible accumulate. Note that for VMLSL we do the accumulate directly with a subtraction rather than doing a negate-then-add as the old code did. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 9 +++++ target/arm/translate-neon.inc.c | 71 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 21 +++------- 3 files changed, 86 insertions(+), 15 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 4f0aaaf6bb2..1da492df146 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -450,5 +450,14 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0= . op:1 1 .... @1reg_imm =20 VABDL_S_3d 1111 001 0 1 . .. .... .... 0111 . 0 . 0 .... @3diff VABDL_U_3d 1111 001 1 1 . .. .... .... 0111 . 0 . 0 .... @3diff + + VMLAL_S_3d 1111 001 0 1 . .. .... .... 1000 . 0 . 0 .... @3diff + VMLAL_U_3d 1111 001 1 1 . .. .... .... 1000 . 0 . 0 .... @3diff + + VMLSL_S_3d 1111 001 0 1 . .. .... .... 1010 . 0 . 0 .... @3diff + VMLSL_U_3d 1111 001 1 1 . .. .... .... 1010 . 0 . 0 .... @3diff + + VMULL_S_3d 1111 001 0 1 . .. .... .... 1100 . 0 . 0 .... @3diff + VMULL_U_3d 1111 001 1 1 . .. .... .... 1100 . 0 . 0 .... @3diff ] } diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index fd85ff5ea50..00a779c65a0 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -2151,3 +2151,74 @@ static bool trans_VABAL_U_3d(DisasContext *s, arg_3d= iff *a) =20 return do_long_3d(s, a, opfn[a->size], addfn[a->size]); } + +static void gen_mull_s32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) +{ + TCGv_i32 lo =3D tcg_temp_new_i32(); + TCGv_i32 hi =3D tcg_temp_new_i32(); + + tcg_gen_muls2_i32(lo, hi, rn, rm); + tcg_gen_concat_i32_i64(rd, lo, hi); + + tcg_temp_free_i32(lo); + tcg_temp_free_i32(hi); +} + +static void gen_mull_u32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) +{ + TCGv_i32 lo =3D tcg_temp_new_i32(); + TCGv_i32 hi =3D tcg_temp_new_i32(); + + tcg_gen_mulu2_i32(lo, hi, rn, rm); + tcg_gen_concat_i32_i64(rd, lo, hi); + + tcg_temp_free_i32(lo); + tcg_temp_free_i32(hi); +} + +static bool trans_VMULL_S_3d(DisasContext *s, arg_3diff *a) +{ + NeonGenTwoOpWidenFn *opfn[] =3D { + gen_helper_neon_mull_s8, + gen_helper_neon_mull_s16, + gen_mull_s32, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], NULL); +} + +static bool trans_VMULL_U_3d(DisasContext *s, arg_3diff *a) +{ + NeonGenTwoOpWidenFn *opfn[] =3D { + gen_helper_neon_mull_u8, + gen_helper_neon_mull_u16, + gen_mull_u32, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], NULL); +} + +#define DO_VMLAL(INSN,MULL,ACC) \ + static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ + { \ + NeonGenTwoOpWidenFn *opfn[] =3D { \ + gen_helper_neon_##MULL##8, \ + gen_helper_neon_##MULL##16, \ + gen_##MULL##32, \ + NULL, \ + }; \ + NeonGenTwo64OpFn *accfn[] =3D { \ + gen_helper_neon_##ACC##l_u16, \ + gen_helper_neon_##ACC##l_u32, \ + tcg_gen_##ACC##_i64, \ + NULL, \ + }; \ + return do_long_3d(s, a, opfn[a->size], accfn[a->size]); \ + } + +DO_VMLAL(VMLAL_S,mull_s,add) +DO_VMLAL(VMLAL_U,mull_u,add) +DO_VMLAL(VMLSL_S,mull_s,sub) +DO_VMLAL(VMLSL_U,mull_u,sub) diff --git a/target/arm/translate.c b/target/arm/translate.c index 37fe9d46e0b..a2c47d19f21 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5246,11 +5246,11 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) {0, 0, 0, 7}, /* VABAL */ {0, 0, 0, 7}, /* VSUBHN: handled by decodetree */ {0, 0, 0, 7}, /* VABDL */ - {0, 0, 0, 0}, /* VMLAL */ + {0, 0, 0, 7}, /* VMLAL */ {0, 0, 0, 9}, /* VQDMLAL */ - {0, 0, 0, 0}, /* VMLSL */ + {0, 0, 0, 7}, /* VMLSL */ {0, 0, 0, 9}, /* VQDMLSL */ - {0, 0, 0, 0}, /* Integer VMULL */ + {0, 0, 0, 7}, /* Integer VMULL */ {0, 0, 0, 9}, /* VQDMULL */ {0, 0, 0, 0xa}, /* Polynomial VMULL */ {0, 0, 0, 7}, /* Reserved: always UNDEF */ @@ -5306,8 +5306,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) tmp2 =3D neon_load_reg(rm, pass); } switch (op) { - case 8: case 9: case 10: case 11: case 12: case 13: - /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL = */ + case 9: case 11: case 13: + /* VQDMLAL, VQDMLSL, VQDMULL */ gen_neon_mull(cpu_V0, tmp, tmp2, size, u); break; default: /* 15 is RESERVED: caught earlier */ @@ -5317,16 +5317,10 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) /* VQDMULL */ gen_neon_addl_saturate(cpu_V0, cpu_V0, size); neon_store_reg64(cpu_V0, rd + pass); - } else if (op =3D=3D 5 || (op >=3D 8 && op <=3D 11)) { + } else { /* Accumulate. */ neon_load_reg64(cpu_V1, rd + pass); switch (op) { - case 10: /* VMLSL */ - gen_neon_negl(cpu_V0, size); - /* Fall through */ - case 8: /* VABAL, VMLAL */ - gen_neon_addl(size); - break; case 9: case 11: /* VQDMLAL, VQDMLSL */ gen_neon_addl_saturate(cpu_V0, cpu_V0, size); if (op =3D=3D 11) { @@ -5338,9 +5332,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) abort(); } neon_store_reg64(cpu_V0, rd + pass); - } else { - /* Write back the result. */ - neon_store_reg64(cpu_V0, rd + pass); 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b81sm3699867wmc.5.2020.06.09.09.02.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 09:02:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S5WzoDYbeVcdXuyj3sF0aRlTViUlM9wFEwqSYBzRTDk=; b=Wl7jLXbaFHltntG2sRu3d5abw6E3ZYazurZyGEwXA4nWRa8Ydfx2rVOZlbs1+8psv1 kCWC5Xr8dZIOtp3SHr06ZA2tXHG3fO8+V3I8nYlqTM49rdsqHdkCIMlBeEqARv0q1ZB6 O5qhdtcGSTmToz2JOz/IaM0e5/Q0ScxP7Fn5f6jp0Lf0LEjVLqb9FXDrGfq+Q9JLM/l9 rX01RS9vs3kVrJpl236/PYg6nqEDGqjkVnAB3sTYiYVfH9gkbnY0Xt1Y2fjgFdOtYiMm wnKWjDLJLtYKN3N2zA0Y6OQRJhe97YIozZGIWY2j0wE7ho2nyXbJLFwNA5nm+19NX1qZ MO9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S5WzoDYbeVcdXuyj3sF0aRlTViUlM9wFEwqSYBzRTDk=; b=YxoKS2FnvlTvTbstdlOl7R8lh7gxCoRhpK2msdXLhFdt3kai33yMY/guFxNsvCBXlY lduwyihsrk+kcCDsT1vv74YQ0PLFvxnhIQJ2hljqeCyrUciUgeoS5HwPv7vTvvYGHxuZ gQfvHgrBFwv0TqttfrLNrKTwNHsmplHf+vo1KcfMi7On6pQ2JTYbK+SiJa5UkCKRQkcA m4do9tmqfnq1BOKUcVkiScuqPY/UZU6BcGTY4KnGKIVaOXJDy9U8Bnmz3srs7oLYKL3/ wsCyRZN/GnZ4H69su0Rmj0dabacKQLtwwzyK2pQ4aMJ7TqrK5ttdRQvbOTqzlHATxVs2 VIkg== X-Gm-Message-State: AOAM531W+qDursgy5TyVtifxXIvfEmiKUwgTng1MjO89rbGuNyig82mQ oMExsjrLkz1kXGpPEqCqdrFekQ== X-Google-Smtp-Source: ABdhPJxRJ3lqhb+gKu71N1z//53msZj2pp3V46o+Ob1oeCuT01kwQ+fi/AMIHmskm/lTxH3fK/uV3w== X-Received: by 2002:a5d:4948:: with SMTP id r8mr5111561wrs.290.1591718540792; Tue, 09 Jun 2020 09:02:20 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 6/7] target/arm: Convert Neon 3-reg-diff saturating doubling multiplies Date: Tue, 9 Jun 2020 17:02:08 +0100 Message-Id: <20200609160209.29960-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200609160209.29960-1-peter.maydell@linaro.org> References: <20200609160209.29960-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon 3-reg-diff insns VQDMULL, VQDMLAL and VQDMLSL: these are all saturating doubling long multiplies with a possible accumulate step. These are the last insns in the group which use the pass-over-each elements loop, so we can delete that code. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 6 +++ target/arm/translate-neon.inc.c | 82 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 59 ++---------------------- 3 files changed, 92 insertions(+), 55 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 1da492df146..65ea30d3edf 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -454,10 +454,16 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 = 0 . op:1 1 .... @1reg_imm VMLAL_S_3d 1111 001 0 1 . .. .... .... 1000 . 0 . 0 .... @3diff VMLAL_U_3d 1111 001 1 1 . .. .... .... 1000 . 0 . 0 .... @3diff =20 + VQDMLAL_3d 1111 001 0 1 . .. .... .... 1001 . 0 . 0 .... @3diff + VMLSL_S_3d 1111 001 0 1 . .. .... .... 1010 . 0 . 0 .... @3diff VMLSL_U_3d 1111 001 1 1 . .. .... .... 1010 . 0 . 0 .... @3diff =20 + VQDMLSL_3d 1111 001 0 1 . .. .... .... 1011 . 0 . 0 .... @3diff + VMULL_S_3d 1111 001 0 1 . .. .... .... 1100 . 0 . 0 .... @3diff VMULL_U_3d 1111 001 1 1 . .. .... .... 1100 . 0 . 0 .... @3diff + + VQDMULL_3d 1111 001 0 1 . .. .... .... 1101 . 0 . 0 .... @3diff ] } diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 00a779c65a0..5965b5ed845 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -2222,3 +2222,85 @@ DO_VMLAL(VMLAL_S,mull_s,add) DO_VMLAL(VMLAL_U,mull_u,add) DO_VMLAL(VMLSL_S,mull_s,sub) DO_VMLAL(VMLSL_U,mull_u,sub) + +static void gen_VQDMULL_16(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) +{ + gen_helper_neon_mull_s16(rd, rn, rm); + gen_helper_neon_addl_saturate_s32(rd, cpu_env, rd, rd); +} + +static void gen_VQDMULL_32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) +{ + gen_mull_s32(rd, rn, rm); + gen_helper_neon_addl_saturate_s64(rd, cpu_env, rd, rd); +} + +static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a) +{ + NeonGenTwoOpWidenFn *opfn[] =3D { + NULL, + gen_VQDMULL_16, + gen_VQDMULL_32, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], NULL); +} + +static void gen_VQDMLAL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm); +} + +static void gen_VQDMLAL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm); +} + +static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a) +{ + NeonGenTwoOpWidenFn *opfn[] =3D { + NULL, + gen_VQDMULL_16, + gen_VQDMULL_32, + NULL, + }; + NeonGenTwo64OpFn *accfn[] =3D { + NULL, + gen_VQDMLAL_acc_16, + gen_VQDMLAL_acc_32, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], accfn[a->size]); +} + +static void gen_VQDMLSL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + gen_helper_neon_negl_u32(rm, rm); + gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm); +} + +static void gen_VQDMLSL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + tcg_gen_neg_i64(rm, rm); + gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm); +} + +static bool trans_VQDMLSL_3d(DisasContext *s, arg_3diff *a) +{ + NeonGenTwoOpWidenFn *opfn[] =3D { + NULL, + gen_VQDMULL_16, + gen_VQDMULL_32, + NULL, + }; + NeonGenTwo64OpFn *accfn[] =3D { + NULL, + gen_VQDMLSL_acc_16, + gen_VQDMLSL_acc_32, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], accfn[a->size]); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index a2c47d19f21..88e91845c02 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5247,11 +5247,11 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) {0, 0, 0, 7}, /* VSUBHN: handled by decodetree */ {0, 0, 0, 7}, /* VABDL */ {0, 0, 0, 7}, /* VMLAL */ - {0, 0, 0, 9}, /* VQDMLAL */ + {0, 0, 0, 7}, /* VQDMLAL */ {0, 0, 0, 7}, /* VMLSL */ - {0, 0, 0, 9}, /* VQDMLSL */ + {0, 0, 0, 7}, /* VQDMLSL */ {0, 0, 0, 7}, /* Integer VMULL */ - {0, 0, 0, 9}, /* VQDMULL */ + {0, 0, 0, 7}, /* VQDMULL */ {0, 0, 0, 0xa}, /* Polynomial VMULL */ {0, 0, 0, 7}, /* Reserved: always UNDEF */ }; @@ -5282,58 +5282,7 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) } return 0; } - - /* Avoid overlapping operands. Wide source operands are - always aligned so will never overlap with wide - destinations in problematic ways. */ - if (rd =3D=3D rm) { - tmp =3D neon_load_reg(rm, 1); - neon_store_scratch(2, tmp); - } else if (rd =3D=3D rn) { - tmp =3D neon_load_reg(rn, 1); - neon_store_scratch(2, tmp); - } - tmp3 =3D NULL; - for (pass =3D 0; pass < 2; pass++) { - if (pass =3D=3D 1 && rd =3D=3D rn) { - tmp =3D neon_load_scratch(2); - } else { - tmp =3D neon_load_reg(rn, pass); - } - if (pass =3D=3D 1 && rd =3D=3D rm) { - tmp2 =3D neon_load_scratch(2); - } else { - tmp2 =3D neon_load_reg(rm, pass); - } - switch (op) { - case 9: case 11: case 13: - /* VQDMLAL, VQDMLSL, VQDMULL */ - gen_neon_mull(cpu_V0, tmp, tmp2, size, u); - break; - default: /* 15 is RESERVED: caught earlier */ - abort(); - } - if (op =3D=3D 13) { - /* VQDMULL */ - gen_neon_addl_saturate(cpu_V0, cpu_V0, size); - neon_store_reg64(cpu_V0, rd + pass); - } else { - /* Accumulate. */ - neon_load_reg64(cpu_V1, rd + pass); - switch (op) { - case 9: case 11: /* VQDMLAL, VQDMLSL */ - gen_neon_addl_saturate(cpu_V0, cpu_V0, size); - if (op =3D=3D 11) { - gen_neon_negl(cpu_V0, size); - } - gen_neon_addl_saturate(cpu_V0, cpu_V1, size); - break; - default: - abort(); - } - neon_store_reg64(cpu_V0, rd + pass); - } - } + abort(); /* all others handled by decodetree */ } else { /* Two registers and a scalar. NB that for ops of this form * the ARM ARM labels bit 24 as Q, but it is in our variab= le --=20 2.20.1 From nobody Mon Feb 9 10:49:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1591719190; cv=none; d=zohomail.com; s=zohoarc; b=XW9vGW9m/SOCwk8JALC16BQ/og86owmdCyk7bSpNyRMIXqUfJiuGvzAAoEXi5qPu0x2zvFehSUQoZ1//9XlmdXqo6crOOxW5OggRLtfn+/4vQ4v2nlrbexuWFICLV+ksTF1uw++8765AmiJU62bOkfADjArbe1KvziG99GKePeU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591719190; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4BxyhI/HWfoITPOBcBEsWHge5VKsc4W1GIwr7qvVtEk=; b=WksR98pdB32lhn18VO4v3YgQtFIaon6ZL6Ebp4vFcLHGWLAmxjWd5E1SrieQ/wc7erCo/HZ2vgGy7fSw6cEWeM0oqzdmXWAuIBW46IYNWL8IhyJ6WDLwf28kd3KztJGAqkd9w3XYPVlpaCfSmiplL95MOP/S6RAKkjga36qU2qc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591719190866416.70229860212135; Tue, 9 Jun 2020 09:13:10 -0700 (PDT) Received: from localhost ([::1]:56836 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jigs8-0007rV-2D for importer@patchew.org; Tue, 09 Jun 2020 12:13:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42750) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jighl-0003QF-Bq for qemu-devel@nongnu.org; Tue, 09 Jun 2020 12:02:25 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:51921) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jighk-0003S9-1M for qemu-devel@nongnu.org; Tue, 09 Jun 2020 12:02:24 -0400 Received: by mail-wm1-x344.google.com with SMTP id u13so3364317wml.1 for ; Tue, 09 Jun 2020 09:02:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b81sm3699867wmc.5.2020.06.09.09.02.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 09:02:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4BxyhI/HWfoITPOBcBEsWHge5VKsc4W1GIwr7qvVtEk=; b=U0Vi58wMh2szpgpW6gLa5+IUnXLA7WbmBmkIfMdN/VBGeAV7I3zL/mcRDOml4WrHcK cu+Vkhnl5cfNBxoqumm69X1mu6NDjCjykwUHfn1pxcRzvFPuws6x0zA82N4jfVyz+s0g 34t8oaQ21r4hX+7Wzeo4+6DWdRBX/czj10rUz1TJHqt8del95InkmupaltA4ZrDD+wz8 G4RWFo1+ypK48C3YEqegU16OFKkhanv3fAHg238x8MYwAS/XmMsxnRTpsi124D8i++ng zyANMIj5xCsxz+Wpa94S9TdWu1eshnLee7K/tLZleGvW2IZBs4xvH97JTpV1xzkGRzJ4 lg7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4BxyhI/HWfoITPOBcBEsWHge5VKsc4W1GIwr7qvVtEk=; b=CwZI7lueaQHm/6RbvfSNITBJYO8H6XA9uLxlRby7vkSy6J9zANtFuNH8hSZlaXmUJJ BqGnjuOL+m8nDkKzQx0nn5d0qrMepKzJ0mIRFw1qZBu+8qjCyyLRRVIKm5fCgp8bqL5y /bq+hYvUCMbTVVr97ysz1shpE/83+NFDaAOsOrUcwdP01pf5EF/4nlBKvrL+vVHh7gkR joU1IoHds+CokjC7MwTYMeNRI5WUScr8ASSYJvL0/NY0ccOayaLffvVid5RpKgOZ9chU zqQqdfh5lzMrebMIUjJlmqyVkra6/b3R9klVTSkUcI7pjXTU8sEogp+SPbJtSGfPZQoH qbCw== X-Gm-Message-State: AOAM533WkuGx6boNkS0wIlEoOIlLQUu3c5hZs5TeDpG9jrMzjbVBzvyq rRr1marT82+agWTuA0PfgsQ/9A== X-Google-Smtp-Source: ABdhPJzu3HAtqxJ852+lgKj7oRhV4kLkhR5kjc5BgpN6uJRxxgPyQx0SRDYtZ9ceLnMCWhoPTK38yw== X-Received: by 2002:a1c:6583:: with SMTP id z125mr4838456wmb.102.1591718542281; Tue, 09 Jun 2020 09:02:22 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 7/7] target/arm: Convert Neon 3-reg-diff polynomial VMULL Date: Tue, 9 Jun 2020 17:02:09 +0100 Message-Id: <20200609160209.29960-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200609160209.29960-1-peter.maydell@linaro.org> References: <20200609160209.29960-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon 3-reg-diff insn polynomial VMULL. This is the last insn in this group to be converted. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 2 ++ target/arm/translate-neon.inc.c | 43 +++++++++++++++++++++++ target/arm/translate.c | 60 ++------------------------------- 3 files changed, 48 insertions(+), 57 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 65ea30d3edf..ed49726abf5 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -465,5 +465,7 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm VMULL_U_3d 1111 001 1 1 . .. .... .... 1100 . 0 . 0 .... @3diff =20 VQDMULL_3d 1111 001 0 1 . .. .... .... 1101 . 0 . 0 .... @3diff + + VMULL_P_3d 1111 001 0 1 . .. .... .... 1110 . 0 . 0 .... @3diff ] } diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 5965b5ed845..7dbbfaaac41 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -2304,3 +2304,46 @@ static bool trans_VQDMLSL_3d(DisasContext *s, arg_3d= iff *a) =20 return do_long_3d(s, a, opfn[a->size], accfn[a->size]); } + +static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a) +{ + gen_helper_gvec_3 *fn_gvec; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (a->vd & 1) { + return false; + } + + switch (a->size) { + case 0: + fn_gvec =3D gen_helper_neon_pmull_h; + break; + case 2: + if (!dc_isar_feature(aa32_pmull, s)) { + return false; + } + fn_gvec =3D gen_helper_gvec_pmull_q; + break; + default: + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0), + neon_reg_offset(a->vn, 0), + neon_reg_offset(a->vm, 0), + 16, 16, 0, fn_gvec); + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 88e91845c02..f459fad8646 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5181,7 +5181,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) { int op; int q; - int rd, rn, rm, rd_ofs, rn_ofs, rm_ofs; + int rd, rn, rm, rd_ofs, rm_ofs; int size; int pass; int u; @@ -5215,7 +5215,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) size =3D (insn >> 20) & 3; vec_size =3D q ? 16 : 8; rd_ofs =3D neon_reg_offset(rd, 0); - rn_ofs =3D neon_reg_offset(rn, 0); rm_ofs =3D neon_reg_offset(rm, 0); =20 if ((insn & (1 << 23)) =3D=3D 0) { @@ -5228,61 +5227,8 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) if (size !=3D 3) { op =3D (insn >> 8) & 0xf; if ((insn & (1 << 6)) =3D=3D 0) { - /* Three registers of different lengths. */ - /* undefreq: bit 0 : UNDEF if size =3D=3D 0 - * bit 1 : UNDEF if size =3D=3D 1 - * bit 2 : UNDEF if size =3D=3D 2 - * bit 3 : UNDEF if U =3D=3D 1 - * Note that [2:0] set implies 'always UNDEF' - */ - int undefreq; - /* prewiden, src1_wide, src2_wide, undefreq */ - static const int neon_3reg_wide[16][4] =3D { - {0, 0, 0, 7}, /* VADDL: handled by decodetree */ - {0, 0, 0, 7}, /* VADDW: handled by decodetree */ - {0, 0, 0, 7}, /* VSUBL: handled by decodetree */ - {0, 0, 0, 7}, /* VSUBW: handled by decodetree */ - {0, 0, 0, 7}, /* VADDHN: handled by decodetree */ - {0, 0, 0, 7}, /* VABAL */ - {0, 0, 0, 7}, /* VSUBHN: handled by decodetree */ - {0, 0, 0, 7}, /* VABDL */ - {0, 0, 0, 7}, /* VMLAL */ - {0, 0, 0, 7}, /* VQDMLAL */ - {0, 0, 0, 7}, /* VMLSL */ - {0, 0, 0, 7}, /* VQDMLSL */ - {0, 0, 0, 7}, /* Integer VMULL */ - {0, 0, 0, 7}, /* VQDMULL */ - {0, 0, 0, 0xa}, /* Polynomial VMULL */ - {0, 0, 0, 7}, /* Reserved: always UNDEF */ - }; - - undefreq =3D neon_3reg_wide[op][3]; - - if ((undefreq & (1 << size)) || - ((undefreq & 8) && u)) { - return 1; - } - if (rd & 1) { - return 1; - } - - /* Handle polynomial VMULL in a single pass. */ - if (op =3D=3D 14) { - if (size =3D=3D 0) { - /* VMULL.P8 */ - tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16, - 0, gen_helper_neon_pmull_h); - } else { - /* VMULL.P64 */ - if (!dc_isar_feature(aa32_pmull, s)) { - return 1; - } - tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16, - 0, gen_helper_gvec_pmull_q); - } - return 0; - } - abort(); /* all others handled by decodetree */ + /* Three registers of different lengths: handled by decode= tree */ + return 1; } else { /* Two registers and a scalar. NB that for ops of this form * the ARM ARM labels bit 24 as Q, but it is in our variab= le --=20 2.20.1