From nobody Sun May 19 09:23:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=flygoat.com ARC-Seal: i=1; a=rsa-sha256; t=1591670929; cv=none; d=zohomail.com; s=zohoarc; b=m1onHwFwSmpV/Oxhwucl4vRY3I5lpRCFmoYTacjiXuAt6yFbnWy/+2eouMFfpKvvUJWqgXTKOPIgISXOMT8Mt7r49IaCIuLYJL9WTzo6K7GgXxaVj1HOPVN6VCL1um/iT886R2D3bdacvRnKRUxOZlDNrximLRBebqaYM4fDDfA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591670929; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=R7smD0OfaHfnLEK4M2KvPvSBI9IQQwG2QiAAWZQjfNU=; b=NvVpR4oQQeJdY9Kyjd9yVPSwuoTee5QGq0GK+iwZ55cuCRwWtQ+xiMWv8+frHK9KyaapeGzzANZ6tatB2XjAR1UHE0XucT3ups5hb937zaws5gCZaB78snLrag2TCImcIFlepmSIDoGA6yx8zK5rcnPvMBA/+z5fY2LidsEZkHc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15916709296993.160462165543322; Mon, 8 Jun 2020 19:48:49 -0700 (PDT) Received: from localhost ([::1]:33834 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jiUJj-0002NJ-VN for importer@patchew.org; Mon, 08 Jun 2020 22:48:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45290) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jiUJ4-0001tn-UX for qemu-devel@nongnu.org; Mon, 08 Jun 2020 22:48:06 -0400 Received: from vultr.net.flygoat.com ([2001:19f0:6001:3633:5400:2ff:fe8c:553]:38224) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jiUJ3-0002TE-Jq for qemu-devel@nongnu.org; Mon, 08 Jun 2020 22:48:06 -0400 Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id 6DC751FAF8; Tue, 9 Jun 2020 02:48:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1591670881; bh=veK+SR4g8Ulqn5TtYEUsTTTv/wHdxDcm2yT9dXEkZCg=; h=From:To:Cc:Subject:Date:From; b=FDS4Suupwu7WsVX/e2KdlRhIliQwLPI4jtj0HKzWtNtIwDewESh71/sx7PywONiQH +VBLWdprbLW3yCSye0ThXsneKFBfagOwHMKU/e01zTsoUXi9MOcvxKhqdXt7rCDzoI wUW0o2zmTN2Ft6pKOfW09XQbWcvmjsktk5/W/PDBlb4G083DEZMAk6R5is0KdpCI/4 pIFGpg4LgD5QKT7wG/HuYQoks0oSUm372cmypCAFctk6tgOgkOuWhYVkm/B3bfebNq rvp6uR1nrsCyhb7Bpt/+k/MvUx8ZqZNhFAAw7N/CInz0rFyTYIDnfF9pPYnyI5Q952 s3m3Csbl2RTRw== From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH] target/mips: Fix PageMask with variable page size Date: Tue, 9 Jun 2020 10:47:46 +0800 Message-Id: <20200609024746.2498909-1-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.27.0.rc2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:19f0:6001:3633:5400:2ff:fe8c:553; envelope-from=jiaxun.yang@flygoat.com; helo=vultr.net.flygoat.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/08 22:48:01 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chenhc@lemote.com, aleksandar.qemu.devel@gmail.com, Jiaxun Yang , aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Our current code assumed the target page size is always 4k when handling PageMask and VPN2, however, variable page size was just added to mips target and that's nolonger true. So we refined this piece of code to handle any target page size. Also added Big Page support defined by MIPS64 Release2. Signed-off-by: Jiaxun Yang --- target/mips/cp0_helper.c | 48 ++++++++++++++++++++++++++++++---------- target/mips/cpu.h | 3 ++- 2 files changed, 38 insertions(+), 13 deletions(-) diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index bbf12e4a97..7a134085f7 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -872,20 +872,44 @@ void helper_mtc0_memorymapid(CPUMIPSState *env, targe= t_ulong arg1) } } =20 -void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk) +void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) { - uint64_t mask =3D arg1 >> (TARGET_PAGE_BITS + 1); - if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 =3D=3D ~0) || - (mask =3D=3D 0x0000 || mask =3D=3D 0x0003 || mask =3D=3D 0x000F || - mask =3D=3D 0x003F || mask =3D=3D 0x00FF || mask =3D=3D 0x03FF || - mask =3D=3D 0x0FFF || mask =3D=3D 0x3FFF || mask =3D=3D 0xFFFF)) { - env->CP0_PageMask =3D arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)= ); + uint64_t mask; + int maxmaskbits, maskbits; + + if (env->insn_flags & ISA_MIPS32R6) { + return; } -} =20 -void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) -{ - update_pagemask(env, arg1, &env->CP0_PageMask); + /* Don't care MASKX as we don't support 1KB page */ +#ifdef TARGET_MIPS64 + if (env->CP0_Config3 & CP0C3_BPG) { + maxmaskbits =3D 47; + } else { + maxmaskbits =3D 16; + } +#else + maxmaskbits =3D 16; +#endif + mask =3D extract64((uint64_t)arg1, CP0PM_MASK, maxmaskbits); + + maskbits =3D find_first_zero_bit(&mask, 64); + + /* Ensure no more set bit after first zero */ + if (mask >> maskbits) { + goto invalid; + } + /* We don't support VTLB entry smaller than target page */ + if ((maskbits + 12) < TARGET_PAGE_BITS) { + goto invalid; + } + env->CP0_PageMask =3D mask << CP0PM_MASK; + + return; + +invalid: + maskbits =3D MIN(maxmaskbits, MAX(maskbits, TARGET_PAGE_BITS - 12)); + env->CP0_PageMask =3D ((1 << (maskbits + 1)) - 1) << CP0PM_MASK; } =20 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) @@ -1111,7 +1135,7 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulon= g arg1) void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val, mask; - mask =3D (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask; + mask =3D ~((1 << 14) - 1) | env->CP0_EntryHi_ASID_mask; if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >=3D 2) { mask |=3D 1 << CP0EnHi_EHINV; } diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 0b3c987bb3..b69806792d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -617,7 +617,8 @@ struct CPUMIPSState { /* * CP0 Register 5 */ - int32_t CP0_PageMask; + target_ulong CP0_PageMask; +#define CP0PM_MASK 13 int32_t CP0_PageGrain_rw_bitmask; int32_t CP0_PageGrain; #define CP0PG_RIE 31 --=20 2.27.0.rc2