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[82.1.209.49]) by smtp.gmail.com with ESMTPSA id y5sm24225932wrs.63.2020.06.08.04.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2020 04:40:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V2TSsHVRZv5n6nm4rd17wgB0vrMj5AgJjY7Tq8D4v7E=; b=XFg1V4fZYjjfguvr9MNLuyck1yG+0Hb7wzfa14c2/wyF9unIy2e0ghtwAIqhRhXXU2 43YKuKn+AcYawMqkdofiH/ykZYphdHN6Z4ZuRGdbVvQSIG5Y+Pdl34P0DODLQhn1tUSf pGk2hgUsHSmns/0lNL8jQXbbc0j2fUZXpTwZPhkjidrRCwjWZsrMcvuiB2sEGxH3/TQN reExKqBEptWPHiAOOcmgFYAnLHPOEU/d4kBDh/pSRoPL0ZTrtByNfzhwm1pxW4Omwc+o P6tXdS6v4k7yI8+7t/aRHiKdjamuNrvSaYy2d4o3BzYPwzu5fkAqDqB+kd732h8R4H53 RRVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V2TSsHVRZv5n6nm4rd17wgB0vrMj5AgJjY7Tq8D4v7E=; b=TBYxXL0GQ89pX14qhRrUqOFmU7/PbWsTQzkX/rUw1vo9LofaY5kHyTsXDfM/nc1KSm fNEAKg08OAMNftgdPpdgoGb6XLFm/QrV3IqV/qxEyG3uLIxeD8P/bL9/UCyTLdfB0uei a1sshvwBhA6SaBTNIzgQll70RgqVU8fOwqZ3hAM3zrXP4fG4ZNSjLBoEATQymbhBwwJs kRdMM1A873De1AJmqT2hfRcbBzLOroxf/CyCuOmQMW4PnHUE46/G2kFAe1Kf2w8TP0ur zaXHU+tHPKsFSB2RGwB2UBbhzarbcpAXrdyBdKHnpANpLu14igcVxAUOo5wweJcpuW+Q raFA== X-Gm-Message-State: AOAM531bIgXmr3KHqJDUa8/0Itlz40t5CyquLgzO5aFmi9M9Optljyer ACES4cmJeWLK4Ri64K3pfjrUB1+KGoichuQcUqPc9BolbUOy3cvltf2ihGbQcdSfWUs1Dv9EPaP WTDv8RHBDwEVauEhUnsdqJ7aMwHRC8aLex9hYFs7Ee9qvmMiQwF5YlgAaTBqXyOLq X-Google-Smtp-Source: ABdhPJymsjJm917aEJtm9K5EcUiGiikvasFd5PKmpW40SN+naA031/zpsLD4uQI0LPb82odE+IPXFg== X-Received: by 2002:adf:de84:: with SMTP id w4mr23496358wrl.54.1591616431157; Mon, 08 Jun 2020 04:40:31 -0700 (PDT) From: Leif Lindholm To: QEMU Developers Subject: [RFC PATCH 1/3] target/arm: commonalize aarch64 cpu init Date: Mon, 8 Jun 2020 12:40:26 +0100 Message-Id: <20200608114028.25345-2-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200608114028.25345-1-leif@nuviainc.com> References: <20200608114028.25345-1-leif@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=leif@nuviainc.com; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jones , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @nuviainc-com.20150623.gappssmtp.com) Content-Type: text/plain; charset="utf-8" Some basic options will be set by all aarch64 platforms. Break those out into a separate aarch64_cpu_common_init function, which also takes implementer, partnum, variant, and revision as arguments to set up MIDR. Invoke this to remove duplication between a57/a53/a72 init. Signed-off-by: Leif Lindholm --- target/arm/cpu-qom.h | 3 +++ target/arm/cpu64.c | 46 ++++++++++++++++++++++++-------------------- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 56395b87f6..48f6303308 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -44,6 +44,9 @@ typedef struct ARMCPUInfo { void arm_cpu_register(const ARMCPUInfo *info); void aarch64_cpu_register(const ARMCPUInfo *info); =20 +void aarch64_cpu_common_init(Object *obj, uint8_t impl, uint16_t part, + uint8_t var, uint8_t rev); + /** * ARMCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index cbc5c3868f..79786e034f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -29,6 +29,8 @@ #include "kvm_arm.h" #include "qapi/visitor.h" =20 +#define MIDR_IMPLEMENTER_ARM 0x41 + #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) { @@ -86,11 +88,19 @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo= [] =3D { REGINFO_SENTINEL }; =20 -static void aarch64_a57_initfn(Object *obj) +void aarch64_cpu_common_init(Object *obj, uint8_t impl, uint16_t part, + uint8_t var, uint8_t rev) { ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t t; + + t =3D FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, impl); + t =3D FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); + t =3D FIELD_DP64(t, MIDR_EL1, PARTNUM, part); + t =3D FIELD_DP64(t, MIDR_EL1, VARIANT, var); + t =3D FIELD_DP64(t, MIDR_EL1, REVISION, rev); + cpu->midr =3D t; =20 - cpu->dtb_compatible =3D "arm,cortex-a57"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); @@ -99,8 +109,16 @@ static void aarch64_a57_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); +} + +static void aarch64_a57_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + aarch64_cpu_common_init(obj, MIDR_IMPLEMENTER_ARM, 0xd07, 1, 0); + + cpu->dtb_compatible =3D "arm,cortex-a57"; cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A57; - cpu->midr =3D 0x411fd070; cpu->revidr =3D 0x00000000; cpu->reset_fpsid =3D 0x41034070; cpu->isar.mvfr0 =3D 0x10110222; @@ -143,17 +161,10 @@ static void aarch64_a53_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 + aarch64_cpu_common_init(obj, MIDR_IMPLEMENTER_ARM, 0xd03, 0, 4); + cpu->dtb_compatible =3D "arm,cortex-a53"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A53; - cpu->midr =3D 0x410fd034; cpu->revidr =3D 0x00000000; cpu->reset_fpsid =3D 0x41034070; cpu->isar.mvfr0 =3D 0x10110222; @@ -196,16 +207,9 @@ static void aarch64_a72_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 + aarch64_cpu_common_init(obj, MIDR_IMPLEMENTER_ARM, 0xd08, 0, 3); + cpu->dtb_compatible =3D "arm,cortex-a72"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr =3D 0x410fd083; cpu->revidr =3D 0x00000000; cpu->reset_fpsid =3D 0x41034080; cpu->isar.mvfr0 =3D 0x10110222; --=20 2.20.1