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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- v5: Assign cs->num_ases to the final value first. Downgrade to ID_AA64PFR1.MTE=3D1 if tag memory is not available. v6: Add secure tag memory for EL3. --- target/arm/cpu.h | 6 ++++++ hw/arm/virt.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu.c | 51 ++++++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 106 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 17594226eb..deb270f25b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -792,6 +792,10 @@ struct ARMCPU { /* MemoryRegion to use for secure physical accesses */ MemoryRegion *secure_memory; =20 + /* MemoryRegion to use for allocation tag accesses */ + MemoryRegion *tag_memory; + MemoryRegion *secure_tag_memory; + /* For v8M, pointer to the IDAU interface provided by board/SoC */ Object *idau; =20 @@ -2985,6 +2989,8 @@ typedef enum ARMMMUIdxBit { typedef enum ARMASIdx { ARMASIdx_NS =3D 0, ARMASIdx_S =3D 1, + ARMASIdx_TagNS =3D 2, + ARMASIdx_TagS =3D 3, } ARMASIdx; =20 /* Return the Exception Level targeted by debug exceptions. */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 37462a6f78..c74cc3d78d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1412,6 +1412,16 @@ static void create_secure_ram(VirtMachineState *vms, g_free(nodename); } =20 +static void create_tag_ram(MemoryRegion *tag_sysmem, + hwaddr base, hwaddr size, + const char *name) +{ + MemoryRegion *tagram =3D g_new(MemoryRegion, 1); + + memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); + memory_region_add_subregion(tag_sysmem, base / 32, tagram); +} + static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) { const VirtMachineState *board =3D container_of(binfo, VirtMachineState, @@ -1665,6 +1675,8 @@ static void machvirt_init(MachineState *machine) const CPUArchIdList *possible_cpus; MemoryRegion *sysmem =3D get_system_memory(); MemoryRegion *secure_sysmem =3D NULL; + MemoryRegion *tag_sysmem =3D NULL; + MemoryRegion *secure_tag_sysmem =3D NULL; int n, virt_max_cpus; bool firmware_loaded; bool aarch64 =3D true; @@ -1819,6 +1831,35 @@ static void machvirt_init(MachineState *machine) "secure-memory", &error_abort); } =20 + /* + * The cpu adds the property if and only if MemTag is supported. + * If it is, we must allocate the ram to back that up. + */ + if (object_property_find(cpuobj, "tag-memory", NULL)) { + if (!tag_sysmem) { + tag_sysmem =3D g_new(MemoryRegion, 1); + memory_region_init(tag_sysmem, OBJECT(machine), + "tag-memory", UINT64_MAX / 32); + + if (vms->secure) { + secure_tag_sysmem =3D g_new(MemoryRegion, 1); + memory_region_init(secure_tag_sysmem, OBJECT(machine), + "secure-tag-memory", UINT64_MAX / 3= 2); + + /* As with ram, secure-tag takes precedence over tag. = */ + memory_region_add_subregion_overlap(secure_tag_sysmem,= 0, + tag_sysmem, -1); + } + } + + object_property_set_link(cpuobj, OBJECT(tag_sysmem), + "tag-memory", &error_abort); + if (vms->secure) { + object_property_set_link(cpuobj, OBJECT(secure_tag_sysmem), + "secure-tag-memory", &error_abort= ); + } + } + object_property_set_bool(cpuobj, true, "realized", &error_fatal); object_unref(cpuobj); } @@ -1861,6 +1902,17 @@ static void machvirt_init(MachineState *machine) create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); } =20 + if (tag_sysmem) { + create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, + machine->ram_size, "mach-virt.tag"); + if (vms->secure) { + create_tag_ram(secure_tag_sysmem, + vms->memmap[VIRT_SECURE_MEM].base, + vms->memmap[VIRT_SECURE_MEM].size, + "mach-virt.secure-tag"); + } + } + vms->highmem_ecam &=3D vms->highmem && (!firmware_loaded || aarch64); =20 create_rtc(vms); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8e6d4371cb..37b7cc2c9c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1245,6 +1245,25 @@ void arm_cpu_post_init(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); } + +#ifndef CONFIG_USER_ONLY + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_mte, cpu)) { + object_property_add_link(obj, "tag-memory", + TYPE_MEMORY_REGION, + (Object **)&cpu->tag_memory, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { + object_property_add_link(obj, "secure-tag-memory", + TYPE_MEMORY_REGION, + (Object **)&cpu->secure_tag_memory, + qdev_prop_allow_set_link_before_reali= ze, + OBJ_PROP_LINK_STRONG); + } + } +#endif } =20 static void arm_cpu_finalizefn(Object *obj) @@ -1735,17 +1754,43 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) MachineState *ms =3D MACHINE(qdev_get_machine()); unsigned int smp_cpus =3D ms->smp.cpus; =20 - if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { + /* + * We must set cs->num_ases to the final value before + * the first call to cpu_address_space_init. + */ + if (cpu->tag_memory !=3D NULL) { + cs->num_ases =3D 4; + } else if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { cs->num_ases =3D 2; + } else { + cs->num_ases =3D 1; + } =20 + if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { if (!cpu->secure_memory) { cpu->secure_memory =3D cs->memory; } cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", cpu->secure_memory); - } else { - cs->num_ases =3D 1; } + + if (cpu->tag_memory !=3D NULL) { + cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", + cpu->tag_memory); + if (cpu->has_el3) { + cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", + cpu->secure_tag_memory); + } + } else if (cpu_isar_feature(aa64_mte, cpu)) { + /* + * Since there is no tag memory, we can't meaningfully support MTE + * to its fullest. To avoid problems later, when we would come to + * use the tag memory, downgrade support to insns only. + */ + cpu->isar.id_aa64pfr1 =3D + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); + } + cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); =20 /* No core_count specified, default to smp_cpus. */ --=20 2.25.1