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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h11sm2723630pjk.20.2020.06.02.10.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 10:02:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M61z5W4XC9s3fR/C2OCkY5mKyFMP7INMRDrb7WIzehM=; b=ti2njoz34nQLbQS9+TOEh+rMYs4y8fmSGc1Xu8G0DVo/oCYJtVQhMl8OZE9guDKTFv +aUIqxB414oPev7r4AHja42/X1D6Pbx4N5Pe4anda0a57tmLiEvFGCPki9WjWqhkZUpb RPbf1Vpm0ufeOifz5nLFoGNZ9pLYwy34VxZBAcSA0Wx90VESDqy1TNNr0DAM+YsXubA9 Kt64aeQjZKwcs8sBd2bsi5qLR2avZ1A1HQXWllQ7wsS1bFtnAqeDJZGIXPNheyVW4X8e +uWtCZNez/FMqhd2Ep+MktXNSHgrOVJizmmDHQ8RMIwzlPAcmvJOe2b8JCWIG9c1yqRk hSeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M61z5W4XC9s3fR/C2OCkY5mKyFMP7INMRDrb7WIzehM=; b=FejRH5/UoGm+wuLOlFUYEtZUbDYk1Ohyj9iwU5I9JFM2oCF+i+TEGi9YLbZvFOoVXc 2pcJ2WvsNZI6gUnxhAn3SK8YWYn4t534kAjOj2QzkGbrKed6F2mhm1kbbH5C3+zKlw8T KMhEMJ3yuoMuwBJcoSJJvhPz3MjuCFbIIm98F6u4B91QdglI4+JrofTDaq1760zk6q+E 3U0TQXzbcW4PlBE3UpLLFI7b3qUAxrcK3PJKb2e60LLKBrc0xIdzmnecg6zsqORnBpCM B/B345Wc5jlsGpMUjcMMpID6e5Q3eNrd897lGpJC1W/8Xc22YohIiuHHIKhH5VND1oy8 Dpqg== X-Gm-Message-State: AOAM531iFZy2ABlZ69KKFeq9U1NiU+0ajF3v7hAt57Mkyed1gG+hMjVA rDsWNI5ZhPCzujVIwcdKognz88boWFM= X-Google-Smtp-Source: ABdhPJwg8LVozyzOqg2ScKsTlmhQsQWqZG7EbbKhGFC6aGEkA/z93n3jiW+yOP1xDk4x6Ye8Fc8rnw== X-Received: by 2002:a62:1d89:: with SMTP id d131mr26061827pfd.294.1591117321624; Tue, 02 Jun 2020 10:02:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 06/12] tcg/aarch64: Implement INDEX_op_rotl{i,v}_vec Date: Tue, 2 Jun 2020 10:01:45 -0700 Message-Id: <20200602170151.321389-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602170151.321389-1-richard.henderson@linaro.org> References: <20200602170151.321389-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For immediate rotate , we can implement this in two instructions, using SLI. For variable rotate, the oddness of aarch64 right-shift- as-negative-left-shift means a backend-specific expansion works best. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.opc.h | 1 + tcg/aarch64/tcg-target.inc.c | 53 ++++++++++++++++++++++++++++++++++-- 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target.opc.h index 26bfd9c460..bce30accd9 100644 --- a/tcg/aarch64/tcg-target.opc.h +++ b/tcg/aarch64/tcg-target.opc.h @@ -12,3 +12,4 @@ */ =20 DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC) +DEF(aa64_sli_vec, 1, 2, 1, IMPLVEC) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 843fd0ca69..760b0e742d 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -557,6 +557,7 @@ typedef enum { I3614_SSHR =3D 0x0f000400, I3614_SSRA =3D 0x0f001400, I3614_SHL =3D 0x0f005400, + I3614_SLI =3D 0x2f005400, I3614_USHR =3D 0x2f000400, I3614_USRA =3D 0x2f001400, =20 @@ -2411,6 +2412,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_sari_vec: tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2); break; + case INDEX_op_aa64_sli_vec: + tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece)); + break; case INDEX_op_shlv_vec: tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2); break; @@ -2498,8 +2502,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_shlv_vec: case INDEX_op_bitsel_vec: return 1; + case INDEX_op_rotli_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: return -1; case INDEX_op_mul_vec: case INDEX_op_smax_vec: @@ -2517,14 +2524,24 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2, t1; + TCGv_vec v0, v1, v2, t1, t2; + TCGArg a2; =20 va_start(va, a0); v0 =3D temp_tcgv_vec(arg_temp(a0)); v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - v2 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + a2 =3D va_arg(va, TCGArg); + v2 =3D temp_tcgv_vec(arg_temp(a2)); =20 switch (opc) { + case INDEX_op_rotli_vec: + t1 =3D tcg_temp_new_vec(type); + tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); + vec_gen_4(INDEX_op_aa64_sli_vec, type, vece, + tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2= ); + tcg_temp_free_vec(t1); + break; + case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: /* Right shifts are negative left shifts for AArch64. */ @@ -2537,6 +2554,35 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, tcg_temp_free_vec(t1); break; =20 + case INDEX_op_rotlv_vec: + t1 =3D tcg_temp_new_vec(type); + tcg_gen_dupi_vec(vece, t1, 8 << vece); + tcg_gen_sub_vec(vece, t1, v2, t1); + /* Right shifts are negative left shifts for AArch64. */ + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_or_vec(vece, v0, v0, t1); + tcg_temp_free_vec(t1); + break; + + case INDEX_op_rotrv_vec: + t1 =3D tcg_temp_new_vec(type); + t2 =3D tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t1, v2); + tcg_gen_dupi_vec(vece, t2, 8 << vece); + tcg_gen_add_vec(vece, t2, t1, t2); + /* Right shifts are negative left shifts for AArch64. */ + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(t2)); + tcg_gen_or_vec(vece, v0, t1, t2); + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); + break; + default: g_assert_not_reached(); } @@ -2557,6 +2603,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef lZ_l =3D { .args_ct_str =3D { "lZ", "l" } = }; static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; static const TCGTargetOpDef w_w_w =3D { .args_ct_str =3D { "w", "w", "= w" } }; + static const TCGTargetOpDef w_0_w =3D { .args_ct_str =3D { "w", "0", "= w" } }; static const TCGTargetOpDef w_w_wO =3D { .args_ct_str =3D { "w", "w", = "wO" } }; static const TCGTargetOpDef w_w_wN =3D { .args_ct_str =3D { "w", "w", = "wN" } }; static const TCGTargetOpDef w_w_wZ =3D { .args_ct_str =3D { "w", "w", = "wZ" } }; @@ -2751,6 +2798,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &w_w_wZ; case INDEX_op_bitsel_vec: return &w_w_w_w; + case INDEX_op_aa64_sli_vec: + return &w_0_w; =20 default: return NULL; --=20 2.25.1