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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h11sm2723630pjk.20.2020.06.02.10.01.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 10:01:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cgOiitbO0iyDYlrduQDieXmGBR9obHXryBYv28yQQP4=; b=GwrxtY8D69fd/WfrprrqTtQgyRhnoAGiXVsFBqGcK3OcjUYbddEEHeakRG/Ekuxq8T dGCK8SzeoeMwEb/Ysw2ywGPXZYag/ZvGKO8pycGDBXU4fXJIowsRKADkFsx3PA0NFMnw cGgu9bbuOe+kcUqDpDYF2SUU/SQRPe6sYrG8A6bFG7k1M3pMrBEPpmbwAnaXhYYTFYEw TiPBbuE9qsrOpHhrmo9JWjPffsqKF3z+LhQmni1WYMAU/S4NsNUgQb8gQX6LLSp9yFUX 7rY5b5Toryy41bm+tBkTRqLxmdeQAuQePPNwyrcV3Vz5DGE5GCt3Z9fhL7kNc4l8324m g9cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cgOiitbO0iyDYlrduQDieXmGBR9obHXryBYv28yQQP4=; b=UQgIfyKHaWFbiP+OPfjZSeMtPlSLMBqd8WeKfH1FyjvrWTLvwb2JxEc/lMpIVuX+eu cX9VFBElHsRTJ6++BIAHEB9/6gihQGlCwSSPTzDFVVldEdJHJe4yd8J85O2z1oIDg0o/ l9Ep+P6fVL1Bsz2xjI/mwID9JGVhU7q7gnLcKS35LRNdg7NR0ee+5s0M8+jQY4ZUOHeW i9mnTFP4WlQSEe2bYNEAv6aQuJr5eYXjWunW4C0Je7Ebjf9L9SpDosoG5Hwgz2FwtPrl n9fioeEdzfAih9sePcytCmX4DvGrPhuP/kOJ/mgRiVJoTw5ZBmbWoHiWHhyKlzXXmg2r 3SBw== X-Gm-Message-State: AOAM531IfnRw+nlWh9m97CTbxF1fZNordHGDdIGUAgZ94g6Ma0OhTmC6 NuyCqAJ0TJH13eKfoezK47dfH9O9Kr8= X-Google-Smtp-Source: ABdhPJytLqLNKFnRdjTpOfASm3JObVN4Prjhm2PLUTbV7J51viS9H3Lyw+8Nm9OtNBd8XkJ4ho5HgQ== X-Received: by 2002:a62:e219:: with SMTP id a25mr26505426pfi.303.1591117319866; Tue, 02 Jun 2020 10:01:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/12] tcg/i386: Implement INDEX_op_rotl{i,s,v}_vec Date: Tue, 2 Jun 2020 10:01:44 -0700 Message-Id: <20200602170151.321389-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602170151.321389-1-richard.henderson@linaro.org> References: <20200602170151.321389-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For immediates, we must continue the special casing of 8-bit elements. The other element sizes and shift types are trivially implemented with shifts. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 116 ++++++++++++++++++++++++++++++++------ 1 file changed, 100 insertions(+), 16 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index ec083bddcf..ae0228238b 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -3233,6 +3233,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_shls_vec: case INDEX_op_shrs_vec: case INDEX_op_sars_vec: + case INDEX_op_rotls_vec: case INDEX_op_cmp_vec: case INDEX_op_x86_shufps_vec: case INDEX_op_x86_blend_vec: @@ -3271,6 +3272,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_xor_vec: case INDEX_op_andc_vec: return 1; + case INDEX_op_rotli_vec: case INDEX_op_cmp_vec: case INDEX_op_cmpsel_vec: return -1; @@ -3297,12 +3299,17 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type= , unsigned vece) return vece >=3D MO_16; case INDEX_op_sars_vec: return vece >=3D MO_16 && vece <=3D MO_32; + case INDEX_op_rotls_vec: + return vece >=3D MO_16 ? -1 : 0; =20 case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: return have_avx2 && vece >=3D MO_32; case INDEX_op_sarv_vec: return have_avx2 && vece =3D=3D MO_32; + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + return have_avx2 && vece >=3D MO_32 ? -1 : 0; =20 case INDEX_op_mul_vec: if (vece =3D=3D MO_8) { @@ -3331,7 +3338,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) } } =20 -static void expand_vec_shi(TCGType type, unsigned vece, bool shr, +static void expand_vec_shi(TCGType type, unsigned vece, TCGOpcode opc, TCGv_vec v0, TCGv_vec v1, TCGArg imm) { TCGv_vec t1, t2; @@ -3341,26 +3348,31 @@ static void expand_vec_shi(TCGType type, unsigned v= ece, bool shr, t1 =3D tcg_temp_new_vec(type); t2 =3D tcg_temp_new_vec(type); =20 - /* Unpack to W, shift, and repack. Tricky bits: - (1) Use punpck*bw x,x to produce DDCCBBAA, - i.e. duplicate in other half of the 16-bit lane. - (2) For right-shift, add 8 so that the high half of - the lane becomes zero. For left-shift, we must - shift up and down again. - (3) Step 2 leaves high half zero such that PACKUSWB - (pack with unsigned saturation) does not modify - the quantity. */ + /* + * Unpack to W, shift, and repack. Tricky bits: + * (1) Use punpck*bw x,x to produce DDCCBBAA, + * i.e. duplicate in other half of the 16-bit lane. + * (2) For right-shift, add 8 so that the high half of the lane + * becomes zero. For left-shift, and left-rotate, we must + * shift up and down again. + * (3) Step 2 leaves high half zero such that PACKUSWB + * (pack with unsigned saturation) does not modify + * the quantity. + */ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); =20 - if (shr) { - tcg_gen_shri_vec(MO_16, t1, t1, imm + 8); - tcg_gen_shri_vec(MO_16, t2, t2, imm + 8); + if (opc !=3D INDEX_op_rotli_vec) { + imm +=3D 8; + } + if (opc =3D=3D INDEX_op_shri_vec) { + tcg_gen_shri_vec(MO_16, t1, t1, imm); + tcg_gen_shri_vec(MO_16, t2, t2, imm); } else { - tcg_gen_shli_vec(MO_16, t1, t1, imm + 8); - tcg_gen_shli_vec(MO_16, t2, t2, imm + 8); + tcg_gen_shli_vec(MO_16, t1, t1, imm); + tcg_gen_shli_vec(MO_16, t2, t2, imm); tcg_gen_shri_vec(MO_16, t1, t1, 8); tcg_gen_shri_vec(MO_16, t2, t2, 8); } @@ -3427,6 +3439,61 @@ static void expand_vec_sari(TCGType type, unsigned v= ece, } } =20 +static void expand_vec_rotli(TCGType type, unsigned vece, + TCGv_vec v0, TCGv_vec v1, TCGArg imm) +{ + TCGv_vec t; + + if (vece =3D=3D MO_8) { + expand_vec_shi(type, vece, INDEX_op_rotli_vec, v0, v1, imm); + return; + } + + t =3D tcg_temp_new_vec(type); + tcg_gen_shli_vec(vece, t, v1, imm); + tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm); + tcg_gen_or_vec(vece, v0, v0, t); + tcg_temp_free_vec(t); +} + +static void expand_vec_rotls(TCGType type, unsigned vece, + TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh) +{ + TCGv_i32 rsh; + TCGv_vec t; + + tcg_debug_assert(vece !=3D MO_8); + + t =3D tcg_temp_new_vec(type); + rsh =3D tcg_temp_new_i32(); + + tcg_gen_neg_i32(rsh, lsh); + tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1); + tcg_gen_shls_vec(vece, t, v1, lsh); + tcg_gen_shrs_vec(vece, v0, v1, rsh); + tcg_gen_or_vec(vece, v0, v0, t); + tcg_temp_free_vec(t); + tcg_temp_free_i32(rsh); +} + +static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec sh, bool right) +{ + TCGv_vec t =3D tcg_temp_new_vec(type); + + tcg_gen_dupi_vec(vece, t, 8 << vece); + tcg_gen_sub_vec(vece, t, t, sh); + if (right) { + tcg_gen_shlv_vec(vece, t, v1, t); + tcg_gen_shrv_vec(vece, v0, v1, sh); + } else { + tcg_gen_shrv_vec(vece, t, v1, t); + tcg_gen_shlv_vec(vece, v0, v1, sh); + } + tcg_gen_or_vec(vece, v0, v0, t); + tcg_temp_free_vec(t); +} + static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) { @@ -3636,13 +3703,30 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, switch (opc) { case INDEX_op_shli_vec: case INDEX_op_shri_vec: - expand_vec_shi(type, vece, opc =3D=3D INDEX_op_shri_vec, v0, v1, a= 2); + expand_vec_shi(type, vece, opc, v0, v1, a2); break; =20 case INDEX_op_sari_vec: expand_vec_sari(type, vece, v0, v1, a2); break; =20 + case INDEX_op_rotli_vec: + expand_vec_rotli(type, vece, v0, v1, a2); + break; + + case INDEX_op_rotls_vec: + expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2))); + break; + + case INDEX_op_rotlv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + expand_vec_rotv(type, vece, v0, v1, v2, false); + break; + case INDEX_op_rotrv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + expand_vec_rotv(type, vece, v0, v1, v2, true); + break; + case INDEX_op_mul_vec: v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_mul(type, vece, v0, v1, v2); --=20 2.25.1