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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h11sm2723630pjk.20.2020.06.02.10.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 10:01:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lcNWhrjkDy7FbfNE6oruy9Ivc3Ph5d8bVUFXuqg+mSo=; b=RHniPnR8RyR9hIptgoe4WIgiI9pCXPXzApTGnHDIJjgXiWF1y61iAdsjGhUrq0ErnO mW58JkYhuPVE0STE8zz3Th8J4mVPeXWWBoIZSxEMx3P3VFBGmqrlm0RqDfEC6/LD0nWl aO6RwMXTCTusF/juch+6ACj2L9iv1ssAPvGQXkh7lxEGEgG1y8saaER72Wd7wkGEaIHV /9KBofTFXIfIF65s+D1musbm0CsIZbfX/aTVTP6QSFX1ItN2PteajbOA2/MUEtWzlSsH gAg3X+U1Z/pfyRubd8CIusP8lFO09g/LAovX21rIDvAXU/xCgWmIu9YTN/l/n4VVbgCG aZ8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lcNWhrjkDy7FbfNE6oruy9Ivc3Ph5d8bVUFXuqg+mSo=; b=DFMmGkFpMfFLandImjVOLGGqaIUM9vhqqdnBVKTRXENZJjEC51Jb0wNSonbduCaMER 28WaoAod9hDmLqPA0YOUvML/qCi7kzaTEbHvlid+KB1vISL/iLiddq8LrIm8q9mtfqX5 KapibnqMgVM+km9yw2GOQkKBhS8wae9SRn9nkQIhjdix/4GbBNzGFWO5sPYmf63Zxy/y gZF0L7Y+pXw4CkJDo3XBfVofZJ+80/KLUYUEkBBZW1soW/otbW9wSk4GxP28djIUUU/m rkIhCp06peioYHiSlToG7eu4DJbk32c2F8zUC0F0ewC2X/NYFRhg7/pMScOyJVWkAxgg 0pSA== X-Gm-Message-State: AOAM533wW7s7qmCAH4AfYJJKjrrdEF217f0oMCU31Bcf9+6X1ZVBJcE6 /PAnCtnALU1LJU8oUO2vwj/DSBd9Px8= X-Google-Smtp-Source: ABdhPJydiGBn/ZjPM/GhYxbFUn4zp69qQPnOHCTM6hz1GsQzvfIUOrDATIMKHJTTxHoMLVN1+hznGg== X-Received: by 2002:a17:90b:188d:: with SMTP id mn13mr165533pjb.84.1591117314235; Tue, 02 Jun 2020 10:01:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/12] tcg: Implement gvec support for rotate by immediate Date: Tue, 2 Jun 2020 10:01:40 -0700 Message-Id: <20200602170151.321389-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602170151.321389-1-richard.henderson@linaro.org> References: <20200602170151.321389-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) No host backend support yet, but the interfaces for rotli are in place. Canonicalize immediate rotate to the left, based on a survey of architectures, but provide both left and right shift interfaces to the translators. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 5 +++ include/tcg/tcg-op-gvec.h | 6 ++++ include/tcg/tcg-op.h | 2 ++ include/tcg/tcg-opc.h | 1 + include/tcg/tcg.h | 1 + tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + accel/tcg/tcg-runtime-gvec.c | 48 +++++++++++++++++++++++++ tcg/tcg-op-gvec.c | 68 ++++++++++++++++++++++++++++++++++++ tcg/tcg-op-vec.c | 12 +++++++ tcg/tcg.c | 2 ++ tcg/README | 3 +- 13 files changed, 150 insertions(+), 1 deletion(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 4fa61b49b4..cf10c8361e 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -259,6 +259,11 @@ DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void,= ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_3(gvec_rotl8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_rotl16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_rotl32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_rotl64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(gvec_shl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_shl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_shl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index cea6497341..1afc3ebf03 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -334,6 +334,10 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, u= int32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); =20 void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); @@ -388,5 +392,7 @@ void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int6= 4_t); void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); +void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); =20 #endif diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index e3399d6a5e..848d91ce74 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -999,6 +999,8 @@ void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_v= ec a, TCGv_vec b); void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); =20 void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 9288a04946..a6ab4a147f 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -248,6 +248,7 @@ DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not= _vec)) DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) +DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec)) =20 DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index c48bd76b0a..56bedbd03b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -182,6 +182,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_not_vec 0 #define TCG_TARGET_HAS_andc_vec 0 #define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index ca214f6909..225a597f84 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -133,6 +133,7 @@ typedef enum { #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 1 +#define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index bfb3f5f6e9..23aabde992 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -183,6 +183,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_not_vec 0 #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_abs_vec 1 +#define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 4fa21f0e71..e57b891aa5 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -161,6 +161,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec have_isa_3_00 #define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index ca449702e6..34b1030365 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -716,6 +716,54 @@ void HELPER(gvec_sar64i)(void *d, void *a, uint32_t de= sc) clear_high(d, oprsz, desc); } =20 +void HELPER(gvec_rotl8i)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + int shift =3D simd_data(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint8_t)) { + *(uint8_t *)(d + i) =3D rol8(*(uint8_t *)(a + i), shift); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl16i)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + int shift =3D simd_data(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint16_t)) { + *(uint16_t *)(d + i) =3D rol16(*(uint16_t *)(a + i), shift); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl32i)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + int shift =3D simd_data(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + *(uint32_t *)(d + i) =3D rol32(*(uint32_t *)(a + i), shift); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl64i)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + int shift =3D simd_data(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + *(uint64_t *)(d + i) =3D rol64(*(uint64_t *)(a + i), shift); + } + clear_high(d, oprsz, desc); +} + void HELPER(gvec_shl8v)(void *d, void *a, void *b, uint32_t desc) { intptr_t oprsz =3D simd_oprsz(desc); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 049a55e700..25300b1577 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2694,6 +2694,74 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs,= uint32_t aofs, } } =20 +void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) +{ + uint64_t mask =3D dup_const(MO_8, 0xff << c); + + tcg_gen_shli_i64(d, a, c); + tcg_gen_shri_i64(a, a, 8 - c); + tcg_gen_andi_i64(d, d, mask); + tcg_gen_andi_i64(a, a, ~mask); + tcg_gen_or_i64(d, d, a); +} + +void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) +{ + uint64_t mask =3D dup_const(MO_16, 0xffff << c); + + tcg_gen_shli_i64(d, a, c); + tcg_gen_shri_i64(a, a, 16 - c); + tcg_gen_andi_i64(d, d, mask); + tcg_gen_andi_i64(a, a, ~mask); + tcg_gen_or_i64(d, d, a); +} + +void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_rotli_vec, 0 }; + static const GVecGen2i g[4] =3D { + { .fni8 =3D tcg_gen_vec_rotl8i_i64, + .fniv =3D tcg_gen_rotli_vec, + .fno =3D gen_helper_gvec_rotl8i, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fni8 =3D tcg_gen_vec_rotl16i_i64, + .fniv =3D tcg_gen_rotli_vec, + .fno =3D gen_helper_gvec_rotl16i, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_rotli_i32, + .fniv =3D tcg_gen_rotli_vec, + .fno =3D gen_helper_gvec_rotl32i, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_rotli_i64, + .fniv =3D tcg_gen_rotli_vec, + .fno =3D gen_helper_gvec_rotl64i, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_debug_assert(shift >=3D 0 && shift < (8 << vece)); + if (shift =3D=3D 0) { + tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + } else { + tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); + } +} + +void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_debug_assert(vece <=3D MO_64); + tcg_debug_assert(shift >=3D 0 && shift < (8 << vece)); + tcg_gen_gvec_rotli(vece, dofs, aofs, -shift & ((8 << vece) - 1), + oprsz, maxsz); +} + /* * Specialized generation vector shifts by a non-constant scalar. */ diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index b6937e8d64..660ad9be88 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -545,6 +545,18 @@ void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, int64_t i) do_shifti(INDEX_op_sari_vec, vece, r, a, i); } =20 +void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) +{ + do_shifti(INDEX_op_rotli_vec, vece, r, a, i); +} + +void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) +{ + int bits =3D 8 << vece; + tcg_debug_assert(i >=3D 0 && i < bits); + do_shifti(INDEX_op_rotli_vec, vece, r, a, -i & (bits - 1)); +} + void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { diff --git a/tcg/tcg.c b/tcg/tcg.c index a2268d9db0..73a3a4fb9e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1661,6 +1661,8 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: return have_vec && TCG_TARGET_HAS_shv_vec; + case INDEX_op_rotli_vec: + return have_vec && TCG_TARGET_HAS_roti_vec; case INDEX_op_ssadd_vec: case INDEX_op_usadd_vec: case INDEX_op_sssub_vec: diff --git a/tcg/README b/tcg/README index bfa2e4ed24..1e3e4654f4 100644 --- a/tcg/README +++ b/tcg/README @@ -605,10 +605,11 @@ E.g. VECL=3D1 -> 64 << 1 -> v128, and VECE=3D2 -> 1 <= < 2 -> i32. =20 * shri_vec v0, v1, i2 * sari_vec v0, v1, i2 +* rotli_vec v0, v1, i2 * shrs_vec v0, v1, s2 * sars_vec v0, v1, s2 =20 - Similarly for logical and arithmetic right shift. + Similarly for logical and arithmetic right shift, and left rotate. =20 * shlv_vec v0, v1, v2 =20 --=20 2.25.1 From nobody Thu May 16 09:34:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1591117466; cv=none; d=zohomail.com; s=zohoarc; b=ZEZclCvG6V1871Yl5QPGt4RvyHr5JPGD1937/p02Uc5Pph1wz4V2ley/zxN3FG5D6ndjzmb3rvMvNLSUxZJfwWDTQf3cfIkxOv7Mrlbv4tPXetgdntoLfSczN9iII4z64KaDbY4HpcdwLqPJV8/BzrTC8wfVQVq5yjP34EqSo+c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591117466; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Mu2saZOWPED4vR7UdUs4dqcH4IgZTJumToHiRAA4Yio=; b=RbGgbXRuZww8zRVdiP1awyP4RD8OmbUqsjEMVn70+va3vQTSO0haLXbv+O17niZSuRBXJVLC0TGPlNmRuO0HDPdvczEGHDkwmAhja2VESF3F3N8ss1zUp4Cm2FzSF8kme6o/xSSZ0aHUVLcNGx2qQKpwRvlbR9Y26/KT+M/NF5w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591117466201422.6627800061176; Tue, 2 Jun 2020 10:04:26 -0700 (PDT) Received: from localhost ([::1]:52992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jgAKu-00028R-Of for importer@patchew.org; Tue, 02 Jun 2020 13:04:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgAIZ-0005YD-DF for qemu-devel@nongnu.org; Tue, 02 Jun 2020 13:01:59 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:37290) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jgAIX-0007Pj-UR for qemu-devel@nongnu.org; Tue, 02 Jun 2020 13:01:59 -0400 Received: by mail-pj1-x1029.google.com with SMTP id m2so1753991pjv.2 for ; Tue, 02 Jun 2020 10:01:57 -0700 (PDT) Received: from localhost.localdomain (174-21-143-238.tukw.qwest.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) No host backend support yet, but the interfaces for rotlv and rotrv are in place. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- v3: Drop the generic expansion from rot to shift; we can do better for each backend, and then this code becomes unused. --- accel/tcg/tcg-runtime.h | 10 +++ include/tcg/tcg-op-gvec.h | 4 ++ include/tcg/tcg-op.h | 2 + include/tcg/tcg-opc.h | 2 + include/tcg/tcg.h | 1 + tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + accel/tcg/tcg-runtime-gvec.c | 96 +++++++++++++++++++++++++++ tcg/tcg-op-gvec.c | 122 +++++++++++++++++++++++++++++++++++ tcg/tcg-op-vec.c | 10 +++ tcg/tcg.c | 3 + tcg/README | 4 +- 13 files changed, 256 insertions(+), 1 deletion(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index cf10c8361e..4eda24e63a 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -279,6 +279,16 @@ DEF_HELPER_FLAGS_4(gvec_sar16v, TCG_CALL_NO_RWG, void,= ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_sar32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_sar64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(gvec_rotl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotl64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_rotr8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotr16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotr32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotr64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index 1afc3ebf03..2d768f1160 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -356,6 +356,10 @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, u= int32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); =20 void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 848d91ce74..5523ee7810 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -1009,6 +1009,8 @@ void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv= _vec a, TCGv_i32 s); void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); =20 void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index a6ab4a147f..69f98d6523 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -257,6 +257,8 @@ DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sh= s_vec)) DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) +DEF(rotlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) +DEF(rotrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) =20 DEF(cmp_vec, 1, 2, 1, IMPLVEC) =20 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 56bedbd03b..b2cb30305c 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -183,6 +183,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_andc_vec 0 #define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 225a597f84..a5477bbc07 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -134,6 +134,7 @@ typedef enum { #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 23aabde992..4c806c97db 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -184,6 +184,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index e57b891aa5..7993422526 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -162,6 +162,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_neg_vec have_isa_3_00 #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 34b1030365..521da4a813 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -908,6 +908,102 @@ void HELPER(gvec_sar64v)(void *d, void *a, void *b, u= int32_t desc) clear_high(d, oprsz, desc); } =20 +void HELPER(gvec_rotl8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint8_t)) { + uint8_t sh =3D *(uint8_t *)(b + i) & 7; + *(uint8_t *)(d + i) =3D rol8(*(uint8_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint16_t)) { + uint8_t sh =3D *(uint16_t *)(b + i) & 15; + *(uint16_t *)(d + i) =3D rol16(*(uint16_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + uint8_t sh =3D *(uint32_t *)(b + i) & 31; + *(uint32_t *)(d + i) =3D rol32(*(uint32_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + uint8_t sh =3D *(uint64_t *)(b + i) & 63; + *(uint64_t *)(d + i) =3D rol64(*(uint64_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotr8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint8_t)) { + uint8_t sh =3D *(uint8_t *)(b + i) & 7; + *(uint8_t *)(d + i) =3D ror8(*(uint8_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotr16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint16_t)) { + uint8_t sh =3D *(uint16_t *)(b + i) & 15; + *(uint16_t *)(d + i) =3D ror16(*(uint16_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotr32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + uint8_t sh =3D *(uint32_t *)(b + i) & 31; + *(uint32_t *)(d + i) =3D ror32(*(uint32_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotr64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + uint8_t sh =3D *(uint64_t *)(b + i) & 63; + *(uint64_t *)(d + i) =3D ror64(*(uint64_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + #define DO_CMP1(NAME, TYPE, OP) = \ void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) = \ { = \ diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 25300b1577..2b71725883 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -3171,6 +3171,128 @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs= , uint32_t aofs, tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); } =20 +/* + * Similarly for rotates. + */ + +static void tcg_gen_rotlv_mod_vec(unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t =3D tcg_temp_new_vec_matching(d); + + tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); + tcg_gen_and_vec(vece, t, t, b); + tcg_gen_rotlv_vec(vece, d, a, t); + tcg_temp_free_vec(t); +} + +static void tcg_gen_rotl_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_andi_i32(t, b, 31); + tcg_gen_rotl_i32(d, a, t); + tcg_temp_free_i32(t); +} + +static void tcg_gen_rotl_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(t, b, 63); + tcg_gen_rotl_i64(d, a, t); + tcg_temp_free_i64(t); +} + +void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_rotlv_vec, 0 }; + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_rotlv_mod_vec, + .fno =3D gen_helper_gvec_rotl8v, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_rotlv_mod_vec, + .fno =3D gen_helper_gvec_rotl16v, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_rotl_mod_i32, + .fniv =3D tcg_gen_rotlv_mod_vec, + .fno =3D gen_helper_gvec_rotl32v, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_rotl_mod_i64, + .fniv =3D tcg_gen_rotlv_mod_vec, + .fno =3D gen_helper_gvec_rotl64v, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + +static void tcg_gen_rotrv_mod_vec(unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t =3D tcg_temp_new_vec_matching(d); + + tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); + tcg_gen_and_vec(vece, t, t, b); + tcg_gen_rotrv_vec(vece, d, a, t); + tcg_temp_free_vec(t); +} + +static void tcg_gen_rotr_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_andi_i32(t, b, 31); + tcg_gen_rotr_i32(d, a, t); + tcg_temp_free_i32(t); +} + +static void tcg_gen_rotr_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(t, b, 63); + tcg_gen_rotr_i64(d, a, t); + tcg_temp_free_i64(t); +} + +void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_rotrv_vec, 0 }; + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_rotrv_mod_vec, + .fno =3D gen_helper_gvec_rotr8v, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_rotrv_mod_vec, + .fno =3D gen_helper_gvec_rotr16v, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_rotr_mod_i32, + .fniv =3D tcg_gen_rotrv_mod_vec, + .fno =3D gen_helper_gvec_rotr32v, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_rotr_mod_i64, + .fniv =3D tcg_gen_rotrv_mod_vec, + .fno =3D gen_helper_gvec_rotr64v, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + /* Expand OPSZ bytes worth of three-operand operations using i32 elements.= */ static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, TCGCond cond) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 660ad9be88..488f9bd27b 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -696,6 +696,16 @@ void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_vec b) do_op3_nofail(vece, r, a, b, INDEX_op_sarv_vec); } =20 +void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3_nofail(vece, r, a, b, INDEX_op_rotlv_vec); +} + +void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3_nofail(vece, r, a, b, INDEX_op_rotrv_vec); +} + static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 73a3a4fb9e..bd6ffab79b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1663,6 +1663,9 @@ bool tcg_op_supported(TCGOpcode op) return have_vec && TCG_TARGET_HAS_shv_vec; case INDEX_op_rotli_vec: return have_vec && TCG_TARGET_HAS_roti_vec; + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + return have_vec && TCG_TARGET_HAS_rotv_vec; case INDEX_op_ssadd_vec: case INDEX_op_usadd_vec: case INDEX_op_sssub_vec: diff --git a/tcg/README b/tcg/README index 1e3e4654f4..a64f67809b 100644 --- a/tcg/README +++ b/tcg/README @@ -621,8 +621,10 @@ E.g. VECL=3D1 -> 64 << 1 -> v128, and VECE=3D2 -> 1 <<= 2 -> i32. =20 * shrv_vec v0, v1, v2 * sarv_vec v0, v1, v2 +* rotlv_vec v0, v1, v2 +* rotrv_vec v0, v1, v2 =20 - Similarly for logical and arithmetic right shift. + Similarly for logical and arithmetic right shift, and rotates. =20 * cmp_vec v0, v1, v2, cond =20 --=20 2.25.1 From nobody Thu May 16 09:34:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1591117446; cv=none; d=zohomail.com; s=zohoarc; b=HeIfd7IVq9XE39Rsu11BXKyAZRYyutJ3X1+yxTsEFIySGLNFhYEWivQRfkWkuuep5mWfiLZTi7Q+yg35Lpt2154RvvMtDFiKtq9cHhhq0qyRpoQaSxjSqQ2U36M6CAX5kqffvhvQVm030Sw5YCgY7B60PT7UcUUtbBpwQdAKro4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591117446; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dJwDuWSZeLE696I9+Yn1ZicAuqxGocQvw+7wiJTGy8g=; b=EaYm7owaNgYcmGB3D9mOA0XIPmg6Tto4leVXirYtCZnXa9kG1gIlv7pm8ylL4QjNvDnXSfQ46iQIrQfyuijk4e2tp0/y9SnEdG+wXEY7TvZEcY6LufT6WD1UOk356FEJy5nqrFIW9pdCEdd8misG5sBhyEE0uXLXidaE3W69iEU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591117446232213.09659519599802; Tue, 2 Jun 2020 10:04:06 -0700 (PDT) Received: from localhost ([::1]:50908 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jgAKa-0001Gt-Sa for importer@patchew.org; Tue, 02 Jun 2020 13:04:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgAIa-0005au-JB for qemu-devel@nongnu.org; Tue, 02 Jun 2020 13:02:00 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:36320) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jgAIZ-0007Py-4Y for qemu-devel@nongnu.org; Tue, 02 Jun 2020 13:02:00 -0400 Received: by mail-pl1-x644.google.com with SMTP id bg4so1589529plb.3 for ; Tue, 02 Jun 2020 10:01:58 -0700 (PDT) Received: from localhost.localdomain (174-21-143-238.tukw.qwest.net. [174.21.143.238]) by smtp.gmail.com with ESMTPSA id h11sm2723630pjk.20.2020.06.02.10.01.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 10:01:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dJwDuWSZeLE696I9+Yn1ZicAuqxGocQvw+7wiJTGy8g=; b=JsxMmYP9V58SOreJPqCe2Bup5PAIAS2gJCk+MiXYBLXbw8d9TDJDc9+x8zIt0IkzOg D3o/2HHWX9cptvmgO7kt5LZ2ewU6TYgvu5NqJDaamsvrDaRXFtwbNTq1EpoZaP/Kntvn 4gsCVH6+gK7MW0RDROlE/K+/6xe+70Uae6f1eQlWemXiu8GzvvCt0KybheOK4KG3erwF Nq4vrG7EEJ/cEmcGcL8Rtz4pppHQ7Zn0jiJCohWMXPTWIfSMkomvFKGyyCSqVvyTpNJE Bb8RGjRjVSNqF6zNb5TmGSX6R5yHGTalxKkrPTmG05f4hqpxiWIVQAJE6V2SziSZfU5P 4V7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dJwDuWSZeLE696I9+Yn1ZicAuqxGocQvw+7wiJTGy8g=; b=qkoUUiZBDbdIdT6wXgFi3rccnMqt1F1vGR3vfIfZ0q4ww/YrkaCMOFl94rX52cKcUY /uPaIKllMMQ7/YPj2506wji32LcTKC7YEpEby6r8/I9ogYe+sgoZcRVEtt7r3l4lBAtw jE6Vvoco+fAffk+a1si3lwagFzE17sC9EJCCAXy+j8NGqwj3QtCL50oMJ5Q3NqH8KlbA kDG+9oLqi4GW4Q4q6F3OgFfaM5Fx9Df8+AlZw/KDDLyLNjfMZwQkxiAlYLkbC5DfxuYD Y4r9w8mfQkDpfOv6BvO9YTNLggYqpnK80PjtIyFKog6WvYQ3GhE/VlcXNghrV7LeUNcR VvAg== X-Gm-Message-State: AOAM531f0R7PUBNlSIZTSM6M9pN9sTwiwx1ipNdlOb7ohop7jSd3iCam 6aIBNg2PJG+Pe8ykt3eSYYSXCGZ/+5M= X-Google-Smtp-Source: ABdhPJwvsolhROaMT6dbwZfJ9CkfT3/OHFMGIuL16zmhWLHbmMJdRn89b5rfH/fHesD6GhBfPO2Qyg== X-Received: by 2002:a17:90a:17e9:: with SMTP id q96mr171373pja.56.1591117317393; Tue, 02 Jun 2020 10:01:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 03/12] tcg: Remove expansion to shift by vector from do_shifts Date: Tue, 2 Jun 2020 10:01:42 -0700 Message-Id: <20200602170151.321389-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602170151.321389-1-richard.henderson@linaro.org> References: <20200602170151.321389-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We do not reflect this expansion in tcg_can_emit_vecop_list, so it is unused and unusable. However, we actually perform the same expansion in do_gvec_shifts, so it is also unneeded. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 35 +++++++++++------------------------ 1 file changed, 11 insertions(+), 24 deletions(-) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 488f9bd27b..fb1250fee6 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -707,7 +707,7 @@ void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_vec b) } =20 static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a, - TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v) + TCGv_i32 s, TCGOpcode opc) { TCGTemp *rt =3D tcgv_vec_temp(r); TCGTemp *at =3D tcgv_vec_temp(a); @@ -716,48 +716,35 @@ static void do_shifts(unsigned vece, TCGv_vec r, TCGv= _vec a, TCGArg ai =3D temp_arg(at); TCGArg si =3D temp_arg(st); TCGType type =3D rt->base_type; - const TCGOpcode *hold_list; int can; =20 tcg_debug_assert(at->base_type >=3D type); - tcg_assert_listed_vecop(opc_s); - hold_list =3D tcg_swap_vecop_list(NULL); - - can =3D tcg_can_emit_vec_op(opc_s, type, vece); + tcg_assert_listed_vecop(opc); + can =3D tcg_can_emit_vec_op(opc, type, vece); if (can > 0) { - vec_gen_3(opc_s, type, vece, ri, ai, si); + vec_gen_3(opc, type, vece, ri, ai, si); } else if (can < 0) { - tcg_expand_vec_op(opc_s, type, vece, ri, ai, si); + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); + tcg_expand_vec_op(opc, type, vece, ri, ai, si); + tcg_swap_vecop_list(hold_list); } else { - TCGv_vec vec_s =3D tcg_temp_new_vec(type); - - if (vece =3D=3D MO_64) { - TCGv_i64 s64 =3D tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(s64, s); - tcg_gen_dup_i64_vec(MO_64, vec_s, s64); - tcg_temp_free_i64(s64); - } else { - tcg_gen_dup_i32_vec(vece, vec_s, s); - } - do_op3_nofail(vece, r, a, vec_s, opc_v); - tcg_temp_free_vec(vec_s); + g_assert_not_reached(); } - tcg_swap_vecop_list(hold_list); } =20 void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) { - do_shifts(vece, r, a, b, INDEX_op_shls_vec, INDEX_op_shlv_vec); + do_shifts(vece, r, a, b, INDEX_op_shls_vec); } =20 void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) { - do_shifts(vece, r, a, b, INDEX_op_shrs_vec, INDEX_op_shrv_vec); + do_shifts(vece, r, a, b, INDEX_op_shrs_vec); } =20 void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) { - do_shifts(vece, r, a, b, INDEX_op_sars_vec, INDEX_op_sarv_vec); + do_shifts(vece, r, a, b, INDEX_op_sars_vec); } =20 void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, --=20 2.25.1 From nobody Thu May 16 09:34:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1591117560; cv=none; d=zohomail.com; s=zohoarc; b=jsZ8NwVfZHZcWsSdOHimWc47XDjZ591l98V9s6PWwD9Q911RnD4p60CO0u4JwIhTn6fvt4tfcqcObTYtPe9ykhNDbVnH1WST2TU4ydYAaDXH5OmHSCKzu52/mTvc+vL6PPfC4SELTGgjnEEEFwqHMbtGMItOTcSPKsmsufF/U80= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591117560; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Hk+iH5vXCwSqMT7V5a8G2hQq/dm0/a4SltBeNIVr26o=; b=BbsXf9qk9lYV7ZYcSKZXJjgZIwyOKie/IbC4g+tnPAY4BhbRPr9PnIlTaOSzTBKaN+K3mzFoSqvEMC7cVjqqAvMPtyq1ov2qJd4M7DaenzeXGEAdxzeLoUTe2ZvHs3GuOCi50AKi2abV8Bwbb80PrkVowPshJCBxrQA4yiPstFM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591117560369539.9157508806381; Tue, 2 Jun 2020 10:06:00 -0700 (PDT) Received: from localhost ([::1]:59114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jgAMQ-0004gF-Uw for importer@patchew.org; Tue, 02 Jun 2020 13:05:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39784) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgAIb-0005dL-LO for qemu-devel@nongnu.org; Tue, 02 Jun 2020 13:02:01 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:33405) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jgAIa-0007Q8-FL for qemu-devel@nongnu.org; Tue, 02 Jun 2020 13:02:01 -0400 Received: by mail-pg1-x532.google.com with SMTP id s10so5351300pgm.0 for ; Tue, 02 Jun 2020 10:02:00 -0700 (PDT) Received: from localhost.localdomain (174-21-143-238.tukw.qwest.net. [174.21.143.238]) by smtp.gmail.com with ESMTPSA id h11sm2723630pjk.20.2020.06.02.10.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 10:01:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Hk+iH5vXCwSqMT7V5a8G2hQq/dm0/a4SltBeNIVr26o=; b=pUsCMgglXneHm4jZk6wHJHRwyTqwmBQwpeY7j8lNJYZBYRO8QnI9mqBFi6Kgkp7w82 ve4nT7vdDawHVHW7Qn9u8jHw3L7KX5oGjNuJqPyEfumm9HOXI4QF28DQnvTu0VkOVReG /Dd+Ll41eBmaYFJNJ9E2EqkSx0Dj/frCqMhb6tnUYUhEG7LXVJN9YKOBjTKPVdraa0+b UJhYexVod4dL2C2zybnO2j2I4oc/xzXltdpCrp4YXQMxOauHAE5Z6MBP0F2jM/SDnkxj qprvTsNOxPFFdk1gBRZOsNQQCc+L7JZCY/1kizu/OtCjyFlVp/JI5i3mNRipFzFbvW2d nUCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hk+iH5vXCwSqMT7V5a8G2hQq/dm0/a4SltBeNIVr26o=; b=Rx705fRv1DzgqgDYZKj4XbgT+5FG5q+0jLowL7ZcSxnmx69IWGz1/sGNwjKcZBhZHb l2AGqnFnS9jxKON61HXuCKV4VNhQD7wpQ5deSUYTecVB+0BHYvIYN7CDR4MgFGe5x7e+ f2KpFMN1lQIHADJxtS8T+YDi9MNhKWxHRHHLiHdOclDzQoe+ENwMnXFH7U/j/xX5zhJK Jpvmq3zIYzkhrOVGxWlvMV2swtg7AbioEwv8RPMdfvtJoweZ9/uWjYaI6RZpctGrJodZ sinY+33svVpdCj7gxrxteq7Zza1U5mcpz2i1fd5tREk+/ppM3a4zSDVT42cufstm8hr4 dLxw== X-Gm-Message-State: AOAM530G1YkijTJg0awhZ9dUx4eJN8wDRE6FJPyGgBG8V4SOUaySMMTA 9vyNbAbRJwD/2smGbNkb8vfH7jIdOm4= X-Google-Smtp-Source: ABdhPJzkpnsZGHztOhHua5dSmFl17eZFR6/NGhxkwzRmvvOIuU0amWsMt+spZh9Lrob1SBWkLhZ8sg== X-Received: by 2002:a62:1606:: with SMTP id 6mr3395273pfw.148.1591117318605; Tue, 02 Jun 2020 10:01:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/12] tcg: Implement gvec support for rotate by scalar Date: Tue, 2 Jun 2020 10:01:43 -0700 Message-Id: <20200602170151.321389-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602170151.321389-1-richard.henderson@linaro.org> References: <20200602170151.321389-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) No host backend support yet, but the interfaces for rotls are in place. Only implement left-rotate for now, as the only known use of vector rotate by scalar is s390x, so any right-rotate would be unused and untestable. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 2 ++ include/tcg/tcg-op.h | 1 + include/tcg/tcg-opc.h | 1 + include/tcg/tcg.h | 1 + tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/tcg-op-gvec.c | 22 ++++++++++++++++++++++ tcg/tcg-op-vec.c | 5 +++++ tcg/tcg.c | 2 ++ 10 files changed, 37 insertions(+) diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index 2d768f1160..c69a7de984 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -345,6 +345,8 @@ void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, ui= nt32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); =20 /* * Perform vector shift by vector element, modulo the element size. diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 5523ee7810..5abf17fecc 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -1005,6 +1005,7 @@ void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCG= v_vec a, int64_t i); void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); =20 void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 69f98d6523..e3929b80d2 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -253,6 +253,7 @@ DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_r= oti_vec)) DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) +DEF(rotls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rots_vec)) =20 DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index b2cb30305c..380014ed80 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -183,6 +183,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_andc_vec 0 #define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index a5477bbc07..9bc2a5ecbe 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -134,6 +134,7 @@ typedef enum { #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 4c806c97db..99ac1e3958 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -184,6 +184,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 7993422526..4a17aebc5a 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -162,6 +162,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_neg_vec have_isa_3_00 #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 2b71725883..3707c0effb 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2976,6 +2976,28 @@ void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs,= uint32_t aofs, do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); } =20 +void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen2sh g =3D { + .fni4 =3D tcg_gen_rotl_i32, + .fni8 =3D tcg_gen_rotl_i64, + .fniv_s =3D tcg_gen_rotls_vec, + .fniv_v =3D tcg_gen_rotlv_vec, + .fno =3D { + gen_helper_gvec_rotl8i, + gen_helper_gvec_rotl16i, + gen_helper_gvec_rotl32i, + gen_helper_gvec_rotl64i, + }, + .s_list =3D { INDEX_op_rotls_vec, 0 }, + .v_list =3D { INDEX_op_rotlv_vec, 0 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); +} + /* * Expand D =3D A << (B % element bits) * diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index fb1250fee6..f784517d84 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -747,6 +747,11 @@ void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_i32 b) do_shifts(vece, r, a, b, INDEX_op_sars_vec); } =20 +void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s) +{ + do_shifts(vece, r, a, s, INDEX_op_rotls_vec); +} + void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b, TCGv_vec c) { diff --git a/tcg/tcg.c b/tcg/tcg.c index bd6ffab79b..97558ec068 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1663,6 +1663,8 @@ bool tcg_op_supported(TCGOpcode op) return have_vec && TCG_TARGET_HAS_shv_vec; case INDEX_op_rotli_vec: return have_vec && TCG_TARGET_HAS_roti_vec; + case INDEX_op_rotls_vec: + return have_vec && TCG_TARGET_HAS_rots_vec; case INDEX_op_rotlv_vec: case INDEX_op_rotrv_vec: return have_vec && TCG_TARGET_HAS_rotv_vec; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For immediates, we must continue the special casing of 8-bit elements. The other element sizes and shift types are trivially implemented with shifts. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 116 ++++++++++++++++++++++++++++++++------ 1 file changed, 100 insertions(+), 16 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index ec083bddcf..ae0228238b 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -3233,6 +3233,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_shls_vec: case INDEX_op_shrs_vec: case INDEX_op_sars_vec: + case INDEX_op_rotls_vec: case INDEX_op_cmp_vec: case INDEX_op_x86_shufps_vec: case INDEX_op_x86_blend_vec: @@ -3271,6 +3272,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_xor_vec: case INDEX_op_andc_vec: return 1; + case INDEX_op_rotli_vec: case INDEX_op_cmp_vec: case INDEX_op_cmpsel_vec: return -1; @@ -3297,12 +3299,17 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type= , unsigned vece) return vece >=3D MO_16; case INDEX_op_sars_vec: return vece >=3D MO_16 && vece <=3D MO_32; + case INDEX_op_rotls_vec: + return vece >=3D MO_16 ? -1 : 0; =20 case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: return have_avx2 && vece >=3D MO_32; case INDEX_op_sarv_vec: return have_avx2 && vece =3D=3D MO_32; + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + return have_avx2 && vece >=3D MO_32 ? -1 : 0; =20 case INDEX_op_mul_vec: if (vece =3D=3D MO_8) { @@ -3331,7 +3338,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) } } =20 -static void expand_vec_shi(TCGType type, unsigned vece, bool shr, +static void expand_vec_shi(TCGType type, unsigned vece, TCGOpcode opc, TCGv_vec v0, TCGv_vec v1, TCGArg imm) { TCGv_vec t1, t2; @@ -3341,26 +3348,31 @@ static void expand_vec_shi(TCGType type, unsigned v= ece, bool shr, t1 =3D tcg_temp_new_vec(type); t2 =3D tcg_temp_new_vec(type); =20 - /* Unpack to W, shift, and repack. Tricky bits: - (1) Use punpck*bw x,x to produce DDCCBBAA, - i.e. duplicate in other half of the 16-bit lane. - (2) For right-shift, add 8 so that the high half of - the lane becomes zero. For left-shift, we must - shift up and down again. - (3) Step 2 leaves high half zero such that PACKUSWB - (pack with unsigned saturation) does not modify - the quantity. */ + /* + * Unpack to W, shift, and repack. Tricky bits: + * (1) Use punpck*bw x,x to produce DDCCBBAA, + * i.e. duplicate in other half of the 16-bit lane. + * (2) For right-shift, add 8 so that the high half of the lane + * becomes zero. For left-shift, and left-rotate, we must + * shift up and down again. + * (3) Step 2 leaves high half zero such that PACKUSWB + * (pack with unsigned saturation) does not modify + * the quantity. + */ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); =20 - if (shr) { - tcg_gen_shri_vec(MO_16, t1, t1, imm + 8); - tcg_gen_shri_vec(MO_16, t2, t2, imm + 8); + if (opc !=3D INDEX_op_rotli_vec) { + imm +=3D 8; + } + if (opc =3D=3D INDEX_op_shri_vec) { + tcg_gen_shri_vec(MO_16, t1, t1, imm); + tcg_gen_shri_vec(MO_16, t2, t2, imm); } else { - tcg_gen_shli_vec(MO_16, t1, t1, imm + 8); - tcg_gen_shli_vec(MO_16, t2, t2, imm + 8); + tcg_gen_shli_vec(MO_16, t1, t1, imm); + tcg_gen_shli_vec(MO_16, t2, t2, imm); tcg_gen_shri_vec(MO_16, t1, t1, 8); tcg_gen_shri_vec(MO_16, t2, t2, 8); } @@ -3427,6 +3439,61 @@ static void expand_vec_sari(TCGType type, unsigned v= ece, } } =20 +static void expand_vec_rotli(TCGType type, unsigned vece, + TCGv_vec v0, TCGv_vec v1, TCGArg imm) +{ + TCGv_vec t; + + if (vece =3D=3D MO_8) { + expand_vec_shi(type, vece, INDEX_op_rotli_vec, v0, v1, imm); + return; + } + + t =3D tcg_temp_new_vec(type); + tcg_gen_shli_vec(vece, t, v1, imm); + tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm); + tcg_gen_or_vec(vece, v0, v0, t); + tcg_temp_free_vec(t); +} + +static void expand_vec_rotls(TCGType type, unsigned vece, + TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh) +{ + TCGv_i32 rsh; + TCGv_vec t; + + tcg_debug_assert(vece !=3D MO_8); + + t =3D tcg_temp_new_vec(type); + rsh =3D tcg_temp_new_i32(); + + tcg_gen_neg_i32(rsh, lsh); + tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1); + tcg_gen_shls_vec(vece, t, v1, lsh); + tcg_gen_shrs_vec(vece, v0, v1, rsh); + tcg_gen_or_vec(vece, v0, v0, t); + tcg_temp_free_vec(t); + tcg_temp_free_i32(rsh); +} + +static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec sh, bool right) +{ + TCGv_vec t =3D tcg_temp_new_vec(type); + + tcg_gen_dupi_vec(vece, t, 8 << vece); + tcg_gen_sub_vec(vece, t, t, sh); + if (right) { + tcg_gen_shlv_vec(vece, t, v1, t); + tcg_gen_shrv_vec(vece, v0, v1, sh); + } else { + tcg_gen_shrv_vec(vece, t, v1, t); + tcg_gen_shlv_vec(vece, v0, v1, sh); + } + tcg_gen_or_vec(vece, v0, v0, t); + tcg_temp_free_vec(t); +} + static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) { @@ -3636,13 +3703,30 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, switch (opc) { case INDEX_op_shli_vec: case INDEX_op_shri_vec: - expand_vec_shi(type, vece, opc =3D=3D INDEX_op_shri_vec, v0, v1, a= 2); + expand_vec_shi(type, vece, opc, v0, v1, a2); break; =20 case INDEX_op_sari_vec: expand_vec_sari(type, vece, v0, v1, a2); break; =20 + case INDEX_op_rotli_vec: + expand_vec_rotli(type, vece, v0, v1, a2); + break; + + case INDEX_op_rotls_vec: + expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2))); + break; + + case INDEX_op_rotlv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + expand_vec_rotv(type, vece, v0, v1, v2, false); + break; + case INDEX_op_rotrv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + expand_vec_rotv(type, vece, v0, v1, v2, true); + break; + case INDEX_op_mul_vec: v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_mul(type, vece, v0, v1, v2); --=20 2.25.1 From nobody Thu May 16 09:34:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1591117589; cv=none; d=zohomail.com; s=zohoarc; b=T06SJerASLYTydkYSxfznc5ARNJI2Y/L45CbHtcPWB34hSfJSJxLKZEnkCfvYL8NKGuIAhIKeasbMOjx4+4qwlN/q2l0vmlBKCgv1NuPzPCLwKxkllkS2owK9ZQrEXH7u36od6/eLg9dqR4Z1xKuNNrYzYJgNbSCNu7v51g0II8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591117589; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h11sm2723630pjk.20.2020.06.02.10.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 10:02:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M61z5W4XC9s3fR/C2OCkY5mKyFMP7INMRDrb7WIzehM=; b=ti2njoz34nQLbQS9+TOEh+rMYs4y8fmSGc1Xu8G0DVo/oCYJtVQhMl8OZE9guDKTFv +aUIqxB414oPev7r4AHja42/X1D6Pbx4N5Pe4anda0a57tmLiEvFGCPki9WjWqhkZUpb RPbf1Vpm0ufeOifz5nLFoGNZ9pLYwy34VxZBAcSA0Wx90VESDqy1TNNr0DAM+YsXubA9 Kt64aeQjZKwcs8sBd2bsi5qLR2avZ1A1HQXWllQ7wsS1bFtnAqeDJZGIXPNheyVW4X8e +uWtCZNez/FMqhd2Ep+MktXNSHgrOVJizmmDHQ8RMIwzlPAcmvJOe2b8JCWIG9c1yqRk hSeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M61z5W4XC9s3fR/C2OCkY5mKyFMP7INMRDrb7WIzehM=; b=FejRH5/UoGm+wuLOlFUYEtZUbDYk1Ohyj9iwU5I9JFM2oCF+i+TEGi9YLbZvFOoVXc 2pcJ2WvsNZI6gUnxhAn3SK8YWYn4t534kAjOj2QzkGbrKed6F2mhm1kbbH5C3+zKlw8T KMhEMJ3yuoMuwBJcoSJJvhPz3MjuCFbIIm98F6u4B91QdglI4+JrofTDaq1760zk6q+E 3U0TQXzbcW4PlBE3UpLLFI7b3qUAxrcK3PJKb2e60LLKBrc0xIdzmnecg6zsqORnBpCM B/B345Wc5jlsGpMUjcMMpID6e5Q3eNrd897lGpJC1W/8Xc22YohIiuHHIKhH5VND1oy8 Dpqg== X-Gm-Message-State: AOAM531iFZy2ABlZ69KKFeq9U1NiU+0ajF3v7hAt57Mkyed1gG+hMjVA rDsWNI5ZhPCzujVIwcdKognz88boWFM= X-Google-Smtp-Source: ABdhPJwg8LVozyzOqg2ScKsTlmhQsQWqZG7EbbKhGFC6aGEkA/z93n3jiW+yOP1xDk4x6Ye8Fc8rnw== X-Received: by 2002:a62:1d89:: with SMTP id d131mr26061827pfd.294.1591117321624; Tue, 02 Jun 2020 10:02:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 06/12] tcg/aarch64: Implement INDEX_op_rotl{i,v}_vec Date: Tue, 2 Jun 2020 10:01:45 -0700 Message-Id: <20200602170151.321389-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602170151.321389-1-richard.henderson@linaro.org> References: <20200602170151.321389-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For immediate rotate , we can implement this in two instructions, using SLI. For variable rotate, the oddness of aarch64 right-shift- as-negative-left-shift means a backend-specific expansion works best. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.opc.h | 1 + tcg/aarch64/tcg-target.inc.c | 53 ++++++++++++++++++++++++++++++++++-- 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target.opc.h index 26bfd9c460..bce30accd9 100644 --- a/tcg/aarch64/tcg-target.opc.h +++ b/tcg/aarch64/tcg-target.opc.h @@ -12,3 +12,4 @@ */ =20 DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC) +DEF(aa64_sli_vec, 1, 2, 1, IMPLVEC) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 843fd0ca69..760b0e742d 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -557,6 +557,7 @@ typedef enum { I3614_SSHR =3D 0x0f000400, I3614_SSRA =3D 0x0f001400, I3614_SHL =3D 0x0f005400, + I3614_SLI =3D 0x2f005400, I3614_USHR =3D 0x2f000400, I3614_USRA =3D 0x2f001400, =20 @@ -2411,6 +2412,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_sari_vec: tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2); break; + case INDEX_op_aa64_sli_vec: + tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece)); + break; case INDEX_op_shlv_vec: tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2); break; @@ -2498,8 +2502,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_shlv_vec: case INDEX_op_bitsel_vec: return 1; + case INDEX_op_rotli_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: return -1; case INDEX_op_mul_vec: case INDEX_op_smax_vec: @@ -2517,14 +2524,24 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2, t1; + TCGv_vec v0, v1, v2, t1, t2; + TCGArg a2; =20 va_start(va, a0); v0 =3D temp_tcgv_vec(arg_temp(a0)); v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - v2 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + a2 =3D va_arg(va, TCGArg); + v2 =3D temp_tcgv_vec(arg_temp(a2)); =20 switch (opc) { + case INDEX_op_rotli_vec: + t1 =3D tcg_temp_new_vec(type); + tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); + vec_gen_4(INDEX_op_aa64_sli_vec, type, vece, + tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2= ); + tcg_temp_free_vec(t1); + break; + case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: /* Right shifts are negative left shifts for AArch64. */ @@ -2537,6 +2554,35 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, tcg_temp_free_vec(t1); break; =20 + case INDEX_op_rotlv_vec: + t1 =3D tcg_temp_new_vec(type); + tcg_gen_dupi_vec(vece, t1, 8 << vece); + tcg_gen_sub_vec(vece, t1, v2, t1); + /* Right shifts are negative left shifts for AArch64. */ + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_or_vec(vece, v0, v0, t1); + tcg_temp_free_vec(t1); + break; + + case INDEX_op_rotrv_vec: + t1 =3D tcg_temp_new_vec(type); + t2 =3D tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t1, v2); + tcg_gen_dupi_vec(vece, t2, 8 << vece); + tcg_gen_add_vec(vece, t2, t1, t2); + /* Right shifts are negative left shifts for AArch64. */ + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(t2)); + tcg_gen_or_vec(vece, v0, t1, t2); + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); + break; + default: g_assert_not_reached(); } @@ -2557,6 +2603,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef lZ_l =3D { .args_ct_str =3D { "lZ", "l" } = }; static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; static const TCGTargetOpDef w_w_w =3D { .args_ct_str =3D { "w", "w", "= w" } }; + static const TCGTargetOpDef w_0_w =3D { .args_ct_str =3D { "w", "0", "= w" } }; static const TCGTargetOpDef w_w_wO =3D { .args_ct_str =3D { "w", "w", = "wO" } }; static const TCGTargetOpDef w_w_wN =3D { .args_ct_str =3D { "w", "w", = "wN" } }; static const TCGTargetOpDef w_w_wZ =3D { .args_ct_str =3D { "w", "w", = "wZ" } }; @@ -2751,6 +2798,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &w_w_wZ; case INDEX_op_bitsel_vec: return &w_w_w_w; + case INDEX_op_aa64_sli_vec: + return &w_0_w; =20 default: return NULL; --=20 2.25.1 From nobody Thu May 16 09:34:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1591117469; cv=none; d=zohomail.com; s=zohoarc; b=h2KBd4iWG6x3QHetIdfsqi/YMpu9HY5i3hiduDGYDFuSobe46zCuyzsd8w+iva9SF0UspM6qbf651xatYKlI4PA2pB2MOlU0mzEF4TeBUS+LrHWp2KdUwC7QtF1s15P1INBXl0lVr1OChUIQVmXQN0/P/1yRpA5hEwChnhIE9Vw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591117469; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h11sm2723630pjk.20.2020.06.02.10.02.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 10:02:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=k8C/GQtIdOwZhYe9ry4RvUtTwTpZcqFEriAcRPm0GJU=; b=zOUfDWf1AOBCC2PM8rvcswZBtoNEenEmDJD7AT0WoGH0Eovhlhofh3YsNYnTkIeO4s 6vqyh+EelLsDMF5IUCrCBS4gjoHVWc44LxVYQyE4KYJNISpniZJyCIEpVI8af0dDH5UO lpyocWIPih8wLciHcmQUqIZVlQ1IaOyDCekVSgCSEAiHVU46QktMQEMHTaLTx31Ty83o zPJxtDQLYTMUWrcIJqZNIBgRdPQ66la6UYM3HxBkBVA9EusdArKXjzgIPJsv/S4KH2Md jHYqSicLPvtCMfVimB+/cwQm29eR1Yz88ZghF/hw+3FQtdIkTt3lYLEQN2x5NUlNqoCT cbGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k8C/GQtIdOwZhYe9ry4RvUtTwTpZcqFEriAcRPm0GJU=; b=JnFKLiayuAx0Ap/XbFhyoYRz+rF4RAsCxV2jX53+LfMmVAI91PWcrKyhvY5x6F/nNE +EIfXFzTAuGdRY7sdOyDIm4B7eCKQJf0vSAWvliYT6DFhIlytbmtTwJ3Lp4bM8Du6uAF ZZzhitcXnwWwIutMjgjY+7v2cafZ+VGQqW7JKTFhMn+g4vLPULg0x9ngcNq5mlAKRIO2 sRHg6z413X+knh41fIpD27b+upqQ2kX+FqagLkI/JwYcS8vrKl6/n6Kww+ATwWi2lkWd 40NBqz/00UnoDVedMbzc1W3KFx90E8dLGzWi/9j/oMEIXwevhezAfjH8uBg2xK/uKFC1 H0Mg== X-Gm-Message-State: AOAM532NNjJFY2YaDP3MfgOyFXN5uTWAXVpGsHRfFeqoZrH9AWwwyOSF rZ2hvuGIhYJ7JEB21Cx/khaO2tA0MOk= X-Google-Smtp-Source: ABdhPJwipHm0xuOYXp8zqZoEfh/Dlg3ShCakNWLXsUxg4f1H4clp48eLwDK2r7UWEv3BOSUXwrNiAA== X-Received: by 2002:a63:6dc9:: with SMTP id i192mr22560694pgc.402.1591117323072; Tue, 02 Jun 2020 10:02:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 07/12] tcg/ppc: Implement INDEX_op_rot[lr]v_vec Date: Tue, 2 Jun 2020 10:01:46 -0700 Message-Id: <20200602170151.321389-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602170151.321389-1-richard.henderson@linaro.org> References: <20200602170151.321389-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We already had support for rotlv, using a target-specific opcode; convert to use the generic opcode. Handle rotrv via simple negation. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.opc.h | 1 - tcg/ppc/tcg-target.inc.c | 23 +++++++++++++++++++---- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 4a17aebc5a..be5b2901c3 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -163,7 +163,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_rots_vec 0 -#define TCG_TARGET_HAS_rotv_vec 0 +#define TCG_TARGET_HAS_rotv_vec 1 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h index 1373f77e82..db514403c3 100644 --- a/tcg/ppc/tcg-target.opc.h +++ b/tcg/ppc/tcg-target.opc.h @@ -30,4 +30,3 @@ DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC) DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC) DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC) DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC) -DEF(ppc_rotl_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index ee1f9227c1..7da67086c6 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -2995,6 +2995,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: return vece <=3D MO_32 || have_isa_2_07; case INDEX_op_ssadd_vec: case INDEX_op_sssub_vec: @@ -3005,6 +3006,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: + case INDEX_op_rotli_vec: return vece <=3D MO_32 || have_isa_2_07 ? -1 : 0; case INDEX_op_neg_vec: return vece >=3D MO_32 && have_isa_3_00; @@ -3019,6 +3021,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) return 0; case INDEX_op_bitsel_vec: return have_vsx; + case INDEX_op_rotrv_vec: + return -1; default: return 0; } @@ -3301,7 +3305,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_ppc_pkum_vec: insn =3D pkum_op[vece]; break; - case INDEX_op_ppc_rotl_vec: + case INDEX_op_rotlv_vec: insn =3D rotl_op[vece]; break; case INDEX_op_ppc_msum_vec: @@ -3409,7 +3413,7 @@ static void expand_vec_mul(TCGType type, unsigned vec= e, TCGv_vec v0, t3 =3D tcg_temp_new_vec(type); t4 =3D tcg_temp_new_vec(type); tcg_gen_dupi_vec(MO_8, t4, -16); - vec_gen_3(INDEX_op_ppc_rotl_vec, type, MO_32, tcgv_vec_arg(t1), + vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), tcgv_vec_arg(v2), tcgv_vec_arg(t4)); vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v2)); @@ -3434,7 +3438,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, u= nsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2; + TCGv_vec v0, v1, v2, t0; TCGArg a2; =20 va_start(va, a0); @@ -3452,6 +3456,9 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, u= nsigned vece, case INDEX_op_sari_vec: expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); break; + case INDEX_op_rotli_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec); + break; case INDEX_op_cmp_vec: v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); @@ -3460,6 +3467,13 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_mul(type, vece, v0, v1, v2); break; + case INDEX_op_rotlv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + t0 =3D tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t0, v2); + tcg_gen_rotlv_vec(vece, v0, v1, t0); + tcg_temp_free_vec(t0); + break; default: g_assert_not_reached(); } @@ -3664,12 +3678,13 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: case INDEX_op_ppc_mrgh_vec: case INDEX_op_ppc_mrgl_vec: case INDEX_op_ppc_muleu_vec: case INDEX_op_ppc_mulou_vec: case INDEX_op_ppc_pkum_vec: - case INDEX_op_ppc_rotl_vec: case INDEX_op_dup2_vec: return &v_v_v; case INDEX_op_not_vec: --=20 2.25.1 From nobody Thu May 16 09:34:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1591117670; cv=none; d=zohomail.com; s=zohoarc; b=Jt92gDOo76cg7YJmu+RIgzHFMs8FAXcjg0m72vPNjo14hZ3QiiuzmIB3rOQ2UgR/0CjnpOOpwQs7qoKi/UySwF4aguaDHz7DzbhMRllSYpZeH6L3irH+lnlfQQLZ7zFphhJIPdAqm4sauMvPWjX2Mx3OhBzKVpwkVcQT7rfkcW0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591117670; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=P9h5TBP5WOCBKRHaXQjwNWHN1Wi1jSCendyQQuP2OXQ=; b=Q3rVPQHqCXZQd7f6g60U2+UZCEREbYdBReTsR4Aklmcw75cuIKfe3wAmsIJtxZylfydGz0E8eFjoq/IBspC6hCedCLLTivllFEPsP1A5W7jt5fckhw3Vp72wBqbbUXD/Ln+u3MVNWWey3NTjRwT2sff2wmwWfLZmBHvnYgTczq4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591117670477357.12531266635847; Tue, 2 Jun 2020 10:07:50 -0700 (PDT) Received: from localhost ([::1]:39854 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jgAOD-0008Ty-BM for importer@patchew.org; Tue, 02 Jun 2020 13:07:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39814) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgAIh-0005pX-Fl for qemu-devel@nongnu.org; Tue, 02 Jun 2020 13:02:07 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:47015) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jgAIg-0007Qo-CI for qemu-devel@nongnu.org; Tue, 02 Jun 2020 13:02:07 -0400 Received: by mail-pl1-x62b.google.com with SMTP id n2so1562091pld.13 for ; Tue, 02 Jun 2020 10:02:05 -0700 (PDT) Received: from localhost.localdomain (174-21-143-238.tukw.qwest.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Acked-by: David Gibson Signed-off-by: Richard Henderson --- target/ppc/helper.h | 4 ---- target/ppc/int_helper.c | 17 ----------------- target/ppc/translate/vmx-impl.inc.c | 8 ++++---- 3 files changed, 4 insertions(+), 25 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 2dfa1c6942..90166cbabd 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -214,10 +214,6 @@ DEF_HELPER_3(vsubuqm, void, avr, avr, avr) DEF_HELPER_4(vsubecuq, void, avr, avr, avr, avr) DEF_HELPER_4(vsubeuqm, void, avr, avr, avr, avr) DEF_HELPER_3(vsubcuq, void, avr, avr, avr) -DEF_HELPER_3(vrlb, void, avr, avr, avr) -DEF_HELPER_3(vrlh, void, avr, avr, avr) -DEF_HELPER_3(vrlw, void, avr, avr, avr) -DEF_HELPER_3(vrld, void, avr, avr, avr) DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32) DEF_HELPER_3(vextractub, void, avr, avr, i32) DEF_HELPER_3(vextractuh, void, avr, avr, i32) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index be53cd6f68..d8bd3c234a 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -1348,23 +1348,6 @@ VRFI(p, float_round_up) VRFI(z, float_round_to_zero) #undef VRFI =20 -#define VROTATE(suffix, element, mask) \ - void helper_vrl##suffix(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ - { \ - int i; \ - \ - for (i =3D 0; i < ARRAY_SIZE(r->element); i++) { \ - unsigned int shift =3D b->element[i] & mask; \ - r->element[i] =3D (a->element[i] << shift) | \ - (a->element[i] >> (sizeof(a->element[0]) * 8 - shift)); \ - } \ - } -VROTATE(b, u8, 0x7) -VROTATE(h, u16, 0xF) -VROTATE(w, u32, 0x1F) -VROTATE(d, u64, 0x3F) -#undef VROTATE - void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b) { int i; diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index 403ed3a01c..de2fd136ff 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -900,13 +900,13 @@ GEN_VXFORM3(vsubeuqm, 31, 0); GEN_VXFORM3(vsubecuq, 31, 0); GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ vsubecuq, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM(vrlb, 2, 0); -GEN_VXFORM(vrlh, 2, 1); -GEN_VXFORM(vrlw, 2, 2); +GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0); +GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1); +GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2); GEN_VXFORM(vrlwmi, 2, 2); GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \ vrlwmi, PPC_NONE, PPC2_ISA300) -GEN_VXFORM(vrld, 2, 3); +GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3); GEN_VXFORM(vrldmi, 2, 3); GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \ vrldmi, PPC_NONE, PPC2_ISA300) --=20 2.25.1 From nobody Thu May 16 09:34:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1591117589; cv=none; d=zohomail.com; s=zohoarc; b=D0dW4/6jOKJbe52wHqjYbdthWqBaZntQhFVGyRSX+8w3wsFbEXtNSRZzSItSHgkn0KD9ZwjiS3OdkIlOvcWYIKWhOevmYCmlcKBVCDhYtQANN9/cz9djKxzooePEkbEOSA0IUegYFN5t7VNC5IaPVzoiGl95cgNETg75a1z+OdU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591117588; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Merge VERLL and VERLLV into op_vesv and op_ves, alongside all of the other vector shift operations. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/helper.h | 4 -- target/s390x/translate_vx.inc.c | 66 +++++---------------------------- target/s390x/vec_int_helper.c | 31 ---------------- target/s390x/insn-data.def | 4 +- 4 files changed, 11 insertions(+), 94 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index b5813c2ac2..b7887b552b 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -198,10 +198,6 @@ DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void,= ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i3= 2) DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32) DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32) -DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i= 32) -DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, = i32) -DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) -DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i3= 2) DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i3= 2) DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i= 32) DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.in= c.c index 12347f8a03..eb767f5288 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -1825,63 +1825,6 @@ static DisasJumpType op_vpopct(DisasContext *s, Disa= sOps *o) return DISAS_NEXT; } =20 -static void gen_rll_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_i32 t0 =3D tcg_temp_new_i32(); - - tcg_gen_andi_i32(t0, b, 31); - tcg_gen_rotl_i32(d, a, t0); - tcg_temp_free_i32(t0); -} - -static void gen_rll_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - TCGv_i64 t0 =3D tcg_temp_new_i64(); - - tcg_gen_andi_i64(t0, b, 63); - tcg_gen_rotl_i64(d, a, t0); - tcg_temp_free_i64(t0); -} - -static DisasJumpType op_verllv(DisasContext *s, DisasOps *o) -{ - const uint8_t es =3D get_field(s, m4); - static const GVecGen3 g[4] =3D { - { .fno =3D gen_helper_gvec_verllv8, }, - { .fno =3D gen_helper_gvec_verllv16, }, - { .fni4 =3D gen_rll_i32, }, - { .fni8 =3D gen_rll_i64, }, - }; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - gen_gvec_3(get_field(s, v1), get_field(s, v2), - get_field(s, v3), &g[es]); - return DISAS_NEXT; -} - -static DisasJumpType op_verll(DisasContext *s, DisasOps *o) -{ - const uint8_t es =3D get_field(s, m4); - static const GVecGen2s g[4] =3D { - { .fno =3D gen_helper_gvec_verll8, }, - { .fno =3D gen_helper_gvec_verll16, }, - { .fni4 =3D gen_rll_i32, }, - { .fni8 =3D gen_rll_i64, }, - }; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - gen_gvec_2s(get_field(s, v1), get_field(s, v3), o->addr1, - &g[es]); - return DISAS_NEXT; -} - static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c) { TCGv_i32 t =3D tcg_temp_new_i32(); @@ -1946,6 +1889,9 @@ static DisasJumpType op_vesv(DisasContext *s, DisasOp= s *o) case 0x70: gen_gvec_fn_3(shlv, es, v1, v2, v3); break; + case 0x73: + gen_gvec_fn_3(rotlv, es, v1, v2, v3); + break; case 0x7a: gen_gvec_fn_3(sarv, es, v1, v2, v3); break; @@ -1977,6 +1923,9 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps= *o) case 0x30: gen_gvec_fn_2i(shli, es, v1, v3, d2); break; + case 0x33: + gen_gvec_fn_2i(rotli, es, v1, v3, d2); + break; case 0x3a: gen_gvec_fn_2i(sari, es, v1, v3, d2); break; @@ -1994,6 +1943,9 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps= *o) case 0x30: gen_gvec_fn_2s(shls, es, v1, v3, shift); break; + case 0x33: + gen_gvec_fn_2s(rotls, es, v1, v3, shift); + break; case 0x3a: gen_gvec_fn_2s(sars, es, v1, v3, shift); break; diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c index 0d6bc13dd6..5561b3ed90 100644 --- a/target/s390x/vec_int_helper.c +++ b/target/s390x/vec_int_helper.c @@ -515,37 +515,6 @@ void HELPER(gvec_vpopct##BITS)(void *v1, const void *v= 2, uint32_t desc) \ DEF_VPOPCT(8) DEF_VPOPCT(16) =20 -#define DEF_VERLLV(BITS) = \ -void HELPER(gvec_verllv##BITS)(void *v1, const void *v2, const void *v3, = \ - uint32_t desc) = \ -{ = \ - int i; = \ - = \ - for (i =3D 0; i < (128 / BITS); i++) { = \ - const uint##BITS##_t a =3D s390_vec_read_element##BITS(v2, i); = \ - const uint##BITS##_t b =3D s390_vec_read_element##BITS(v3, i); = \ - = \ - s390_vec_write_element##BITS(v1, i, rol##BITS(a, b)); = \ - } = \ -} -DEF_VERLLV(8) -DEF_VERLLV(16) - -#define DEF_VERLL(BITS) = \ -void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count, = \ - uint32_t desc) = \ -{ = \ - int i; = \ - = \ - for (i =3D 0; i < (128 / BITS); i++) { = \ - const uint##BITS##_t a =3D s390_vec_read_element##BITS(v2, i); = \ - = \ - s390_vec_write_element##BITS(v1, i, rol##BITS(a, count)); = \ - } = \ -} -DEF_VERLL(8) -DEF_VERLL(16) - #define DEF_VERIM(BITS) = \ void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3, = \ uint32_t desc) = \ diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 2bc77f0871..91ddaedd84 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1147,8 +1147,8 @@ /* VECTOR POPULATION COUNT */ F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC) /* VECTOR ELEMENT ROTATE LEFT LOGICAL */ - F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC) - F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC) + F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC) + F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC) /* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */ F(0xe772, VERIM, VRI_d, V, 0, 0, 0, 0, verim, 0, IF_VEC) /* VECTOR ELEMENT SHIFT LEFT */ --=20 2.25.1 From nobody Thu May 16 09:34:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h11sm2723630pjk.20.2020.06.02.10.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 10:02:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tHqpToSLuNmT3+mxdztxkjY6kBf+OhopPIY/mAzI0FM=; b=zWXRad9lLOfYB1kXttHNm+JcpktLPnPGpwp7jC0FwNZQCg6PRYkS/OIVgOKccBA2TM /B3USpHFUcUsyinpJiow+8rOYAwHUbDr0Kud7Ec3k6gZS6qdKFZoUcZn4ptlBgxUdB7W G4olbpY4UX7ECn4Cn4SAhG56tycAYLDCdztHq+w4kDvn5QknpsGq/VPBwo+utQNttTwv HvL1uKdBB6QEUi0MZkegsskymKLBSe4rcdMvLZ0OBL3FH4/bwyQ+0sSrXdBPlUT2jCo+ avA56rJnHa07OjSF05fUoGSlAJKy/WbsLlkm3SW3oV3ehkBE3RIu3Rn5cbiCKuHG1K86 O8kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tHqpToSLuNmT3+mxdztxkjY6kBf+OhopPIY/mAzI0FM=; b=NQFBf2cJmqAPtL6+9fwPI33WfWDniJiincnKqoa9pEPcxEpMp8jzpR7ftUd4EUG1hb o/iIQzqmTXcPKV4OkLuW6nF3QR9kn2kqW2sDM29VKpZI2g/YmCpv/Lis7Tg3Kto1kIlJ AUferlV8GEIYUoZ37uooOUgfCJ2pZGHcH4uqz1iIZljI9RSSiGQFEmflgWx9rpU/K14u 5tyGtcYe0Ky4Stw0gdREz0Euv8QuABIoieFm5yXtopQzWYyOCPfIYnb8njQJNmTb0BdI pudmBGjKHMY6vmAKR9INEqaAEtx42LTvM73h7oHP7CooGfYAGI0i7mPF+htdFVjLstRC v9aA== X-Gm-Message-State: AOAM530079jYTOFzhNDxuGs9fI6fG7H/shnAfdiYVAbcHztXZH5SJiin jzqboaJJaeTf5rE+Si6R+Q4jSf6pVcA= X-Google-Smtp-Source: ABdhPJxGjH5MdEur0AM3tXciVZgUXl0C6kbK91WqbKJVgQU1pkO91xxYk7KNGEg0Y6LfueCl8a05DQ== X-Received: by 2002:a17:902:c3d3:: with SMTP id j19mr26285210plj.47.1591117326991; Tue, 02 Jun 2020 10:02:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/12] tcg: Improve move ops in liveness_pass_2 Date: Tue, 2 Jun 2020 10:01:49 -0700 Message-Id: <20200602170151.321389-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602170151.321389-1-richard.henderson@linaro.org> References: <20200602170151.321389-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" If the output of the move is dead, then the last use is in the store. If we propagate the input to the store, then we can remove the move opcode entirely. Signed-off-by: Richard Henderson --- tcg/tcg.c | 78 +++++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 56 insertions(+), 22 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 97558ec068..1aa6cb47f2 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2982,34 +2982,68 @@ static bool liveness_pass_2(TCGContext *s) } =20 /* Outputs become available. */ - for (i =3D 0; i < nb_oargs; i++) { - arg_ts =3D arg_temp(op->args[i]); + if (opc =3D=3D INDEX_op_mov_i32 || opc =3D=3D INDEX_op_mov_i64) { + arg_ts =3D arg_temp(op->args[0]); dir_ts =3D arg_ts->state_ptr; - if (!dir_ts) { - continue; + if (dir_ts) { + op->args[0] =3D temp_arg(dir_ts); + changes =3D true; + + /* The output is now live and modified. */ + arg_ts->state =3D 0; + + if (NEED_SYNC_ARG(0)) { + TCGOpcode sopc =3D (arg_ts->type =3D=3D TCG_TYPE_I32 + ? INDEX_op_st_i32 + : INDEX_op_st_i64); + TCGOp *sop =3D tcg_op_insert_after(s, op, sopc); + TCGTemp *out_ts =3D dir_ts; + + if (IS_DEAD_ARG(0)) { + out_ts =3D arg_temp(op->args[1]); + arg_ts->state =3D TS_DEAD; + tcg_op_remove(s, op); + } else { + arg_ts->state =3D TS_MEM; + } + + sop->args[0] =3D temp_arg(out_ts); + sop->args[1] =3D temp_arg(arg_ts->mem_base); + sop->args[2] =3D arg_ts->mem_offset; + } else { + tcg_debug_assert(!IS_DEAD_ARG(0)); + } } - op->args[i] =3D temp_arg(dir_ts); - changes =3D true; + } else { + for (i =3D 0; i < nb_oargs; i++) { + arg_ts =3D arg_temp(op->args[i]); + dir_ts =3D arg_ts->state_ptr; + if (!dir_ts) { + continue; + } + op->args[i] =3D temp_arg(dir_ts); + changes =3D true; =20 - /* The output is now live and modified. */ - arg_ts->state =3D 0; + /* The output is now live and modified. */ + arg_ts->state =3D 0; =20 - /* Sync outputs upon their last write. */ - if (NEED_SYNC_ARG(i)) { - TCGOpcode sopc =3D (arg_ts->type =3D=3D TCG_TYPE_I32 - ? INDEX_op_st_i32 - : INDEX_op_st_i64); - TCGOp *sop =3D tcg_op_insert_after(s, op, sopc); + /* Sync outputs upon their last write. */ + if (NEED_SYNC_ARG(i)) { + TCGOpcode sopc =3D (arg_ts->type =3D=3D TCG_TYPE_I32 + ? INDEX_op_st_i32 + : INDEX_op_st_i64); + TCGOp *sop =3D tcg_op_insert_after(s, op, sopc); =20 - sop->args[0] =3D temp_arg(dir_ts); - sop->args[1] =3D temp_arg(arg_ts->mem_base); - sop->args[2] =3D arg_ts->mem_offset; + sop->args[0] =3D temp_arg(dir_ts); + sop->args[1] =3D temp_arg(arg_ts->mem_base); + sop->args[2] =3D arg_ts->mem_offset; =20 - arg_ts->state =3D TS_MEM; - } - /* Drop outputs that are dead. */ - if (IS_DEAD_ARG(i)) { - arg_ts->state =3D TS_DEAD; + arg_ts->state =3D TS_MEM; + } + /* Drop outputs that are dead. */ + if (IS_DEAD_ARG(i)) { + arg_ts->state =3D TS_DEAD; + } } } } --=20 2.25.1 From nobody Thu May 16 09:34:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1591117677; cv=none; d=zohomail.com; s=zohoarc; b=B96CcgwYfdVS3b6mpiVD4a7lXGYMpKaR8+e+s+Bskfd+m+FhvqEp5NL+HUn3wmAvibwRbcwCHbXf59wIirLm6/6DrcUhB82FA5u34wAIOEHYXy4BPWhdtSZEQ06xDzmWPNzS/q3C2ZAAH8+X/lc4x7Kmc1TR5n8FJVq7bTyO25k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591117677; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v9PYVllY3D8WNVt+/GwKgHsq/9t/7VocWb4hJT0OXq8=; b=Flzmg2WAnbhh8HIURXFc3l+hcgOUh17D5hU0g7k8l/e/OHN0kwsIaQdRvA6DvZnZ4cKaelqbk9pJRjfa72CEhbeFxRQKXUX0CY8pVN9VoDbDuLLE6zjGaCXc2+XvQoyykxDcY/QMgK2tFQOj2NmOMTOn6PWzvQVHLeUO6PM/8fU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591117677160429.2817924978659; Tue, 2 Jun 2020 10:07:57 -0700 (PDT) Received: from localhost ([::1]:39988 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jgAOH-00005j-VQ for importer@patchew.org; Tue, 02 Jun 2020 13:07:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgAIl-00060q-U6 for qemu-devel@nongnu.org; Tue, 02 Jun 2020 13:02:11 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:46880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jgAIk-0007R9-UV for qemu-devel@nongnu.org; Tue, 02 Jun 2020 13:02:11 -0400 Received: by mail-pg1-x542.google.com with SMTP id p21so5331777pgm.13 for ; Tue, 02 Jun 2020 10:02:10 -0700 (PDT) Received: from localhost.localdomain (174-21-143-238.tukw.qwest.net. [174.21.143.238]) by smtp.gmail.com with ESMTPSA id h11sm2723630pjk.20.2020.06.02.10.02.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 10:02:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v9PYVllY3D8WNVt+/GwKgHsq/9t/7VocWb4hJT0OXq8=; b=DUdqWApC0mD3QNG3NHWDAoEp6AeMLviM5Ltzd//uViT8ztuR4zhDiIqWpXr8/67See DBbv3ps0XeHWqfy5gDGJKoSe3w0SkUw6rBUX/HcbMMA1UuYVlqL0YPjmsYT1Ygp0SZ/i gicj2s4i7z9llKYQXZtGzUiSRxHLHoGsxZAJTt8+Kb5td8eV2pscyBNwTfW05KMG5uxq iCMwW9APn96zQABSKcKQrd9xiEdjX8J1Djh5/Qd7bGE27yGlQhX2Zm3Z7yN6T7UiB/xX fLp3MljyRaQDUs6opaP3wuWiJUnsyg2l0rpuZx26hMTpLTHNGAMu0RlRM+g/EsWXhSWs gmFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v9PYVllY3D8WNVt+/GwKgHsq/9t/7VocWb4hJT0OXq8=; b=adnptLaXCCpg3TrKqa90JRjmlCJrH5PtgwxD3RxDxcWExqRTv+BTkEar6tDybZZs0k 2P9IhhFQ9SgEs1GMdY1mtZwjvn9Pb9QmtLXqKlebhNzVAUCZnxbn2+3NmlnGuZqu+4cy JMNfha9NFaT3tvtPqReNAtqrL/OOnujankwG9rNAxUhvLvwW11ylqfscehYhC7puWRtM X23UECNUZtM9gfayG3/3fFbZwtQvBu++4fpa2yzkqy4LWjLwgKrQZPOHaBw88J5nPUEM C2i0Jx99Oc9fSfRe+V+xmvj1C2Rfa1t/MiA6R9a9Sa4qMogJIEIE0fDJsMcfeJuNbWYi 04ew== X-Gm-Message-State: AOAM533yVJRc7WBYXYhp091KzKPsLNRFcCsHsdD0A0ZR9zw2atarrK6i ukvczWTgGTXYucd50KQYMK/fJrISv2A= X-Google-Smtp-Source: ABdhPJxoPtaqaA0Y5mlpcLKtnsmfYi2cp5VbxYGp+2HlAU6LEsWJ3NWxdThCpMZSdrSE2iiuNHGFlQ== X-Received: by 2002:a63:724a:: with SMTP id c10mr24670392pgn.130.1591117328540; Tue, 02 Jun 2020 10:02:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 11/12] accel/tcg: Adjust cpu_signal_handler for NetBSD/arm Date: Tue, 2 Jun 2020 10:01:50 -0700 Message-Id: <20200602170151.321389-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602170151.321389-1-richard.henderson@linaro.org> References: <20200602170151.321389-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nick Hudson , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Nick Hudson Fix building on NetBSD/arm by extracting the FSR value from the correct siginfo_t field. Reviewed-by: Richard Henderson Signed-off-by: Nick Hudson Message-Id: <20200516154147.24842-1-skrll@netbsd.org> Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 52359949df..bc391eb454 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -517,6 +517,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, =20 #if defined(__NetBSD__) #include +#include #endif =20 int cpu_signal_handler(int host_signum, void *pinfo, @@ -525,10 +526,12 @@ int cpu_signal_handler(int host_signum, void *pinfo, siginfo_t *info =3D pinfo; #if defined(__NetBSD__) ucontext_t *uc =3D puc; + siginfo_t *si =3D pinfo; #else ucontext_t *uc =3D puc; #endif unsigned long pc; + uint32_t fsr; int is_write; =20 #if defined(__NetBSD__) @@ -539,10 +542,17 @@ int cpu_signal_handler(int host_signum, void *pinfo, pc =3D uc->uc_mcontext.arm_pc; #endif =20 - /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 = or - * later processor; on v5 we will always report this as a read). +#ifdef __NetBSD__ + fsr =3D si->si_trap; +#else + fsr =3D uc->uc_mcontext.error_code; +#endif + /* + * In the FSR, bit 11 is WnR, assuming a v6 or + * later processor. On v5 we will always report + * this as a read, which will fail later. */ - is_write =3D extract32(uc->uc_mcontext.error_code, 11, 1); + is_write =3D extract32(fsr, 11, 1); return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } =20 --=20 2.25.1 From nobody Thu May 16 09:34:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1591117753; cv=none; d=zohomail.com; s=zohoarc; b=L4zL90i1F+CDqEzmzW+DrOTV0Y/+VKDYMVxSusiq2q/bxdfoBTlXchOrZSqOZkQBouiXVmdTWor/ydIWBsixTd6cLqcoawMdSm0MvRH5awenOuJrSVWW7SwuqWKScAUpCCKMzXSYMwwmHD0VuJjuZeKnmOKs5I+Layh+uO5rfVw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591117753; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=75Vplu19HS/DHLmTzwjn2UXzNvNogzB2TCcDPegRLPA=; b=Asj6hTJhvjdLGt9o//kErDo2OCoG7RTfA+m9KgqF7XewKYtCcPos4PsthNyxEXTF3FW3YzMKDx436yTt4CFV6olx2jWwsFJzih1CAjBF5MHNdQ1RFeqyI2MfW+iTtFNaAd/y59LvaO5j2PfQd2pOKNom4jt3Mc6x3YS+rmC+Dzs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15911177538161012.0720590154102; Tue, 2 Jun 2020 10:09:13 -0700 (PDT) Received: from localhost ([::1]:46386 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jgAPY-0002n0-Hb for importer@patchew.org; Tue, 02 Jun 2020 13:09:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgAIn-00063S-1E for qemu-devel@nongnu.org; Tue, 02 Jun 2020 13:02:13 -0400 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:35881) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jgAIm-0007RK-0b for qemu-devel@nongnu.org; Tue, 02 Jun 2020 13:02:12 -0400 Received: by mail-pj1-x1044.google.com with SMTP id q24so1759278pjd.1 for ; Tue, 02 Jun 2020 10:02:11 -0700 (PDT) Received: from localhost.localdomain (174-21-143-238.tukw.qwest.net. [174.21.143.238]) by smtp.gmail.com with ESMTPSA id h11sm2723630pjk.20.2020.06.02.10.02.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 10:02:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=75Vplu19HS/DHLmTzwjn2UXzNvNogzB2TCcDPegRLPA=; b=TD//greZdcMVGpGCfkS/vfsPiN2mKqVLWb+Y8M7P0ZGSt/amqE2M8AXXFH+BxmBiak /QRL7cnOYYAi4UQbcnoauITjbxEPcpV2UD+oedqOee9rIL3wEs5rvuSia7Kutr3rzhJs RjV8AeU3sVxvPa1B+r0ePqlk2ycy0PAPv7aZf4etkw9Pken3JUOeO/quZ5FhIe2JxKr8 WriBkWQpo1OVDHKstYsiKdy+iB/4wLaPn5o6OqoYVUn3DCv/sVS30tQ0fFTk1qvXVjX8 5aTobF2oh/X7EauNtEE6+gYMtbBZ+P2r4mCxJKjqDTTYhdOCF8yZhoJH6MSs/9zJd2V2 9EoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=75Vplu19HS/DHLmTzwjn2UXzNvNogzB2TCcDPegRLPA=; b=gv9CbVl+k3nQa43sofMuaOz6cBWWDRX1HhD7rDD0UGDQBpSWjyMkwKOB6hBxZ/WPra uv9GO+lvN/H1cmOyWksZCrDgimXEN0o38c7s2NUwS/mpIO3C88IL5C3u7NtOoyYTT8er eMTpu/mEkz9u7V/Ve26wHxdJ3iv8/J7y/E1nOrov/kO8+8qS1qL6R2XMo/IVoNneZTcQ CwjX6Pfg+x+ObMU4oC9MI+9vNH3w7v5S94q/141q/s73xWZ19k7F9Cga7YvyXRuloXuL roccVNfhiUgBU65cvKn6INZ1GzKAjEp/H48FbJoOKd34tcuLgHBs5puUIs9oD4oqfyAu S7aw== X-Gm-Message-State: AOAM530k/r9J/FeDlsnukKRquivVZGKukTjNIaLFUg56YKB85pTqgXiV 0Jc/eEce/Ujth2KEJ7MlzO+UaiespfU= X-Google-Smtp-Source: ABdhPJwpd0KeBHNo/5K+SiOr4V3x3JcLE32/rkmjRXcnOjbBoxo2dchrxs7wiDj8AzbpedcC28RH1Q== X-Received: by 2002:a17:902:b904:: with SMTP id bf4mr25761929plb.89.1591117330197; Tue, 02 Jun 2020 10:02:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 12/12] accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handler Date: Tue, 2 Jun 2020 10:01:51 -0700 Message-Id: <20200602170151.321389-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602170151.321389-1-richard.henderson@linaro.org> References: <20200602170151.321389-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nick Hudson , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Nick Hudson Fix qemu build on NetBSD/evbarm-aarch64 by providing a NetBSD specific cpu_signal_handler. Reviewed-by: Richard Henderson Signed-off-by: Nick Hudson Message-Id: <20200517101529.5367-1-skrll@netbsd.org> Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index bc391eb454..d8b027f8c1 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -558,6 +558,32 @@ int cpu_signal_handler(int host_signum, void *pinfo, =20 #elif defined(__aarch64__) =20 +#if defined(__NetBSD__) + +#include +#include + +int cpu_signal_handler(int host_signum, void *pinfo, void *puc) +{ + ucontext_t *uc =3D puc; + siginfo_t *si =3D pinfo; + unsigned long pc; + int is_write; + uint32_t esr; + + pc =3D uc->uc_mcontext.__gregs[_REG_PC]; + esr =3D si->si_trap; + + /* + * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC + * is 0b10010x: then bit 6 is the WnR bit + */ + is_write =3D extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6, 1)= =3D=3D 1; + return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask); +} + +#else + #ifndef ESR_MAGIC /* Pre-3.16 kernel headers don't have these, so provide fallback definitio= ns */ #define ESR_MAGIC 0x45535201 @@ -620,6 +646,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, vo= id *puc) } return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } +#endif =20 #elif defined(__s390__) =20 --=20 2.25.1