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X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/cpu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/rx/cpu.h b/target/rx/cpu.h index d1fb1ef3ca..0645ba3b6f 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -19,8 +19,6 @@ #ifndef RX_CPU_H #define RX_CPU_H =20 -#include "qemu/bitops.h" -#include "qemu-common.h" #include "hw/registerfields.h" #include "cpu-qom.h" =20 --=20 2.21.3 From nobody Fri May 17 01:43:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1591028184; cv=none; d=zohomail.com; s=zohoarc; b=CZIGl40HBcvXugpB+CUUlx9T0/eh+BUObpEZLUO8b/9ycSFjs0bOFxGoielLUfgI1V8mK8W2eUdq/TRwxTADx1SxvyofpQjNgMPz2P5+TSeD/PDagtciVgz6bF0RskEJXnrcUMTpewTAK0UnEVSXdRlvdZjGFHI9OdjTajI+/x0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591028184; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NA3HxowRBgdQR4zG7dIwLOdIlhd4o6KOpVFcc0np+Vo=; b=XX0WJ4FANbmOweWaMnMvUhIlVoIr3XnUrHJJXdSt8TaTb+YTx6MuRo1PyttMGxhDGX3FwoS5CVlN7B7rJ7Qcnx8jt8UlEuC+XP+ININJ05G/kXYd+kE1CmLcrrgoEkWgRtnQmNUqKnGTBPEnXqliAyyjRmzCX9LNh+ErHTIOKt4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159102818486659.14181878467798; Mon, 1 Jun 2020 09:16:24 -0700 (PDT) Received: from localhost ([::1]:55922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jfn6t-0006hd-Cp for importer@patchew.org; Mon, 01 Jun 2020 12:16:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50882) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jfn5L-0004zh-NR for qemu-devel@nongnu.org; Mon, 01 Jun 2020 12:14:47 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:41186) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jfn5L-0001VU-1o for qemu-devel@nongnu.org; Mon, 01 Jun 2020 12:14:47 -0400 Received: by mail-wr1-x434.google.com with SMTP id j10so393963wrw.8 for ; Mon, 01 Jun 2020 09:14:46 -0700 (PDT) Received: from localhost.localdomain (43.red-83-51-162.dynamicip.rima-tde.net. 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That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato Signed-off-by: Yoshinori Sato Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-2-ysato@users.sourceforge.jp> [PMD: Renamed as gdbsim, add acceptance test file and rST doc] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0944d9c731..ac2e82eb19 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1238,6 +1238,21 @@ F: pc-bios/canyonlands.dt[sb] F: pc-bios/u-boot-sam460ex-20100605.bin F: roms/u-boot-sam460ex =20 +RX Machines +----------- +rx-gdbsim +M: Yoshinori Sato +S: Maintained +F: docs/system/target-rx.rst +F: hw/rx/ +F: hw/intc/rx_icu.c +F: hw/timer/renesas_*.c +F: hw/char/renesas_sci.c +F: include/hw/rx/ +F: include/hw/timer/renesas_*.h +F: include/hw/char/renesas_sci.h +F: tests/acceptance/machine_rx_gdbsim.py + SH4 Machines ------------ R2D --=20 2.21.3 From nobody Fri May 17 01:43:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1591028313; cv=none; d=zohomail.com; s=zohoarc; b=SUvaG727F+8sj0iqucwdkKy3U7L+DeC0klutrCfzvWm6yDTzfB0gFUDYacMusVKOToY2ppj+O0UJ5h7HAgkHXtt8wbklGA3UsvGSdYYtqTbsJ988/nVyDUd90W2J2cc7+Fnce2oDal5bukm5Vsk4659a684LB9NKCgS+MlVcoyc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591028313; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p2jgajganxLEDZOO6UpHmOY8HDjZV+a5//BhQvTt+ck=; b=DGFDCkiGjn+l8Wfj/VkLH1DfGczm7vBsKf0KX+g4UY46Y8v2D1uv63wTgr/1Wc0xTQGuSQky6J2N5jpkV2tm0idgdWqlmv1Kg/t3Gj1ieE0dcYxGfGZhbtADuXF+MxDzQKf6O3SdjzGGf3jKqc3rECSWDNvmFS+gw21fz0t+N2M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591028313791257.60367743549773; Mon, 1 Jun 2020 09:18:33 -0700 (PDT) Received: from localhost ([::1]:36366 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jfn8y-0001mQ-B9 for importer@patchew.org; Mon, 01 Jun 2020 12:18:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50894) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jfn5O-00055f-J5 for qemu-devel@nongnu.org; Mon, 01 Jun 2020 12:14:50 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:33642) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jfn5N-0001Vn-5F for qemu-devel@nongnu.org; Mon, 01 Jun 2020 12:14:50 -0400 Received: by mail-wr1-x429.google.com with SMTP id l11so445553wru.0 for ; Mon, 01 Jun 2020 09:14:48 -0700 (PDT) Received: from localhost.localdomain (43.red-83-51-162.dynamicip.rima-tde.net. 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That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato This implementation supported only ICUa. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej= 0140_rx62n.pdf Signed-off-by: Yoshinori Sato Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-15-ysato@users.sourceforge.jp> [PMD: Filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/intc/rx_icu.h | 76 ++++++++ hw/intc/rx_icu.c | 397 +++++++++++++++++++++++++++++++++++++++ hw/intc/Kconfig | 3 + hw/intc/Makefile.objs | 1 + 4 files changed, 477 insertions(+) create mode 100644 include/hw/intc/rx_icu.h create mode 100644 hw/intc/rx_icu.c diff --git a/include/hw/intc/rx_icu.h b/include/hw/intc/rx_icu.h new file mode 100644 index 0000000000..7176015cd9 --- /dev/null +++ b/include/hw/intc/rx_icu.h @@ -0,0 +1,76 @@ +/* + * RX Interrupt Control Unit + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_INTC_RX_ICU_H +#define HW_INTC_RX_ICU_H + +#include "hw/sysbus.h" + +enum TRG_MODE { + TRG_LEVEL =3D 0, + TRG_NEDGE =3D 1, /* Falling */ + TRG_PEDGE =3D 2, /* Raising */ + TRG_BEDGE =3D 3, /* Both */ +}; + +struct IRQSource { + enum TRG_MODE sense; + int level; +}; + +enum { + /* Software interrupt request */ + SWI =3D 27, + NR_IRQS =3D 256 +}; + +struct RXICUState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion memory; + struct IRQSource src[NR_IRQS]; + uint32_t nr_irqs; + uint8_t *map; + uint32_t nr_sense; + uint8_t *init_sense; + + uint8_t ir[NR_IRQS]; + uint8_t dtcer[NR_IRQS]; + uint8_t ier[NR_IRQS / 8]; + uint8_t ipr[142]; + uint8_t dmasr[4]; + uint16_t fir; + uint8_t nmisr; + uint8_t nmier; + uint8_t nmiclr; + uint8_t nmicr; + int16_t req_irq; + qemu_irq _irq; + qemu_irq _fir; + qemu_irq _swi; +}; +typedef struct RXICUState RXICUState; + +#define TYPE_RX_ICU "rx-icu" +#define RX_ICU(obj) OBJECT_CHECK(RXICUState, (obj), TYPE_RX_ICU) + +#endif /* RX_ICU_H */ diff --git a/hw/intc/rx_icu.c b/hw/intc/rx_icu.c new file mode 100644 index 0000000000..df4b6a8d22 --- /dev/null +++ b/hw/intc/rx_icu.c @@ -0,0 +1,397 @@ +/* + * RX Interrupt Control Unit + * + * Warning: Only ICUa is supported. + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/qdev-properties.h" +#include "hw/intc/rx_icu.h" +#include "migration/vmstate.h" + +REG8(IR, 0) + FIELD(IR, IR, 0, 1) +REG8(DTCER, 0x100) + FIELD(DTCER, DTCE, 0, 1) +REG8(IER, 0x200) +REG8(SWINTR, 0x2e0) + FIELD(SWINTR, SWINT, 0, 1) +REG16(FIR, 0x2f0) + FIELD(FIR, FVCT, 0, 8) + FIELD(FIR, FIEN, 15, 1) +REG8(IPR, 0x300) + FIELD(IPR, IPR, 0, 4) +REG8(DMRSR, 0x400) +REG8(IRQCR, 0x500) + FIELD(IRQCR, IRQMD, 2, 2) +REG8(NMISR, 0x580) + FIELD(NMISR, NMIST, 0, 1) + FIELD(NMISR, LVDST, 1, 1) + FIELD(NMISR, OSTST, 2, 1) +REG8(NMIER, 0x581) + FIELD(NMIER, NMIEN, 0, 1) + FIELD(NMIER, LVDEN, 1, 1) + FIELD(NMIER, OSTEN, 2, 1) +REG8(NMICLR, 0x582) + FIELD(NMICLR, NMICLR, 0, 1) + FIELD(NMICLR, OSTCLR, 2, 1) +REG8(NMICR, 0x583) + FIELD(NMICR, NMIMD, 3, 1) + +static void set_irq(RXICUState *icu, int n_IRQ, int req) +{ + if ((icu->fir & R_FIR_FIEN_MASK) && + (icu->fir & R_FIR_FVCT_MASK) =3D=3D n_IRQ) { + qemu_set_irq(icu->_fir, req); + } else { + qemu_set_irq(icu->_irq, req); + } +} + +static uint16_t rxicu_level(RXICUState *icu, unsigned n) +{ + return (icu->ipr[icu->map[n]] << 8) | n; +} + +static void rxicu_request(RXICUState *icu, int n_IRQ) +{ + int enable; + + enable =3D icu->ier[n_IRQ / 8] & (1 << (n_IRQ & 7)); + if (n_IRQ > 0 && enable !=3D 0 && atomic_read(&icu->req_irq) < 0) { + atomic_set(&icu->req_irq, n_IRQ); + set_irq(icu, n_IRQ, rxicu_level(icu, n_IRQ)); + } +} + +static void rxicu_set_irq(void *opaque, int n_IRQ, int level) +{ + RXICUState *icu =3D opaque; + struct IRQSource *src; + int issue; + + if (n_IRQ >=3D NR_IRQS) { + error_report("%s: IRQ %d out of range", __func__, n_IRQ); + return; + } + + src =3D &icu->src[n_IRQ]; + + level =3D (level !=3D 0); + switch (src->sense) { + case TRG_LEVEL: + /* level-sensitive irq */ + issue =3D level; + src->level =3D level; + break; + case TRG_NEDGE: + issue =3D (level =3D=3D 0 && src->level =3D=3D 1); + src->level =3D level; + break; + case TRG_PEDGE: + issue =3D (level =3D=3D 1 && src->level =3D=3D 0); + src->level =3D level; + break; + case TRG_BEDGE: + issue =3D ((level ^ src->level) & 1); + src->level =3D level; + break; + default: + g_assert_not_reached(); + } + if (issue =3D=3D 0 && src->sense =3D=3D TRG_LEVEL) { + icu->ir[n_IRQ] =3D 0; + if (atomic_read(&icu->req_irq) =3D=3D n_IRQ) { + /* clear request */ + set_irq(icu, n_IRQ, 0); + atomic_set(&icu->req_irq, -1); + } + return; + } + if (issue) { + icu->ir[n_IRQ] =3D 1; + rxicu_request(icu, n_IRQ); + } +} + +static void rxicu_ack_irq(void *opaque, int no, int level) +{ + RXICUState *icu =3D opaque; + int i; + int n_IRQ; + int max_pri; + + n_IRQ =3D atomic_read(&icu->req_irq); + if (n_IRQ < 0) { + return; + } + atomic_set(&icu->req_irq, -1); + if (icu->src[n_IRQ].sense !=3D TRG_LEVEL) { + icu->ir[n_IRQ] =3D 0; + } + + max_pri =3D 0; + n_IRQ =3D -1; + for (i =3D 0; i < NR_IRQS; i++) { + if (icu->ir[i]) { + if (max_pri < icu->ipr[icu->map[i]]) { + n_IRQ =3D i; + max_pri =3D icu->ipr[icu->map[i]]; + } + } + } + + if (n_IRQ >=3D 0) { + rxicu_request(icu, n_IRQ); + } +} + +static uint64_t icu_read(void *opaque, hwaddr addr, unsigned size) +{ + RXICUState *icu =3D opaque; + int reg =3D addr & 0xff; + + if ((addr !=3D A_FIR && size !=3D 1) || + (addr =3D=3D A_FIR && size !=3D 2)) { + qemu_log_mask(LOG_GUEST_ERROR, "rx_icu: Invalid read size 0x%" + HWADDR_PRIX "\n", + addr); + return UINT64_MAX; + } + switch (addr) { + case A_IR ... A_IR + 0xff: + return icu->ir[reg] & R_IR_IR_MASK; + case A_DTCER ... A_DTCER + 0xff: + return icu->dtcer[reg] & R_DTCER_DTCE_MASK; + case A_IER ... A_IER + 0x1f: + return icu->ier[reg]; + case A_SWINTR: + return 0; + case A_FIR: + return icu->fir & (R_FIR_FIEN_MASK | R_FIR_FVCT_MASK); + case A_IPR ... A_IPR + 0x8f: + return icu->ipr[reg] & R_IPR_IPR_MASK; + case A_DMRSR: + case A_DMRSR + 4: + case A_DMRSR + 8: + case A_DMRSR + 12: + return icu->dmasr[reg >> 2]; + case A_IRQCR ... A_IRQCR + 0x1f: + return icu->src[64 + reg].sense << R_IRQCR_IRQMD_SHIFT; + case A_NMISR: + case A_NMICLR: + return 0; + case A_NMIER: + return icu->nmier; + case A_NMICR: + return icu->nmicr; + default: + qemu_log_mask(LOG_UNIMP, "rx_icu: Register 0x%" HWADDR_PRIX " " + "not implemented.\n", + addr); + break; + } + return UINT64_MAX; +} + +static void icu_write(void *opaque, hwaddr addr, uint64_t val, unsigned si= ze) +{ + RXICUState *icu =3D opaque; + int reg =3D addr & 0xff; + + if ((addr !=3D A_FIR && size !=3D 1) || + (addr =3D=3D A_FIR && size !=3D 2)) { + qemu_log_mask(LOG_GUEST_ERROR, "rx_icu: Invalid write size at " + "0x%" HWADDR_PRIX "\n", + addr); + return; + } + switch (addr) { + case A_IR ... A_IR + 0xff: + if (icu->src[reg].sense !=3D TRG_LEVEL && val =3D=3D 0) { + icu->ir[reg] =3D 0; + } + break; + case A_DTCER ... A_DTCER + 0xff: + icu->dtcer[reg] =3D val & R_DTCER_DTCE_MASK; + qemu_log_mask(LOG_UNIMP, "rx_icu: DTC not implemented\n"); + break; + case A_IER ... A_IER + 0x1f: + icu->ier[reg] =3D val; + break; + case A_SWINTR: + if (val & R_SWINTR_SWINT_MASK) { + qemu_irq_pulse(icu->_swi); + } + break; + case A_FIR: + icu->fir =3D val & (R_FIR_FIEN_MASK | R_FIR_FVCT_MASK); + break; + case A_IPR ... A_IPR + 0x8f: + icu->ipr[reg] =3D val & R_IPR_IPR_MASK; + break; + case A_DMRSR: + case A_DMRSR + 4: + case A_DMRSR + 8: + case A_DMRSR + 12: + icu->dmasr[reg >> 2] =3D val; + qemu_log_mask(LOG_UNIMP, "rx_icu: DMAC not implemented\n"); + break; + case A_IRQCR ... A_IRQCR + 0x1f: + icu->src[64 + reg].sense =3D val >> R_IRQCR_IRQMD_SHIFT; + break; + case A_NMICLR: + break; + case A_NMIER: + icu->nmier |=3D val & (R_NMIER_NMIEN_MASK | + R_NMIER_LVDEN_MASK | + R_NMIER_OSTEN_MASK); + break; + case A_NMICR: + if ((icu->nmier & R_NMIER_NMIEN_MASK) =3D=3D 0) { + icu->nmicr =3D val & R_NMICR_NMIMD_MASK; + } + break; + default: + qemu_log_mask(LOG_UNIMP, "rx_icu: Register 0x%" HWADDR_PRIX " " + "not implemented\n", + addr); + break; + } +} + +static const MemoryRegionOps icu_ops =3D { + .write =3D icu_write, + .read =3D icu_read, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 2, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 2, + }, +}; + +static void rxicu_realize(DeviceState *dev, Error **errp) +{ + RXICUState *icu =3D RX_ICU(dev); + int i, j; + + if (icu->init_sense =3D=3D NULL) { + qemu_log_mask(LOG_GUEST_ERROR, + "rx_icu: trigger-level property must be set."); + return; + } + for (i =3D j =3D 0; i < NR_IRQS; i++) { + if (icu->init_sense[j] =3D=3D i) { + icu->src[i].sense =3D TRG_LEVEL; + if (j < icu->nr_sense) { + j++; + } + } else { + icu->src[i].sense =3D TRG_PEDGE; + } + } + icu->req_irq =3D -1; +} + +static void rxicu_init(Object *obj) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(obj); + RXICUState *icu =3D RX_ICU(obj); + + memory_region_init_io(&icu->memory, OBJECT(icu), &icu_ops, + icu, "rx-icu", 0x600); + sysbus_init_mmio(d, &icu->memory); + + qdev_init_gpio_in(DEVICE(d), rxicu_set_irq, NR_IRQS); + qdev_init_gpio_in_named(DEVICE(d), rxicu_ack_irq, "ack", 1); + sysbus_init_irq(d, &icu->_irq); + sysbus_init_irq(d, &icu->_fir); + sysbus_init_irq(d, &icu->_swi); +} + +static void rxicu_fini(Object *obj) +{ + RXICUState *icu =3D RX_ICU(obj); + g_free(icu->map); + g_free(icu->init_sense); +} + +static const VMStateDescription vmstate_rxicu =3D { + .name =3D "rx-icu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8_ARRAY(ir, RXICUState, NR_IRQS), + VMSTATE_UINT8_ARRAY(dtcer, RXICUState, NR_IRQS), + VMSTATE_UINT8_ARRAY(ier, RXICUState, NR_IRQS / 8), + VMSTATE_UINT8_ARRAY(ipr, RXICUState, 142), + VMSTATE_UINT8_ARRAY(dmasr, RXICUState, 4), + VMSTATE_UINT16(fir, RXICUState), + VMSTATE_UINT8(nmisr, RXICUState), + VMSTATE_UINT8(nmier, RXICUState), + VMSTATE_UINT8(nmiclr, RXICUState), + VMSTATE_UINT8(nmicr, RXICUState), + VMSTATE_INT16(req_irq, RXICUState), + VMSTATE_END_OF_LIST() + } +}; + +static Property rxicu_properties[] =3D { + DEFINE_PROP_ARRAY("ipr-map", RXICUState, nr_irqs, map, + qdev_prop_uint8, uint8_t), + DEFINE_PROP_ARRAY("trigger-level", RXICUState, nr_sense, init_sense, + qdev_prop_uint8, uint8_t), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rxicu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D rxicu_realize; + dc->vmsd =3D &vmstate_rxicu; + device_class_set_props(dc, rxicu_properties); +} + +static const TypeInfo rxicu_info =3D { + .name =3D TYPE_RX_ICU, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RXICUState), + .instance_init =3D rxicu_init, + .instance_finalize =3D rxicu_fini, + .class_init =3D rxicu_class_init, +}; + +static void rxicu_register_types(void) +{ + type_register_static(&rxicu_info); +} + +type_init(rxicu_register_types) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index a189d6fedd..f562342bab 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -61,3 +61,6 @@ config S390_FLIC_KVM =20 config OMPIC bool + +config RX_ICU + bool diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index f726d87532..98a0b0f3bc 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -20,6 +20,7 @@ common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_dist.o common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_redist.o common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_its_common.o common-obj-$(CONFIG_OPENPIC) +=3D openpic.o +common-obj-$(CONFIG_RX_ICU) +=3D rx_icu.o common-obj-y +=3D intc.o =20 obj-$(CONFIG_APIC) +=3D apic.o apic_common.o --=20 2.21.3 From nobody Fri May 17 01:43:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[83.51.162.43]) by smtp.gmail.com with ESMTPSA id a6sm21309896wrn.38.2020.06.01.09.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2020 09:14:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ErceqITnGhLCPYkCifzq710iEZfD+Gb1EMJUjvYvPyk=; b=UAEcn3bS8BDbr2dRRdDILGIMQavd9FiDzG9h7aMZNnYWtMzHEfcD2vKkM16q2JqhnK sztjGewD7iEw+zAPedHXak8euOAHscfcOMAHsH//J6nE+tBikRVHZmPMqLXVaO/YbC7X P16tqMfngPIk1Gl1xHgWuPX99t/r4NCXNI0cEiQ7XNGK1LjGHYXMFywAONSHAfEIvyqz Hc0COr+YCQxf3TKA+GfL2QEQYDacXWGCLoLmY1oVOwcPe5rG2131LuQogSZg00NhCpHn ROPh4FpnRN7t7ErzwPaas4c11iabqD6CZLPvlJRrOeVPRtGbBKV7Z0bNSeWBMkpm41yC DVsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ErceqITnGhLCPYkCifzq710iEZfD+Gb1EMJUjvYvPyk=; b=KQbDz+G2VhHTOK6qgCgk1IgOm0F3eG8u0qLy9SDo6y/TKh8hiTbv7AEUTCf9GsH8LP 8PYvY7/ajLCsm2WfRxIC2q+2zkxJamArhg6FWUTmXmhNUbMQU5VZH4zzmodO4Fnbzk0r KYHb5lU2kNJ0GJRaZDp5woN2s3YX1Uefaunc/rBfErhrZuaa/D1OiR6aVRJVgwjVsvSj guQvokerP5jDj/HFXKXsBFNWVOgRfKL3HPO/9cGhacrkHr1sMsB/cw4rWe1wltxZnS7N ACgWqudLAvnRvWvftN9hSET6EU106TcshPkMiTyZkydoZY0cvVJSU7DDiZmFZiOtHijO UVAw== X-Gm-Message-State: AOAM531WDniGTBjOHX3L1Q2DfPS3uSx7GOiGSUA0Ky1NiFIjpBnVS1gc aY1vciKr7O/2zJ627wb8xNQ= X-Google-Smtp-Source: ABdhPJxT2KfLyf1O+BdbNLNGQzvFhnfEmVdrHDW2EybFYWktiSNpjg9HXQrXbcePw4/HL4QiM/L52Q== X-Received: by 2002:a1c:c908:: with SMTP id f8mr98912wmb.150.1591028089362; Mon, 01 Jun 2020 09:14:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org, Yoshinori Sato Subject: [PATCH 04/12] hw/timer: RX62N 8-Bit timer (TMR) Date: Mon, 1 Jun 2020 18:14:33 +0200 Message-Id: <20200601161441.8086-5-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200601161441.8086-1-f4bug@amsat.org> References: <20200601161441.8086-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato renesas_tmr: 8bit timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej= 0140_rx62n.pdf Signed-off-by: Yoshinori Sato Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-16-ysato@users.sourceforge.jp> [PMD: Split from CMT, filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/renesas_tmr.h | 55 ++++ hw/timer/renesas_tmr.c | 477 +++++++++++++++++++++++++++++++++ hw/timer/Kconfig | 3 + hw/timer/Makefile.objs | 1 + 4 files changed, 536 insertions(+) create mode 100644 include/hw/timer/renesas_tmr.h create mode 100644 hw/timer/renesas_tmr.c diff --git a/include/hw/timer/renesas_tmr.h b/include/hw/timer/renesas_tmr.h new file mode 100644 index 0000000000..cf3baa7a28 --- /dev/null +++ b/include/hw/timer/renesas_tmr.h @@ -0,0 +1,55 @@ +/* + * Renesas 8bit timer Object + * + * Copyright (c) 2018 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_TIMER_RENESAS_TMR_H +#define HW_TIMER_RENESAS_TMR_H + +#include "qemu/timer.h" +#include "hw/sysbus.h" + +#define TYPE_RENESAS_TMR "renesas-tmr" +#define RTMR(obj) OBJECT_CHECK(RTMRState, (obj), TYPE_RENESAS_TMR) + +enum timer_event { + cmia =3D 0, + cmib =3D 1, + ovi =3D 2, + none =3D 3, + TMR_NR_EVENTS =3D 4 +}; + +enum { + TMR_CH =3D 2, + TMR_NR_IRQ =3D 3 * TMR_CH +}; + +typedef struct RTMRState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + uint64_t input_freq; + MemoryRegion memory; + + int64_t tick; + uint8_t tcnt[TMR_CH]; + uint8_t tcora[TMR_CH]; + uint8_t tcorb[TMR_CH]; + uint8_t tcr[TMR_CH]; + uint8_t tccr[TMR_CH]; + uint8_t tcor[TMR_CH]; + uint8_t tcsr[TMR_CH]; + int64_t div_round[TMR_CH]; + uint8_t next[TMR_CH]; + qemu_irq cmia[TMR_CH]; + qemu_irq cmib[TMR_CH]; + qemu_irq ovi[TMR_CH]; + QEMUTimer timer[TMR_CH]; +} RTMRState; + +#endif diff --git a/hw/timer/renesas_tmr.c b/hw/timer/renesas_tmr.c new file mode 100644 index 0000000000..446f2eacdd --- /dev/null +++ b/hw/timer/renesas_tmr.c @@ -0,0 +1,477 @@ +/* + * Renesas 8bit timer + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/qdev-properties.h" +#include "hw/timer/renesas_tmr.h" +#include "migration/vmstate.h" + +REG8(TCR, 0) + FIELD(TCR, CCLR, 3, 2) + FIELD(TCR, OVIE, 5, 1) + FIELD(TCR, CMIEA, 6, 1) + FIELD(TCR, CMIEB, 7, 1) +REG8(TCSR, 2) + FIELD(TCSR, OSA, 0, 2) + FIELD(TCSR, OSB, 2, 2) + FIELD(TCSR, ADTE, 4, 2) +REG8(TCORA, 4) +REG8(TCORB, 6) +REG8(TCNT, 8) +REG8(TCCR, 10) + FIELD(TCCR, CKS, 0, 3) + FIELD(TCCR, CSS, 3, 2) + FIELD(TCCR, TMRIS, 7, 1) + +#define INTERNAL 0x01 +#define CASCADING 0x03 +#define CCLR_A 0x01 +#define CCLR_B 0x02 + +static const int clkdiv[] =3D {0, 1, 2, 8, 32, 64, 1024, 8192}; + +static uint8_t concat_reg(uint8_t *reg) +{ + return (reg[0] << 8) | reg[1]; +} + +static void update_events(RTMRState *tmr, int ch) +{ + uint16_t diff[TMR_NR_EVENTS], min; + int64_t next_time; + int i, event; + + if (tmr->tccr[ch] =3D=3D 0) { + return ; + } + if (FIELD_EX8(tmr->tccr[ch], TCCR, CSS) =3D=3D 0) { + /* external clock mode */ + /* event not happened */ + return ; + } + if (FIELD_EX8(tmr->tccr[0], TCCR, CSS) =3D=3D CASCADING) { + /* cascading mode */ + if (ch =3D=3D 1) { + tmr->next[ch] =3D none; + return ; + } + diff[cmia] =3D concat_reg(tmr->tcora) - concat_reg(tmr->tcnt); + diff[cmib] =3D concat_reg(tmr->tcorb) - concat_reg(tmr->tcnt); + diff[ovi] =3D 0x10000 - concat_reg(tmr->tcnt); + } else { + /* separate mode */ + diff[cmia] =3D tmr->tcora[ch] - tmr->tcnt[ch]; + diff[cmib] =3D tmr->tcorb[ch] - tmr->tcnt[ch]; + diff[ovi] =3D 0x100 - tmr->tcnt[ch]; + } + /* Search for the most recently occurring event. */ + for (event =3D 0, min =3D diff[0], i =3D 1; i < none; i++) { + if (min > diff[i]) { + event =3D i; + min =3D diff[i]; + } + } + tmr->next[ch] =3D event; + next_time =3D diff[event]; + next_time *=3D clkdiv[FIELD_EX8(tmr->tccr[ch], TCCR, CKS)]; + next_time *=3D NANOSECONDS_PER_SECOND; + next_time /=3D tmr->input_freq; + next_time +=3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + timer_mod(&tmr->timer[ch], next_time); +} + +static int elapsed_time(RTMRState *tmr, int ch, int64_t delta) +{ + int divrate =3D clkdiv[FIELD_EX8(tmr->tccr[ch], TCCR, CKS)]; + int et; + + tmr->div_round[ch] +=3D delta; + if (divrate > 0) { + et =3D tmr->div_round[ch] / divrate; + tmr->div_round[ch] %=3D divrate; + } else { + /* disble clock. so no update */ + et =3D 0; + } + return et; +} + +static uint16_t read_tcnt(RTMRState *tmr, unsigned size, int ch) +{ + int64_t delta, now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + int elapsed, ovf =3D 0; + uint16_t tcnt[2]; + uint32_t ret; + + delta =3D (now - tmr->tick) * NANOSECONDS_PER_SECOND / tmr->input_freq; + if (delta > 0) { + tmr->tick =3D now; + + if (FIELD_EX8(tmr->tccr[1], TCCR, CSS) =3D=3D INTERNAL) { + /* timer1 count update */ + elapsed =3D elapsed_time(tmr, 1, delta); + if (elapsed >=3D 0x100) { + ovf =3D elapsed >> 8; + } + tcnt[1] =3D tmr->tcnt[1] + (elapsed & 0xff); + } + switch (FIELD_EX8(tmr->tccr[0], TCCR, CSS)) { + case INTERNAL: + elapsed =3D elapsed_time(tmr, 0, delta); + tcnt[0] =3D tmr->tcnt[0] + elapsed; + break; + case CASCADING: + if (ovf > 0) { + tcnt[0] =3D tmr->tcnt[0] + ovf; + } + break; + } + } else { + tcnt[0] =3D tmr->tcnt[0]; + tcnt[1] =3D tmr->tcnt[1]; + } + if (size =3D=3D 1) { + return tcnt[ch]; + } else { + ret =3D 0; + ret =3D deposit32(ret, 0, 8, tcnt[1]); + ret =3D deposit32(ret, 8, 8, tcnt[0]); + return ret; + } +} + +static uint8_t read_tccr(uint8_t r) +{ + uint8_t tccr =3D 0; + tccr =3D FIELD_DP8(tccr, TCCR, TMRIS, + FIELD_EX8(r, TCCR, TMRIS)); + tccr =3D FIELD_DP8(tccr, TCCR, CSS, + FIELD_EX8(r, TCCR, CSS)); + tccr =3D FIELD_DP8(tccr, TCCR, CKS, + FIELD_EX8(r, TCCR, CKS)); + return tccr; +} + +static uint64_t tmr_read(void *opaque, hwaddr addr, unsigned size) +{ + RTMRState *tmr =3D opaque; + int ch =3D addr & 1; + uint64_t ret; + + if (size =3D=3D 2 && (ch !=3D 0 || addr =3D=3D A_TCR || addr =3D=3D A_= TCSR)) { + qemu_log_mask(LOG_GUEST_ERROR, "renesas_tmr: Invalid read size 0x%" + HWADDR_PRIX "\n", + addr); + return UINT64_MAX; + } + switch (addr & 0x0e) { + case A_TCR: + ret =3D 0; + ret =3D FIELD_DP8(ret, TCR, CCLR, + FIELD_EX8(tmr->tcr[ch], TCR, CCLR)); + ret =3D FIELD_DP8(ret, TCR, OVIE, + FIELD_EX8(tmr->tcr[ch], TCR, OVIE)); + ret =3D FIELD_DP8(ret, TCR, CMIEA, + FIELD_EX8(tmr->tcr[ch], TCR, CMIEA)); + ret =3D FIELD_DP8(ret, TCR, CMIEB, + FIELD_EX8(tmr->tcr[ch], TCR, CMIEB)); + return ret; + case A_TCSR: + ret =3D 0; + ret =3D FIELD_DP8(ret, TCSR, OSA, + FIELD_EX8(tmr->tcsr[ch], TCSR, OSA)); + ret =3D FIELD_DP8(ret, TCSR, OSB, + FIELD_EX8(tmr->tcsr[ch], TCSR, OSB)); + switch (ch) { + case 0: + ret =3D FIELD_DP8(ret, TCSR, ADTE, + FIELD_EX8(tmr->tcsr[ch], TCSR, ADTE)); + break; + case 1: /* CH1 ADTE unimplement always 1 */ + ret =3D FIELD_DP8(ret, TCSR, ADTE, 1); + break; + } + return ret; + case A_TCORA: + if (size =3D=3D 1) { + return tmr->tcora[ch]; + } else if (ch =3D=3D 0) { + return concat_reg(tmr->tcora); + } + case A_TCORB: + if (size =3D=3D 1) { + return tmr->tcorb[ch]; + } else { + return concat_reg(tmr->tcorb); + } + case A_TCNT: + return read_tcnt(tmr, size, ch); + case A_TCCR: + if (size =3D=3D 1) { + return read_tccr(tmr->tccr[ch]); + } else { + return read_tccr(tmr->tccr[0]) << 8 | read_tccr(tmr->tccr[1]); + } + default: + qemu_log_mask(LOG_UNIMP, "renesas_tmr: Register 0x%" HWADDR_PRIX + " not implemented\n", + addr); + break; + } + return UINT64_MAX; +} + +static void tmr_write_count(RTMRState *tmr, int ch, unsigned size, + uint8_t *reg, uint64_t val) +{ + if (size =3D=3D 1) { + reg[ch] =3D val; + update_events(tmr, ch); + } else { + reg[0] =3D extract32(val, 8, 8); + reg[1] =3D extract32(val, 0, 8); + update_events(tmr, 0); + update_events(tmr, 1); + } +} + +static void tmr_write(void *opaque, hwaddr addr, uint64_t val, unsigned si= ze) +{ + RTMRState *tmr =3D opaque; + int ch =3D addr & 1; + + if (size =3D=3D 2 && (ch !=3D 0 || addr =3D=3D A_TCR || addr =3D=3D A_= TCSR)) { + qemu_log_mask(LOG_GUEST_ERROR, + "renesas_tmr: Invalid write size 0x%" HWADDR_PRIX "\= n", + addr); + return; + } + switch (addr & 0x0e) { + case A_TCR: + tmr->tcr[ch] =3D val; + break; + case A_TCSR: + tmr->tcsr[ch] =3D val; + break; + case A_TCORA: + tmr_write_count(tmr, ch, size, tmr->tcora, val); + break; + case A_TCORB: + tmr_write_count(tmr, ch, size, tmr->tcorb, val); + break; + case A_TCNT: + tmr_write_count(tmr, ch, size, tmr->tcnt, val); + break; + case A_TCCR: + tmr_write_count(tmr, ch, size, tmr->tccr, val); + break; + default: + qemu_log_mask(LOG_UNIMP, "renesas_tmr: Register 0x%" HWADDR_PRIX + " not implemented\n", + addr); + break; + } +} + +static const MemoryRegionOps tmr_ops =3D { + .write =3D tmr_write, + .read =3D tmr_read, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 2, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 2, + }, +}; + +static void timer_events(RTMRState *tmr, int ch); + +static uint16_t issue_event(RTMRState *tmr, int ch, int sz, + uint16_t tcnt, uint16_t tcora, uint16_t tcorb) +{ + uint16_t ret =3D tcnt; + + switch (tmr->next[ch]) { + case none: + break; + case cmia: + if (tcnt >=3D tcora) { + if (FIELD_EX8(tmr->tcr[ch], TCR, CCLR) =3D=3D CCLR_A) { + ret =3D tcnt - tcora; + } + if (FIELD_EX8(tmr->tcr[ch], TCR, CMIEA)) { + qemu_irq_pulse(tmr->cmia[ch]); + } + if (sz =3D=3D 8 && ch =3D=3D 0 && + FIELD_EX8(tmr->tccr[1], TCCR, CSS) =3D=3D CASCADING) { + tmr->tcnt[1]++; + timer_events(tmr, 1); + } + } + break; + case cmib: + if (tcnt >=3D tcorb) { + if (FIELD_EX8(tmr->tcr[ch], TCR, CCLR) =3D=3D CCLR_B) { + ret =3D tcnt - tcorb; + } + if (FIELD_EX8(tmr->tcr[ch], TCR, CMIEB)) { + qemu_irq_pulse(tmr->cmib[ch]); + } + } + break; + case ovi: + if ((tcnt >=3D (1 << sz)) && FIELD_EX8(tmr->tcr[ch], TCR, OVIE)) { + qemu_irq_pulse(tmr->ovi[ch]); + } + break; + default: + g_assert_not_reached(); + } + return ret; +} + +static void timer_events(RTMRState *tmr, int ch) +{ + uint16_t tcnt; + + tmr->tcnt[ch] =3D read_tcnt(tmr, 1, ch); + if (FIELD_EX8(tmr->tccr[0], TCCR, CSS) !=3D CASCADING) { + tmr->tcnt[ch] =3D issue_event(tmr, ch, 8, + tmr->tcnt[ch], + tmr->tcora[ch], + tmr->tcorb[ch]) & 0xff; + } else { + if (ch =3D=3D 1) { + return ; + } + tcnt =3D issue_event(tmr, ch, 16, + concat_reg(tmr->tcnt), + concat_reg(tmr->tcora), + concat_reg(tmr->tcorb)); + tmr->tcnt[0] =3D (tcnt >> 8) & 0xff; + tmr->tcnt[1] =3D tcnt & 0xff; + } + update_events(tmr, ch); +} + +static void timer_event0(void *opaque) +{ + RTMRState *tmr =3D opaque; + + timer_events(tmr, 0); +} + +static void timer_event1(void *opaque) +{ + RTMRState *tmr =3D opaque; + + timer_events(tmr, 1); +} + +static void rtmr_reset(DeviceState *dev) +{ + RTMRState *tmr =3D RTMR(dev); + tmr->tcr[0] =3D tmr->tcr[1] =3D 0x00; + tmr->tcsr[0] =3D 0x00; + tmr->tcsr[1] =3D 0x10; + tmr->tcnt[0] =3D tmr->tcnt[1] =3D 0x00; + tmr->tcora[0] =3D tmr->tcora[1] =3D 0xff; + tmr->tcorb[0] =3D tmr->tcorb[1] =3D 0xff; + tmr->tccr[0] =3D tmr->tccr[1] =3D 0x00; + tmr->next[0] =3D tmr->next[1] =3D none; + tmr->tick =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); +} + +static void rtmr_init(Object *obj) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(obj); + RTMRState *tmr =3D RTMR(obj); + int i; + + memory_region_init_io(&tmr->memory, OBJECT(tmr), &tmr_ops, + tmr, "renesas-tmr", 0x10); + sysbus_init_mmio(d, &tmr->memory); + + for (i =3D 0; i < ARRAY_SIZE(tmr->ovi); i++) { + sysbus_init_irq(d, &tmr->cmia[i]); + sysbus_init_irq(d, &tmr->cmib[i]); + sysbus_init_irq(d, &tmr->ovi[i]); + } + timer_init_ns(&tmr->timer[0], QEMU_CLOCK_VIRTUAL, timer_event0, tmr); + timer_init_ns(&tmr->timer[1], QEMU_CLOCK_VIRTUAL, timer_event1, tmr); +} + +static const VMStateDescription vmstate_rtmr =3D { + .name =3D "rx-tmr", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_INT64(tick, RTMRState), + VMSTATE_UINT8_ARRAY(tcnt, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(tcora, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(tcorb, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(tcr, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(tccr, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(tcor, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(tcsr, RTMRState, TMR_CH), + VMSTATE_INT64_ARRAY(div_round, RTMRState, TMR_CH), + VMSTATE_UINT8_ARRAY(next, RTMRState, TMR_CH), + VMSTATE_TIMER_ARRAY(timer, RTMRState, TMR_CH), + VMSTATE_END_OF_LIST() + } +}; + +static Property rtmr_properties[] =3D { + DEFINE_PROP_UINT64("input-freq", RTMRState, input_freq, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rtmr_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_rtmr; + dc->reset =3D rtmr_reset; + device_class_set_props(dc, rtmr_properties); +} + +static const TypeInfo rtmr_info =3D { + .name =3D TYPE_RENESAS_TMR, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RTMRState), + .instance_init =3D rtmr_init, + .class_init =3D rtmr_class_init, +}; + +static void rtmr_register_types(void) +{ + type_register_static(&rtmr_info); +} + +type_init(rtmr_register_types) diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig index 59b3f44d69..7039c2a686 100644 --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -35,3 +35,6 @@ config CMSDK_APB_TIMER config CMSDK_APB_DUALTIMER bool select PTIMER + +config RENESAS_TMR + bool diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index dece235fd7..44fb47a433 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -23,6 +23,7 @@ common-obj-$(CONFIG_OMAP) +=3D omap_gptimer.o common-obj-$(CONFIG_OMAP) +=3D omap_synctimer.o common-obj-$(CONFIG_PXA2XX) +=3D pxa2xx_timer.o common-obj-$(CONFIG_SH4) +=3D sh_timer.o +common-obj-$(CONFIG_RENESAS_TMR) +=3D renesas_tmr.o common-obj-$(CONFIG_DIGIC) +=3D digic-timer.o common-obj-$(CONFIG_MIPS_CPS) +=3D mips_gictimer.o =20 --=20 2.21.3 From nobody Fri May 17 01:43:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[83.51.162.43]) by smtp.gmail.com with ESMTPSA id a6sm21309896wrn.38.2020.06.01.09.14.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2020 09:14:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XZACxZccAAi2TopI+c0OP5VJ17b3bi19ygcofM3uJGA=; b=FzwcUeYW2+67f69pfit/uM1xweSHfFruIv7n29na2PvU8rO23rzqGGoFo0I6Mgn6ER 7kslkyVDV6NPFXUBVZkqACwthSqUVLVtWq6uSnWOeOdFS6CqGZshAMsHxhnfMdB5163V Bsfmxx0ROVLAV4R/VxVCmFwB2kVTqaxA/hqD0xb+QfKjdy5iEDf8/YQQmd48fOjaK3m6 svx46cp015xYXUqkLMmU1pm8c5zMQCjFvh1WnLoOvHBPYmFahDLCClkr40z/NFHTPwsi r2BhZHtE0h9Ae1+OcI2iCqDBA5C8DQsvw9HSLCLRwNokd4RIkNlNefIudWWdtqgwfelt VCsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=XZACxZccAAi2TopI+c0OP5VJ17b3bi19ygcofM3uJGA=; b=Uh3NczRmDTRf3fDraxloxZoNTNng+HkyU34JCpUUkJLbG7UjT1tRUrXyVrwu/2/zfv mXi9YcHlYycphC7l9w0DuezCTprvskOYwN1QnAweZobjMrURKMOAaxvQoMM/Et4DhRr6 mOQuqKxrptnLhMfgcN33biglQezKZ3dbi2LK/ujLseNrkz9X678gnGkEjDpGrHS+47Mv 9n7nhIA/3PBN2/DAmzWkv0GtG74OvvNb3y6K8ktV/GymWQivO2O5dM6OAi+SaAcyX8OC bDQboA9ejpHmEXzDw+a+4Axh+JHYdJXIhILe+N/ulDt66CICzcBXZ5nvutvGd19qaxuH hWvQ== X-Gm-Message-State: AOAM531hBqemI2AC/RyyH1J3v9i3Gj3n5AsGk57qDgKaJZaog7DgzdcH UYpQ+pddUkycR8o8j3R6aGk= X-Google-Smtp-Source: ABdhPJwRdNIqEYeWvz2xgbQzZPCIbKgtd4BA5VEJR7pzvBgCrBmUq5KPA4N2iRX6pWlP/EU7yISMog== X-Received: by 2002:a7b:cb4e:: with SMTP id v14mr122849wmj.54.1591028091100; Mon, 01 Jun 2020 09:14:51 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org, Yoshinori Sato Subject: [PATCH 05/12] hw/timer: RX62N compare match timer (CMT) Date: Mon, 1 Jun 2020 18:14:34 +0200 Message-Id: <20200601161441.8086-6-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200601161441.8086-1-f4bug@amsat.org> References: <20200601161441.8086-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato renesas_cmt: 16bit compare match timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej= 0140_rx62n.pdf Signed-off-by: Yoshinori Sato Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-16-ysato@users.sourceforge.jp> [PMD: Split from TMR, filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/renesas_cmt.h | 40 +++++ hw/timer/renesas_cmt.c | 283 +++++++++++++++++++++++++++++++++ hw/timer/Kconfig | 3 + hw/timer/Makefile.objs | 1 + 4 files changed, 327 insertions(+) create mode 100644 include/hw/timer/renesas_cmt.h create mode 100644 hw/timer/renesas_cmt.c diff --git a/include/hw/timer/renesas_cmt.h b/include/hw/timer/renesas_cmt.h new file mode 100644 index 0000000000..e28a15cb38 --- /dev/null +++ b/include/hw/timer/renesas_cmt.h @@ -0,0 +1,40 @@ +/* + * Renesas Compare-match timer Object + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_TIMER_RENESAS_CMT_H +#define HW_TIMER_RENESAS_CMT_H + +#include "qemu/timer.h" +#include "hw/sysbus.h" + +#define TYPE_RENESAS_CMT "renesas-cmt" +#define RCMT(obj) OBJECT_CHECK(RCMTState, (obj), TYPE_RENESAS_CMT) + +enum { + CMT_CH =3D 2, + CMT_NR_IRQ =3D 1 * CMT_CH +}; + +typedef struct RCMTState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + uint64_t input_freq; + MemoryRegion memory; + + uint16_t cmstr; + uint16_t cmcr[CMT_CH]; + uint16_t cmcnt[CMT_CH]; + uint16_t cmcor[CMT_CH]; + int64_t tick[CMT_CH]; + qemu_irq cmi[CMT_CH]; + QEMUTimer timer[CMT_CH]; +} RCMTState; + +#endif diff --git a/hw/timer/renesas_cmt.c b/hw/timer/renesas_cmt.c new file mode 100644 index 0000000000..2e0fd21a36 --- /dev/null +++ b/hw/timer/renesas_cmt.c @@ -0,0 +1,283 @@ +/* + * Renesas 16bit Compare-match timer + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/qdev-properties.h" +#include "hw/timer/renesas_cmt.h" +#include "migration/vmstate.h" + +/* + * +0 CMSTR - common control + * +2 CMCR - ch0 + * +4 CMCNT - ch0 + * +6 CMCOR - ch0 + * +8 CMCR - ch1 + * +10 CMCNT - ch1 + * +12 CMCOR - ch1 + * If we think that the address of CH 0 has an offset of +2, + * we can treat it with the same address as CH 1, so define it like that. + */ +REG16(CMSTR, 0) + FIELD(CMSTR, STR0, 0, 1) + FIELD(CMSTR, STR1, 1, 1) + FIELD(CMSTR, STR, 0, 2) +/* This addeess is channel offset */ +REG16(CMCR, 0) + FIELD(CMCR, CKS, 0, 2) + FIELD(CMCR, CMIE, 6, 1) +REG16(CMCNT, 2) +REG16(CMCOR, 4) + +static void update_events(RCMTState *cmt, int ch) +{ + int64_t next_time; + + if ((cmt->cmstr & (1 << ch)) =3D=3D 0) { + /* count disable, so not happened next event. */ + return ; + } + next_time =3D cmt->cmcor[ch] - cmt->cmcnt[ch]; + next_time *=3D NANOSECONDS_PER_SECOND; + next_time /=3D cmt->input_freq; + /* + * CKS -> div rate + * 0 -> 8 (1 << 3) + * 1 -> 32 (1 << 5) + * 2 -> 128 (1 << 7) + * 3 -> 512 (1 << 9) + */ + next_time *=3D 1 << (3 + FIELD_EX16(cmt->cmcr[ch], CMCR, CKS) * 2); + next_time +=3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + timer_mod(&cmt->timer[ch], next_time); +} + +static int64_t read_cmcnt(RCMTState *cmt, int ch) +{ + int64_t delta, now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + + if (cmt->cmstr & (1 << ch)) { + delta =3D (now - cmt->tick[ch]); + delta /=3D NANOSECONDS_PER_SECOND; + delta /=3D cmt->input_freq; + delta /=3D 1 << (3 + FIELD_EX16(cmt->cmcr[ch], CMCR, CKS) * 2); + cmt->tick[ch] =3D now; + return cmt->cmcnt[ch] + delta; + } else { + return cmt->cmcnt[ch]; + } +} + +static uint64_t cmt_read(void *opaque, hwaddr offset, unsigned size) +{ + RCMTState *cmt =3D opaque; + int ch =3D offset / 0x08; + uint64_t ret; + + if (offset =3D=3D A_CMSTR) { + ret =3D 0; + ret =3D FIELD_DP16(ret, CMSTR, STR, + FIELD_EX16(cmt->cmstr, CMSTR, STR)); + return ret; + } else { + offset &=3D 0x07; + if (ch =3D=3D 0) { + offset -=3D 0x02; + } + switch (offset) { + case A_CMCR: + ret =3D 0; + ret =3D FIELD_DP16(ret, CMCR, CKS, + FIELD_EX16(cmt->cmstr, CMCR, CKS)); + ret =3D FIELD_DP16(ret, CMCR, CMIE, + FIELD_EX16(cmt->cmstr, CMCR, CMIE)); + return ret; + case A_CMCNT: + return read_cmcnt(cmt, ch); + case A_CMCOR: + return cmt->cmcor[ch]; + } + } + qemu_log_mask(LOG_UNIMP, "renesas_cmt: Register 0x%" HWADDR_PRIX " " + "not implemented\n", + offset); + return UINT64_MAX; +} + +static void start_stop(RCMTState *cmt, int ch, int st) +{ + if (st) { + update_events(cmt, ch); + } else { + timer_del(&cmt->timer[ch]); + } +} + +static void cmt_write(void *opaque, hwaddr offset, uint64_t val, unsigned = size) +{ + RCMTState *cmt =3D opaque; + int ch =3D offset / 0x08; + + if (offset =3D=3D A_CMSTR) { + cmt->cmstr =3D FIELD_EX16(val, CMSTR, STR); + start_stop(cmt, 0, FIELD_EX16(cmt->cmstr, CMSTR, STR0)); + start_stop(cmt, 1, FIELD_EX16(cmt->cmstr, CMSTR, STR1)); + } else { + offset &=3D 0x07; + if (ch =3D=3D 0) { + offset -=3D 0x02; + } + switch (offset) { + case A_CMCR: + cmt->cmcr[ch] =3D FIELD_DP16(cmt->cmcr[ch], CMCR, CKS, + FIELD_EX16(val, CMCR, CKS)); + cmt->cmcr[ch] =3D FIELD_DP16(cmt->cmcr[ch], CMCR, CMIE, + FIELD_EX16(val, CMCR, CMIE)); + break; + case 2: + cmt->cmcnt[ch] =3D val; + break; + case 4: + cmt->cmcor[ch] =3D val; + break; + default: + qemu_log_mask(LOG_UNIMP, "renesas_cmt: Register 0x%" HWADDR_PR= IX " " + "not implemented\n", + offset); + return; + } + if (FIELD_EX16(cmt->cmstr, CMSTR, STR) & (1 << ch)) { + update_events(cmt, ch); + } + } +} + +static const MemoryRegionOps cmt_ops =3D { + .write =3D cmt_write, + .read =3D cmt_read, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 2, + .max_access_size =3D 2, + }, + .valid =3D { + .min_access_size =3D 2, + .max_access_size =3D 2, + }, +}; + +static void timer_events(RCMTState *cmt, int ch) +{ + cmt->cmcnt[ch] =3D 0; + cmt->tick[ch] =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + update_events(cmt, ch); + if (FIELD_EX16(cmt->cmcr[ch], CMCR, CMIE)) { + qemu_irq_pulse(cmt->cmi[ch]); + } +} + +static void timer_event0(void *opaque) +{ + RCMTState *cmt =3D opaque; + + timer_events(cmt, 0); +} + +static void timer_event1(void *opaque) +{ + RCMTState *cmt =3D opaque; + + timer_events(cmt, 1); +} + +static void rcmt_reset(DeviceState *dev) +{ + RCMTState *cmt =3D RCMT(dev); + cmt->cmstr =3D 0; + cmt->cmcr[0] =3D cmt->cmcr[1] =3D 0; + cmt->cmcnt[0] =3D cmt->cmcnt[1] =3D 0; + cmt->cmcor[0] =3D cmt->cmcor[1] =3D 0xffff; +} + +static void rcmt_init(Object *obj) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(obj); + RCMTState *cmt =3D RCMT(obj); + int i; + + memory_region_init_io(&cmt->memory, OBJECT(cmt), &cmt_ops, + cmt, "renesas-cmt", 0x10); + sysbus_init_mmio(d, &cmt->memory); + + for (i =3D 0; i < ARRAY_SIZE(cmt->cmi); i++) { + sysbus_init_irq(d, &cmt->cmi[i]); + } + timer_init_ns(&cmt->timer[0], QEMU_CLOCK_VIRTUAL, timer_event0, cmt); + timer_init_ns(&cmt->timer[1], QEMU_CLOCK_VIRTUAL, timer_event1, cmt); +} + +static const VMStateDescription vmstate_rcmt =3D { + .name =3D "rx-cmt", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT16(cmstr, RCMTState), + VMSTATE_UINT16_ARRAY(cmcr, RCMTState, CMT_CH), + VMSTATE_UINT16_ARRAY(cmcnt, RCMTState, CMT_CH), + VMSTATE_UINT16_ARRAY(cmcor, RCMTState, CMT_CH), + VMSTATE_INT64_ARRAY(tick, RCMTState, CMT_CH), + VMSTATE_TIMER_ARRAY(timer, RCMTState, CMT_CH), + VMSTATE_END_OF_LIST() + } +}; + +static Property rcmt_properties[] =3D { + DEFINE_PROP_UINT64("input-freq", RCMTState, input_freq, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rcmt_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_rcmt; + dc->reset =3D rcmt_reset; + device_class_set_props(dc, rcmt_properties); +} + +static const TypeInfo rcmt_info =3D { + .name =3D TYPE_RENESAS_CMT, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RCMTState), + .instance_init =3D rcmt_init, + .class_init =3D rcmt_class_init, +}; + +static void rcmt_register_types(void) +{ + type_register_static(&rcmt_info); +} + +type_init(rcmt_register_types) diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig index 7039c2a686..59a667c503 100644 --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -38,3 +38,6 @@ config CMSDK_APB_DUALTIMER =20 config RENESAS_TMR bool + +config RENESAS_CMT + bool diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 44fb47a433..a39f6ec0c2 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -24,6 +24,7 @@ common-obj-$(CONFIG_OMAP) +=3D omap_synctimer.o common-obj-$(CONFIG_PXA2XX) +=3D pxa2xx_timer.o common-obj-$(CONFIG_SH4) +=3D sh_timer.o common-obj-$(CONFIG_RENESAS_TMR) +=3D renesas_tmr.o +common-obj-$(CONFIG_RENESAS_CMT) +=3D renesas_cmt.o common-obj-$(CONFIG_DIGIC) +=3D digic-timer.o common-obj-$(CONFIG_MIPS_CPS) +=3D mips_gictimer.o =20 --=20 2.21.3 From nobody Fri May 17 01:43:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; 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[83.51.162.43]) by smtp.gmail.com with ESMTPSA id a6sm21309896wrn.38.2020.06.01.09.14.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2020 09:14:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Li+ZxqOvBnHhwlFkNS7cHG2yKEmymfLFzHdiZWMqey8=; b=STS9AzodsE7qq473JsyXWHzjOdcIIeIGOnjmCqo+EXPsuegk6SKS4UxhAQ8IzhfxQo zJGiHjLioMTzbIjiS7OAs9+8d9o8NXp9zbD1/m7bevsRBUOVixaXzK2tHbkD6iR7zWBR BAjeAslVhW17ljYlC8mepCHmIQqQCMl+3/DVCxEVN21/zOlz7Xinn42XoquiQ0nzIRA+ 2fVI4YhKRMpi+f5xRznH6FrM60I8FWGQHFwrUF2fwPugK9hmWP1LtX4J0Zrk85qSP0V5 dJj6tcuMmbcWMrFmZXaWotz8//DSVCiI6EiarQ9qZW85zgTGqOZas+32A4C2ZHw6wc07 j/TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Li+ZxqOvBnHhwlFkNS7cHG2yKEmymfLFzHdiZWMqey8=; b=cm03Joasf8liYqpohzRJZcBbraC1YdmNjTnr8+qrG/9DRovOtOZTlxs2+b17ArbZS5 UFk9P2bbovd3gbGk9Y127dG6/iBHIPzH6hmc90QLrLSlL0lwsl1dIeSztjVquYbnHs4U AQdf7hMLm2h+uMRUfdxXVLuoptwm/kDM54WaGqxr2y/HbfU2EijllE2qvotUEUXDQosP AvFvNz56rTBswRZisBK2iU3zxEjEgaMwCsnuOvHOWz74Yb79YJDY8gOE9wZidtfqxLqj o09K5R5x45BB7+wh3V6pq/hsLtwat9gDwoC/mYqIRVZo6/wwiRhp6v0V/+r3RaPazugf 2VNA== X-Gm-Message-State: AOAM530USYpGuwwH57TRrtLquu3kDTTQ63MjqDuZ98/9OCm/FHEQ/Z3l 9QUb93+Sn7miPM5r5o5vc6c= X-Google-Smtp-Source: ABdhPJyZcrsF+SLaEzfxijqiROsrL1xJlA+B3QO2VRbxVEkTGDI5QPw/irNQpZvCteoI2HzNTRy9Kg== X-Received: by 2002:a1c:a901:: with SMTP id s1mr117563wme.66.1591028092565; Mon, 01 Jun 2020 09:14:52 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org, Yoshinori Sato Subject: [PATCH 06/12] hw/char: RX62N serial communication interface (SCI) Date: Mon, 1 Jun 2020 18:14:35 +0200 Message-Id: <20200601161441.8086-7-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200601161441.8086-1-f4bug@amsat.org> References: <20200601161441.8086-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej= 0140_rx62n.pdf Signed-off-by: Yoshinori Sato Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-17-ysato@users.sourceforge.jp> [PMD: Filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/char/renesas_sci.h | 51 +++++ hw/char/renesas_sci.c | 350 ++++++++++++++++++++++++++++++++++ hw/char/Kconfig | 3 + hw/char/Makefile.objs | 1 + 4 files changed, 405 insertions(+) create mode 100644 include/hw/char/renesas_sci.h create mode 100644 hw/char/renesas_sci.c diff --git a/include/hw/char/renesas_sci.h b/include/hw/char/renesas_sci.h new file mode 100644 index 0000000000..efdebc620a --- /dev/null +++ b/include/hw/char/renesas_sci.h @@ -0,0 +1,51 @@ +/* + * Renesas Serial Communication Interface + * + * Copyright (c) 2018 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_CHAR_RENESAS_SCI_H +#define HW_CHAR_RENESAS_SCI_H + +#include "chardev/char-fe.h" +#include "hw/sysbus.h" + +#define TYPE_RENESAS_SCI "renesas-sci" +#define RSCI(obj) OBJECT_CHECK(RSCIState, (obj), TYPE_RENESAS_SCI) + +enum { + ERI =3D 0, + RXI =3D 1, + TXI =3D 2, + TEI =3D 3, + SCI_NR_IRQ =3D 4 +}; + +typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion memory; + QEMUTimer timer; + CharBackend chr; + qemu_irq irq[SCI_NR_IRQ]; + + uint8_t smr; + uint8_t brr; + uint8_t scr; + uint8_t tdr; + uint8_t ssr; + uint8_t rdr; + uint8_t scmr; + uint8_t semr; + + uint8_t read_ssr; + int64_t trtime; + int64_t rx_next; + uint64_t input_freq; +} RSCIState; + +#endif diff --git a/hw/char/renesas_sci.c b/hw/char/renesas_sci.c new file mode 100644 index 0000000000..5d7c6e6523 --- /dev/null +++ b/hw/char/renesas_sci.c @@ -0,0 +1,350 @@ +/* + * Renesas Serial Communication Interface + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/qdev-properties.h" +#include "hw/char/renesas_sci.h" +#include "migration/vmstate.h" + +/* SCI register map */ +REG8(SMR, 0) + FIELD(SMR, CKS, 0, 2) + FIELD(SMR, MP, 2, 1) + FIELD(SMR, STOP, 3, 1) + FIELD(SMR, PM, 4, 1) + FIELD(SMR, PE, 5, 1) + FIELD(SMR, CHR, 6, 1) + FIELD(SMR, CM, 7, 1) +REG8(BRR, 1) +REG8(SCR, 2) + FIELD(SCR, CKE, 0, 2) + FIELD(SCR, TEIE, 2, 1) + FIELD(SCR, MPIE, 3, 1) + FIELD(SCR, RE, 4, 1) + FIELD(SCR, TE, 5, 1) + FIELD(SCR, RIE, 6, 1) + FIELD(SCR, TIE, 7, 1) +REG8(TDR, 3) +REG8(SSR, 4) + FIELD(SSR, MPBT, 0, 1) + FIELD(SSR, MPB, 1, 1) + FIELD(SSR, TEND, 2, 1) + FIELD(SSR, ERR, 3, 3) + FIELD(SSR, PER, 3, 1) + FIELD(SSR, FER, 4, 1) + FIELD(SSR, ORER, 5, 1) + FIELD(SSR, RDRF, 6, 1) + FIELD(SSR, TDRE, 7, 1) +REG8(RDR, 5) +REG8(SCMR, 6) + FIELD(SCMR, SMIF, 0, 1) + FIELD(SCMR, SINV, 2, 1) + FIELD(SCMR, SDIR, 3, 1) + FIELD(SCMR, BCP2, 7, 1) +REG8(SEMR, 7) + FIELD(SEMR, ACS0, 0, 1) + FIELD(SEMR, ABCS, 4, 1) + +static int can_receive(void *opaque) +{ + RSCIState *sci =3D RSCI(opaque); + if (sci->rx_next > qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { + return 0; + } else { + return FIELD_EX8(sci->scr, SCR, RE); + } +} + +static void receive(void *opaque, const uint8_t *buf, int size) +{ + RSCIState *sci =3D RSCI(opaque); + sci->rx_next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime; + if (FIELD_EX8(sci->ssr, SSR, RDRF) || size > 1) { + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, ORER, 1); + if (FIELD_EX8(sci->scr, SCR, RIE)) { + qemu_set_irq(sci->irq[ERI], 1); + } + } else { + sci->rdr =3D buf[0]; + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, RDRF, 1); + if (FIELD_EX8(sci->scr, SCR, RIE)) { + qemu_irq_pulse(sci->irq[RXI]); + } + } +} + +static void send_byte(RSCIState *sci) +{ + if (qemu_chr_fe_backend_connected(&sci->chr)) { + qemu_chr_fe_write_all(&sci->chr, &sci->tdr, 1); + } + timer_mod(&sci->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->tr= time); + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TEND, 0); + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TDRE, 1); + qemu_set_irq(sci->irq[TEI], 0); + if (FIELD_EX8(sci->scr, SCR, TIE)) { + qemu_irq_pulse(sci->irq[TXI]); + } +} + +static void txend(void *opaque) +{ + RSCIState *sci =3D RSCI(opaque); + if (!FIELD_EX8(sci->ssr, SSR, TDRE)) { + send_byte(sci); + } else { + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TEND, 1); + if (FIELD_EX8(sci->scr, SCR, TEIE)) { + qemu_set_irq(sci->irq[TEI], 1); + } + } +} + +static void update_trtime(RSCIState *sci) +{ + /* char per bits */ + sci->trtime =3D 8 - FIELD_EX8(sci->smr, SMR, CHR); + sci->trtime +=3D FIELD_EX8(sci->smr, SMR, PE); + sci->trtime +=3D FIELD_EX8(sci->smr, SMR, STOP) + 1; + /* x bit transmit time (32 * divrate * brr) / base freq */ + sci->trtime *=3D 32 * sci->brr; + sci->trtime *=3D 1 << (2 * FIELD_EX8(sci->smr, SMR, CKS)); + sci->trtime *=3D NANOSECONDS_PER_SECOND; + sci->trtime /=3D sci->input_freq; +} + +static bool sci_is_tr_enabled(RSCIState *sci) +{ + return FIELD_EX8(sci->scr, SCR, TE) || FIELD_EX8(sci->scr, SCR, RE); +} + +static void sci_write(void *opaque, hwaddr offset, uint64_t val, unsigned = size) +{ + RSCIState *sci =3D RSCI(opaque); + + switch (offset) { + case A_SMR: + if (!sci_is_tr_enabled(sci)) { + sci->smr =3D val; + update_trtime(sci); + } + break; + case A_BRR: + if (!sci_is_tr_enabled(sci)) { + sci->brr =3D val; + update_trtime(sci); + } + break; + case A_SCR: + sci->scr =3D val; + if (FIELD_EX8(sci->scr, SCR, TE)) { + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TDRE, 1); + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TEND, 1); + if (FIELD_EX8(sci->scr, SCR, TIE)) { + qemu_irq_pulse(sci->irq[TXI]); + } + } + if (!FIELD_EX8(sci->scr, SCR, TEIE)) { + qemu_set_irq(sci->irq[TEI], 0); + } + if (!FIELD_EX8(sci->scr, SCR, RIE)) { + qemu_set_irq(sci->irq[ERI], 0); + } + break; + case A_TDR: + sci->tdr =3D val; + if (FIELD_EX8(sci->ssr, SSR, TEND)) { + send_byte(sci); + } else { + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TDRE, 0); + } + break; + case A_SSR: + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, MPBT, + FIELD_EX8(val, SSR, MPBT)); + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, ERR, + FIELD_EX8(val, SSR, ERR) & 0x07); + if (FIELD_EX8(sci->read_ssr, SSR, ERR) && + FIELD_EX8(sci->ssr, SSR, ERR) =3D=3D 0) { + qemu_set_irq(sci->irq[ERI], 0); + } + break; + case A_RDR: + qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: RDR is read only.\n"); + break; + case A_SCMR: + sci->scmr =3D val; break; + case A_SEMR: /* SEMR */ + sci->semr =3D val; break; + default: + qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX "= " + "not implemented\n", + offset); + } +} + +static uint64_t sci_read(void *opaque, hwaddr offset, unsigned size) +{ + RSCIState *sci =3D RSCI(opaque); + + switch (offset) { + case A_SMR: + return sci->smr; + case A_BRR: + return sci->brr; + case A_SCR: + return sci->scr; + case A_TDR: + return sci->tdr; + case A_SSR: + sci->read_ssr =3D sci->ssr; + return sci->ssr; + case A_RDR: + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, RDRF, 0); + return sci->rdr; + case A_SCMR: + return sci->scmr; + case A_SEMR: + return sci->semr; + default: + qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX + " not implemented.\n", offset); + } + return UINT64_MAX; +} + +static const MemoryRegionOps sci_ops =3D { + .write =3D sci_write, + .read =3D sci_read, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl.max_access_size =3D 1, + .valid.max_access_size =3D 1, +}; + +static void rsci_reset(DeviceState *dev) +{ + RSCIState *sci =3D RSCI(dev); + sci->smr =3D sci->scr =3D 0x00; + sci->brr =3D 0xff; + sci->tdr =3D 0xff; + sci->rdr =3D 0x00; + sci->ssr =3D 0x84; + sci->scmr =3D 0x00; + sci->semr =3D 0x00; + sci->rx_next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); +} + +static void sci_event(void *opaque, QEMUChrEvent event) +{ + RSCIState *sci =3D RSCI(opaque); + if (event =3D=3D CHR_EVENT_BREAK) { + sci->ssr =3D FIELD_DP8(sci->ssr, SSR, FER, 1); + if (FIELD_EX8(sci->scr, SCR, RIE)) { + qemu_set_irq(sci->irq[ERI], 1); + } + } +} + +static void rsci_realize(DeviceState *dev, Error **errp) +{ + RSCIState *sci =3D RSCI(dev); + + if (sci->input_freq =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "renesas_sci: input-freq property must be set."); + return; + } + qemu_chr_fe_set_handlers(&sci->chr, can_receive, receive, + sci_event, NULL, sci, NULL, true); +} + +static void rsci_init(Object *obj) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(obj); + RSCIState *sci =3D RSCI(obj); + int i; + + memory_region_init_io(&sci->memory, OBJECT(sci), &sci_ops, + sci, "renesas-sci", 0x8); + sysbus_init_mmio(d, &sci->memory); + + for (i =3D 0; i < SCI_NR_IRQ; i++) { + sysbus_init_irq(d, &sci->irq[i]); + } + timer_init_ns(&sci->timer, QEMU_CLOCK_VIRTUAL, txend, sci); +} + +static const VMStateDescription vmstate_rsci =3D { + .name =3D "renesas-sci", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_INT64(trtime, RSCIState), + VMSTATE_INT64(rx_next, RSCIState), + VMSTATE_UINT8(smr, RSCIState), + VMSTATE_UINT8(brr, RSCIState), + VMSTATE_UINT8(scr, RSCIState), + VMSTATE_UINT8(tdr, RSCIState), + VMSTATE_UINT8(ssr, RSCIState), + VMSTATE_UINT8(rdr, RSCIState), + VMSTATE_UINT8(scmr, RSCIState), + VMSTATE_UINT8(semr, RSCIState), + VMSTATE_UINT8(read_ssr, RSCIState), + VMSTATE_TIMER(timer, RSCIState), + VMSTATE_END_OF_LIST() + } +}; + +static Property rsci_properties[] =3D { + DEFINE_PROP_UINT64("input-freq", RSCIState, input_freq, 0), + DEFINE_PROP_CHR("chardev", RSCIState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rsci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D rsci_realize; + dc->vmsd =3D &vmstate_rsci; + dc->reset =3D rsci_reset; + device_class_set_props(dc, rsci_properties); +} + +static const TypeInfo rsci_info =3D { + .name =3D TYPE_RENESAS_SCI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RSCIState), + .instance_init =3D rsci_init, + .class_init =3D rsci_class_init, +}; + +static void rsci_register_types(void) +{ + type_register_static(&rsci_info); +} + +type_init(rsci_register_types) diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 40e7a8b8bb..874627520c 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -46,3 +46,6 @@ config SCLPCONSOLE =20 config TERMINAL3270 bool + +config RENESAS_SCI + bool diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index 9e9a6c1aff..996c170750 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -20,6 +20,7 @@ common-obj-$(CONFIG_SH4) +=3D sh_serial.o common-obj-$(CONFIG_DIGIC) +=3D digic-uart.o common-obj-$(CONFIG_STM32F2XX_USART) +=3D stm32f2xx_usart.o common-obj-$(CONFIG_RASPI) +=3D bcm2835_aux.o +common-obj-$(CONFIG_RENESAS_SCI) +=3D renesas_sci.o =20 common-obj-$(CONFIG_CMSDK_APB_UART) +=3D cmsdk-apb-uart.o common-obj-$(CONFIG_ETRAXFS) +=3D etraxfs_ser.o --=20 2.21.3 From nobody Fri May 17 01:43:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[83.51.162.43]) by smtp.gmail.com with ESMTPSA id a6sm21309896wrn.38.2020.06.01.09.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2020 09:14:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AyUQ99AduwXqrVguyV5FFF6ZORrAOfJgEUZqhjZDkcg=; b=fw8+9A1ij1hAHlRFRaNzSXIrnsMpcoL76Zdz5tDeHX7LJ8iAx2Hcr6v548qiOBHNai V/tyRU2ghTUDoPqUZt4TydNEuuN0O70QtMFnqBVDPPT/To6urUmUNkWJMxorCc6mfv91 EkRHn5QaeUqBHtor/ethoHlJNnexC85J1eHciZ9G+Zr5p/W9qoYPZCJqCobN1t39pv8e GdFRQWjELftlRwKXtf8pR2ygdeCQ4mqHnwgGNSjQiM/4N2BGcT2kZnA/ZDz9iD+qYXD5 SdpI79rshk1vj/vGF956Urmfq0BZnB/ChSDNQKt22ZRVYLd3fo+6o2+fe8armVQkILFV 04gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=AyUQ99AduwXqrVguyV5FFF6ZORrAOfJgEUZqhjZDkcg=; b=hKTLNcitMTry/yaIQdhi8SxRGSFcrQcAvMQhPy6GRAuw4ReZ2IURXlnP/XSWeEqaRm GKND409nj8ltMak+bzX48Z2guhq5g6qXFtwhQnyldQE04radVzgqyM76Mke07lms/YYY I2yVfD3oiZQTzHiHufmdHwro9HMbSkIy1yTb5WbYIPIa6l04X6KnRuzBvlLcu/4FWZ1Y HtHYU+D6DFYDPiKfCOq+5x5tf5KcN13USZFgIZtYH7yfdSm2yLpRTm4tIlLWEPskSucG izRlYFx+SXxpffoibZ8ZhGCjerjxpOul/Xki/IwQ4NWrBEUpkfDn9aeFZFnmhJxeLZQr oPKA== X-Gm-Message-State: AOAM533E3yYmDgDqsrRIVMKiTfsLCHg7sjg3X85HmzJnWRMNPG8su41L Bd+/M4JSWjC/LK0P8idiVZM= X-Google-Smtp-Source: ABdhPJz0qVj3+6cjcqJmV0MuU9E8LhSviLqPRqksedoj2xRpHrj09Q7BfO4qRwIRnS4Q3EY+2R5t6w== X-Received: by 2002:a7b:c7d8:: with SMTP id z24mr117489wmk.28.1591028093930; Mon, 01 Jun 2020 09:14:53 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org, Yoshinori Sato Subject: [PATCH 07/12] hw/rx: RX62N microcontroller (MCU) Date: Mon, 1 Jun 2020 18:14:36 +0200 Message-Id: <20200601161441.8086-8-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200601161441.8086-1-f4bug@amsat.org> References: <20200601161441.8086-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato rx62n - RX62N cpu. Signed-off-by: Yoshinori Sato Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson [PMD: Use TYPE_RX62N_CPU, use #define for RX62N_NR_TMR/CMT/SCI, renamed CPU -> MCU, device -> microcontroller] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20200224141923.82118-18-ysato@users.sourceforge.jp> [PMD: Split of machine, use &error_abort] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/rx/rx62n.h | 75 ++++++++++++ hw/rx/rx62n.c | 264 ++++++++++++++++++++++++++++++++++++++++++ hw/Kconfig | 1 + hw/rx/Kconfig | 6 + hw/rx/Makefile.objs | 1 + 5 files changed, 347 insertions(+) create mode 100644 include/hw/rx/rx62n.h create mode 100644 hw/rx/rx62n.c create mode 100644 hw/rx/Kconfig create mode 100644 hw/rx/Makefile.objs diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h new file mode 100644 index 0000000000..7c6023bcd6 --- /dev/null +++ b/include/hw/rx/rx62n.h @@ -0,0 +1,75 @@ +/* + * RX62N MCU Object + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2019 Yoshinori Sato + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_RX_RX62N_MCU_H +#define HW_RX_RX62N_MCU_H + +#include "target/rx/cpu.h" +#include "hw/intc/rx_icu.h" +#include "hw/timer/renesas_tmr.h" +#include "hw/timer/renesas_cmt.h" +#include "hw/char/renesas_sci.h" +#include "qemu/units.h" + +#define TYPE_RX62N_MCU "rx62n-mcu" +#define RX62N_MCU(obj) OBJECT_CHECK(RX62NState, (obj), TYPE_RX62N_MCU) + +#define RX62N_NR_TMR 2 +#define RX62N_NR_CMT 2 +#define RX62N_NR_SCI 6 + +typedef struct RX62NState { + /*< private >*/ + DeviceState parent_obj; + /*< public >*/ + + RXCPU cpu; + RXICUState icu; + RTMRState tmr[RX62N_NR_TMR]; + RCMTState cmt[RX62N_NR_CMT]; + RSCIState sci[RX62N_NR_SCI]; + + MemoryRegion *sysmem; + bool kernel; + + MemoryRegion iram; + MemoryRegion iomem1; + MemoryRegion d_flash; + MemoryRegion iomem2; + MemoryRegion iomem3; + MemoryRegion c_flash; + qemu_irq irq[NR_IRQS]; +} RX62NState; + +/* + * RX62N Internal Memory + * It is the value of R5F562N8. + * Please change the size for R5F562N7. + */ +#define RX62N_IRAM_SIZE (96 * KiB) +#define RX62N_DFLASH_SIZE (32 * KiB) +#define RX62N_CFLASH_SIZE (512 * KiB) + +#define RX62N_PCLK (48 * 1000 * 1000) + +#endif diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c new file mode 100644 index 0000000000..13c90102b1 --- /dev/null +++ b/hw/rx/rx62n.c @@ -0,0 +1,264 @@ +/* + * RX62N Microcontroller + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/rx/rx62n.h" +#include "hw/loader.h" +#include "hw/sysbus.h" +#include "hw/qdev-properties.h" +#include "sysemu/sysemu.h" +#include "cpu.h" + +/* + * RX62N Internal Memory + */ +#define RX62N_IRAM_BASE 0x00000000 +#define RX62N_DFLASH_BASE 0x00100000 +#define RX62N_CFLASH_BASE 0xfff80000 + +/* + * RX62N Peripheral Address + * See users manual section 5 + */ +#define RX62N_ICU_BASE 0x00087000 +#define RX62N_TMR_BASE 0x00088200 +#define RX62N_CMT_BASE 0x00088000 +#define RX62N_SCI_BASE 0x00088240 + +/* + * RX62N Peripheral IRQ + * See users manual section 11 + */ +#define RX62N_TMR_IRQ 174 +#define RX62N_CMT_IRQ 28 +#define RX62N_SCI_IRQ 214 + +/* + * IRQ -> IPR mapping table + * 0x00 - 0x91: IPR no (IPR00 to IPR91) + * 0xff: IPR not assigned + * See "11.3.1 Interrupt Vector Table" in hardware manual. + */ +static const uint8_t ipr_table[NR_IRQS] =3D { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 15 */ + 0x00, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0x02, + 0xff, 0xff, 0xff, 0x03, 0x04, 0x05, 0x06, 0x07, /* 31 */ + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x14, 0x14, 0x14, /* 47 */ + 0x15, 0x15, 0x15, 0x15, 0xff, 0xff, 0xff, 0xff, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x1d, 0x1e, 0x1f, /* 63 */ + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, /* 79 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x3a, 0x3b, 0x3c, 0xff, 0xff, 0xff, /* 95 */ + 0x40, 0xff, 0x44, 0x45, 0xff, 0xff, 0x48, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 111 */ + 0xff, 0xff, 0x51, 0x51, 0x51, 0x51, 0x52, 0x52, + 0x52, 0x53, 0x53, 0x54, 0x54, 0x55, 0x55, 0x56, /* 127 */ + 0x56, 0x57, 0x57, 0x57, 0x57, 0x58, 0x59, 0x59, + 0x59, 0x59, 0x5a, 0x5b, 0x5b, 0x5b, 0x5c, 0x5c, /* 143 */ + 0x5c, 0x5c, 0x5d, 0x5d, 0x5d, 0x5e, 0x5e, 0x5f, + 0x5f, 0x60, 0x60, 0x61, 0x61, 0x62, 0x62, 0x62, /* 159 */ + 0x62, 0x63, 0x64, 0x64, 0x64, 0x64, 0x65, 0x66, + 0x66, 0x66, 0x67, 0x67, 0x67, 0x67, 0x68, 0x68, /* 175 */ + 0x68, 0x69, 0x69, 0x69, 0x6a, 0x6a, 0x6a, 0x6b, + 0x6b, 0x6b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 191 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x71, + 0x72, 0x73, 0x74, 0x75, 0xff, 0xff, 0xff, 0xff, /* 207 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x80, + 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x82, 0x82, /* 223 */ + 0x82, 0x82, 0x83, 0x83, 0x83, 0x83, 0xff, 0xff, + 0xff, 0xff, 0x85, 0x85, 0x85, 0x85, 0x86, 0x86, /* 239 */ + 0x86, 0x86, 0xff, 0xff, 0xff, 0xff, 0x88, 0x89, + 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, /* 255 */ +}; + +/* + * Level triggerd IRQ list + * Not listed IRQ is Edge trigger. + * See "11.3.1 Interrupt Vector Table" in hardware manual. + */ +static const uint8_t levelirq[] =3D { + 16, 21, 32, 44, 47, 48, 51, 64, 65, 66, + 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, + 77, 78, 79, 90, 91, 170, 171, 172, 173, 214, + 217, 218, 221, 222, 225, 226, 229, 234, 237, 238, + 241, 246, 249, 250, 253, +}; + +static void register_icu(RX62NState *s) +{ + int i; + SysBusDevice *icu; + + object_initialize_child(OBJECT(s), "icu", &s->icu, sizeof(RXICUState), + TYPE_RX_ICU, &error_abort, NULL); + + icu =3D SYS_BUS_DEVICE(&s->icu); + qdev_prop_set_uint32(DEVICE(icu), "len-ipr-map", NR_IRQS); + for (i =3D 0; i < NR_IRQS; i++) { + char propname[32]; + snprintf(propname, sizeof(propname), "ipr-map[%d]", i); + qdev_prop_set_uint32(DEVICE(icu), propname, ipr_table[i]); + } + qdev_prop_set_uint32(DEVICE(icu), "len-trigger-level", + ARRAY_SIZE(levelirq)); + for (i =3D 0; i < ARRAY_SIZE(levelirq); i++) { + char propname[32]; + snprintf(propname, sizeof(propname), "trigger-level[%d]", i); + qdev_prop_set_uint32(DEVICE(icu), propname, levelirq[i]); + } + + for (i =3D 0; i < NR_IRQS; i++) { + s->irq[i] =3D qdev_get_gpio_in(DEVICE(icu), i); + } + qdev_init_nofail(DEVICE(icu)); + + sysbus_connect_irq(icu, 0, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_IR= Q)); + sysbus_connect_irq(icu, 1, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_FI= R)); + sysbus_connect_irq(icu, 2, s->irq[SWI]); + sysbus_mmio_map(SYS_BUS_DEVICE(icu), 0, RX62N_ICU_BASE); +} + +static void register_tmr(RX62NState *s, int unit) +{ + SysBusDevice *tmr; + int i, irqbase; + + object_initialize_child(OBJECT(s), "tmr[*]", &s->tmr[unit], + sizeof(RTMRState), TYPE_RENESAS_TMR, + &error_abort, NULL); + + tmr =3D SYS_BUS_DEVICE(&s->tmr[unit]); + qdev_prop_set_uint64(DEVICE(tmr), "input-freq", RX62N_PCLK); + qdev_init_nofail(DEVICE(tmr)); + + irqbase =3D RX62N_TMR_IRQ + TMR_NR_IRQ * unit; + for (i =3D 0; i < TMR_NR_IRQ; i++) { + sysbus_connect_irq(tmr, i, s->irq[irqbase + i]); + } + sysbus_mmio_map(tmr, 0, RX62N_TMR_BASE + unit * 0x10); +} + +static void register_cmt(RX62NState *s, int unit) +{ + SysBusDevice *cmt; + int i, irqbase; + + object_initialize_child(OBJECT(s), "cmt[*]", &s->cmt[unit], + sizeof(RCMTState), TYPE_RENESAS_CMT, + &error_abort, NULL); + + cmt =3D SYS_BUS_DEVICE(&s->cmt[unit]); + qdev_prop_set_uint64(DEVICE(cmt), "input-freq", RX62N_PCLK); + qdev_init_nofail(DEVICE(cmt)); + + irqbase =3D RX62N_CMT_IRQ + CMT_NR_IRQ * unit; + for (i =3D 0; i < CMT_NR_IRQ; i++) { + sysbus_connect_irq(cmt, i, s->irq[irqbase + i]); + } + sysbus_mmio_map(cmt, 0, RX62N_CMT_BASE + unit * 0x10); +} + +static void register_sci(RX62NState *s, int unit) +{ + SysBusDevice *sci; + int i, irqbase; + + object_initialize_child(OBJECT(s), "sci[*]", &s->sci[unit], + sizeof(RSCIState), TYPE_RENESAS_SCI, + &error_abort, NULL); + + sci =3D SYS_BUS_DEVICE(&s->sci[unit]); + qdev_prop_set_chr(DEVICE(sci), "chardev", serial_hd(unit)); + qdev_prop_set_uint64(DEVICE(sci), "input-freq", RX62N_PCLK); + qdev_init_nofail(DEVICE(sci)); + + irqbase =3D RX62N_SCI_IRQ + SCI_NR_IRQ * unit; + for (i =3D 0; i < SCI_NR_IRQ; i++) { + sysbus_connect_irq(sci, i, s->irq[irqbase + i]); + } + sysbus_mmio_map(sci, 0, RX62N_SCI_BASE + unit * 0x08); +} + +static void rx62n_realize(DeviceState *dev, Error **errp) +{ + RX62NState *s =3D RX62N_MCU(dev); + + memory_region_init_ram(&s->iram, OBJECT(dev), "iram", + rxc->ram_size, &error_abort); + memory_region_add_subregion(s->sysmem, RX62N_IRAM_BASE, &s->iram); + memory_region_init_rom(&s->d_flash, OBJECT(dev), "flash-data", + rxc->data_flash_size, &error_abort); + memory_region_add_subregion(s->sysmem, RX62N_DFLASH_BASE, &s->d_flash); + memory_region_init_rom(&s->c_flash, OBJECT(dev), "flash-code", + rxc->rom_flash_size, &error_abort); + memory_region_add_subregion(s->sysmem, RX62N_CFLASH_BASE, &s->c_flash); + + if (!s->kernel) { + rom_add_file_fixed(bios_name, RX62N_CFLASH_BASE, 0); + } + + /* Initialize CPU */ + object_initialize_child(OBJECT(s), "cpu", &s->cpu, sizeof(RXCPU), + TYPE_RX62N_CPU, &error_abort, NULL); + object_property_set_bool(OBJECT(&s->cpu), true, "realized", &error_abo= rt); + + register_icu(s); + s->cpu.env.ack =3D qdev_get_gpio_in_named(DEVICE(&s->icu), "ack", 0); + register_tmr(s, 0); + register_tmr(s, 1); + register_cmt(s, 0); + register_cmt(s, 1); + register_sci(s, 0); +} + +static Property rx62n_properties[] =3D { + DEFINE_PROP_LINK("main-bus", RX62NState, sysmem, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_BOOL("load-kernel", RX62NState, kernel, false), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rx62n_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D rx62n_realize; + device_class_set_props(dc, rx62n_properties); +} + +static const TypeInfo rx62n_info =3D { + .name =3D TYPE_RX62N_MCU, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(RX62NState), + .class_init =3D rx62n_class_init, +}; + +static void rx62n_register_types(void) +{ + type_register_static(&rx62n_info); +} + +type_init(rx62n_register_types) diff --git a/hw/Kconfig b/hw/Kconfig index ecf491bf04..62f9ebdc22 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -55,6 +55,7 @@ source nios2/Kconfig source openrisc/Kconfig source ppc/Kconfig source riscv/Kconfig +source rx/Kconfig source s390x/Kconfig source sh4/Kconfig source sparc/Kconfig diff --git a/hw/rx/Kconfig b/hw/rx/Kconfig new file mode 100644 index 0000000000..e7b1c59516 --- /dev/null +++ b/hw/rx/Kconfig @@ -0,0 +1,6 @@ +config RX62N_MCU + bool + select RX_ICU + select RENESAS_TMR + select RENESAS_CMT + select RENESAS_SCI diff --git a/hw/rx/Makefile.objs b/hw/rx/Makefile.objs new file mode 100644 index 0000000000..fe19ee7984 --- /dev/null +++ b/hw/rx/Makefile.objs @@ -0,0 +1 @@ +obj-$(CONFIG_RX62N_MCU) +=3D rx62n.o --=20 2.21.3 From nobody Fri May 17 01:43:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Richard Henderson Issue an error if no kernel, no bios, and not qtest'ing. Fixes make check-qtest-rx: test/qom-test. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Yoshinori Sato Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-19-ysato@users.sourceforge.jp> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/rx/rx62n.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index 13c90102b1..92d215f07a 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -21,12 +21,14 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "hw/hw.h" #include "hw/rx/rx62n.h" #include "hw/loader.h" #include "hw/sysbus.h" #include "hw/qdev-properties.h" #include "sysemu/sysemu.h" +#include "sysemu/qtest.h" #include "cpu.h" =20 /* @@ -217,7 +219,12 @@ static void rx62n_realize(DeviceState *dev, Error **er= rp) memory_region_add_subregion(s->sysmem, RX62N_CFLASH_BASE, &s->c_flash); =20 if (!s->kernel) { - rom_add_file_fixed(bios_name, RX62N_CFLASH_BASE, 0); + if (bios_name) { + rom_add_file_fixed(bios_name, RX62N_CFLASH_BASE, 0); + } else if (!qtest_enabled()) { + error_report("No bios or kernel specified"); + exit(1); + } } =20 /* Initialize CPU */ --=20 2.21.3 From nobody Fri May 17 01:43:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1591028198; cv=none; d=zohomail.com; s=zohoarc; b=KInCCTr+5srsz925bX5T+xwFXLBfqOeMx4zA/tHa3DZ+YgrbDuhhW1PlbSM/ecNdYpZf3G88jlu5DqInQ/gXbiuU5ooLJMVC53IL1hXuPLbEMaqpZKaSsio09vgpSYv6cAdbHKYEVoQvltkg6HrdqfX8h6YO2ZQKQMwzDSrBf/A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591028198; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8k7Q+h1dMdB8Hm8Essuow3OOXb1LrqVXcXCbj2V7FbQ=; b=Nm9kTDzHPrhNJN53w540kqR2M0aobLQsw7YL8yoz82VIZvSgX0li86rXSo3QuiqVZlIKYSel3Q1B/st9Ce/bSLEdGOF6v+kUc/nLL/52QfXZ0Iqakv8Xk642/LM9qeFV+g5guZUrdYYBa4u+DhHZ4aRAZn2VOW866DBLaXU0mhw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591028198727904.2716020316525; Mon, 1 Jun 2020 09:16:38 -0700 (PDT) Received: from localhost ([::1]:57326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jfn77-0007GI-EE for importer@patchew.org; Mon, 01 Jun 2020 12:16:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50948) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jfn5X-0005QG-7i for qemu-devel@nongnu.org; Mon, 01 Jun 2020 12:14:59 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:45527) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jfn5W-0001XH-CL for qemu-devel@nongnu.org; Mon, 01 Jun 2020 12:14:58 -0400 Received: by mail-wr1-x430.google.com with SMTP id c3so367793wru.12 for ; Mon, 01 Jun 2020 09:14:57 -0700 (PDT) Received: from localhost.localdomain (43.red-83-51-162.dynamicip.rima-tde.net. [83.51.162.43]) by smtp.gmail.com with ESMTPSA id a6sm21309896wrn.38.2020.06.01.09.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2020 09:14:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8k7Q+h1dMdB8Hm8Essuow3OOXb1LrqVXcXCbj2V7FbQ=; b=Xkksl8umDVSE2m1H4nw6lFZkRXnoxFEzsHN0bG6bgxkOq6CTghqI1ao7iV1GV1onC3 vxGj8NfEbmkYxgRra6ngDUYA9L6syDhQLroASyA3ULqXXVq257S0j1A3FedLEqRuO8Yq hX3qeK6KQ1EfcCqowmEuueKrgfoe71zpsjhOwpptrFydPrZJRrS3OrMHfB9R79UQ08bw 0f0kccCRtyfojWCtdvgCUnL1//UNjj4XP88ybEid2JZsZ+5Drux7Ien/nN7lDrR6kx33 29g5b2p+Kib9a+ZX6zIa16z6sFYvl58Do0Ka4uqN9H+GAJ/ZB7I9UsLifW2XNboTfAKd Ia6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8k7Q+h1dMdB8Hm8Essuow3OOXb1LrqVXcXCbj2V7FbQ=; b=op5E6w3FrJHJ20I+DAJCKMlHuaOO+ZJsVZAVC/b7cJR8d7fYV0m1HE1FHrTi9WY1ng G0RBdz5ygCnDAnDK+J4FiCT7MjS5vV/kAOMCVaLJFNprVZOVLKs0J5+tDElZw4WnW0s+ OZcxfItKQIlCdspoZs2MOB07q/81y4eJa1clyDASlxr8VGgiMZHKx8PtDOvyk3lnZTUz Uf1g5CSqi3jZ2Anf/wweXakNlPkjnwm4Uybj9hcKc3ORvDKQxJztK6bX2F9JFhZtsdZM fAjWl56r/hE2U+AJ4yeKHO3U7h7uY0DqZaOI9BHuKr2G/wjXWzIrwRtmfkos+xQpnUwh EEJQ== X-Gm-Message-State: AOAM53113bm5uZqUyACwDWyTbKeqzY0E19G6s3o7DHtpoxD8AGfLz6/f V59rwQgm4c0K7ZVMwtA6VyQ= X-Google-Smtp-Source: ABdhPJwtY1BkkUdUs1fwbzZ5ZO46XGJxbXwrug23+DPUdJLUIwpoMhiZmv1dU3LAm4AIi6CpNz7M4A== X-Received: by 2002:a05:6000:1289:: with SMTP id f9mr22868509wrx.5.1591028096923; Mon, 01 Jun 2020 09:14:56 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org, Yoshinori Sato Subject: [PATCH 09/12] hw/rx: Register R5F562N7 and R5F562N8 MCUs Date: Mon, 1 Jun 2020 18:14:38 +0200 Message-Id: <20200601161441.8086-10-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200601161441.8086-1-f4bug@amsat.org> References: <20200601161441.8086-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Make the current TYPE_RX62N_MCU an abstract class, and generate TYPE_R5F562N7_MCU and TYPE_R5F562N8_MCU models. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/rx/rx62n.h | 17 +++++---- hw/rx/rx62n.c | 81 ++++++++++++++++++++++++++++++++++++------- 2 files changed, 77 insertions(+), 21 deletions(-) diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index 7c6023bcd6..0421cd6d4d 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h @@ -34,6 +34,9 @@ #define TYPE_RX62N_MCU "rx62n-mcu" #define RX62N_MCU(obj) OBJECT_CHECK(RX62NState, (obj), TYPE_RX62N_MCU) =20 +#define TYPE_R5F562N7_MCU "r5f562n7-mcu" +#define TYPE_R5F562N8_MCU "r5f562n8-mcu" + #define RX62N_NR_TMR 2 #define RX62N_NR_CMT 2 #define RX62N_NR_SCI 6 @@ -59,16 +62,12 @@ typedef struct RX62NState { MemoryRegion iomem3; MemoryRegion c_flash; qemu_irq irq[NR_IRQS]; -} RX62NState; =20 -/* - * RX62N Internal Memory - * It is the value of R5F562N8. - * Please change the size for R5F562N7. - */ -#define RX62N_IRAM_SIZE (96 * KiB) -#define RX62N_DFLASH_SIZE (32 * KiB) -#define RX62N_CFLASH_SIZE (512 * KiB) + /* Input Clock (XTAL) frequency */ + uint32_t xtal_freq_hz; + /* Peripheral Module Clock frequency */ + uint32_t pclk_freq_hz; +} RX62NState; =20 #define RX62N_PCLK (48 * 1000 * 1000) =20 diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index 92d215f07a..69dc5e5da9 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -5,6 +5,7 @@ * (Rev.1.40 R01UH0033EJ0140) * * Copyright (c) 2019 Yoshinori Sato + * Copyright (c) 2020 Philippe Mathieu-Daud=C3=A9 * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -55,6 +56,21 @@ #define RX62N_CMT_IRQ 28 #define RX62N_SCI_IRQ 214 =20 +typedef struct RX62NClass { + /*< private >*/ + DeviceClass parent_class; + /*< public >*/ + const char *name; + uint64_t ram_size; + uint64_t rom_flash_size; + uint64_t data_flash_size; +} RX62NClass; + +#define RX62N_MCU_CLASS(klass) \ + OBJECT_CLASS_CHECK(RX62NClass, (klass), TYPE_RX62N_MCU) +#define RX62N_MCU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(RX62NClass, (obj), TYPE_RX62N_MCU) + /* * IRQ -> IPR mapping table * 0x00 - 0x91: IPR no (IPR00 to IPR91) @@ -153,7 +169,7 @@ static void register_tmr(RX62NState *s, int unit) &error_abort, NULL); =20 tmr =3D SYS_BUS_DEVICE(&s->tmr[unit]); - qdev_prop_set_uint64(DEVICE(tmr), "input-freq", RX62N_PCLK); + qdev_prop_set_uint64(DEVICE(tmr), "input-freq", s->pclk_freq_hz); qdev_init_nofail(DEVICE(tmr)); =20 irqbase =3D RX62N_TMR_IRQ + TMR_NR_IRQ * unit; @@ -173,7 +189,7 @@ static void register_cmt(RX62NState *s, int unit) &error_abort, NULL); =20 cmt =3D SYS_BUS_DEVICE(&s->cmt[unit]); - qdev_prop_set_uint64(DEVICE(cmt), "input-freq", RX62N_PCLK); + qdev_prop_set_uint64(DEVICE(cmt), "input-freq", s->pclk_freq_hz); qdev_init_nofail(DEVICE(cmt)); =20 irqbase =3D RX62N_CMT_IRQ + CMT_NR_IRQ * unit; @@ -194,7 +210,7 @@ static void register_sci(RX62NState *s, int unit) =20 sci =3D SYS_BUS_DEVICE(&s->sci[unit]); qdev_prop_set_chr(DEVICE(sci), "chardev", serial_hd(unit)); - qdev_prop_set_uint64(DEVICE(sci), "input-freq", RX62N_PCLK); + qdev_prop_set_uint64(DEVICE(sci), "input-freq", s->pclk_freq_hz); qdev_init_nofail(DEVICE(sci)); =20 irqbase =3D RX62N_SCI_IRQ + SCI_NR_IRQ * unit; @@ -207,6 +223,21 @@ static void register_sci(RX62NState *s, int unit) static void rx62n_realize(DeviceState *dev, Error **errp) { RX62NState *s =3D RX62N_MCU(dev); + RX62NClass *rxc =3D RX62N_MCU_GET_CLASS(dev); + + if (s->xtal_freq_hz =3D=3D 0) { + error_setg(errp, "\"xtal-frequency-hz\" property must be provided.= "); + return; + } + /* XTAL range: 8-14 MHz */ + if (s->xtal_freq_hz < 8e6 || s->xtal_freq_hz > 14e6) { + error_setg(errp, "\"xtal-frequency-hz\" property in incorrect rang= e."); + return; + } + /* Use a 4x fixed multiplier */ + s->pclk_freq_hz =3D 4 * s->xtal_freq_hz; + /* PCLK range: 8-50 MHz */ + assert(s->pclk_freq_hz <=3D 50e6); =20 memory_region_init_ram(&s->iram, OBJECT(dev), "iram", rxc->ram_size, &error_abort); @@ -245,6 +276,7 @@ static Property rx62n_properties[] =3D { DEFINE_PROP_LINK("main-bus", RX62NState, sysmem, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_BOOL("load-kernel", RX62NState, kernel, false), + DEFINE_PROP_UINT32("xtal-frequency-hz", RX62NState, xtal_freq_hz, 0), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -256,16 +288,41 @@ static void rx62n_class_init(ObjectClass *klass, void= *data) device_class_set_props(dc, rx62n_properties); } =20 -static const TypeInfo rx62n_info =3D { - .name =3D TYPE_RX62N_MCU, - .parent =3D TYPE_DEVICE, - .instance_size =3D sizeof(RX62NState), - .class_init =3D rx62n_class_init, +static void r5f562n7_class_init(ObjectClass *oc, void *data) +{ + RX62NClass *rxc =3D RX62N_MCU_CLASS(oc); + + rxc->ram_size =3D 64 * KiB; + rxc->rom_flash_size =3D 384 * KiB; + rxc->data_flash_size =3D 32 * KiB; }; =20 -static void rx62n_register_types(void) +static void r5f562n8_class_init(ObjectClass *oc, void *data) { - type_register_static(&rx62n_info); -} + RX62NClass *rxc =3D RX62N_MCU_CLASS(oc); =20 -type_init(rx62n_register_types) + rxc->ram_size =3D 96 * KiB; + rxc->rom_flash_size =3D 512 * KiB; + rxc->data_flash_size =3D 32 * KiB; +}; + +static const TypeInfo rx62n_types[] =3D { + { + .name =3D TYPE_R5F562N7_MCU, + .parent =3D TYPE_RX62N_MCU, + .class_init =3D r5f562n7_class_init, + }, { + .name =3D TYPE_R5F562N8_MCU, + .parent =3D TYPE_RX62N_MCU, + .class_init =3D r5f562n8_class_init, + }, { + .name =3D TYPE_RX62N_MCU, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(RX62NState), + .class_size =3D sizeof(RX62NClass), + .class_init =3D rx62n_class_init, + .abstract =3D true, + } +}; + +DEFINE_TYPES(rx62n_types) --=20 2.21.3 From nobody Fri May 17 01:43:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1591028652; cv=none; d=zohomail.com; s=zohoarc; b=gu6VutzDrtnh8jlPLz90K0dusVPTArChBLgGADVO0YYZhPcFsBHq5gXbYqMjmuJnlxzczS3hAEkE3u3seiWawyTO+doiN97fSXIMkp69/jbHNayjP9PPO5Nu3ec+ghCXiZa2rnqS3um0dtuBEvc46XMPr0SvMmzbaJqKGspHS0E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591028652; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RWdudFnYi0EUSMbnOj3UHoO35ptoSzGdI/tJkRX1nw8=; b=KpcqL3L/duVKcMhLtu7wFHZtPltj/jJL0IP7jfC8ASK68PNM3QN3pu3plVfKLVJblxv9yYJvE3QifTxD/3CbH88Y4CUvm5CK5CTZON9qTG+5wz6OE+pH2hdzohLoWSU6V5utPtR/6ND7AJpim41Tpglk8pd/qleUSdg1XnWxZhA= ARC-Authentication-Results: i=1; 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[83.51.162.43]) by smtp.gmail.com with ESMTPSA id a6sm21309896wrn.38.2020.06.01.09.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2020 09:14:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RWdudFnYi0EUSMbnOj3UHoO35ptoSzGdI/tJkRX1nw8=; b=r6Wf/8EY9Luxf6B8WKIgqElxzWm5aqquJiEyKEaSAv4F6J03dWmjk98l8CrgK9gJ+p 10+QmunAOVAISmZ9q+MNpk0TBUlbUVg9RFPKhcwyZP28ysIdwurtlFM9LD9kFv7Gdxv8 PQa6W8R4yjfq6AjavM7o510tUoq/TL+C2J9FMO9ajx86+anPB/LFdkHmvWlaBdpDMkQq YVFkoC+MfiwPBIWj3Wt9h6yEVmPla3iAVYuhIZO9fC43ZYkhLfyFwCV9SjlJcG6mShdT bG2y7jUHp0CBguG9L5XIfbHCO4f320pyXtM09WhIJyqY3U2hLSYlxN3068K3RxJfIC9E dq1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=RWdudFnYi0EUSMbnOj3UHoO35ptoSzGdI/tJkRX1nw8=; b=PCa8/pmTCcO4K/yZL3pdehijRZPnG/XY6G+11I4Dn/lCXpAzP7wFPXwzWW3SMLCdEl JF9+zqfNyToB7avYxom1klFkEhVpzOTwhF/1Uhp1E++/qw+PAI+qBuEik6zvkBCsuR/s 5xTG9ywMSZfj484AVJbqQYrF4SOSrkZmwwDxNwVcY6l5gnlF5eZoGLkGiZOcmEKvFOSj 5ShD1xXJb8eqkZmXKZL9XHUEdq0fuspnukSZ03VBIZMnBXOfOKvPZufuXQDVoZICw8VO AX0e3tbh/WOWmsDM8aX1l+L1SNq5xEuz3KCXhCXW0VxvTbgGH1oyMY7H936aeZVIq4cb oYCQ== X-Gm-Message-State: AOAM530tqhFQPrvc7q5fuT4lLeXwyPMdm7LfU9DpE1opgKBdX7nIrTSL iVMk62yZRIBASD6vuuJuvlI= X-Google-Smtp-Source: ABdhPJx1QqnsgsSyopoZc9LyyuPHSK3VVOI2xr1cppW9cxXo+MIpNaVH4NRcHZqIz1wYEFBjsfhOBQ== X-Received: by 2002:a1c:9d09:: with SMTP id g9mr84056wme.31.1591028098209; Mon, 01 Jun 2020 09:14:58 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org, Yoshinori Sato Subject: [PATCH 10/12] hw/rx: Add RX GDB simulator Date: Mon, 1 Jun 2020 18:14:39 +0200 Message-Id: <20200601161441.8086-11-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200601161441.8086-1-f4bug@amsat.org> References: <20200601161441.8086-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato Add the RX machine internally simulated in GDB. Signed-off-by: Yoshinori Sato Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson [PMD: Use TYPE_RX62N_CPU, use #define for RX62N_NR_TMR/CMT/SCI, renamed CPU -> MCU, device -> microcontroller] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20200224141923.82118-18-ysato@users.sourceforge.jp> [PMD: Split of MCU, rename gdbsim, Add gdbsim-r5f562n7/r5f562n8] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- default-configs/rx-softmmu.mak | 1 + include/hw/rx/rx62n.h | 4 + hw/rx/rx-gdbsim.c | 198 +++++++++++++++++++++++++++++++++ hw/rx/Kconfig | 4 + hw/rx/Makefile.objs | 1 + 5 files changed, 208 insertions(+) create mode 100644 hw/rx/rx-gdbsim.c diff --git a/default-configs/rx-softmmu.mak b/default-configs/rx-softmmu.mak index 7c4eb2c1a0..df2b4e4f42 100644 --- a/default-configs/rx-softmmu.mak +++ b/default-configs/rx-softmmu.mak @@ -1,2 +1,3 @@ # Default configuration for rx-softmmu =20 +CONFIG_RX_GDBSIM=3Dy diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index 0421cd6d4d..121caedbe9 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h @@ -37,6 +37,10 @@ #define TYPE_R5F562N7_MCU "r5f562n7-mcu" #define TYPE_R5F562N8_MCU "r5f562n8-mcu" =20 +#define EXT_CS_BASE 0x01000000 +#define VECTOR_TABLE_BASE 0xffffff80 +#define RX62N_CFLASH_BASE 0xfff80000 + #define RX62N_NR_TMR 2 #define RX62N_NR_CMT 2 #define RX62N_NR_SCI 6 diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c new file mode 100644 index 0000000000..01751790ed --- /dev/null +++ b/hw/rx/rx-gdbsim.c @@ -0,0 +1,198 @@ +/* + * RX QEMU GDB simulator + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/loader.h" +#include "hw/rx/rx62n.h" +#include "sysemu/sysemu.h" +#include "sysemu/qtest.h" +#include "sysemu/device_tree.h" +#include "hw/boards.h" + +/* Same address of GDB integrated simulator */ +#define SDRAM_BASE EXT_CS_BASE + +typedef struct RxGdbSimMachineClass { + /*< private >*/ + MachineClass parent_class; + /*< public >*/ + const char *mcu_name; + uint32_t xtal_freq_hz; +} RxGdbSimMachineClass; + +typedef struct RxGdbSimMachineState { + /*< private >*/ + MachineState parent_obj; + /*< public >*/ + RX62NState mcu; +} RxGdbSimMachineState; + +#define TYPE_RX_GDBSIM_MACHINE MACHINE_TYPE_NAME("rx62n-common") + +#define RX_GDBSIM_MACHINE(obj) \ + OBJECT_CHECK(RxGdbSimMachineState, (obj), TYPE_RX_GDBSIM_MACHINE) + +#define RX_GDBSIM_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(RxGdbSimMachineClass, (klass), TYPE_RX_GDBSIM_MACHI= NE) +#define RX_GDBSIM_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(RxGdbSimMachineClass, (obj), TYPE_RX_GDBSIM_MACHINE) + +static void rx_load_image(RXCPU *cpu, const char *filename, + uint32_t start, uint32_t size) +{ + static uint32_t extable[32]; + long kernel_size; + int i; + + kernel_size =3D load_image_targphys(filename, start, size); + if (kernel_size < 0) { + fprintf(stderr, "qemu: could not load kernel '%s'\n", filename); + exit(1); + } + cpu->env.pc =3D start; + + /* setup exception trap trampoline */ + /* linux kernel only works little-endian mode */ + for (i =3D 0; i < ARRAY_SIZE(extable); i++) { + extable[i] =3D cpu_to_le32(0x10 + i * 4); + } + rom_add_blob_fixed("extable", extable, sizeof(extable), VECTOR_TABLE_B= ASE); +} + +static void rx_gdbsim_init(MachineState *machine) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + RxGdbSimMachineState *s =3D RX_GDBSIM_MACHINE(machine); + RxGdbSimMachineClass *rxc =3D RX_GDBSIM_MACHINE_GET_CLASS(machine); + MemoryRegion *sysmem =3D get_system_memory(); + const char *kernel_filename =3D machine->kernel_filename; + const char *dtb_filename =3D machine->dtb; + + if (machine->ram_size < mc->default_ram_size) { + error_report("Invalid RAM size, should be more than %" PRIi64 " By= tes", + mc->default_ram_size); + } + + /* Allocate memory space */ + memory_region_add_subregion(sysmem, SDRAM_BASE, machine->ram); + + /* Initialize MCU */ + object_initialize_child(OBJECT(machine), "mcu", &s->mcu, + sizeof(RX62NState), rxc->mcu_name, + &error_fatal, NULL); + object_property_set_link(OBJECT(&s->mcu), OBJECT(sysmem), + "main-bus", &error_abort); + object_property_set_uint(OBJECT(&s->mcu), rxc->xtal_freq_hz, + "xtal-frequency-hz", &error_abort); + object_property_set_bool(OBJECT(&s->mcu), kernel_filename !=3D NULL, + "load-kernel", &error_abort); + object_property_set_bool(OBJECT(&s->mcu), true, "realized", &error_abo= rt); + + /* Load kernel and dtb */ + if (kernel_filename) { + ram_addr_t kernel_offset; + + /* + * The kernel image is loaded into + * the latter half of the SDRAM space. + */ + kernel_offset =3D machine->ram_size / 2; + rx_load_image(RXCPU(first_cpu), kernel_filename, + SDRAM_BASE + kernel_offset, kernel_offset); + if (dtb_filename) { + ram_addr_t dtb_offset; + int dtb_size; + void *dtb; + + dtb =3D load_device_tree(dtb_filename, &dtb_size); + if (dtb =3D=3D NULL) { + error_report("Couldn't open dtb file %s", dtb_filename); + exit(1); + } + if (machine->kernel_cmdline && + qemu_fdt_setprop_string(dtb, "/chosen", "bootargs", + machine->kernel_cmdline) < 0) { + error_report("Couldn't set /chosen/bootargs"); + exit(1); + } + /* DTB is located at the end of SDRAM space. */ + dtb_offset =3D machine->ram_size - dtb_size; + rom_add_blob_fixed("dtb", dtb, dtb_size, + SDRAM_BASE + dtb_offset); + /* Set dtb address to R1 */ + RXCPU(first_cpu)->env.regs[1] =3D SDRAM_BASE + dtb_offset; + } + } +} + +static void rx_gdbsim_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->init =3D rx_gdbsim_init; + mc->default_cpu_type =3D TYPE_RX62N_CPU; + mc->default_ram_size =3D 16 * MiB; + mc->default_ram_id =3D "ext-sdram"; +} + +static void rx62n7_class_init(ObjectClass *oc, void *data) +{ + RxGdbSimMachineClass *rxc =3D RX_GDBSIM_MACHINE_CLASS(oc); + MachineClass *mc =3D MACHINE_CLASS(oc); + + rxc->mcu_name =3D TYPE_R5F562N7_MCU; + rxc->xtal_freq_hz =3D 12 * 1000 * 1000; + mc->desc =3D "gdb simulator (R5F562N7 MCU and external RAM)"; +}; + +static void rx62n8_class_init(ObjectClass *oc, void *data) +{ + RxGdbSimMachineClass *rxc =3D RX_GDBSIM_MACHINE_CLASS(oc); + MachineClass *mc =3D MACHINE_CLASS(oc); + + rxc->mcu_name =3D TYPE_R5F562N8_MCU; + rxc->xtal_freq_hz =3D 12 * 1000 * 1000; + mc->desc =3D "gdb simulator (R5F562N8 MCU and external RAM)"; +}; + +static const TypeInfo rx_gdbsim_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("gdbsim-r5f562n7"), + .parent =3D TYPE_RX_GDBSIM_MACHINE, + .class_init =3D rx62n7_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("gdbsim-r5f562n8"), + .parent =3D TYPE_RX_GDBSIM_MACHINE, + .class_init =3D rx62n8_class_init, + }, { + .name =3D TYPE_RX_GDBSIM_MACHINE, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(RxGdbSimMachineState), + .class_size =3D sizeof(RxGdbSimMachineClass), + .class_init =3D rx_gdbsim_class_init, + .abstract =3D true, + } +}; + +DEFINE_TYPES(rx_gdbsim_types) diff --git a/hw/rx/Kconfig b/hw/rx/Kconfig index e7b1c59516..2b297c5a6a 100644 --- a/hw/rx/Kconfig +++ b/hw/rx/Kconfig @@ -4,3 +4,7 @@ config RX62N_MCU select RENESAS_TMR select RENESAS_CMT select RENESAS_SCI + +config RX_GDBSIM + bool + select RX62N_MCU diff --git a/hw/rx/Makefile.objs b/hw/rx/Makefile.objs index fe19ee7984..4ef6b9e5b1 100644 --- a/hw/rx/Makefile.objs +++ b/hw/rx/Makefile.objs @@ -1 +1,2 @@ obj-$(CONFIG_RX62N_MCU) +=3D rx62n.o +obj-$(CONFIG_RX_GDBSIM) +=3D rx-gdbsim.o --=20 2.21.3 From nobody Fri May 17 01:43:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1591028340; cv=none; d=zohomail.com; s=zohoarc; b=HAD7DhlrHZOz1oH6ohf6HNu2gdJJPI1MzKWz9dNzytj3xsk3GSQyeDdCjIahCNFOlIzm5bEWKrUWS77ZW9KJZBg/FhW2doou5Zn+Qz5DnLC6drc0DrZFKO3s3i7qsYKgiinrJbykbfnBTWrVbxGxk0fW0KX/qkNAtC6DHmlnrEc= ARC-Message-Signature: i=1; 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[83.51.162.43]) by smtp.gmail.com with ESMTPSA id a6sm21309896wrn.38.2020.06.01.09.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2020 09:14:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KLSUgMn8z8HS4y/cukG+SgOuvLLwHPQH27GL6WIk32I=; b=Go/t8RajS17By99j6nkDCUHNpn/QouXOmEjpwegiBZaEU1PeGxUm+9ZRG6PtmZafjM PNbw0Mm7XmRI0NR47+/w32qkCrbDyMM2XLNYfTwZI8nnznIxTOqscYYKH6UaF/jF2PEe 3Z0XtkSJx3bP4SMGKQnAkr8vqcJLsIODgjszIOBpqZV2q/lh2RAClw8l+LzqbjQ0ZZnZ 7TMI4vsEhZW5M1/Jf/t+E9qLx+cLAHug7ztPSD6Um6HneSdMRGyVGBvcuxPVzke/xMDy IPrCwrf2lWMu3RtDsKxnr82I/uQIzAYWZF7a5ZA3UZGO/uwsTIMEUmlfqMB+lrwWOk5a rYVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=KLSUgMn8z8HS4y/cukG+SgOuvLLwHPQH27GL6WIk32I=; b=k566SI3wwcsklwkRTikskIj3sECx1YH0f3iMdrJ6npu/5T1tpWaaWh0aFx38PEkcCG NwW+2eQj/YSJjRcemLOcEzA1X8IU9REVqx7bU/mE/YgH/iHcqarSnhAhA5Ck6yIVIgHK 3xGaY3oY903HklC9E0xv8E6X67MkoFVh2Jyl7rhEYXOtS9GJzodQ/2amvJep3GgV5+v3 M7ckUK44D/0cNzu4coJWJrOLfJ2iCGYoSK/nOnEuRGp0xMYqR14F+Z7bMox9rUqGJFat ZdDqTBPfBHL4XtSiwslGpGMWsB9YDZOcpIZkzmSAmJP01+IMD//jowghqP1Ra8x/Rpap PTfw== X-Gm-Message-State: AOAM532bQKRnWf3V0/XrMsKJYvCvkuDbbOHCKOzHGsb9h+0FX2h7SOEe lCveo4aL5LX+QzdE8U8OXr4bfP44 X-Google-Smtp-Source: ABdhPJxWvkwmuoqyRA0855EZkzqYXeAjyIPllAr9yL5XsvZ9u0misUFmsEydLef0++iCAumqJXRzRg== X-Received: by 2002:a1c:c2c5:: with SMTP id s188mr122949wmf.18.1591028099721; Mon, 01 Jun 2020 09:14:59 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org, Yoshinori Sato Subject: [PATCH 11/12] BootLinuxConsoleTest: Test the RX GDB simulator Date: Mon, 1 Jun 2020 18:14:40 +0200 Message-Id: <20200601161441.8086-12-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200601161441.8086-1-f4bug@amsat.org> References: <20200601161441.8086-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Add two tests for the rx-gdbsim machine, based on the recommended test setup from Yoshinori Sato: https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg03586.html - U-Boot prompt - Linux kernel with Sash shell These are very quick tests: $ avocado run -t arch:rx tests/acceptance/machine_rx_gdbsim.py JOB ID : 84a6ef01c0b87975ecbfcb31a920afd735753ace JOB LOG : /home/phil/avocado/job-results/job-2019-05-24T05.02-84a6ef0/= job.log (1/2) tests/acceptance/machine_rx_gdbsim.py:RxVirtMachine.test_uboot: PA= SS (0.11 s) (2/2) tests/acceptance/machine_rx_gdbsim.py:RxVirtMachine.test_linux_sas= h: PASS (0.45 s) RESULTS : PASS 2 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | = CANCEL 0 Tests can also be run with: $ avocado --show=3Dconsole run -t arch:rx tests/acceptance/machine_rx_gdb= sim.py console: U-Boot 2016.05-rc3-23705-ga1ef3c71cb-dirty (Feb 05 2019 - 21:56:= 06 +0900) console: Linux version 4.19.0+ (yo-satoh@yo-satoh-debian) (gcc version 9.= 0.0 20181105 (experimental) (GCC)) #137 Wed Feb 20 23:20:02 JST 2019 console: Built 1 zonelists, mobility grouping on. Total pages: 8128 ... console: SuperH (H)SCI(F) driver initialized console: 88240.serial: ttySC0 at MMIO 0x88240 (irq =3D 215, base_baud =3D= 0) is a sci console: console [ttySC0] enabled console: 88248.serial: ttySC1 at MMIO 0x88248 (irq =3D 219, base_baud =3D= 0) is a sci Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Yoshinori Sato Message-Id: <20200224141923.82118-22-ysato@users.sourceforge.jp> [PMD: Replace obsolete set_machine() by machine tag, and rename as gdbsim] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- tests/acceptance/machine_rx_gdbsim.py | 68 +++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 tests/acceptance/machine_rx_gdbsim.py diff --git a/tests/acceptance/machine_rx_gdbsim.py b/tests/acceptance/machi= ne_rx_gdbsim.py new file mode 100644 index 0000000000..a44f2c87da --- /dev/null +++ b/tests/acceptance/machine_rx_gdbsim.py @@ -0,0 +1,68 @@ +# Functional test that boots a Linux kernel and checks the console +# +# Copyright (c) 2018 Red Hat, Inc. +# +# Author: +# Cleber Rosa +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +from avocado_qemu import Test +from avocado_qemu import exec_command_and_wait_for_pattern +from avocado_qemu import wait_for_console_pattern +from avocado.utils import archive + + +class RxGdbSimMachine(Test): + + timeout =3D 30 + KERNEL_COMMON_COMMAND_LINE =3D 'printk.time=3D0 ' + + def test_uboot(self): + """ + U-Boot and checks that the console is operational. + + :avocado: tags=3Darch:rx + :avocado: tags=3Dmachine:gdbsim-r5f562n8 + :avocado: tags=3Dendian:little + """ + uboot_url =3D ('https://acc.dl.osdn.jp/users/23/23888/u-boot.bin.g= z') + uboot_hash =3D '9b78dbd43b40b2526848c0b1ce9de02c24f4dcdb' + uboot_path =3D self.fetch_asset(uboot_url, asset_hash=3Duboot_hash) + uboot_path =3D archive.uncompress(uboot_path, self.workdir) + + self.vm.set_console() + self.vm.add_args('-bios', uboot_path, + '-no-reboot') + self.vm.launch() + uboot_version =3D 'U-Boot 2016.05-rc3-23705-ga1ef3c71cb-dirty' + wait_for_console_pattern(self, uboot_version) + gcc_version =3D 'rx-unknown-linux-gcc (GCC) 9.0.0 20181105 (experi= mental)' + # FIXME limit baudrate on chardev, else we type too fast + #exec_command_and_wait_for_pattern(self, 'version', gcc_version) + + def test_linux_sash(self): + """ + Boots a Linux kernel and checks that the console is operational. + + :avocado: tags=3Darch:rx + :avocado: tags=3Dmachine:gdbsim-r5f562n7 + :avocado: tags=3Dendian:little + """ + dtb_url =3D ('https://acc.dl.osdn.jp/users/23/23887/rx-qemu.dtb') + dtb_hash =3D '7b4e4e2c71905da44e86ce47adee2210b026ac18' + dtb_path =3D self.fetch_asset(dtb_url, asset_hash=3Ddtb_hash) + kernel_url =3D ('http://acc.dl.osdn.jp/users/23/23845/zImage') + kernel_hash =3D '39a81067f8d72faad90866ddfefa19165d68fc99' + kernel_path =3D self.fetch_asset(kernel_url, asset_hash=3Dkernel_h= ash) + + self.vm.set_console() + kernel_command_line =3D self.KERNEL_COMMON_COMMAND_LINE + 'earlyco= n' + self.vm.add_args('-kernel', kernel_path, + '-dtb', dtb_path, + '-no-reboot') + self.vm.launch() + wait_for_console_pattern(self, 'Sash command shell (version 1.1.1)= ', + failure_message=3D'Kernel panic - not syn= cing') + exec_command_and_wait_for_pattern(self, 'printenv', 'TERM=3Dlinux') --=20 2.21.3 From nobody Fri May 17 01:43:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1591028734; cv=none; d=zohomail.com; s=zohoarc; b=JN8H0QhT4ptLojEBCL5rbg8j4Hazat2E3Y4vY6HGdluCstGQh2n+a1MzbWBM4KkDEntU4NKJM78KyZeoUSMylhqJPMXXKcPTGKk9eKfvDt7a7Sdk8SjkgLaWTcoCXJ36DI/szlikyfRz9CCcp3g2xYgNujz6kFNBUC39UDh2tjo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591028734; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=amxg9X1rCo75sQHICXUZgtnGOFtg3lKKCE8gKrKVo5Q=; b=bguLRc8cJagIJNX6VQOavbUJg6/ggMTwpDtoH1ASoQMpJyZJ08E1lqZ7Qj5CFo+BuWZelJpRVqXcMXFC6vo7hpjEW1B0J4p0z1yLl4Xxt2CNlBoNl2cTf01vNn1ncx/OeeXtjBbHZbZ6dV8rP/e0lhaIR3VCsnvFW7nwRCfIO78= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591028734941183.89809381661405; Mon, 1 Jun 2020 09:25:34 -0700 (PDT) Received: from localhost ([::1]:54666 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jfnFl-00015Z-M7 for importer@patchew.org; Mon, 01 Jun 2020 12:25:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50962) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jfn5c-0005YM-Dg for qemu-devel@nongnu.org; Mon, 01 Jun 2020 12:15:05 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:37403) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jfn5a-0001Xs-Dj for qemu-devel@nongnu.org; Mon, 01 Jun 2020 12:15:02 -0400 Received: by mail-wr1-x441.google.com with SMTP id x13so423424wrv.4 for ; Mon, 01 Jun 2020 09:15:01 -0700 (PDT) Received: from localhost.localdomain (43.red-83-51-162.dynamicip.rima-tde.net. [83.51.162.43]) by smtp.gmail.com with ESMTPSA id a6sm21309896wrn.38.2020.06.01.09.14.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2020 09:15:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=amxg9X1rCo75sQHICXUZgtnGOFtg3lKKCE8gKrKVo5Q=; b=jtfozgZ3SO4DbUM0iYv2+yW8MkqW1ekPKT/P8TscU3xnMRGt1Adkn1KEwLOTiDXnP1 Msg4ccPFrTpYLs1lvpzo2lM/nCdVD5zM4AK9I/HFxepU49JKB/1SC2HtAkKB7AUhwSXs CSJPT7AESvMEcpP/c7nOFtudLRwp5yRk7V2v8vCxp3S0MJEIXkQ6OzloSqdc4XZaZdYB /6pDeUCDOXt1/puvOIl5T7e3tW19pSkMyoXRLmwcGwNmvHXBjBJL7IL07iAivXngWViX gIqLNioADjIbUGmQcMAmbQDqedcnui6IByAK3U9oWmBGQi70hoHqBqDQKpMrueGuaLKH 9jLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=amxg9X1rCo75sQHICXUZgtnGOFtg3lKKCE8gKrKVo5Q=; b=lMfSsiVsU5xMwGJ3ozLMG7K45gVsQBj934ItK0t/T+t7C1weezkBr0BfF4ldlCbqQi B1izt6suHw/sHFlBgqE8pbC3hacdXrVddQVvdRvi34zL8g8BrW5cGzzTPqW9MjaXJloe 8YVK6NO/wIqbfumXR+dECkkmrLfA2/sk/46D6BA0Hkp8m0rYUN/lG6zGG/OfYQ8yt2e9 7qUk+Ut9aby84SPF6j/6zBb9qnckPXTNIrnBxvW15rGK7FVJI6DsBTXaLVr3ChDiKHSl xnd+un28tE+rTSxpBX7nYT/cdvC/x3Sr0pu7/dOzupem2gkhP/9dGVe9gYYmQrCACZzo Kngw== X-Gm-Message-State: AOAM53284G5VVkRkQ8LxAL4n28WNBkv7bdVCq0D9OjLjovon7Sh0wA4i b+v2mmOsXyaWeaML1poBZyU= X-Google-Smtp-Source: ABdhPJz/1mJM1P5xIYlynP6s4CwbZEOwkoUpdvQ9HU9Gwy65h+qnVd90oXSL97e+q3HJOxMBhLq+FQ== X-Received: by 2002:a05:6000:1184:: with SMTP id g4mr21301500wrx.46.1591028101076; Mon, 01 Jun 2020 09:15:01 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org, Yoshinori Sato Subject: [PATCH 12/12] docs: Document the RX target Date: Mon, 1 Jun 2020 18:14:41 +0200 Message-Id: <20200601161441.8086-13-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200601161441.8086-1-f4bug@amsat.org> References: <20200601161441.8086-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato Add rx-virt target specification document. Signed-off-by: Yoshinori Sato Message-Id: <20200308130637.37651-1-ysato@users.sourceforge.jp> [PMD: Rename as gdbsim, use machine argument] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- docs/system/target-rx.rst | 36 ++++++++++++++++++++++++++++++++++++ docs/system/targets.rst | 1 + 2 files changed, 37 insertions(+) create mode 100644 docs/system/target-rx.rst diff --git a/docs/system/target-rx.rst b/docs/system/target-rx.rst new file mode 100644 index 0000000000..4a20a89a06 --- /dev/null +++ b/docs/system/target-rx.rst @@ -0,0 +1,36 @@ +.. _RX-System-emulator: + +RX System emulator +-------------------- + +Use the executable ``qemu-system-rx`` to simulate RX target (GDB simulator= ). +This target emulated following devices. + +- R5F562N8 MCU + + - On-chip memory (ROM 512KB, RAM 96KB) + - Interrupt Control Unit (ICUa) + - 8Bit Timer x 1CH (TMR0,1) + - Compare Match Timer x 2CH (CMT0,1) + - Serial Communication Interface x 1CH (SCI0) + +- External memory 16MByte + +Example of ``qemu-system-rx`` usage for RX is shown below: + +Download ```` from +https://osdn.net/users/ysato/pf/qemu/dl/u-boot.bin.gz + +Start emulation of rx-virt:: + qemu-system-rx -M gdbsim-r5f562n8 -bios + +Download ``kernel_image_file`` from +https://osdn.net/users/ysato/pf/qemu/dl/zImage + +Download ``device_tree_blob`` from +https://osdn.net/users/ysato/pf/qemu/dl/rx-virt.dtb + +Start emulation of rx-virt:: + qemu-system-rx -M gdbsim-r5f562n8 \ + -kernel -dtb \ + -append "earlycon" diff --git a/docs/system/targets.rst b/docs/system/targets.rst index 0d8f91580a..99435a3eba 100644 --- a/docs/system/targets.rst +++ b/docs/system/targets.rst @@ -18,3 +18,4 @@ Contents: target-m68k target-xtensa target-s390x + target-rx --=20 2.21.3