From nobody Thu May 16 08:27:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1590793667; cv=none; d=zohomail.com; s=zohoarc; b=CB21wXaTdXGoznfMyjffE8uj7Q8xN+xCth7aIK/nMuba6iuP7olxcUWnau/CamTOrLxujSUrtsf99Pc3VbpzJTYHNRqe4A+uTAYagrA6dD1xedEnQo0Ziufwj7XLcLAB7R5G3cwKtvPe89bPnbhoYlI3dirCudNvV9njsJSs5KI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1590793667; h=Content-Type:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=r71n/dkRSMvACFGFh3Zt7P6/yNHA//JSl11m0H1OSxw=; b=ksQSyedcxKVF2lAo0ipH9goosSyZM4tk2e1AyuyVdOoN6lUula/G0T77V4RTd3zZa4ISR4V9TIslvQsLRbgDM+mXGk/4aUIoK+aB6ACI6JK/C6uelRup/PEOfv0oRXk0gHTFAF6sREwM2M0Jassfzwn/Q9cYGSLD7+70aKxDxSU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1590793666981668.4309939877284; Fri, 29 May 2020 16:07:46 -0700 (PDT) Received: from localhost ([::1]:57016 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jeo6L-00046H-RH for importer@patchew.org; Fri, 29 May 2020 19:07:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jeo5i-0003a1-Jj for qemu-devel@nongnu.org; Fri, 29 May 2020 19:07:06 -0400 Received: from os.inf.tu-dresden.de ([2002:8d4c:3001:48::99]:36514) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jeo5h-0002vZ-HC for qemu-devel@nongnu.org; Fri, 29 May 2020 19:07:06 -0400 Received: from erwin.inf.tu-dresden.de ([141.76.48.80] helo=os.inf.tu-dresden.de) by os.inf.tu-dresden.de with esmtps (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.93.0.3) id 1jeo5b-0005VE-PY; Sat, 30 May 2020 01:06:59 +0200 Date: Sat, 30 May 2020 01:06:53 +0200 From: Adam Lackorzynski To: qemu-devel@nongnu.org, Peter Maydell Subject: [PATCH] target/arm: Init GIC CPU IF regs for A15/A7 Message-ID: <20200529230653.GD776951@os.inf.tu-dresden.de> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.14.0 (2020-05-02) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2002:8d4c:3001:48::99; envelope-from=adam@l4re.org; helo=os.inf.tu-dresden.de X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Initialize the CPU interface registers also for Cortex-A15 and Cortex-A7 CPU models, in the same way as done for 64bit CPU models. This fixes usage of GICv3 in virtualization contexts in 32bit configurations. Signed-off-by: Adam Lackorzynski --- target/arm/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 32bec156f2..f525d45f6a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1972,6 +1972,9 @@ static void cortex_a7_initfn(Object *obj) cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ } =20 @@ -2014,6 +2017,9 @@ static void cortex_a15_initfn(Object *obj) cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } =20 --=20 2.27.0.rc2