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charset="utf-8" We extend CLINT emulation to allow multiple instances of CLINT in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from CLINT emulation. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- hw/riscv/sifive_clint.c | 20 ++++++++++++-------- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c | 6 +++--- hw/riscv/virt.c | 2 +- include/hw/riscv/sifive_clint.h | 7 ++++--- 6 files changed, 22 insertions(+), 17 deletions(-) diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index e933d35092..7d713fd743 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -78,7 +78,7 @@ static uint64_t sifive_clint_read(void *opaque, hwaddr ad= dr, unsigned size) SiFiveCLINTState *clint =3D opaque; if (addr >=3D clint->sip_base && addr < clint->sip_base + (clint->num_harts << 2)) { - size_t hartid =3D (addr - clint->sip_base) >> 2; + size_t hartid =3D clint->hartid_base + ((addr - clint->sip_base) >= > 2); CPUState *cpu =3D qemu_get_cpu(hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { @@ -91,7 +91,8 @@ static uint64_t sifive_clint_read(void *opaque, hwaddr ad= dr, unsigned size) } } else if (addr >=3D clint->timecmp_base && addr < clint->timecmp_base + (clint->num_harts << 3)) { - size_t hartid =3D (addr - clint->timecmp_base) >> 3; + size_t hartid =3D clint->hartid_base + + ((addr - clint->timecmp_base) >> 3); CPUState *cpu =3D qemu_get_cpu(hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { @@ -128,7 +129,7 @@ static void sifive_clint_write(void *opaque, hwaddr add= r, uint64_t value, =20 if (addr >=3D clint->sip_base && addr < clint->sip_base + (clint->num_harts << 2)) { - size_t hartid =3D (addr - clint->sip_base) >> 2; + size_t hartid =3D clint->hartid_base + ((addr - clint->sip_base) >= > 2); CPUState *cpu =3D qemu_get_cpu(hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { @@ -141,7 +142,8 @@ static void sifive_clint_write(void *opaque, hwaddr add= r, uint64_t value, return; } else if (addr >=3D clint->timecmp_base && addr < clint->timecmp_base + (clint->num_harts << 3)) { - size_t hartid =3D (addr - clint->timecmp_base) >> 3; + size_t hartid =3D clint->hartid_base + + ((addr - clint->timecmp_base) >> 3); CPUState *cpu =3D qemu_get_cpu(hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { @@ -185,6 +187,7 @@ static const MemoryRegionOps sifive_clint_ops =3D { }; =20 static Property sifive_clint_properties[] =3D { + DEFINE_PROP_UINT32("hartid-base", SiFiveCLINTState, hartid_base, 0), DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0), DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0), DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0), @@ -226,13 +229,13 @@ type_init(sifive_clint_register_types) /* * Create CLINT device. */ -DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_ha= rts, - uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base, - bool provide_rdtime) +DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, + uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base, + uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime) { int i; for (i =3D 0; i < num_harts; i++) { - CPUState *cpu =3D qemu_get_cpu(i); + CPUState *cpu =3D qemu_get_cpu(hartid_base + i); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { continue; @@ -246,6 +249,7 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr si= ze, uint32_t num_harts, } =20 DeviceState *dev =3D qdev_create(NULL, TYPE_SIFIVE_CLINT); + qdev_prop_set_uint32(dev, "hartid-base", hartid_base); qdev_prop_set_uint32(dev, "num-harts", num_harts); qdev_prop_set_uint32(dev, "sip-base", sip_base); qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index b53109521e..1c3b37d0ba 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -163,7 +163,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev= , Error **errp) SIFIVE_E_PLIC_CONTEXT_STRIDE, memmap[SIFIVE_E_PLIC].size); sifive_clint_create(memmap[SIFIVE_E_CLINT].base, - memmap[SIFIVE_E_CLINT].size, ms->smp.cpus, + memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); create_unimplemented_device("riscv.sifive.e.aon", memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 4299bdf480..c193761916 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -602,7 +602,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev= , Error **errp) sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ= )); sifive_clint_create(memmap[SIFIVE_U_CLINT].base, - memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, + memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); =20 object_property_set_bool(OBJECT(&s->prci), true, "realized", &err); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index d0c4843712..d5e0103d89 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -253,7 +253,7 @@ static void spike_board_init(MachineState *machine) =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, - smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + 0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BAS= E, false); } =20 @@ -343,7 +343,7 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, - smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + 0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BAS= E, false); } =20 @@ -452,7 +452,7 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, - smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + 0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BAS= E, false); =20 g_free(config_string); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c695a44979..51afe7e23b 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -595,7 +595,7 @@ static void riscv_virt_board_init(MachineState *machine) VIRT_PLIC_CONTEXT_STRIDE, memmap[VIRT_PLIC].size); sifive_clint_create(memmap[VIRT_CLINT].base, - memmap[VIRT_CLINT].size, smp_cpus, + memmap[VIRT_CLINT].size, 0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true); sifive_test_create(memmap[VIRT_TEST].base); =20 diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clin= t.h index 4a720bfece..9f5fb3d31d 100644 --- a/include/hw/riscv/sifive_clint.h +++ b/include/hw/riscv/sifive_clint.h @@ -33,6 +33,7 @@ typedef struct SiFiveCLINTState { =20 /*< public >*/ MemoryRegion mmio; + uint32_t hartid_base; uint32_t num_harts; uint32_t sip_base; uint32_t timecmp_base; @@ -40,9 +41,9 @@ typedef struct SiFiveCLINTState { uint32_t aperture_size; } SiFiveCLINTState; =20 -DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_ha= rts, - uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base, - bool provide_rdtime); +DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, + uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base, + uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime); =20 enum { SIFIVE_SIP_BASE =3D 0x0, --=20 2.25.1 From nobody Sat Nov 15 03:36:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" We extend RISC-V spike machine to allow creating a multi-socket machine. Each RISC-V spike machine socket is a set of HARTs and a CLINT instance. Other peripherals are shared between all RISC-V spike machine sockets. We also update RISC-V spike machine device tree to treat each socket as a NUMA node. By default, multi-socket support is disabled for RISC-V spike machine. To enable multi-socket support, users can pass "multi-socket=3Don" option in machine name. The number of sockets in RISC-V spike machine can be specified using the "sockets=3D" sub-option of QEMU "-smp" command-line option. Currently, we only allow creating upto maximum 4 sockets but this limit can be changed in future. Signed-off-by: Anup Patel --- hw/riscv/spike.c | 269 ++++++++++++++++++++++++++------------- include/hw/riscv/spike.h | 13 +- 2 files changed, 195 insertions(+), 87 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index d5e0103d89..b60350e912 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -64,9 +64,11 @@ static void create_fdt(SpikeState *s, const struct Memma= pEntry *memmap, uint64_t mem_size, const char *cmdline) { void *fdt; - int cpu; - uint32_t *cells; - char *nodename; + int cpu, socket; + uint32_t *clint_cells; + unsigned long clint_addr; + uint32_t cpu_phandle, intc_phandle, phandle =3D 1; + char *name, *clint_name, *clust_name, *core_name, *cpu_name, *intc_nam= e; =20 fdt =3D s->fdt =3D create_device_tree(&s->fdt_size); if (!fdt) { @@ -88,68 +90,87 @@ static void create_fdt(SpikeState *s, const struct Memm= apEntry *memmap, qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); =20 - nodename =3D g_strdup_printf("/memory@%lx", - (long)memmap[SPIKE_DRAM].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "reg", + name =3D g_strdup_printf("/memory@%lx", (long)memmap[SPIKE_DRAM].base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_cells(fdt, name, "reg", memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base, mem_size >> 32, mem_size); - qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); - g_free(nodename); + qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); + g_free(name); =20 qemu_fdt_add_subnode(fdt, "/cpus"); qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", SIFIVE_CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); =20 - for (cpu =3D s->soc.num_harts - 1; cpu >=3D 0; cpu--) { - nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); - char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); - char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); - qemu_fdt_add_subnode(fdt, nodename); + for (socket =3D (s->num_socs - 1); socket >=3D 0; socket--) { + clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); + qemu_fdt_add_subnode(fdt, clust_name); + + clint_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 4); + + for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { + cpu_phandle =3D phandle++; + + cpu_name =3D g_strdup_printf("/cpus/cpu@%d", + s->soc[socket].hartid_base + cpu); + qemu_fdt_add_subnode(fdt, cpu_name); #if defined(TARGET_RISCV32) - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32= "); #else - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48= "); #endif - qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); - qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); - qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); - qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); - qemu_fdt_add_subnode(fdt, intc); - qemu_fdt_setprop_cell(fdt, intc, "phandle", 1); - qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); - qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); - g_free(isa); - g_free(intc); - g_free(nodename); - } + name =3D riscv_isa_string(&s->soc[socket].harts[cpu]); + qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); + g_free(name); + qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); + qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); + qemu_fdt_setprop_cell(fdt, cpu_name, "reg", + s->soc[socket].hartid_base + cpu); + qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); + qemu_fdt_setprop_cell(fdt, cpu_name, "numa-node-id", socket); + qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); + + intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_n= ame); + qemu_fdt_add_subnode(fdt, intc_name); + intc_phandle =3D phandle++; + qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); + qemu_fdt_setprop_string(fdt, intc_name, "compatible", + "riscv,cpu-intc"); + qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL,= 0); + qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); + + clint_cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); + clint_cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); + clint_cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); + clint_cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); + + core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); + qemu_fdt_add_subnode(fdt, core_name); + qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); + + g_free(core_name); + g_free(intc_name); + g_free(cpu_name); + } =20 - cells =3D g_new0(uint32_t, s->soc.num_harts * 4); - for (cpu =3D 0; cpu < s->soc.num_harts; cpu++) { - nodename =3D - g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); - uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); - cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); - cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); - cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); - g_free(nodename); + clint_addr =3D memmap[SPIKE_CLINT].base + + (memmap[SPIKE_CLINT].size * socket); + clint_name =3D g_strdup_printf("/soc/clint@%lx", clint_addr); + qemu_fdt_add_subnode(fdt, clint_name); + qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clin= t0"); + qemu_fdt_setprop_cells(fdt, clint_name, "reg", + 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); + qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", + clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); + qemu_fdt_setprop_cell(fdt, clint_name, "numa-node-id", socket); + + g_free(clint_name); + g_free(clint_cells); + g_free(clust_name); } - nodename =3D g_strdup_printf("/soc/clint@%lx", - (long)memmap[SPIKE_CLINT].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SPIKE_CLINT].base, - 0x0, memmap[SPIKE_CLINT].size); - qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.num_harts * sizeof(uint32_t) * 4); - g_free(cells); - g_free(nodename); =20 if (cmdline) { qemu_fdt_add_subnode(fdt, "/chosen"); @@ -160,23 +181,50 @@ static void create_fdt(SpikeState *s, const struct Me= mmapEntry *memmap, static void spike_board_init(MachineState *machine) { const struct MemmapEntry *memmap =3D spike_memmap; - - SpikeState *s =3D g_new0(SpikeState, 1); + SpikeState *s =3D SPIKE_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); int i; + char *soc_name; unsigned int smp_cpus =3D machine->smp.cpus; + unsigned int base_hartid, cpus_per_socket; =20 - /* Initialize SOC */ - object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc= ), - TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", - &error_abort); - object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", - &error_abort); - object_property_set_bool(OBJECT(&s->soc), true, "realized", - &error_abort); + /* Figure-out number of sockets */ + s->num_socs =3D (s->multi_socket) ? machine->smp.sockets : 1; + + /* Limit the number of sockets */ + if (SPIKE_SOCKETS_MAX < s->num_socs) { + s->num_socs =3D SPIKE_SOCKETS_MAX; + } + + /* Initialize socket */ + for (i =3D 0; i < s->num_socs; i++) { + base_hartid =3D i * (smp_cpus / s->num_socs); + if (i =3D=3D (s->num_socs - 1)) { + cpus_per_socket =3D smp_cpus - base_hartid; + } else { + cpus_per_socket =3D smp_cpus / s->num_socs; + } + soc_name =3D g_strdup_printf("soc%d", i); + object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], + sizeof(s->soc[i]), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); + g_free(soc_name); + object_property_set_str(OBJECT(&s->soc[i]), + machine->cpu_type, "cpu-type", &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), + base_hartid, "hartid-base", &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), + cpus_per_socket, "num-harts", &error_abort); + object_property_set_bool(OBJECT(&s->soc[i]), + true, "realized", &error_abort); + + /* Core Local Interruptor (timer and IPI) for each socket */ + sifive_clint_create( + memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, + memmap[SPIKE_CLINT].size, base_hartid, cpus_per_socket, + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); + } =20 /* register system main memory (actual RAM) */ memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", @@ -249,12 +297,8 @@ static void spike_board_init(MachineState *machine) &address_space_memory); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(= 0)); - - /* Core Local Interruptor (timer and IPI) */ - sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, - 0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BAS= E, - false); + htif_mm_init(system_memory, mask_rom, + &s->soc[0].harts[0].env, serial_hd(0)); } =20 static void spike_v1_10_0_board_init(MachineState *machine) @@ -268,6 +312,8 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) int i; unsigned int smp_cpus =3D machine->smp.cpus; =20 + s->num_socs =3D 1; + if (!qtest_enabled()) { info_report("The Spike v1.10.0 machine has been deprecated. " "Please use the generic spike machine and specify the = ISA " @@ -275,13 +321,14 @@ static void spike_v1_10_0_board_init(MachineState *ma= chine) } =20 /* Initialize SOC */ - object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc= ), + object_initialize_child(OBJECT(machine), "soc", + &s->soc[0], sizeof(s->soc[0]), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type", + object_property_set_str(OBJECT(&s->soc[0]), SPIKE_V1_10_0_CPU, "cpu-ty= pe", &error_abort); - object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", + object_property_set_int(OBJECT(&s->soc[0]), smp_cpus, "num-harts", &error_abort); - object_property_set_bool(OBJECT(&s->soc), true, "realized", + object_property_set_bool(OBJECT(&s->soc[0]), true, "realized", &error_abort); =20 /* register system main memory (actual RAM) */ @@ -339,7 +386,8 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) &address_space_memory); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(= 0)); + htif_mm_init(system_memory, mask_rom, + &s->soc[0].harts[0].env, serial_hd(0)); =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, @@ -358,6 +406,8 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) int i; unsigned int smp_cpus =3D machine->smp.cpus; =20 + s->num_socs =3D 1; + if (!qtest_enabled()) { info_report("The Spike v1.09.1 machine has been deprecated. " "Please use the generic spike machine and specify the = ISA " @@ -365,13 +415,14 @@ static void spike_v1_09_1_board_init(MachineState *ma= chine) } =20 /* Initialize SOC */ - object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc= ), + object_initialize_child(OBJECT(machine), "soc", + &s->soc[0], sizeof(s->soc[0]), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type", + object_property_set_str(OBJECT(&s->soc[0]), SPIKE_V1_09_1_CPU, "cpu-ty= pe", &error_abort); - object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", + object_property_set_int(OBJECT(&s->soc[0]), smp_cpus, "num-harts", &error_abort); - object_property_set_bool(OBJECT(&s->soc), true, "realized", + object_property_set_bool(OBJECT(&s->soc[0]), true, "realized", &error_abort); =20 /* register system main memory (actual RAM) */ @@ -425,7 +476,7 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) "};\n"; =20 /* build config string with supplied memory size */ - char *isa =3D riscv_isa_string(&s->soc.harts[0]); + char *isa =3D riscv_isa_string(&s->soc[0].harts[0]); char *config_string =3D g_strdup_printf(config_string_tmpl, (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE, (uint64_t)memmap[SPIKE_DRAM].base, @@ -448,7 +499,8 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) &address_space_memory); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(= 0)); + htif_mm_init(system_memory, mask_rom, + &s->soc[0].harts[0].env, serial_hd(0)); =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, @@ -472,15 +524,62 @@ static void spike_v1_10_0_machine_init(MachineClass *= mc) mc->max_cpus =3D 1; } =20 -static void spike_machine_init(MachineClass *mc) +DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) +DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) + +static bool spike_get_multi_socket(Object *obj, Error **errp) +{ + SpikeState *s =3D SPIKE_MACHINE(obj); + + return s->multi_socket; +} + +static void spike_set_multi_socket(Object *obj, bool value, Error **errp) +{ + SpikeState *s =3D SPIKE_MACHINE(obj); + + s->multi_socket =3D value; +} + +static void spike_machine_instance_init(Object *obj) { - mc->desc =3D "RISC-V Spike Board"; + SpikeState *s =3D SPIKE_MACHINE(obj); + + /* + * Multi-socket is disabled by default so users have to + * explicitly enable it from command-line. + */ + s->multi_socket =3D false; + object_property_add_bool(obj, "multi-socket", + spike_get_multi_socket, + spike_set_multi_socket); + object_property_set_description(obj, "multi-socket", + "Set on/off to enable/disable the " + "multi-socket support"); +} + +static void spike_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "RISC-V Spike board"; mc->init =3D spike_board_init; - mc->max_cpus =3D 8; + mc->max_cpus =3D SPIKE_CPUS_MAX; mc->is_default =3D true; mc->default_cpu_type =3D SPIKE_V1_10_0_CPU; } =20 -DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) -DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) -DEFINE_MACHINE("spike", spike_machine_init) +static const TypeInfo spike_machine_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("spike"), + .parent =3D TYPE_MACHINE, + .class_init =3D spike_machine_class_init, + .instance_init =3D spike_machine_instance_init, + .instance_size =3D sizeof(SpikeState), +}; + +static void spike_machine_init_register_types(void) +{ + type_register_static(&spike_machine_typeinfo); +} + +type_init(spike_machine_init_register_types) diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index dc770421bc..f0ab381a88 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -22,12 +22,21 @@ #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" =20 +#define SPIKE_CPUS_MAX 8 +#define SPIKE_SOCKETS_MAX 4 + +#define TYPE_SPIKE_MACHINE MACHINE_TYPE_NAME("spike") +#define SPIKE_MACHINE(obj) \ + OBJECT_CHECK(SpikeState, (obj), TYPE_SPIKE_MACHINE) + typedef struct { /*< private >*/ - SysBusDevice parent_obj; + MachineState parent; =20 /*< public >*/ - RISCVHartArrayState soc; + bool multi_socket; + unsigned int num_socs; + RISCVHartArrayState soc[SPIKE_SOCKETS_MAX]; void *fdt; int fdt_size; } SpikeState; --=20 2.25.1 From nobody Sat Nov 15 03:36:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@wdc.com; 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charset="utf-8" We extend PLIC emulation to allow multiple instances of PLIC in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from PLIC emulation. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_plic.c | 24 +++++++++++++----------- hw/riscv/sifive_u.c | 2 +- hw/riscv/virt.c | 2 +- include/hw/riscv/sifive_plic.h | 12 +++++++----- 5 files changed, 23 insertions(+), 19 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 1c3b37d0ba..bd122e71ae 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -152,7 +152,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev= , Error **errp) =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[SIFIVE_E_PLIC].base, - (char *)SIFIVE_E_PLIC_HART_CONFIG, + (char *)SIFIVE_E_PLIC_HART_CONFIG, 0, SIFIVE_E_PLIC_NUM_SOURCES, SIFIVE_E_PLIC_NUM_PRIORITIES, SIFIVE_E_PLIC_PRIORITY_BASE, diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index c1e04cbb98..f88bb48053 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -352,6 +352,7 @@ static const MemoryRegionOps sifive_plic_ops =3D { =20 static Property sifive_plic_properties[] =3D { DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config), + DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0), DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0), DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, = 0), DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0), @@ -400,10 +401,12 @@ static void parse_hart_config(SiFivePLICState *plic) } hartid++; =20 - /* store hart/mode combinations */ plic->num_addrs =3D addrid; + plic->num_harts =3D hartid; + + /* store hart/mode combinations */ plic->addr_config =3D g_new(PLICAddr, plic->num_addrs); - addrid =3D 0, hartid =3D 0; + addrid =3D 0, hartid =3D plic->hartid_base; p =3D plic->hart_config; while ((c =3D *p++)) { if (c =3D=3D ',') { @@ -429,8 +432,6 @@ static void sifive_plic_irq_request(void *opaque, int i= rq, int level) =20 static void sifive_plic_realize(DeviceState *dev, Error **errp) { - MachineState *ms =3D MACHINE(qdev_get_machine()); - unsigned int smp_cpus =3D ms->smp.cpus; SiFivePLICState *plic =3D SIFIVE_PLIC(dev); int i; =20 @@ -451,8 +452,8 @@ static void sifive_plic_realize(DeviceState *dev, Error= **errp) * lost a interrupt in the case a PLIC is attached. The SEIP bit must = be * hardware controlled when a PLIC is attached. */ - for (i =3D 0; i < smp_cpus; i++) { - RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(i)); + for (i =3D 0; i < plic->num_harts; i++) { + RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(plic->hartid_base + i)); if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) { error_report("SEIP already claimed"); exit(1); @@ -488,16 +489,17 @@ type_init(sifive_plic_register_types) * Create PLIC device. */ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, - uint32_t num_sources, uint32_t num_priorities, - uint32_t priority_base, uint32_t pending_base, - uint32_t enable_base, uint32_t enable_stride, - uint32_t context_base, uint32_t context_stride, - uint32_t aperture_size) + uint32_t hartid_base, uint32_t num_sources, + uint32_t num_priorities, uint32_t priority_base, + uint32_t pending_base, uint32_t enable_base, + uint32_t enable_stride, uint32_t context_base, + uint32_t context_stride, uint32_t aperture_size) { DeviceState *dev =3D qdev_create(NULL, TYPE_SIFIVE_PLIC); assert(enable_stride =3D=3D (enable_stride & -enable_stride)); assert(context_stride =3D=3D (context_stride & -context_stride)); qdev_prop_set_string(dev, "hart-config", hart_config); + qdev_prop_set_uint32(dev, "hartid-base", hartid_base); qdev_prop_set_uint32(dev, "num-sources", num_sources); qdev_prop_set_uint32(dev, "num-priorities", num_priorities); qdev_prop_set_uint32(dev, "priority-base", priority_base); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index c193761916..53e48e2ff5 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -586,7 +586,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev= , Error **errp) =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[SIFIVE_U_PLIC].base, - plic_hart_config, + plic_hart_config, 0, SIFIVE_U_PLIC_NUM_SOURCES, SIFIVE_U_PLIC_NUM_PRIORITIES, SIFIVE_U_PLIC_PRIORITY_BASE, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 51afe7e23b..421815081d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -584,7 +584,7 @@ static void riscv_virt_board_init(MachineState *machine) =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[VIRT_PLIC].base, - plic_hart_config, + plic_hart_config, 0, VIRT_PLIC_NUM_SOURCES, VIRT_PLIC_NUM_PRIORITIES, VIRT_PLIC_PRIORITY_BASE, diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h index 4421e81249..ace76d0f1b 100644 --- a/include/hw/riscv/sifive_plic.h +++ b/include/hw/riscv/sifive_plic.h @@ -48,6 +48,7 @@ typedef struct SiFivePLICState { /*< public >*/ MemoryRegion mmio; uint32_t num_addrs; + uint32_t num_harts; uint32_t bitfield_words; PLICAddr *addr_config; uint32_t *source_priority; @@ -58,6 +59,7 @@ typedef struct SiFivePLICState { =20 /* config */ char *hart_config; + uint32_t hartid_base; uint32_t num_sources; uint32_t num_priorities; uint32_t priority_base; @@ -70,10 +72,10 @@ typedef struct SiFivePLICState { } SiFivePLICState; =20 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, - uint32_t num_sources, uint32_t num_priorities, - uint32_t priority_base, uint32_t pending_base, - uint32_t enable_base, uint32_t enable_stride, - uint32_t context_base, uint32_t context_stride, - uint32_t aperture_size); + uint32_t hartid_base, uint32_t num_sources, + uint32_t num_priorities, uint32_t priority_base, + uint32_t pending_base, uint32_t enable_base, + uint32_t enable_stride, uint32_t context_base, + uint32_t context_stride, uint32_t aperture_size); =20 #endif --=20 2.25.1 From nobody Sat Nov 15 03:36:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" We extend RISC-V virt machine to allow creating a multi-socket machine. Each RISC-V virt machine socket is a set of HARTs, a CLINT instance, and a PLIC instance. Other peripherals are shared between all RISC-V virt machine sockets. We also update RISC-V virt machine device tree to treat each socket as a NUMA node. By default, multi-socket support is disabled for RISC-V virt machine. To enable multi-socket support, users can pass "multi-socket=3Don" option in machine name. The number of sockets in RISC-V virt machine can be specified using the "sockets=3D" sub-option of QEMU "-smp" command-line option. Currently, we only allow creating upto maximum 4 sockets but this limit can be changed in future. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- hw/riscv/virt.c | 523 +++++++++++++++++++++++----------------- include/hw/riscv/virt.h | 11 +- 2 files changed, 311 insertions(+), 223 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 421815081d..40a6185b1c 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -60,7 +60,7 @@ static const struct MemmapEntry { [VIRT_TEST] =3D { 0x100000, 0x1000 }, [VIRT_RTC] =3D { 0x101000, 0x1000 }, [VIRT_CLINT] =3D { 0x2000000, 0x10000 }, - [VIRT_PLIC] =3D { 0xc000000, 0x4000000 }, + [VIRT_PLIC] =3D { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2)= }, [VIRT_UART0] =3D { 0x10000000, 0x100 }, [VIRT_VIRTIO] =3D { 0x10001000, 0x1000 }, [VIRT_FLASH] =3D { 0x20000000, 0x4000000 }, @@ -182,10 +182,15 @@ static void create_fdt(RISCVVirtState *s, const struc= t MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { void *fdt; - int cpu, i; - uint32_t *cells; - char *nodename; - uint32_t plic_phandle, test_phandle, phandle =3D 1; + int i, cpu, socket; + uint32_t *clint_cells, *plic_cells; + unsigned long clint_addr, plic_addr; + uint32_t plic_phandle[VIRT_SOCKETS_MAX]; + uint32_t cpu_phandle, intc_phandle, test_phandle; + uint32_t phandle =3D 1, plic_mmio_phandle =3D 1; + uint32_t plic_pcie_phandle =3D 1, plic_virtio_phandle =3D 1; + char *name, *cpu_name, *core_name, *intc_name; + char *clint_name, *plic_name, *clust_name; hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; =20 @@ -206,231 +211,235 @@ static void create_fdt(RISCVVirtState *s, const str= uct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); =20 - nodename =3D g_strdup_printf("/memory@%lx", + name =3D g_strdup_printf("/memory@%lx", (long)memmap[VIRT_DRAM].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "reg", + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_cells(fdt, name, "reg", memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base, mem_size >> 32, mem_size); - qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); - g_free(nodename); + qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); + g_free(name); =20 qemu_fdt_add_subnode(fdt, "/cpus"); qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", SIFIVE_CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); + + for (socket =3D (s->num_socs - 1); socket >=3D 0; socket--) { + clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); + qemu_fdt_add_subnode(fdt, clust_name); + + plic_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 4); + clint_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 4); =20 - for (cpu =3D s->soc.num_harts - 1; cpu >=3D 0; cpu--) { - int cpu_phandle =3D phandle++; - int intc_phandle; - nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); - char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); - char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); - qemu_fdt_add_subnode(fdt, nodename); + for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { + cpu_phandle =3D phandle++; + + cpu_name =3D g_strdup_printf("/cpus/cpu@%d", + s->soc[socket].hartid_base + cpu); + qemu_fdt_add_subnode(fdt, cpu_name); #if defined(TARGET_RISCV32) - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32= "); #else - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48= "); #endif - qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); - qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); - qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); - qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle); - intc_phandle =3D phandle++; - qemu_fdt_add_subnode(fdt, intc); - qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle); - qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); - qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); - g_free(isa); - g_free(intc); - g_free(nodename); - } + name =3D riscv_isa_string(&s->soc[socket].harts[cpu]); + qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); + g_free(name); + qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); + qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); + qemu_fdt_setprop_cell(fdt, cpu_name, "reg", + s->soc[socket].hartid_base + cpu); + qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); + qemu_fdt_setprop_cell(fdt, cpu_name, "numa-node-id", socket); + qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); + + intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_n= ame); + qemu_fdt_add_subnode(fdt, intc_name); + intc_phandle =3D phandle++; + qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); + qemu_fdt_setprop_string(fdt, intc_name, "compatible", + "riscv,cpu-intc"); + qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL,= 0); + qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); + + clint_cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); + clint_cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); + clint_cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); + clint_cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); + + plic_cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); + plic_cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_EXT); + plic_cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); + plic_cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_S_EXT); + + core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); + qemu_fdt_add_subnode(fdt, core_name); + qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); + + g_free(core_name); + g_free(intc_name); + g_free(cpu_name); + } =20 - /* Add cpu-topology node */ - qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); - qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0"); - for (cpu =3D s->soc.num_harts - 1; cpu >=3D 0; cpu--) { - char *core_nodename =3D g_strdup_printf("/cpus/cpu-map/cluster0/co= re%d", - cpu); - char *cpu_nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); - uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, cpu_nodename); - qemu_fdt_add_subnode(fdt, core_nodename); - qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle); - g_free(core_nodename); - g_free(cpu_nodename); + clint_addr =3D memmap[VIRT_CLINT].base + + (memmap[VIRT_CLINT].size * socket); + clint_name =3D g_strdup_printf("/soc/clint@%lx", clint_addr); + qemu_fdt_add_subnode(fdt, clint_name); + qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clin= t0"); + qemu_fdt_setprop_cells(fdt, clint_name, "reg", + 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); + qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", + clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); + qemu_fdt_setprop_cell(fdt, clint_name, "numa-node-id", socket); + g_free(clint_name); + + plic_phandle[socket] =3D phandle++; + plic_addr =3D memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * s= ocket); + plic_name =3D g_strdup_printf("/soc/plic@%lx", plic_addr); + qemu_fdt_add_subnode(fdt, plic_name); + qemu_fdt_setprop_cell(fdt, plic_name, + "#address-cells", FDT_PLIC_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, plic_name, + "#interrupt-cells", FDT_PLIC_INT_CELLS); + qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0= "); + qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", + plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); + qemu_fdt_setprop_cells(fdt, plic_name, "reg", + 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); + qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); + qemu_fdt_setprop_cell(fdt, plic_name, "numa-node-id", socket); + qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[sock= et]); + g_free(plic_name); + + g_free(clint_cells); + g_free(plic_cells); + g_free(clust_name); } =20 - cells =3D g_new0(uint32_t, s->soc.num_harts * 4); - for (cpu =3D 0; cpu < s->soc.num_harts; cpu++) { - nodename =3D - g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); - uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); - cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); - cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); - cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); - g_free(nodename); - } - nodename =3D g_strdup_printf("/soc/clint@%lx", - (long)memmap[VIRT_CLINT].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[VIRT_CLINT].base, - 0x0, memmap[VIRT_CLINT].size); - qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.num_harts * sizeof(uint32_t) * 4); - g_free(cells); - g_free(nodename); - - plic_phandle =3D phandle++; - cells =3D g_new0(uint32_t, s->soc.num_harts * 4); - for (cpu =3D 0; cpu < s->soc.num_harts; cpu++) { - nodename =3D - g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); - uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); - cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_EXT); - cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); - cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_S_EXT); - g_free(nodename); + for (socket =3D 0; socket < s->num_socs; socket++) { + if (socket =3D=3D 0) { + plic_mmio_phandle =3D plic_phandle[socket]; + plic_virtio_phandle =3D plic_phandle[socket]; + plic_pcie_phandle =3D plic_phandle[socket]; + } + if (socket =3D=3D 1) { + plic_virtio_phandle =3D plic_phandle[socket]; + plic_pcie_phandle =3D plic_phandle[socket]; + } + if (socket =3D=3D 2) { + plic_pcie_phandle =3D plic_phandle[socket]; + } } - nodename =3D g_strdup_printf("/soc/interrupt-controller@%lx", - (long)memmap[VIRT_PLIC].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", - FDT_PLIC_ADDR_CELLS); - qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", - FDT_PLIC_INT_CELLS); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); - qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.num_harts * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[VIRT_PLIC].base, - 0x0, memmap[VIRT_PLIC].size); - qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); - plic_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - g_free(cells); - g_free(nodename); =20 for (i =3D 0; i < VIRTIO_COUNT; i++) { - nodename =3D g_strdup_printf("/virtio_mmio@%lx", + name =3D g_strdup_printf("/soc/virtio_mmio@%lx", (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size= )); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio"= ); - qemu_fdt_setprop_cells(fdt, nodename, "reg", + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); + qemu_fdt_setprop_cells(fdt, name, "reg", 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 0x0, memmap[VIRT_VIRTIO].size); - qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phan= dle); - qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i); - g_free(nodename); + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", + plic_virtio_phandle); + qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); + g_free(name); } =20 - nodename =3D g_strdup_printf("/soc/pci@%lx", + name =3D g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", - FDT_PCI_ADDR_CELLS); - qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", - FDT_PCI_INT_CELLS); - qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2); - qemu_fdt_setprop_string(fdt, nodename, "compatible", - "pci-host-ecam-generic"); - qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); - qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0); - qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0, - memmap[VIRT_PCIE_ECAM].size / - PCIE_MMCFG_SIZE_MIN - 1); - qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); - qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM]= .base, - 0, memmap[VIRT_PCIE_ECAM].size); - qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges", + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS= ); + qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); + qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generi= c"); + qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); + qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, + memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); + qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); + qemu_fdt_setprop_cells(fdt, name, "reg", 0, + memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); + qemu_fdt_setprop_sized_cells(fdt, name, "ranges", 1, FDT_PCI_RANGE_IOPORT, 2, 0, 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 1, FDT_PCI_RANGE_MMIO, 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size); - create_pcie_irq_map(fdt, nodename, plic_phandle); - g_free(nodename); + create_pcie_irq_map(fdt, name, plic_pcie_phandle); + g_free(name); =20 test_phandle =3D phandle++; - nodename =3D g_strdup_printf("/test@%lx", + name =3D g_strdup_printf("/soc/test@%lx", (long)memmap[VIRT_TEST].base); - qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_add_subnode(fdt, name); { const char compat[] =3D "sifive,test1\0sifive,test0\0syscon"; - qemu_fdt_setprop(fdt, nodename, "compatible", compat, sizeof(compa= t)); + qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat)); } - qemu_fdt_setprop_cells(fdt, nodename, "reg", + qemu_fdt_setprop_cells(fdt, name, "reg", 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_phandle); - test_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - - nodename =3D g_strdup_printf("/reboot"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot"); - qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET); - g_free(nodename); - - nodename =3D g_strdup_printf("/poweroff"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff"= ); - qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS); - g_free(nodename); - - nodename =3D g_strdup_printf("/uart@%lx", - (long)memmap[VIRT_UART0].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a"); - qemu_fdt_setprop_cells(fdt, nodename, "reg", + qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); + test_phandle =3D qemu_fdt_get_phandle(fdt, name); + g_free(name); + + name =3D g_strdup_printf("/soc/reboot"); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); + qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); + g_free(name); + + name =3D g_strdup_printf("/soc/poweroff"); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); + qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); + g_free(name); + + name =3D g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].bas= e); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); + qemu_fdt_setprop_cells(fdt, name, "reg", 0x0, memmap[VIRT_UART0].base, 0x0, memmap[VIRT_UART0].size); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ); + qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle= ); + qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ); =20 qemu_fdt_add_subnode(fdt, "/chosen"); - qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); + qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); if (cmdline) { qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } - g_free(nodename); - - nodename =3D g_strdup_printf("/rtc@%lx", - (long)memmap[VIRT_RTC].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", - "google,goldfish-rtc"); - qemu_fdt_setprop_cells(fdt, nodename, "reg", + g_free(name); + + name =3D g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"= ); + qemu_fdt_setprop_cells(fdt, name, "reg", 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); - qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "interrupts", RTC_IRQ); - g_free(nodename); - - nodename =3D g_strdup_printf("/flash@%" PRIx64, flashbase); - qemu_fdt_add_subnode(s->fdt, nodename); - qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash"); - qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle= ); + qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); + g_free(name); + + name =3D g_strdup_printf("/soc/flash@%" PRIx64, flashbase); + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop_string(s->fdt, name, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 2, flashbase, 2, flashsize, 2, flashbase + flashsize, 2, flashsize); - qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4); - g_free(nodename); + qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4); + g_free(name); } =20 - static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, hwaddr ecam_base, hwaddr ecam_si= ze, hwaddr mmio_base, hwaddr mmio_si= ze, @@ -478,21 +487,92 @@ static void riscv_virt_board_init(MachineState *machi= ne) MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); - char *plic_hart_config; + char *plic_hart_config, *soc_name; size_t plic_hart_config_len; target_ulong start_addr =3D memmap[VIRT_DRAM].base; - int i; + int i, j; unsigned int smp_cpus =3D machine->smp.cpus; + unsigned int base_hartid, cpus_per_socket; + DeviceState *mmio_plic, *virtio_plic, *pcie_plic; + + /* Figure-out number of sockets */ + s->num_socs =3D (s->multi_socket) ? machine->smp.sockets : 1; + + /* Limit the number of sockets */ + if (VIRT_SOCKETS_MAX < s->num_socs) { + s->num_socs =3D VIRT_SOCKETS_MAX; + } =20 /* Initialize SOC */ - object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc= ), - TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", - &error_abort); - object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", - &error_abort); - object_property_set_bool(OBJECT(&s->soc), true, "realized", - &error_abort); + mmio_plic =3D virtio_plic =3D pcie_plic =3D NULL; + for (i =3D 0; i < s->num_socs; i++) { + base_hartid =3D i * (smp_cpus / s->num_socs); + if (i =3D=3D (s->num_socs - 1)) { + cpus_per_socket =3D smp_cpus - base_hartid; + } else { + cpus_per_socket =3D smp_cpus / s->num_socs; + } + soc_name =3D g_strdup_printf("soc%d", i); + object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], + sizeof(s->soc[i]), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); + g_free(soc_name); + object_property_set_str(OBJECT(&s->soc[i]), + machine->cpu_type, "cpu-type", &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), + base_hartid, "hartid-base", &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), + cpus_per_socket, "num-harts", &error_abort); + object_property_set_bool(OBJECT(&s->soc[i]), + true, "realized", &error_abort); + + /* Per-socket CLINT */ + sifive_clint_create( + memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, + memmap[VIRT_CLINT].size, base_hartid, cpus_per_socket, + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true); + + /* Per-socket PLIC hart topology configuration string */ + plic_hart_config_len =3D + (strlen(VIRT_PLIC_HART_CONFIG) + 1) * cpus_per_socket; + plic_hart_config =3D g_malloc0(plic_hart_config_len); + for (j =3D 0; j < cpus_per_socket; j++) { + if (j !=3D 0) { + strncat(plic_hart_config, ",", plic_hart_config_len); + } + strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, + plic_hart_config_len); + plic_hart_config_len -=3D (strlen(VIRT_PLIC_HART_CONFIG) + 1); + } + + /* Per-socket PLIC */ + s->plic[i] =3D sifive_plic_create( + memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, + plic_hart_config, base_hartid, + VIRT_PLIC_NUM_SOURCES, + VIRT_PLIC_NUM_PRIORITIES, + VIRT_PLIC_PRIORITY_BASE, + VIRT_PLIC_PENDING_BASE, + VIRT_PLIC_ENABLE_BASE, + VIRT_PLIC_ENABLE_STRIDE, + VIRT_PLIC_CONTEXT_BASE, + VIRT_PLIC_CONTEXT_STRIDE, + memmap[VIRT_PLIC].size); + g_free(plic_hart_config); + + /* Try to use different PLIC instance based device type */ + if (i =3D=3D 0) { + mmio_plic =3D s->plic[i]; + virtio_plic =3D s->plic[i]; + pcie_plic =3D s->plic[i]; + } + if (i =3D=3D 1) { + virtio_plic =3D s->plic[i]; + pcie_plic =3D s->plic[i]; + } + if (i =3D=3D 2) { + pcie_plic =3D s->plic[i]; + } + } =20 /* register system main memory (actual RAM) */ memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", @@ -571,38 +651,14 @@ static void riscv_virt_board_init(MachineState *machi= ne) memmap[VIRT_MROM].base + sizeof(reset_vec), &address_space_memory); =20 - /* create PLIC hart topology configuration string */ - plic_hart_config_len =3D (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpu= s; - plic_hart_config =3D g_malloc0(plic_hart_config_len); - for (i =3D 0; i < smp_cpus; i++) { - if (i !=3D 0) { - strncat(plic_hart_config, ",", plic_hart_config_len); - } - strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_= len); - plic_hart_config_len -=3D (strlen(VIRT_PLIC_HART_CONFIG) + 1); - } - - /* MMIO */ - s->plic =3D sifive_plic_create(memmap[VIRT_PLIC].base, - plic_hart_config, 0, - VIRT_PLIC_NUM_SOURCES, - VIRT_PLIC_NUM_PRIORITIES, - VIRT_PLIC_PRIORITY_BASE, - VIRT_PLIC_PENDING_BASE, - VIRT_PLIC_ENABLE_BASE, - VIRT_PLIC_ENABLE_STRIDE, - VIRT_PLIC_CONTEXT_BASE, - VIRT_PLIC_CONTEXT_STRIDE, - memmap[VIRT_PLIC].size); - sifive_clint_create(memmap[VIRT_CLINT].base, - memmap[VIRT_CLINT].size, 0, smp_cpus, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true); + /* SiFive Test MMIO device */ sifive_test_create(memmap[VIRT_TEST].base); =20 + /* VirtIO MMIO devices */ for (i =3D 0; i < VIRTIO_COUNT; i++) { sysbus_create_simple("virtio-mmio", memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, - qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i)); + qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); } =20 gpex_pcie_init(system_memory, @@ -611,14 +667,14 @@ static void riscv_virt_board_init(MachineState *machi= ne) memmap[VIRT_PCIE_MMIO].base, memmap[VIRT_PCIE_MMIO].size, memmap[VIRT_PCIE_PIO].base, - DEVICE(s->plic), true); + DEVICE(pcie_plic), true); =20 serial_mm_init(system_memory, memmap[VIRT_UART0].base, - 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193, + 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN); =20 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, - qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ)); + qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); =20 virt_flash_create(s); =20 @@ -628,12 +684,37 @@ static void riscv_virt_board_init(MachineState *machi= ne) drive_get(IF_PFLASH, 0, i)); } virt_flash_map(s, system_memory); +} =20 - g_free(plic_hart_config); +static bool riscv_virt_get_multi_socket(Object *obj, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + return s->multi_socket; +} + +static void riscv_virt_set_multi_socket(Object *obj, bool value, Error **e= rrp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + s->multi_socket =3D value; } =20 static void riscv_virt_machine_instance_init(Object *obj) { + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + /* + * Multi-socket is disabled by default so users have to + * explicitly enable it from command-line. + */ + s->multi_socket =3D false; + object_property_add_bool(obj, "multi-socket", + riscv_virt_get_multi_socket, + riscv_virt_set_multi_socket); + object_property_set_description(obj, "multi-socket", + "Set on/off to enable/disable the " + "multi-socket support"); } =20 static void riscv_virt_machine_class_init(ObjectClass *oc, void *data) @@ -642,7 +723,7 @@ static void riscv_virt_machine_class_init(ObjectClass *= oc, void *data) =20 mc->desc =3D "RISC-V VirtIO board"; mc->init =3D riscv_virt_board_init; - mc->max_cpus =3D 8; + mc->max_cpus =3D VIRT_CPUS_MAX; mc->default_cpu_type =3D VIRT_CPU; mc->pci_allow_0_address =3D true; } diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index e69355efaf..e5fe10ad48 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -23,6 +23,9 @@ #include "hw/sysbus.h" #include "hw/block/flash.h" =20 +#define VIRT_CPUS_MAX 8 +#define VIRT_SOCKETS_MAX 4 + #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") #define RISCV_VIRT_MACHINE(obj) \ OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE) @@ -32,8 +35,10 @@ typedef struct { MachineState parent; =20 /*< public >*/ - RISCVHartArrayState soc; - DeviceState *plic; + bool multi_socket; + unsigned int num_socs; + RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; + DeviceState *plic[VIRT_SOCKETS_MAX]; PFlashCFI01 *flash[2]; =20 void *fdt; @@ -74,6 +79,8 @@ enum { #define VIRT_PLIC_ENABLE_STRIDE 0x80 #define VIRT_PLIC_CONTEXT_BASE 0x200000 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 +#define VIRT_PLIC_SIZE(__num_context) \ + (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) =20 #define FDT_PCI_ADDR_CELLS 3 #define FDT_PCI_INT_CELLS 1 --=20 2.25.1