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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y8sm1100561wmc.37.2020.05.22.07.55.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2020 07:55:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h8C+sirQq0LQGA2KO8QQ/JH+LvpC1dkrtfwj+w2/EgY=; b=BMxNxv7A9Vy7Urv6dZp/woQVK04umX7oDDjfeYhqcy67rZ++ALmevlO5+6JJP+5kZT beqoF2xNbJP4sbrlvx9jNVHFzoRhtkE098KOnNytmV7cEoG7HIdbME0aiite15o7PRB9 dth4pZeAbgR9OZA7WtIhDx6fbBBdIRLzo+8nMekIi9E25MUIyR0vkTOkS1GWUGASb/0M RtHkJPPip2cv1hHlASCKxsthMVjKhcWK01YvaKErKPl4yyuNZrnS1/Sb2hSboQqGixX2 lQGIRSdKs3Txq6UQICSWKSrK6OrPTnBQljoeAx5QKMv+zy+jSkqih9pmEvXEqJjT6O6j EJjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h8C+sirQq0LQGA2KO8QQ/JH+LvpC1dkrtfwj+w2/EgY=; b=BbTdfsQCWZLguobtRRkOwI3/Ym9PAAQm2UsIDCdAvN6GK3Lw3NqvIHFuoyoZaNZx5d fjS5Hxr+YUjioo6TybDckIrSTFcC2T9Ni+qIKrsOOWVx3qmA6AjVM+NVIWNOQuwuSkiJ zexVbybbKxp7NUQ3sVrZWawVuWvfUSSn65SIIEdb2Rpkw4syAyIufN1Leza4TQAZNOQ4 RyAMUPGHQuRe+QXe73W/RTY1i+HZzpSTGQrQkzy+pcWggCakjct4d5Zim0TLts3uyI1g NiT6rkdrwjo46zRwwZk83fM+KaCwrNsnZQAVhu2F0GWiCxTYq895rBSKUDHGa3kSQ9IX dJaA== X-Gm-Message-State: AOAM532CJ7HRHE0fWuiDnZLNg2ujK4iwt6E1IKKQqlY7uQhWjm1f7ypT L6sxkG86asxPY8s0fm+XPxcFuAmQ24e81Q== X-Google-Smtp-Source: ABdhPJxS2MrbO7Ed8twQngqrzxSCCOlSVsqYd7Ca7qYonI6WUgVxEKo4ufj0ySD3fSPrqI/sFkIUQw== X-Received: by 2002:a05:600c:34c:: with SMTP id u12mr13543022wmd.4.1590159323776; Fri, 22 May 2020 07:55:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 1/9] target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree Date: Fri, 22 May 2020 15:55:12 +0100 Message-Id: <20200522145520.6778-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200522145520.6778-1-peter.maydell@linaro.org> References: <20200522145520.6778-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VSHL and VSLI insns from the Neon 2-registers-and-a-shift group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 25 ++++++++++++++++++++++ target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 18 +++++++--------- 3 files changed, 71 insertions(+), 10 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 8beb1db768b..4bd305e7ea0 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -199,3 +199,28 @@ VRECPS_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ...= 1 .... @3same_fp VRSQRTS_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp VMAXNM_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp + +###################################################################### +# 2-reg-and-shift grouping: +# 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4 +###################################################################### +&2reg_shift vm vd q shift size + +@2reg_shl_d .... ... . . . shift:6 .... .... 1 q:1 . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D3 +@2reg_shl_s .... ... . . . 1 shift:5 .... .... 0 q:1 . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D2 +@2reg_shl_h .... ... . . . 01 shift:4 .... .... 0 q:1 . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D1 +@2reg_shl_b .... ... . . . 001 shift:3 .... .... 0 q:1 . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D0 + +VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d +VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s +VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h +VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b + +VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d +VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s +VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h +VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 3fe65a0b080..305213fe6d9 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1310,3 +1310,41 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3s= ame *a, VFPGen3OpSPFn *fn) DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds) DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs) DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins) + +static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn = *fn) +{ + /* Handle a 2-reg-shift insn which can be vectorized. */ + int vec_size =3D a->q ? 16 : 8; + int rd_ofs =3D neon_reg_offset(a->vd, 0); + int rm_ofs =3D neon_reg_offset(a->vm, 0); + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fn(a->size, rd_ofs, rm_ofs, a->shift, vec_size, vec_size); + return true; +} + +#define DO_2SH(INSN, FUNC) \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_vector_2sh(s, a, FUNC); \ + } \ + +DO_2SH(VSHL, tcg_gen_gvec_shli) +DO_2SH(VSLI, gen_gvec_sli) diff --git a/target/arm/translate.c b/target/arm/translate.c index c8296116d4b..d0a4a08f6d9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5294,6 +5294,14 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) if ((insn & 0x00380080) !=3D 0) { /* Two registers and shift. */ op =3D (insn >> 8) & 0xf; + + switch (op) { + case 5: /* VSHL, VSLI */ + return 1; /* handled by decodetree */ + default: + break; + } + if (insn & (1 << 7)) { /* 64-bit shift. */ if (op > 7) { @@ -5387,16 +5395,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) gen_gvec_sri(size, rd_ofs, rm_ofs, shift, vec_size, vec_size); return 0; - - case 5: /* VSHL, VSLI */ - if (u) { /* VSLI */ - gen_gvec_sli(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } else { /* VSHL */ - tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; } =20 if (size =3D=3D 3) { --=20 2.20.1 From nobody Fri Mar 29 13:38:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1590159392; cv=none; d=zohomail.com; s=zohoarc; b=mrdlmI4HGsqU06ubBilSPMB1D5w8stuKXaIG8yq0PRgxwRM8XOwlaFtvEE+FzXYI8s9YciFnpLccy2urk96mGQizYuFON24oNzLjIPnmsERMJlyus9O3taF6Vr6RezN01ARHxaG+5CgIl3eEsCEkb6nPd42KiItzaGiFKTfckZk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1590159392; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CjpjYzXmKdCTpUVLpvmz68eKh1IW7CdbECnjZ+5X3Wo=; b=MNbPYyK+5WxZrPZ+LkFxz4pADY/gMTdW9NQ4w3ohHF4HqFaSGn540GGW0iLvorSQm8gASFleE/Y8Em6EyWf7tcNSrWIxokAsJhw1IoU+afhCvhloYhuc3kKfL40TpvW+Oduxy0EwlwEm1rAU11Vt/9BOE+VQkSWUtohRVWbKt2A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1590159392493628.4947990401037; Fri, 22 May 2020 07:56:32 -0700 (PDT) Received: from localhost ([::1]:46910 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jc967-0003nF-6W for importer@patchew.org; Fri, 22 May 2020 10:56:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59962) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jc955-0001uX-Dz for qemu-devel@nongnu.org; Fri, 22 May 2020 10:55:27 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:35180) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jc954-0006R5-Ad for qemu-devel@nongnu.org; Fri, 22 May 2020 10:55:27 -0400 Received: by mail-wm1-x341.google.com with SMTP id n5so10106220wmd.0 for ; Fri, 22 May 2020 07:55:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y8sm1100561wmc.37.2020.05.22.07.55.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2020 07:55:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CjpjYzXmKdCTpUVLpvmz68eKh1IW7CdbECnjZ+5X3Wo=; b=uKBhHXlLm1iB5TA2KhlizWoN/3upLqc4aWP72TSLn4IH8IhLLZgzDJR1Uo3dKgP11C nXCWlDixG3oklk/sLryWj+wv1vCtPqfW4D6sqhWDLYLoGmYYm0f7LhoI8DiH8AOec8Qb LdCw3j5ivCVpohkVhF3XTr9ThW5VK8pLBytYtYevMYlpXIePeTJ8RETOnTHFlr2F7tRN 5rSXG+HOub0usT9dDuSklSd3be2fMZrflCs4IDHQ+0NJfQa5CTfoLmztgQt0d0zETWII pW+pLp3jfD2VY3AVaD0rxrr/KM/B9Z/fxspaHm+jBTrvRLGeu/XOTpQ58ZWL5nq/Nwmp PfMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CjpjYzXmKdCTpUVLpvmz68eKh1IW7CdbECnjZ+5X3Wo=; b=HA3+X0oluefu/xk39cl10fAIxB9fOhiocuSKh3amHQvZMfx2QgTRpuGaizrPMqDls3 qKM3A2Hsk5oi6LynWOJK7STkRKvB4ihshTe3mQwyOHytAmviGvZVzP33AnrGd8JGk8OY fags0dM4ekh9CDslV6iGhnzT94gHusZUzn3EWbQEv8WRquWI2JDP/29KCRWY1EgM1aFz dhrwUMHYDoxESjFKq8NSpAeUPLx9QIB3xZvwdleJ7IRY537ANksX9AKKRvDVnqRHYApW eK79lyJyYOc+yk/AaZTXqK2sn5YdgqHPj9TAa/hnoUl1PkYdlEKFJOeoq1unJ8O6LgL8 TXog== X-Gm-Message-State: AOAM531FWb63zoSkkxNOkvQDlZO92gcPpIqXhI9NxQwPBwjpZbHPNv/h kcuUIXYOCBcz3mRQeooq0Duu7g== X-Google-Smtp-Source: ABdhPJyfmxs6izlBPG7AoYie7JpKrTWxBbIEZVQhzbMO+IGEqcMOPV1t5EuJv7MNvfD8tUoPPzswtQ== X-Received: by 2002:a1c:1b4d:: with SMTP id b74mr13585234wmb.123.1590159324939; Fri, 22 May 2020 07:55:24 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 2/9] target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree Date: Fri, 22 May 2020 15:55:13 +0100 Message-Id: <20200522145520.6778-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200522145520.6778-1-peter.maydell@linaro.org> References: <20200522145520.6778-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VSHR 2-reg-shift insns to decodetree. Note that unlike the legacy decoder, we present the right shift amount to the trans_ function as a positive integer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 25 ++++++++++++++++++++ target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 21 +---------------- 3 files changed, 67 insertions(+), 20 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 4bd305e7ea0..cd3a8f936d7 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -206,6 +206,21 @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ...= 1 .... @3same_fp ###################################################################### &2reg_shift vm vd q shift size =20 +# Right shifts are encoded as N - shift, where N is the element size in bi= ts. +%neon_rshift_i6 16:6 !function=3Drsub_64 +%neon_rshift_i5 16:5 !function=3Drsub_32 +%neon_rshift_i4 16:4 !function=3Drsub_16 +%neon_rshift_i3 16:3 !function=3Drsub_8 + +@2reg_shr_d .... ... . . . ...... .... .... 1 q:1 . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D3 shift=3D%neo= n_rshift_i6 +@2reg_shr_s .... ... . . . 1 ..... .... .... 0 q:1 . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D2 shift=3D%neo= n_rshift_i5 +@2reg_shr_h .... ... . . . 01 .... .... .... 0 q:1 . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D1 shift=3D%neo= n_rshift_i4 +@2reg_shr_b .... ... . . . 001 ... .... .... 0 q:1 . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D0 shift=3D%neo= n_rshift_i3 + @2reg_shl_d .... ... . . . shift:6 .... .... 1 q:1 . . .... \ &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D3 @2reg_shl_s .... ... . . . 1 shift:5 .... .... 0 q:1 . . .... \ @@ -215,6 +230,16 @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ...= 1 .... @3same_fp @2reg_shl_b .... ... . . . 001 shift:3 .... .... 0 q:1 . . .... \ &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D0 =20 +VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d +VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s +VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h +VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b + +VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d +VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s +VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h +VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b + VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 305213fe6d9..0475696835f 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -31,6 +31,24 @@ static inline int plus1(DisasContext *s, int x) return x + 1; } =20 +static inline int rsub_64(DisasContext *s, int x) +{ + return 64 - x; +} + +static inline int rsub_32(DisasContext *s, int x) +{ + return 32 - x; +} +static inline int rsub_16(DisasContext *s, int x) +{ + return 16 - x; +} +static inline int rsub_8(DisasContext *s, int x) +{ + return 8 - x; +} + /* Include the generated Neon decoder */ #include "decode-neon-dp.inc.c" #include "decode-neon-ls.inc.c" @@ -1348,3 +1366,26 @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_= shift *a, GVecGen2iFn *fn) =20 DO_2SH(VSHL, tcg_gen_gvec_shli) DO_2SH(VSLI, gen_gvec_sli) + +static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a) +{ + /* Signed shift out of range results in all-sign-bits */ + a->shift =3D MIN(a->shift, (8 << a->size) - 1); + return do_vector_2sh(s, a, tcg_gen_gvec_sari); +} + +static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_of= s, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0); +} + +static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a) +{ + /* Shift out of range is architecturally valid and results in zero. */ + if (a->shift >=3D (8 << a->size)) { + return do_vector_2sh(s, a, gen_zero_rd_2sh); + } else { + return do_vector_2sh(s, a, tcg_gen_gvec_shri); + } +} diff --git a/target/arm/translate.c b/target/arm/translate.c index d0a4a08f6d9..f2ccab1b21c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5296,6 +5296,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) op =3D (insn >> 8) & 0xf; =20 switch (op) { + case 0: /* VSHR */ case 5: /* VSHL, VSLI */ return 1; /* handled by decodetree */ default: @@ -5330,26 +5331,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) } =20 switch (op) { - case 0: /* VSHR */ - /* Right shift comes here negative. */ - shift =3D -shift; - /* Shifts larger than the element size are architectur= ally - * valid. Unsigned results in all zeros; signed resul= ts - * in all sign bits. - */ - if (!u) { - tcg_gen_gvec_sari(size, rd_ofs, rm_ofs, - MIN(shift, (8 << size) - 1), - vec_size, vec_size); - } else if (shift >=3D 8 << size) { - tcg_gen_gvec_dup_imm(MO_8, rd_ofs, vec_size, - vec_size, 0); - } else { - tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; - case 1: /* VSRA */ /* Right shift comes here negative. */ shift =3D -shift; --=20 2.20.1 From nobody Fri Mar 29 13:38:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1590159406; cv=none; d=zohomail.com; s=zohoarc; b=G1eK/2VHwYgZOYJA71A0S/9yF9O/G0iQSFGxN3zzxOOzQjDo4XKwE3o4vYRFiNX9MS4mLLPXb2k616BRdpAxTxvRetPqQcLEBPaRnXqMHrx89ng8MNTmLKqW4KAOoU8V5dinxI0DqRMXkExOP9orV8pzkedLUsKmR2DX5zPoz2g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1590159406; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eoxrdN7F9Qnc+EAvbF65kivETUCxi1TfvMLy0qHgIKA=; b=Oige5sQdBZFlYSl/ANx/dpHnKfMMDsTeY/zCQP4Ax/v4V8W8Xb9SHguzEledgwe31uwzMmlpM6eFjzxv8R8YhvgJ5AnWBl+sr2O3zotCdFCLpYd3HwjgZNfYYJeocpEOA6WEhiWNZW256OTnV0D/NB8X/niTvhJBL7znSJPhScw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1590159406694123.65019319555256; Fri, 22 May 2020 07:56:46 -0700 (PDT) Received: from localhost ([::1]:48442 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jc96L-0004Nq-Cd for importer@patchew.org; Fri, 22 May 2020 10:56:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jc957-00020v-Kj for qemu-devel@nongnu.org; Fri, 22 May 2020 10:55:29 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:46130) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jc955-0006RL-Fp for qemu-devel@nongnu.org; Fri, 22 May 2020 10:55:29 -0400 Received: by mail-wr1-x443.google.com with SMTP id w7so10404296wre.13 for ; Fri, 22 May 2020 07:55:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y8sm1100561wmc.37.2020.05.22.07.55.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2020 07:55:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eoxrdN7F9Qnc+EAvbF65kivETUCxi1TfvMLy0qHgIKA=; b=WTo2Wcp8T0Y63tgXroNQW89PNa+Kc5qIsrF2A0WTb/H2Unfo9WcrL55bF2ouBH9Xhy fqj5QVsLHIke4W6uFmjWY73wisv5zOk3Hr9gnu25tq/gBto63UGAF+CHzuQ0Fv/i+a+Y Zt4EpLzJu2kAVOV/jmgLxC8EBqd1qmxNV8K/yBSuGZy/pGnZMtmHklDM5S5oyFErivYB kWVf5e6s4R6A/Af+v1BIcUjUXbtVjFACdzE+/dAEHK8FsnmDEZkCgmNSJuVbCjeLDJkK QFAKpFoR+mXlLwFjH/G0+9k3dBsK2NXcHEQjPL1g3tmOysERr5knxJqt761zZD/Yp6uP yRUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eoxrdN7F9Qnc+EAvbF65kivETUCxi1TfvMLy0qHgIKA=; b=BRbfU+P/yZeUciGFgxpODNG86Q0RvXAIstuf4PXVw/naLcfICLPvbsaULKxXwCMmmf jWOwud3l50QVlhisKKqw0Zf0hIpvqkelUTwzst5xy1LShAHiIeku3c5Uah7E/l3LXlW5 fOmD3jC+btbElOiOs0HN5ERidk0y+8ONQ25gjFzddS2AiHSxRmoSqFdKAN3Bg19h6sMj sdGifj1yuscSyZNEdLV8iAr3uzMutiX0kd0jOo0rTK+yxErDiHEdZ5og83RVHA9tR3ar ZSuQuQmn8MuPhiolmCwvycpGs3nW1PWQVEleBu2l5yRwLrDlc9+4D4ku1OYHHcbb5mNG OF/Q== X-Gm-Message-State: AOAM531y0cd+Ah7XFEaa1wdgBVfQlVEVf3AL2Cl+bW4WxJiwkIihvIcr /+SI9t6qtOuGBHeSCLqPDOz6xg== X-Google-Smtp-Source: ABdhPJxBOXXxuSioB8LjEnSg6NreCbmlk/WvFolpaaotLXwQUDhdM4J6kH6b777+9W8s9AnM+11Bcw== X-Received: by 2002:adf:a153:: with SMTP id r19mr3445221wrr.285.1590159326064; Fri, 22 May 2020 07:55:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 3/9] target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree Date: Fri, 22 May 2020 15:55:14 +0100 Message-Id: <20200522145520.6778-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200522145520.6778-1-peter.maydell@linaro.org> References: <20200522145520.6778-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree. (These are the last instructions in the group that are vectorized; the rest all require looping over each element.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 35 ++++++++++++++++++++++ target/arm/translate-neon.inc.c | 7 +++++ target/arm/translate.c | 52 +++------------------------------ 3 files changed, 46 insertions(+), 48 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index cd3a8f936d7..d99a07b16d4 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -240,6 +240,41 @@ VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . .= 1 .... @2reg_shr_s VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b =20 +VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d +VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s +VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h +VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b + +VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d +VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s +VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h +VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b + +VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d +VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s +VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h +VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b + +VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d +VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s +VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h +VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b + +VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d +VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s +VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h +VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b + +VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d +VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s +VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h +VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b + +VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_d +VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_s +VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_h +VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_b + VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 0475696835f..f4d42683aea 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1366,6 +1366,13 @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_= shift *a, GVecGen2iFn *fn) =20 DO_2SH(VSHL, tcg_gen_gvec_shli) DO_2SH(VSLI, gen_gvec_sli) +DO_2SH(VSRI, gen_gvec_sri) +DO_2SH(VSRA_S, gen_gvec_ssra) +DO_2SH(VSRA_U, gen_gvec_usra) +DO_2SH(VRSHR_S, gen_gvec_srshr) +DO_2SH(VRSHR_U, gen_gvec_urshr) +DO_2SH(VRSRA_S, gen_gvec_srsra) +DO_2SH(VRSRA_U, gen_gvec_ursra) =20 static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a) { diff --git a/target/arm/translate.c b/target/arm/translate.c index f2ccab1b21c..4a55986aad9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5297,6 +5297,10 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) =20 switch (op) { case 0: /* VSHR */ + case 1: /* VSRA */ + case 2: /* VRSHR */ + case 3: /* VRSRA */ + case 4: /* VSRI */ case 5: /* VSHL, VSLI */ return 1; /* handled by decodetree */ default: @@ -5330,54 +5334,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) shift =3D shift - (1 << (size + 3)); } =20 - switch (op) { - case 1: /* VSRA */ - /* Right shift comes here negative. */ - shift =3D -shift; - if (u) { - gen_gvec_usra(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } else { - gen_gvec_ssra(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; - - case 2: /* VRSHR */ - /* Right shift comes here negative. */ - shift =3D -shift; - if (u) { - gen_gvec_urshr(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } else { - gen_gvec_srshr(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; - - case 3: /* VRSRA */ - /* Right shift comes here negative. */ - shift =3D -shift; - if (u) { - gen_gvec_ursra(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } else { - gen_gvec_srsra(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; - - case 4: /* VSRI */ - if (!u) { - return 1; - } - /* Right shift comes here negative. */ - shift =3D -shift; - gen_gvec_sri(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - return 0; - } - if (size =3D=3D 3) { count =3D q + 1; } else { --=20 2.20.1 From nobody Fri Mar 29 13:38:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1590159496; cv=none; d=zohomail.com; s=zohoarc; b=DQWAaMyahpE/pjZrZFR2WygsBAtd2URE9pOyVbEBRlJn+E/r3NG4/AyFNfOoDVZ82ZWYDX1ewlaCprzCc8ULgnR5fojOoXnGdUIhHKcelb/DjUoVzAjqkolMDQ4Bi3t+3RK6rNy6CkNGcLTLoc+YqPu60O7M3s7+ZtKojTMhAQA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1590159496; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y8sm1100561wmc.37.2020.05.22.07.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2020 07:55:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4rtc+4OzXXy8odEDC6muCMK1fkclsdZsWvhdDDk5nks=; b=utNuzSh09XJ98KnwYjwhqFLFo7y/qYR056aCa1kHmUzEC8dGOsCAXcZZLj5YknNIL5 9LgmzRR3Xh9cmNXJL5SKtx628M1lUzJRbBqYI2akgxAuEHKY1N+6yKVmMZIPz5oSBx1c lRwtvxq6GBsW6dh5TqrPR8DumxMPzlAYX+AChrHv2iqgw50lCF+zvHVCkjqAu75J/BCx mHMOznH+SAG5ecgHtZ/2U8p0iqWBFXMEsq5TKaQMZOaqHgKlIRz0OLCPJuLj8lqOxljb pmKiWmRMnc0o+jAmxtDZ+5IfeV3787k8gWwboMKMoMAeyIwmphvn2k9A4SAmxy577dLg Yhww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4rtc+4OzXXy8odEDC6muCMK1fkclsdZsWvhdDDk5nks=; b=bS2Rzy/R9swJt78xfWVm8lJzoFnVA17fMMgaL00yrsc38qlarp8zp3LhLEVZXMdB/t f3Kvq7i+GSvuvYrib2pJiWUFkM7xA7ncftKjSTN+/1BSIyrd74uCjfIXx9D1e1nsyoHO lmTeo9704Uh4MyxgpLqQcPcFkFtGscExDUYMklbQEFDFIelKEq54lUyZDAnujtot9d5+ k7vH112TUUiExid0yyc3+lrV4VsYKM4fasiSsm6+sAi0lDf/nl4LL/5F3oMxcrNlvw3E ARZJD8fKL02y0tdz+fH9eWMxL/qtNrMcRTWJXLL3VUNFTpgOClkdE70Q/wMF7XrxPrRd s/yA== X-Gm-Message-State: AOAM533Lmph4tPp2CLpn66xENyUhGIeuLpKiXqZaeIf9qPtXkuCd6B/Z SmYmHUH2Hol4csSYlNimdazuf61a7QKzQQ== X-Google-Smtp-Source: ABdhPJxd5UBifsd195GjM2J1JdQRXAKgJJPPJtFWkar7FpHuU81rgN+xlW8vcJsiljyJfYtTf5msYg== X-Received: by 2002:a1c:7e43:: with SMTP id z64mr13194961wmc.72.1590159327615; Fri, 22 May 2020 07:55:27 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 4/9] target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree Date: Fri, 22 May 2020 15:55:15 +0100 Message-Id: <20200522145520.6778-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200522145520.6778-1-peter.maydell@linaro.org> References: <20200522145520.6778-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VQSHLU and QVSHL 2-reg-shift insns to decodetree. These are the last of the simple shift-by-immediate insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 15 +++++ target/arm/translate-neon.inc.c | 108 +++++++++++++++++++++++++++++++ target/arm/translate.c | 110 +------------------------------- 3 files changed, 126 insertions(+), 107 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index d99a07b16d4..f9183060a51 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -284,3 +284,18 @@ VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . .= 1 .... @2reg_shl_d VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b + +VQSHLU_64_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d +VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s +VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h +VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b + +VQSHL_S_64_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d +VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s +VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h +VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b + +VQSHL_U_64_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d +VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s +VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h +VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index f4d42683aea..396db55565f 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1396,3 +1396,111 @@ static bool trans_VSHR_U_2sh(DisasContext *s, arg_2= reg_shift *a) return do_vector_2sh(s, a, tcg_gen_gvec_shri); } } + +static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a, + NeonGenTwo64OpEnvFn *fn) +{ + /* + * 2-reg-and-shift operations, size =3D=3D 3 case, where the + * function needs to be passed cpu_env. + */ + TCGv_i64 constimm; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * To avoid excessive duplication of ops we implement shift + * by immediate using the variable shift operations. + */ + constimm =3D tcg_const_i64(dup_const(a->size, a->shift)); + + for (pass =3D 0; pass < a->q + 1; pass++) { + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + neon_load_reg64(tmp, a->vm + pass); + fn(tmp, cpu_env, tmp, constimm); + neon_store_reg64(tmp, a->vd + pass); + } + tcg_temp_free_i64(constimm); + return true; +} + +static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, + NeonGenTwoOpEnvFn *fn) +{ + /* + * 2-reg-and-shift operations, size < 3 case, where the + * helper needs to be passed cpu_env. + */ + TCGv_i32 constimm; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * To avoid excessive duplication of ops we implement shift + * by immediate using the variable shift operations. + */ + constimm =3D tcg_const_i32(dup_const(a->size, a->shift)); + + for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { + TCGv_i32 tmp =3D neon_load_reg(a->vm, pass); + fn(tmp, cpu_env, tmp, constimm); + neon_store_reg(a->vd, pass, tmp); + } + tcg_temp_free_i32(constimm); + return true; +} + +#define DO_2SHIFT_ENV(INSN, FUNC) \ + static bool trans_##INSN##_64_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64); \ + } \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + static NeonGenTwoOpEnvFn * const fns[] =3D { \ + gen_helper_neon_##FUNC##8, \ + gen_helper_neon_##FUNC##16, \ + gen_helper_neon_##FUNC##32, \ + }; \ + assert(a->size < ARRAY_SIZE(fns)); \ + return do_2shift_env_32(s, a, fns[a->size]); \ + } + +DO_2SHIFT_ENV(VQSHLU, qshlu_s) +DO_2SHIFT_ENV(VQSHL_U, qshl_u) +DO_2SHIFT_ENV(VQSHL_S, qshl_s) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4a55986aad9..d711d39eb9d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3011,29 +3011,6 @@ static inline void gen_neon_rsb(int size, TCGv_i32 t= 0, TCGv_i32 t1) } } =20 -#define GEN_NEON_INTEGER_OP_ENV(name) do { \ - switch ((size << 1) | u) { \ - case 0: \ - gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \ - break; \ - case 1: \ - gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \ - break; \ - case 2: \ - gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \ - break; \ - case 3: \ - gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \ - break; \ - case 4: \ - gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \ - break; \ - case 5: \ - gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \ - break; \ - default: return 1; \ - }} while (0) - static TCGv_i32 neon_load_scratch(int scratch) { TCGv_i32 tmp =3D tcg_temp_new_i32(); @@ -5252,7 +5229,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) int size; int shift; int pass; - int count; int u; int vec_size; uint32_t imm; @@ -5302,6 +5278,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case 3: /* VRSRA */ case 4: /* VSRI */ case 5: /* VSHL, VSLI */ + case 6: /* VQSHLU */ + case 7: /* VQSHL */ return 1; /* handled by decodetree */ default: break; @@ -5319,89 +5297,7 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) size--; } shift =3D (insn >> 16) & ((1 << (3 + size)) - 1); - if (op < 8) { - /* Shift by immediate: - VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */ - if (q && ((rd | rm) & 1)) { - return 1; - } - if (!u && (op =3D=3D 4 || op =3D=3D 6)) { - return 1; - } - /* Right shifts are encoded as N - shift, where N is the - element size in bits. */ - if (op <=3D 4) { - shift =3D shift - (1 << (size + 3)); - } - - if (size =3D=3D 3) { - count =3D q + 1; - } else { - count =3D q ? 4: 2; - } - - /* To avoid excessive duplication of ops we implement shift - * by immediate using the variable shift operations. - */ - imm =3D dup_const(size, shift); - - for (pass =3D 0; pass < count; pass++) { - if (size =3D=3D 3) { - neon_load_reg64(cpu_V0, rm + pass); - tcg_gen_movi_i64(cpu_V1, imm); - switch (op) { - case 6: /* VQSHLU */ - gen_helper_neon_qshlu_s64(cpu_V0, cpu_env, - cpu_V0, cpu_V1); - break; - case 7: /* VQSHL */ - if (u) { - gen_helper_neon_qshl_u64(cpu_V0, cpu_env, - cpu_V0, cpu_V1); - } else { - gen_helper_neon_qshl_s64(cpu_V0, cpu_env, - cpu_V0, cpu_V1); - } - break; - default: - g_assert_not_reached(); - } - neon_store_reg64(cpu_V0, rd + pass); - } else { /* size < 3 */ - /* Operands in T0 and T1. */ - tmp =3D neon_load_reg(rm, pass); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, imm); - switch (op) { - case 6: /* VQSHLU */ - switch (size) { - case 0: - gen_helper_neon_qshlu_s8(tmp, cpu_env, - tmp, tmp2); - break; - case 1: - gen_helper_neon_qshlu_s16(tmp, cpu_env, - tmp, tmp2); - break; - case 2: - gen_helper_neon_qshlu_s32(tmp, cpu_env, - tmp, tmp2); - break; - default: - abort(); - } - break; - case 7: /* VQSHL */ - GEN_NEON_INTEGER_OP_ENV(qshl); - break; - default: - g_assert_not_reached(); - } - tcg_temp_free_i32(tmp2); - neon_store_reg(rd, pass, tmp); - } - } /* for pass */ - } else if (op < 10) { + if (op < 10) { /* Shift by immediate and narrow: VSHRN, VRSHRN, VQSHRN, VQRSHRN. */ int input_unsigned =3D (op =3D=3D 8) ? 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y8sm1100561wmc.37.2020.05.22.07.55.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2020 07:55:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mF+Z1XhT8U/1VxQ4F6ob+fshPU7TCq1DJXBWTZ4vj/o=; b=udv+PsN8wZhW2rZkQlPACtiyJIO3eIJx3iLzcEVjDTIOvqjSCJNlC564VlDDPVUVJK vq3q/qljKEWrWtJpK6VDV07QLQonuUMA2YQ2qJ9yW7g9qeFptDs62gTyXMVl3TPHi6KP f+7qqVJU2dsrYwJKyjEBQNLf1HNyhfhPD7BbtEvwV2UMu05LuS+jtuKBPOpbutrWgw+a rFMOMJfI1bralfON9q3ewnUzwYkJ2FGrGmo1dfYpEqC5np8u6eVH5yaPiwuex5W4pZHa 5gWfUE8mSa6prl+nnwhiezeE5i+suM18Eiw0sfvJqS8GCU5Tlvbi8ZtwcbTOun3GWqol /zgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mF+Z1XhT8U/1VxQ4F6ob+fshPU7TCq1DJXBWTZ4vj/o=; b=FIY7otJTHm7ichpbsMqfo+q2MYzxOAmh37vBTC6etZXJQyQvHMNLLPSdui/gSGDA2G 66RMvbRyh2F1/xdBUD63sMFKPHPOsVXGYShVpk5aOniXZn+LgyL3f7jMKSiAnOorWzYl BN0v2UssJip/LxndTOpY3QqauYovobvDU77rVVsmR0WqoAYsPK7WC/VM2Fa+Aw/vh8Y8 5fRHdH+yrfu6BsmAD8BKmXpO1+mIB/KAtcSvsGnIZDrku/Tmz7bBav/V2kRtspA6m/Sf RiYVsSJ0uEuvXKTaGnZMQoJTIm7/1KbuMjFiO7Lxr5sZUEubygESFXXpd5Vz0ncRYxmd A58A== X-Gm-Message-State: AOAM531xBY2Ioljn0U+EB71d8nFTwEoyAtlEnFJJqmJ01PqG5+oEMz0C 1rysHtd02n39f8Rfk7azc0yHaUG1G6zX1w== X-Google-Smtp-Source: ABdhPJz1XQ8hZY4Fw+jdN83S7mZ+AufV7+XaQU3DHhr6JzfRb3vmMcn5l7oEeOaXCgqm2DiRcfB9vg== X-Received: by 2002:a1c:2bc1:: with SMTP id r184mr13793237wmr.58.1590159328692; Fri, 22 May 2020 07:55:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 5/9] target/arm: Convert Neon narrowing shifts with op==8 to decodetree Date: Fri, 22 May 2020 15:55:16 +0100 Message-Id: <20200522145520.6778-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200522145520.6778-1-peter.maydell@linaro.org> References: <20200522145520.6778-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon narrowing shifts where op=3D=3D8 to decodetree: * VSHRN * VRSHRN * VQSHRUN * VQRSHRUN Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 27 +++++ target/arm/translate-neon.inc.c | 168 ++++++++++++++++++++++++++++++++ target/arm/translate.c | 1 + 3 files changed, 196 insertions(+) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index f9183060a51..01887240b4a 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -230,6 +230,17 @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ...= 1 .... @3same_fp @2reg_shl_b .... ... . . . 001 shift:3 .... .... 0 q:1 . . .... \ &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D0 =20 +# Narrowing right shifts: here the Q bit is part of the opcode decode +@2reg_shrn_d .... ... . . . 1 ..... .... .... 0 . . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D3 q=3D0 \ + shift=3D%neon_rshift_i5 +@2reg_shrn_s .... ... . . . 01 .... .... .... 0 . . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D2 q=3D0 \ + shift=3D%neon_rshift_i4 +@2reg_shrn_h .... ... . . . 001 ... .... .... 0 . . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D1 q=3D0 \ + shift=3D%neon_rshift_i3 + VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h @@ -299,3 +310,19 @@ VQSHL_U_64_2sh 1111 001 1 1 . ...... .... 0111 . . .= 1 .... @2reg_shl_d VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b + +VSHRN_64_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d +VSHRN_32_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s +VSHRN_16_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h + +VRSHRN_64_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d +VRSHRN_32_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s +VRSHRN_16_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h + +VQSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d +VQSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s +VQSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h + +VQRSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d +VQRSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s +VQRSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 396db55565f..18ea7255e38 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1504,3 +1504,171 @@ static bool do_2shift_env_32(DisasContext *s, arg_2= reg_shift *a, DO_2SHIFT_ENV(VQSHLU, qshlu_s) DO_2SHIFT_ENV(VQSHL_U, qshl_u) DO_2SHIFT_ENV(VQSHL_S, qshl_s) + +static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, + NeonGenTwo64OpFn *shiftfn, + NeonGenNarrowEnvFn *narrowfn) +{ + /* 2-reg-and-shift narrowing-shift operations, size =3D=3D 3 case */ + TCGv_i64 constimm, rm1, rm2; + TCGv_i32 rd; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vm & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * This is always a right shift, and the shiftfn is always a + * left-shift helper, which thus needs the negated shift count. + */ + constimm =3D tcg_const_i64(-a->shift); + rm1 =3D tcg_temp_new_i64(); + rm2 =3D tcg_temp_new_i64(); + + /* Load both inputs first to avoid potential overwrite if rm =3D=3D rd= */ + neon_load_reg64(rm1, a->vm); + neon_load_reg64(rm2, a->vm + 1); + + shiftfn(rm1, rm1, constimm); + rd =3D tcg_temp_new_i32(); + narrowfn(rd, cpu_env, rm1); + neon_store_reg(a->vd, 0, rd); + + shiftfn(rm2, rm2, constimm); + rd =3D tcg_temp_new_i32(); + narrowfn(rd, cpu_env, rm2); + neon_store_reg(a->vd, 1, rd); + + tcg_temp_free_i64(rm1); + tcg_temp_free_i64(rm2); + tcg_temp_free_i64(constimm); + + return true; +} + +static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, + NeonGenTwoOpFn *shiftfn, + NeonGenNarrowEnvFn *narrowfn) +{ + /* 2-reg-and-shift narrowing-shift operations, size < 3 case */ + TCGv_i32 constimm, rm1, rm2, rm3, rm4; + TCGv_i64 rtmp; + uint32_t imm; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vm & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * This is always a right shift, and the shiftfn is always a + * left-shift helper, which thus needs the negated shift count + * duplicated into each lane of the immediate value. + */ + if (a->size =3D=3D 1) { + imm =3D (uint16_t)(-a->shift); + imm |=3D imm << 16; + } else { + /* size =3D=3D 2 */ + imm =3D -a->shift; + } + constimm =3D tcg_const_i32(imm); + + /* Load all inputs first to avoid potential overwrite */ + rm1 =3D neon_load_reg(a->vm, 0); + rm2 =3D neon_load_reg(a->vm, 1); + rm3 =3D neon_load_reg(a->vm + 1, 0); + rm4 =3D neon_load_reg(a->vm + 1, 1); + rtmp =3D tcg_temp_new_i64(); + + // todo expand out the shift-narrow and the narrow-op + shiftfn(rm1, rm1, constimm); + shiftfn(rm2, rm2, constimm); + + tcg_gen_concat_i32_i64(rtmp, rm1, rm2); + tcg_temp_free_i32(rm2); + + narrowfn(rm1, cpu_env, rtmp); + neon_store_reg(a->vd, 0, rm1); + + shiftfn(rm3, rm3, constimm); + shiftfn(rm4, rm4, constimm); + tcg_temp_free_i32(constimm); + + tcg_gen_concat_i32_i64(rtmp, rm3, rm4); + tcg_temp_free_i32(rm4); + + narrowfn(rm3, cpu_env, rtmp); + tcg_temp_free_i64(rtmp); + neon_store_reg(a->vd, 1, rm3); + return true; +} + +#define DO_2SN_64(INSN, FUNC, NARROWFUNC) \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_2shift_narrow_64(s, a, FUNC, NARROWFUNC); \ + } +#define DO_2SN_32(INSN, FUNC, NARROWFUNC) \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC); \ + } + +static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) +{ + tcg_gen_extrl_i64_i32(dest, src); +} + +static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) +{ + gen_helper_neon_narrow_u16(dest, src); +} + +static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) +{ + gen_helper_neon_narrow_u8(dest, src); +} + +DO_2SN_64(VSHRN_64, gen_ushl_i64, gen_neon_narrow_u32) +DO_2SN_32(VSHRN_32, gen_ushl_i32, gen_neon_narrow_u16) +DO_2SN_32(VSHRN_16, gen_helper_neon_shl_u16, gen_neon_narrow_u8) + +DO_2SN_64(VRSHRN_64, gen_helper_neon_rshl_u64, gen_neon_narrow_u32) +DO_2SN_32(VRSHRN_32, gen_helper_neon_rshl_u32, gen_neon_narrow_u16) +DO_2SN_32(VRSHRN_16, gen_helper_neon_rshl_u16, gen_neon_narrow_u8) + +DO_2SN_64(VQSHRUN_64, gen_sshl_i64, gen_helper_neon_unarrow_sat32) +DO_2SN_32(VQSHRUN_32, gen_sshl_i32, gen_helper_neon_unarrow_sat16) +DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat= 8) + +DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_s= at32) +DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_s= at16) +DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_s= at8) diff --git a/target/arm/translate.c b/target/arm/translate.c index d711d39eb9d..f884db535b4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5280,6 +5280,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case 5: /* VSHL, VSLI */ case 6: /* VQSHLU */ case 7: /* VQSHL */ + case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */ return 1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y8sm1100561wmc.37.2020.05.22.07.55.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2020 07:55:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Zsvrpi2W2w+CDxMMfrv5ax6LeBleFK4iIcwBhd1+Ups=; b=IJzYrLGOfOTR9Y6ohcHuQcJZ1VHr6vuKN3670am8vP65TJ4gWnNpOG5MWp+GTQkmXq pgu2VOfjDWetYZLpvunnfg4HByOiXBT7iPkiz7cjjdJNVFY2lB3zlRz66fVUXzlqyU1s EeYdGsMkS9paGHO53verfWGl6tzESjK9IARpfg3cij0CVDjm+NCXGXZHAEIpSybbBUvu 1smeRFtjAw/b9FOrg7eCFhTNayugqwX37JwO2T/vsYUcbKtMf3XTJ/IbAA9I/vQid+U6 KvbIAh8B0uWFygxZWXgd24trxbOPFHi8ledhA2yIXDiZjUowo85pYIQpcVH7VDrNs0ij kkZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Zsvrpi2W2w+CDxMMfrv5ax6LeBleFK4iIcwBhd1+Ups=; b=q4ossNdw+UajiCk3kggRQl7qJ5wQjwXW/RNfot+9n2FciRGNEEkyb4t+BFeKg8G7+x KFQ6DOwqsIkND66rsScn/eQn8UZn4EZdQ8Y2qpjF/JseXaRllCcYMn9e6KBY5PzRqAvm ozrjb7su3nmZcGd2JyZBJ5pmt8optAtaOONxnX5lwNxKh++Z7lTZY3ySfFHja7G1ZICM f6dOj6/STIFUDtF7/MCYiIetG0qV5n0fy5trZYJsqRJGVFez8888V1ruaPQjr7fMhEGj z5E5IGQons2qzXgg7iSZVRzA8ctDBSIvRcF51GKjaijEhaUaKc5LYW5PMZ8S3DCKjcTo U2Gg== X-Gm-Message-State: AOAM531ATyqOtzm7O3MS2pqb44ccWlMhUZaWmmJZ1aZ0ZB04iCIDVFO2 d7ERmBWKtYAEfRn+7vUpEquNWQ== X-Google-Smtp-Source: ABdhPJwNNAPvy2luqRFp4lOyFtRtWNy6TQ8pd4yfX+RtKxNxu0PbLX7/IdDLNPYgOc9ENOP9rqkKkQ== X-Received: by 2002:a5d:640f:: with SMTP id z15mr3714754wru.24.1590159329966; Fri, 22 May 2020 07:55:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 6/9] target/arm: Convert Neon narrowing shifts with op==9 to decodetree Date: Fri, 22 May 2020 15:55:17 +0100 Message-Id: <20200522145520.6778-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200522145520.6778-1-peter.maydell@linaro.org> References: <20200522145520.6778-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the remaining Neon narrowing shifts to decodetree: * VQSHRN * VQRSHRN Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 20 ++++++ target/arm/translate-neon.inc.c | 15 +++++ target/arm/translate.c | 110 +------------------------------- 3 files changed, 37 insertions(+), 108 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 01887240b4a..43db393cf76 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -326,3 +326,23 @@ VQSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 0 .= 1 .... @2reg_shrn_h VQRSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d VQRSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s VQRSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h + +# VQSHRN with signed input +VQSHRN_S64_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d +VQSHRN_S32_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s +VQSHRN_S16_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h + +# VQRSHRN with signed input +VQRSHRN_S64_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d +VQRSHRN_S32_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s +VQRSHRN_S16_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h + +# VQSHRN with unsigned input +VQSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d +VQSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s +VQSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h + +# VQRSHRN with unsigned input +VQRSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d +VQRSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s +VQRSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 18ea7255e38..9a75a69a4f5 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1672,3 +1672,18 @@ DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_h= elper_neon_unarrow_sat8) DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_s= at32) DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_s= at16) DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_s= at8) +DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32) +DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16) +DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_= s8) + +DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64, gen_helper_neon_narrow_sa= t_s32) +DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32, gen_helper_neon_narrow_sa= t_s16) +DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sa= t_s8) + +DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32) +DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16) +DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_= u8) + +DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sa= t_u32) +DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sa= t_u16) +DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sa= t_u8) diff --git a/target/arm/translate.c b/target/arm/translate.c index f884db535b4..f728231b198 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3201,40 +3201,6 @@ static inline void gen_neon_unarrow_sats(int size, T= CGv_i32 dest, TCGv_i64 src) } } =20 -static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32 = shift, - int q, int u) -{ - if (q) { - if (u) { - switch (size) { - case 1: gen_helper_neon_rshl_u16(var, var, shift); break; - case 2: gen_helper_neon_rshl_u32(var, var, shift); break; - default: abort(); - } - } else { - switch (size) { - case 1: gen_helper_neon_rshl_s16(var, var, shift); break; - case 2: gen_helper_neon_rshl_s32(var, var, shift); break; - default: abort(); - } - } - } else { - if (u) { - switch (size) { - case 1: gen_helper_neon_shl_u16(var, var, shift); break; - case 2: gen_ushl_i32(var, var, shift); break; - default: abort(); - } - } else { - switch (size) { - case 1: gen_helper_neon_shl_s16(var, var, shift); break; - case 2: gen_sshl_i32(var, var, shift); break; - default: abort(); - } - } - } -} - static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, i= nt u) { if (u) { @@ -5281,6 +5247,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case 6: /* VQSHLU */ case 7: /* VQSHL */ case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */ + case 9: /* VQSHRN, VQRSHRN */ return 1; /* handled by decodetree */ default: break; @@ -5298,80 +5265,7 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) size--; } shift =3D (insn >> 16) & ((1 << (3 + size)) - 1); - if (op < 10) { - /* Shift by immediate and narrow: - VSHRN, VRSHRN, VQSHRN, VQRSHRN. */ - int input_unsigned =3D (op =3D=3D 8) ? !u : u; - if (rm & 1) { - return 1; - } - shift =3D shift - (1 << (size + 3)); - size++; - if (size =3D=3D 3) { - tmp64 =3D tcg_const_i64(shift); - neon_load_reg64(cpu_V0, rm); - neon_load_reg64(cpu_V1, rm + 1); - for (pass =3D 0; pass < 2; pass++) { - TCGv_i64 in; - if (pass =3D=3D 0) { - in =3D cpu_V0; - } else { - in =3D cpu_V1; - } - if (q) { - if (input_unsigned) { - gen_helper_neon_rshl_u64(cpu_V0, in, tmp64= ); - } else { - gen_helper_neon_rshl_s64(cpu_V0, in, tmp64= ); - } - } else { - if (input_unsigned) { - gen_ushl_i64(cpu_V0, in, tmp64); - } else { - gen_sshl_i64(cpu_V0, in, tmp64); - } - } - tmp =3D tcg_temp_new_i32(); - gen_neon_narrow_op(op =3D=3D 8, u, size - 1, tmp, = cpu_V0); - neon_store_reg(rd, pass, tmp); - } /* for pass */ - tcg_temp_free_i64(tmp64); - } else { - if (size =3D=3D 1) { - imm =3D (uint16_t)shift; - imm |=3D imm << 16; - } else { - /* size =3D=3D 2 */ - imm =3D (uint32_t)shift; - } - tmp2 =3D tcg_const_i32(imm); - tmp4 =3D neon_load_reg(rm + 1, 0); - tmp5 =3D neon_load_reg(rm + 1, 1); - for (pass =3D 0; pass < 2; pass++) { - if (pass =3D=3D 0) { - tmp =3D neon_load_reg(rm, 0); - } else { - tmp =3D tmp4; - } - gen_neon_shift_narrow(size, tmp, tmp2, q, - input_unsigned); - if (pass =3D=3D 0) { - tmp3 =3D neon_load_reg(rm, 1); - } else { - tmp3 =3D tmp5; - } - gen_neon_shift_narrow(size, tmp3, tmp2, q, - input_unsigned); - tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp3); - tmp =3D tcg_temp_new_i32(); - gen_neon_narrow_op(op =3D=3D 8, u, size - 1, tmp, = cpu_V0); - neon_store_reg(rd, pass, tmp); - } /* for pass */ - tcg_temp_free_i32(tmp2); - } - } else if (op =3D=3D 10) { + if (op =3D=3D 10) { /* VSHLL, VMOVL */ if (q || (rd & 1)) { return 1; --=20 2.20.1 From nobody Fri Mar 29 13:38:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y8sm1100561wmc.37.2020.05.22.07.55.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2020 07:55:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7F+sswe7SvuqFs2BClGz5tu0K+Z++5uc+IUWnsx/Fmk=; b=zF/Qnzb4ORgmfksauAoCAGu5wN26hUM2uR7Iq4b6WYHI9/94BNfohbwdfes69NyM+9 SizyfBUaEmY3hn1oxPtITW1mjJzuzc/xTeuu0e1C81Yc40pM/OG7Pywnu3j0LqWTpZRG 7971K+Yi5mVMxCsNWr6p1YVGAXneX73IEnWng36VdSYCkKlZuS64SqEBwAJVUPHuLzMR tjy7KeAi/3r9ixYN3pMwYcZDA6NzIcCZZatWdhTOKWrDffD19R4wiY3JloVNEcLSgOxi 0fRxXvifp0G8tLiGoRfncgOUSkIT5a5pdirFQUruyzjDaqsGmHdRNXYg9QOxnyRLUKmw qIcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7F+sswe7SvuqFs2BClGz5tu0K+Z++5uc+IUWnsx/Fmk=; b=BmbPXWfU+zPOOkUFHYY6zz1qJy9uagQeCE0YQ3+t1xIMneCC/B3cboJTGy7K6awc0m r7M2YpX4y9utZt3Lq2+ywPFnKl7MRag1CNFntnGNT9ULiZVlBVecBRbPLAAByuu47zhl iltaQHpTWWJB3b0hrWAJ7iz6/Rjp4/bfrLd4CBfWHtGtf3XPqzi8AEAUYc+k5eYtxAXd 9NsbH86RtcNTPtNYr1XU1gxy2f4ed2mM/BJgZimpbrKM9cdRw1XK7CXxHr2H6TaIst44 ymzqqMaVp4tHoUHK2BQzNrEqvyL/pnwh494sWoj0QN13N5uwUWGYp25lUX3c0PNx8pMv ll7g== X-Gm-Message-State: AOAM530sdMqlDx23aWKc/lhjOE7YN3TmsYMt/27hBWksF2yPVN0UUGcO YOqbrmxF0phdH7v5wiIFvde5VQ== X-Google-Smtp-Source: ABdhPJxuxYt8vGhBY8iZMKtxrUvJMaCOoRyeShWn2urFy0YvB+0myXL5b9lYBboqhRIfUyH2LMx3dA== X-Received: by 2002:a1c:4909:: with SMTP id w9mr13727092wma.95.1590159331041; Fri, 22 May 2020 07:55:31 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 7/9] target/arm: Convert Neon VSHLL, VMOVL to decodetree Date: Fri, 22 May 2020 15:55:18 +0100 Message-Id: <20200522145520.6778-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200522145520.6778-1-peter.maydell@linaro.org> References: <20200522145520.6778-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VSHLL and VMOVL insns from the 2-reg-shift group to decodetree. Since the loop always has two passes, we unroll it to avoid the awkward reassignment of one TCGv to another. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 16 +++++++ target/arm/translate-neon.inc.c | 81 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 46 +------------------ 3 files changed, 99 insertions(+), 44 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 43db393cf76..9dd13d13254 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -241,6 +241,14 @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ...= 1 .... @3same_fp &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D1 q=3D0 \ shift=3D%neon_rshift_i3 =20 +# Long left shifts: again Q is part of opcode decode +@2reg_shll_s .... ... . . . 1 shift:5 .... .... 0 . . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D2 q=3D0 +@2reg_shll_h .... ... . . . 01 shift:4 .... .... 0 . . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D1 q=3D0 +@2reg_shll_b .... ... . . . 001 shift:3 .... .... 0 . . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D0 q=3D0 + VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h @@ -346,3 +354,11 @@ VQSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 0 .= 1 .... @2reg_shrn_h VQRSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d VQRSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s VQRSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h + +VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s +VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h +VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b + +VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s +VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h +VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 9a75a69a4f5..5678bfd0d4d 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1687,3 +1687,84 @@ DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_h= elper_neon_narrow_sat_u8) DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sa= t_u32) DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sa= t_u16) DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sa= t_u8) + +static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, + NeonGenWidenFn *widenfn, bool u) +{ + TCGv_i64 tmp; + TCGv_i32 rm0, rm1; + uint64_t widen_mask =3D 0; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vd & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * This is a widen-and-shift operation. The shift is always less + * than the width of the source type, so after widening the input + * vector we can simply shift the whole 64-bit widened register, + * and then clear the potential overflow bits resulting from left + * bits of the narrow input appearing as right bits of the left + * neighbour narrow input. Calculate a mask of bits to clear. + */ + if ((a->shift !=3D 0) && (a->size < 2 || u)) { + int esize =3D 8 << a->size; + widen_mask =3D MAKE_64BIT_MASK(0, esize); + widen_mask >>=3D esize - a->shift; + widen_mask =3D dup_const(a->size + 1, widen_mask); + } + + rm0 =3D neon_load_reg(a->vm, 0); + rm1 =3D neon_load_reg(a->vm, 1); + tmp =3D tcg_temp_new_i64(); + + widenfn(tmp, rm0); + if (a->shift !=3D 0) { + tcg_gen_shli_i64(tmp, tmp, a->shift); + tcg_gen_andi_i64(tmp, tmp, ~widen_mask); + } + neon_store_reg64(tmp, a->vd); + + widenfn(tmp, rm1); + if (a->shift !=3D 0) { + tcg_gen_shli_i64(tmp, tmp, a->shift); + tcg_gen_andi_i64(tmp, tmp, ~widen_mask); + } + neon_store_reg64(tmp, a->vd + 1); + tcg_temp_free_i64(tmp); + return true; +} + +static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a) +{ + NeonGenWidenFn *widenfn[] =3D { + gen_helper_neon_widen_s8, + gen_helper_neon_widen_s16, + tcg_gen_ext_i32_i64, + }; + return do_vshll_2sh(s, a, widenfn[a->size], false); +} + +static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a) +{ + NeonGenWidenFn *widenfn[] =3D { + gen_helper_neon_widen_u8, + gen_helper_neon_widen_u16, + tcg_gen_extu_i32_i64, + }; + return do_vshll_2sh(s, a, widenfn[a->size], true); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index f728231b198..ef39c89f10a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5248,6 +5248,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case 7: /* VQSHL */ case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */ case 9: /* VQSHRN, VQRSHRN */ + case 10: /* VSHLL, including VMOVL */ return 1; /* handled by decodetree */ default: break; @@ -5265,50 +5266,7 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) size--; } shift =3D (insn >> 16) & ((1 << (3 + size)) - 1); - if (op =3D=3D 10) { - /* VSHLL, VMOVL */ - if (q || (rd & 1)) { - return 1; - } - tmp =3D neon_load_reg(rm, 0); - tmp2 =3D neon_load_reg(rm, 1); - for (pass =3D 0; pass < 2; pass++) { - if (pass =3D=3D 1) - tmp =3D tmp2; - - gen_neon_widen(cpu_V0, tmp, size, u); - - if (shift !=3D 0) { - /* The shift is less than the width of the source - type, so we can just shift the whole register. = */ - tcg_gen_shli_i64(cpu_V0, cpu_V0, shift); - /* Widen the result of shift: we need to clear - * the potential overflow bits resulting from - * left bits of the narrow input appearing as - * right bits of left the neighbour narrow - * input. */ - if (size < 2 || !u) { - uint64_t imm64; - if (size =3D=3D 0) { - imm =3D (0xffu >> (8 - shift)); - imm |=3D imm << 16; - } else if (size =3D=3D 1) { - imm =3D 0xffff >> (16 - shift); - } else { - /* size =3D=3D 2 */ - imm =3D 0xffffffff >> (32 - shift); - } - if (size < 2) { - imm64 =3D imm | (((uint64_t)imm) << 32); - } else { - imm64 =3D imm; - } - tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64); - } - } - neon_store_reg64(cpu_V0, rd + pass); - } - } else if (op >=3D 14) { + if (op >=3D 14) { /* VCVT fixed-point. */ TCGv_ptr fpst; TCGv_i32 shiftv; --=20 2.20.1 From nobody Fri Mar 29 13:38:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y8sm1100561wmc.37.2020.05.22.07.55.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2020 07:55:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FoqQhIGM3HzHgFWnngxDVlaiVoPhQ6wjnnlrtKQGvR4=; b=ZHXvFu0amsNfQpEww09UipIe68TAoumZtDqP79Mt30Unqbez+ZS6JIiClhvQRlAJtw nbfNN36JugBh5gG7sw6C5UReV7OB/NxAJvtrFW+ZGlYFs9aeVg5MdXR2dmy53w08vFLX P7AWb8LbMS652t5YDGTJZeh2BrlS/NWwRGpDnaYDXDcpirGv3yitS4aBWkvNzIBdGkxs 18+2zAhATqkwpNfbzh18lk/RzXsIq1YeKpxVHIzBJHSPdKrVLx0kLfoi7viSWoFYG382 Tc48DnuDL9/087LPNGn/hV0AB1b0N+Y9Lg41is3AXsgToU9aA8k0pcpc/cYRJfw10kQA SpfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FoqQhIGM3HzHgFWnngxDVlaiVoPhQ6wjnnlrtKQGvR4=; b=Rt7IU7Lz0XdgOhKyDBIIhA89UISj2+UfH68KheOk0rgoUY7JRAh80rVywYTxepvPir Dmi3OfVQpyHJU9Bn9w3WfwCW+WIhkUuXnykLbpAnkMwNGYACqv17WeP5HESqZQTsFESN V2Oj9NrV7rPZawDDzXShmGr3+Ke6vi9aqPEHOmrhoV/hiCeFMM8/jUk14v/sqPTPUPea pN2wFXZvcyrnfs6/JZqIShx+PyZ6THLLmgjH9quKrxSBnbNuJGgnfjxF144Z/m/hq1mS 2jgkNbFG6vrjcYivQ1ey9pgZUZ0GEMzZAjRGWQRWn2zIfF2Ou4R1DM7M+jFEo6cpEta4 yzlQ== X-Gm-Message-State: AOAM532lKxkjUhckrSRodB5ZraH88a8cJ6U9jjwvjT+AC4QROmTb9y8X Dp/QfMTybLxDtN1hhtE8CIj9iQ== X-Google-Smtp-Source: ABdhPJyicNemLlj2yhN0zS0feH7TXMM3jOqqT1XkNmrg0UbX4p+SyQLqmBPcHPjVq0Qzbt3tSTF0Zg== X-Received: by 2002:a5d:4dd0:: with SMTP id f16mr2072583wru.117.1590159332270; Fri, 22 May 2020 07:55:32 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 8/9] target/arm: Convert VCVT fixed-point ops to decodetree Date: Fri, 22 May 2020 15:55:19 +0100 Message-Id: <20200522145520.6778-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200522145520.6778-1-peter.maydell@linaro.org> References: <20200522145520.6778-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VCVT fixed-point conversion operations in the Neon 2-regs-and-shift group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 11 +++++ target/arm/translate-neon.inc.c | 49 +++++++++++++++++++++ target/arm/translate.c | 75 +-------------------------------- 3 files changed, 62 insertions(+), 73 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 9dd13d13254..e217d51670d 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -249,6 +249,10 @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ...= 1 .... @3same_fp @2reg_shll_b .... ... . . . 001 shift:3 .... .... 0 . . . .... \ &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D0 q=3D0 =20 +# We use size=3D0 for fp32 and size=3D1 for fp16 to match the 3-same encod= ings. +@2reg_vcvt .... ... . . . 1 ..... .... .... . q:1 . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp size=3D0 shift=3D%neo= n_rshift_i5 + VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h @@ -362,3 +366,10 @@ VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 .= 1 .... @2reg_shll_b VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b + +# VCVT fixed<->float conversions +# TODO: FP16 fixed<->float conversions are opc=3D=3D0b1100 and 0b1101 +VCVT_SF_2sh 1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt +VCVT_UF_2sh 1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt +VCVT_FS_2sh 1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt +VCVT_FU_2sh 1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 5678bfd0d4d..8d1c58eddc2 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1768,3 +1768,52 @@ static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2= reg_shift *a) }; return do_vshll_2sh(s, a, widenfn[a->size], true); } + +static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, + NeonGenTwoSingleOPFn *fn) +{ + /* FP operations in 2-reg-and-shift group */ + TCGv_i32 tmp, shiftv; + TCGv_ptr fpstatus; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpstatus =3D get_fpstatus_ptr(1); + shiftv =3D tcg_const_i32(a->shift); + for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { + tmp =3D neon_load_reg(a->vm, pass); + fn(tmp, tmp, shiftv, fpstatus); + neon_store_reg(a->vd, pass, tmp); + } + tcg_temp_free_ptr(fpstatus); + tcg_temp_free_i32(shiftv); + return true; +} + +#define DO_FP_2SH(INSN, FUNC) \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_fp_2sh(s, a, FUNC); \ + } + +DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos) +DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos) +DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero) +DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero) diff --git a/target/arm/translate.c b/target/arm/translate.c index ef39c89f10a..9cc44e6258e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5193,7 +5193,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) int q; int rd, rn, rm, rd_ofs, rn_ofs, rm_ofs; int size; - int shift; int pass; int u; int vec_size; @@ -5234,78 +5233,8 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) return 1; } else if (insn & (1 << 4)) { if ((insn & 0x00380080) !=3D 0) { - /* Two registers and shift. */ - op =3D (insn >> 8) & 0xf; - - switch (op) { - case 0: /* VSHR */ - case 1: /* VSRA */ - case 2: /* VRSHR */ - case 3: /* VRSRA */ - case 4: /* VSRI */ - case 5: /* VSHL, VSLI */ - case 6: /* VQSHLU */ - case 7: /* VQSHL */ - case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */ - case 9: /* VQSHRN, VQRSHRN */ - case 10: /* VSHLL, including VMOVL */ - return 1; /* handled by decodetree */ - default: - break; - } - - if (insn & (1 << 7)) { - /* 64-bit shift. */ - if (op > 7) { - return 1; - } - size =3D 3; - } else { - size =3D 2; - while ((insn & (1 << (size + 19))) =3D=3D 0) - size--; - } - shift =3D (insn >> 16) & ((1 << (3 + size)) - 1); - if (op >=3D 14) { - /* VCVT fixed-point. */ - TCGv_ptr fpst; - TCGv_i32 shiftv; - VFPGenFixPointFn *fn; - - if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) { - return 1; - } - - if (!(op & 1)) { - if (u) { - fn =3D gen_helper_vfp_ultos; - } else { - fn =3D gen_helper_vfp_sltos; - } - } else { - if (u) { - fn =3D gen_helper_vfp_touls_round_to_zero; - } else { - fn =3D gen_helper_vfp_tosls_round_to_zero; - } - } - - /* We have already masked out the must-be-1 top bit of imm= 6, - * hence this 32-shift where the ARM ARM has 64-imm6. - */ - shift =3D 32 - shift; - fpst =3D get_fpstatus_ptr(1); - shiftv =3D tcg_const_i32(shift); - for (pass =3D 0; pass < (q ? 4 : 2); pass++) { - TCGv_i32 tmpf =3D neon_load_reg(rm, pass); - fn(tmpf, tmpf, shiftv, fpst); - neon_store_reg(rd, pass, tmpf); - } - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(shiftv); - } else { - return 1; - } + /* Two registers and shift: handled by decodetree */ + return 1; } else { /* (insn & 0x00380080) =3D=3D 0 */ int invert, reg_ofs, vec_size; =20 --=20 2.20.1 From nobody Fri Mar 29 13:38:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1590159789; cv=none; d=zohomail.com; s=zohoarc; b=lf+dljJImsnoVApMJ4RpbXF3/OxCFVrepCPy8le49mrumQ9gGOlS9s7bcHdB90n83naFfXMGfiWwHdBx+EbkjNX4G+T/Wn4dwM1nideLrysIg7Gn/E8Ld+CmfxwHwsXNsBhz9ZXnRBXf/+hzxnzqTxLYJ9fn2SUvvO6AipqFZkQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1590159789; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lPAwSc45qlxB/TZuoMmLjNjab6Fr/WrHf/LvzT8lOcU=; b=DoVvyWiFtU3RzFNXWRaLfO4rZvEZXFTEIKiCTYulm1vVELpOftDqWRubykQ9MmX3KaYGP0Gkka2PAOEsrB17yFOTdiwZrE6lo6r4cUduGxofab4+LohdH+fK+qD+U/oV5Zcre+dfpPuYF1lhND+yS6tueyTiH1MSDkFom9sKrmk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1590159789222291.0307613005208; Fri, 22 May 2020 08:03:09 -0700 (PDT) Received: from localhost ([::1]:38830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jc9CV-0007r1-Fb for importer@patchew.org; Fri, 22 May 2020 11:03:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60056) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jc95E-0002Lc-Cn for qemu-devel@nongnu.org; Fri, 22 May 2020 10:55:36 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:46135) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jc95C-0006UJ-Vf for qemu-devel@nongnu.org; Fri, 22 May 2020 10:55:35 -0400 Received: by mail-wr1-x444.google.com with SMTP id w7so10404687wre.13 for ; Fri, 22 May 2020 07:55:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y8sm1100561wmc.37.2020.05.22.07.55.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2020 07:55:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lPAwSc45qlxB/TZuoMmLjNjab6Fr/WrHf/LvzT8lOcU=; b=mmy7GoGJd3UdSMd0cwt5IgHP+aOnPdH1g2r0+KaAhEsDeo4Q5Hmuqv9SGze+tG38aM AJM6p6VvGR6BLSsim97m3yYzqXRRd6Gh6L2bq6+Th+yv3r5OxmLMZKr4yn8qMXCXxMbX dXeWr1NgJbRXeyCZyyBCvPby/zdFx6bd7omKpwnMoeQWd5xd7sdIsO4NWQZl+UcTe97X dmr/gKdnbzcjQNr/CYi1XkPRofcwDN6Hrq3ORxTcqRSXTdMYgapL6TR/ANLVyGpbdwvo EJho45x9qD9COsirBEXMsfLfWg7zGjEln/T/lSPVC8goeiWxlb+xIW9tGSEpYNpJF7VO TxEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lPAwSc45qlxB/TZuoMmLjNjab6Fr/WrHf/LvzT8lOcU=; b=LEp/tq8e7dz84YShO+57qdp+fyE4ivHhIOo4vXqBk4lYMRvGuOEVpJWdx4ZI0Xx0Sd 40GQjxkfbIZFDLUX/4gldP/nviHnZPlFdXr7LBtPfDHO/sRYA9NmlhDm5mApYG1uD9+b 0VIum7njzdNt6gAkonlwj4OCMSL3CF5Q0gs6IPFSJh8BBsrOyu+f8OoiVS6fnw1Gdpsl RbM9ibNdvARoUMDpb28Vtiq7Ie0DnZv/xViT6Ao99AsrGeFPTqNnIDxZHQ8ejV8nPNab hlkSbJqzLBvb6QRnrQEee19yiQWTBwFOYJ1yKTPaPU6l2KqGxgHEqF1FBhy7BJ2HkaZO 1UoA== X-Gm-Message-State: AOAM5332a4UlJWRjTGxfKqHgCiNME/hcK4bt4ILKZA3nUtLba5mfBmX2 91N2UBQUNG9g4T7uvuDRtJbltA== X-Google-Smtp-Source: ABdhPJzEhNnrNAtzfvuhaU0UNxxJIIi7Z44F/ArpoGpK9mCs53NG8JehpaXMEn3s5FCY6RqMtqEaJg== X-Received: by 2002:adf:e441:: with SMTP id t1mr4114328wrm.347.1590159333438; Fri, 22 May 2020 07:55:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 9/9] target/arm: Convert Neon one-register-and-immediate insns to decodetree Date: Fri, 22 May 2020 15:55:20 +0100 Message-Id: <20200522145520.6778-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200522145520.6778-1-peter.maydell@linaro.org> References: <20200522145520.6778-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the insns in the one-register-and-immediate group to decodetree. In the new decode, our asimd_imm_const() function returns a 64-bit value rather than a 32-bit one, which means we don't need to treat cmode=3D14 op= =3D1 as a special case in the decoder (it is the only encoding where the two halves of the 64-bit value are different). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 22 ++++++ target/arm/translate-neon.inc.c | 118 ++++++++++++++++++++++++++++++++ target/arm/translate.c | 101 +-------------------------- 3 files changed, 142 insertions(+), 99 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index e217d51670d..1643d84e9c2 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -373,3 +373,25 @@ VCVT_SF_2sh 1111 001 0 1 . ...... .... 1110 0 . .= 1 .... @2reg_vcvt VCVT_UF_2sh 1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt VCVT_FS_2sh 1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt VCVT_FU_2sh 1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt + +###################################################################### +# 1-reg-and-modified-immediate grouping: +# 1111 001 i 1 D 000 imm:3 Vd:4 cmode:4 0 Q op 1 Vm:4 +###################################################################### + +&1reg_imm vd q imm cmode op + +%asimd_imm_value 24:1 16:3 0:4 + +@1reg_imm .... ... . . . ... ... .... .... . q:1 . . .... \ + &1reg_imm imm=3D%asimd_imm_value vd=3D%vd_dp + +# The cmode/op bits here decode VORR/VBIC/VMOV/VMNV, but +# not in a way we can conveniently represent in decodetree without +# a lot of repetition: +# VORR: op=3D0, (cmode & 1) && cmode < 12 +# VBIC: op=3D1, (cmode & 1) && cmode < 12 +# VMOV: everything else +# So we have a single decode line and check the cmode/op in the +# trans function. +Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg= _imm diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 8d1c58eddc2..39c7e70373a 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1817,3 +1817,121 @@ DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos) DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos) DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero) DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero) + +static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) +{ + /* + * Expand the encoded constant. + * Note that cmode =3D 2,3,4,5,6,7,10,11,12,13 imm=3D0 is UNPREDICTABL= E. + * We choose to not special-case this and will behave as if a + * valid constant encoding of 0 had been given. + * cmode =3D 15 op =3D 1 must UNDEF; we assume decode has handled that. + */ + switch (cmode) { + case 0: case 1: + /* no-op */ + break; + case 2: case 3: + imm <<=3D 8; + break; + case 4: case 5: + imm <<=3D 16; + break; + case 6: case 7: + imm <<=3D 24; + break; + case 8: case 9: + imm |=3D imm << 16; + break; + case 10: case 11: + imm =3D (imm << 8) | (imm << 24); + break; + case 12: + imm =3D (imm << 8) | 0xff; + break; + case 13: + imm =3D (imm << 16) | 0xffff; + break; + case 14: + if (op) { + /* + * This is the only case where the top and bottom 32 bits + * of the encoded constant differ. + */ + uint64_t imm64 =3D 0; + int n; + + for (n =3D 0; n < 8; n++) { + if (imm & (1 << n)) { + imm64 |=3D (0xffULL << (n * 8)); + } + } + return imm64; + } + imm |=3D (imm << 8) | (imm << 16) | (imm << 24); + break; + case 15: + imm =3D ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) + | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); + break; + } + if (op) { + imm =3D ~imm; + } + return dup_const(MO_32, imm); +} + +static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, + GVecGen2iFn *fn) +{ + uint64_t imm; + int reg_ofs, vec_size; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + return false; + } + + if (a->vd & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + reg_ofs =3D neon_reg_offset(a->vd, 0); + vec_size =3D a->q ? 16 : 8; + imm =3D asimd_imm_const(a->imm, a->cmode, a->op); + + fn(MO_64, reg_ofs, reg_ofs, imm, vec_size, vec_size); + return true; +} + +static void gen_VMOV_1r(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c); +} + +static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a) +{ + /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ + GVecGen2iFn *fn; + + if ((a->cmode & 1) && a->cmode < 12) { + /* for op=3D1, the imm will be inverted, so BIC becomes AND. */ + fn =3D a->op ? tcg_gen_gvec_andi : tcg_gen_gvec_ori; + } else { + /* There is one unallocated cmode/op combination in this space */ + if (a->cmode =3D=3D 15 && a->op =3D=3D 1) { + return false; + } + fn =3D gen_VMOV_1r; + } + return do_1reg_imm(s, a, fn); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 9cc44e6258e..20d07e99053 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5232,105 +5232,8 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) /* Three register same length: handled by decodetree */ return 1; } else if (insn & (1 << 4)) { - if ((insn & 0x00380080) !=3D 0) { - /* Two registers and shift: handled by decodetree */ - return 1; - } else { /* (insn & 0x00380080) =3D=3D 0 */ - int invert, reg_ofs, vec_size; - - if (q && (rd & 1)) { - return 1; - } - - op =3D (insn >> 8) & 0xf; - /* One register and immediate. */ - imm =3D (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf); - invert =3D (insn & (1 << 5)) !=3D 0; - /* Note that op =3D 2,3,4,5,6,7,10,11,12,13 imm=3D0 is UNPREDI= CTABLE. - * We choose to not special-case this and will behave as if a - * valid constant encoding of 0 had been given. - */ - switch (op) { - case 0: case 1: - /* no-op */ - break; - case 2: case 3: - imm <<=3D 8; - break; - case 4: case 5: - imm <<=3D 16; - break; - case 6: case 7: - imm <<=3D 24; - break; - case 8: case 9: - imm |=3D imm << 16; - break; - case 10: case 11: - imm =3D (imm << 8) | (imm << 24); - break; - case 12: - imm =3D (imm << 8) | 0xff; - break; - case 13: - imm =3D (imm << 16) | 0xffff; - break; - case 14: - imm |=3D (imm << 8) | (imm << 16) | (imm << 24); - if (invert) { - imm =3D ~imm; - } - break; - case 15: - if (invert) { - return 1; - } - imm =3D ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) - | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); - break; - } - if (invert) { - imm =3D ~imm; - } - - reg_ofs =3D neon_reg_offset(rd, 0); - vec_size =3D q ? 16 : 8; - - if (op & 1 && op < 12) { - if (invert) { - /* The immediate value has already been inverted, - * so BIC becomes AND. - */ - tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm, - vec_size, vec_size); - } else { - tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm, - vec_size, vec_size); - } - } else { - /* VMOV, VMVN. */ - if (op =3D=3D 14 && invert) { - TCGv_i64 t64 =3D tcg_temp_new_i64(); - - for (pass =3D 0; pass <=3D q; ++pass) { - uint64_t val =3D 0; - int n; - - for (n =3D 0; n < 8; n++) { - if (imm & (1 << (n + pass * 8))) { - val |=3D 0xffull << (n * 8); - } - } - tcg_gen_movi_i64(t64, val); - neon_store_reg64(t64, rd + pass); - } - tcg_temp_free_i64(t64); - } else { - tcg_gen_gvec_dup_imm(MO_32, reg_ofs, vec_size, - vec_size, imm); - } - } - } + /* Two registers and shift or reg and imm: handled by decodetree */ + return 1; } else { /* (insn & 0x00800010 =3D=3D 0x00800000) */ if (size !=3D 3) { op =3D (insn >> 8) & 0xf; --=20 2.20.1