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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z124sm7335100wmg.20.2020.05.21.12.16.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2020 12:16:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=P9KCQG/WS9GdDGHqO3MaEt12NQUl4WXAVUVOE7KRnPs=; b=wZpnMc2byuMVHZNKWjRinyea4nLfOfujfXhtk+o9ZuosQYyCYk1RRKTRpO2KXLA1Bf LNr8zFYL/8n9MlvZPIpUhlzmiD+2JI2LpZqed3YkDj+X4t+78jgT+MCv5L+XUxaELbua VTufdJ8yUbS95mRmbFFt3dT9RS2oULmAWZ8kCByttdSdk5ZDSu0dOvUSWAePpz1q0xaX cyqVBV+3gh3DOM9uGIqfBoRm1T1n/XYl9Jnqw2XJKKgHUbFrvVBUeWneZIB4FNwC36P+ za0kbBGTPrfBM0QrVCscAHuOPNtc3ppKH7CnsMzIH3H7Eb606JALN6sM12wL3Zm6puDW sbNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P9KCQG/WS9GdDGHqO3MaEt12NQUl4WXAVUVOE7KRnPs=; b=gjoarppEph9ZR7JzgNccngX/7NNf0Ob/qw9qqg08PTxKga7T5uf6326muRzfxPVWD8 odLgJupf6WY59oO1IfdkGc43Pg9ebJ+p8jum4nDPXaaDikfJdkh7Dvuiz5+CkaCtN85y tx/UKcbjcuIA9JNo7TZydOwK803qnpLvnBek4+lUXZLX5fhnKSYb1odSgFEtXRDg1Ru9 DZ8ZV2B5AJwrJwazxzJUFWvIeWtnYLBjKM6PUCq8D8gjAJTYZWoQOsan9N7+DJm6KzkT e7Fooh6jLteq8HER5eoquEEcgk4qCe1QWb5dcBbZ5mpj1d88qE2Q8N77ZxhIq+SUlP1/ 9iKQ== X-Gm-Message-State: AOAM530T4s4n/HRpAk0qGxSOYX+RecS/GVZJ0mjeEvb5SblasKilzEJh 6L7pfzAK3th1nGmbqy0g4h9AQejNwXMNiA== X-Google-Smtp-Source: ABdhPJxaycj6EF0n1dQ4lPeBK60seLzfuT+oAy6OTfzOcH+GB4r7sA7Hb92WIODDu+a+ZfVC9BcWOQ== X-Received: by 2002:adf:fb08:: with SMTP id c8mr71268wrr.421.1590088597852; Thu, 21 May 2020 12:16:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/29] hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask() Date: Thu, 21 May 2020 20:16:02 +0100 Message-Id: <20200521191610.10941-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200521191610.10941-1-peter.maydell@linaro.org> References: <20200521191610.10941-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 hw_error() calls exit(). This a bit overkill when we can log the accesses as unimplemented or guest error. When fuzzing the devices, we don't want the whole process to exit. Replace some hw_error() calls by qemu_log_mask(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 20200518140309.5220-3-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/pxa2xx_gpio.c | 7 ++++--- hw/display/pxa2xx_lcd.c | 8 +++++--- hw/dma/pxa2xx_dma.c | 14 +++++++++----- 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c index f8df3cc2279..a01db54a518 100644 --- a/hw/arm/pxa2xx_gpio.c +++ b/hw/arm/pxa2xx_gpio.c @@ -9,7 +9,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "hw/hw.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" @@ -199,7 +198,8 @@ static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr o= ffset, return s->status[bank]; =20 default: - hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", + __func__, offset); } =20 return 0; @@ -252,7 +252,8 @@ static void pxa2xx_gpio_write(void *opaque, hwaddr offs= et, break; =20 default: - hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", + __func__, offset); } } =20 diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c index 464e93161a2..d5f2e82a4ec 100644 --- a/hw/display/pxa2xx_lcd.c +++ b/hw/display/pxa2xx_lcd.c @@ -11,7 +11,7 @@ */ =20 #include "qemu/osdep.h" -#include "hw/hw.h" +#include "qemu/log.h" #include "hw/irq.h" #include "migration/vmstate.h" #include "ui/console.h" @@ -407,7 +407,8 @@ static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr o= ffset, =20 default: fail: - hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", + __func__, offset); } =20 return 0; @@ -562,7 +563,8 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offs= et, =20 default: fail: - hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", + __func__, offset); } } =20 diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c index 88ed4b6ff1f..8a2eeb32bc3 100644 --- a/hw/dma/pxa2xx_dma.c +++ b/hw/dma/pxa2xx_dma.c @@ -9,6 +9,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" #include "hw/hw.h" #include "hw/irq.h" #include "hw/qdev-properties.h" @@ -268,7 +269,8 @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr of= fset, unsigned int channel; =20 if (size !=3D 4) { - hw_error("%s: Bad access width\n", __func__); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n", + __func__, size); return 5; } =20 @@ -315,8 +317,8 @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr of= fset, return s->chan[channel].cmd; } } - - hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", + __func__, offset); return 7; } =20 @@ -327,7 +329,8 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offse= t, unsigned int channel; =20 if (size !=3D 4) { - hw_error("%s: Bad access width\n", __func__); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n", + __func__, size); return; } =20 @@ -420,7 +423,8 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offse= t, break; } fail: - hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", + __func__, offset); } } =20 --=20 2.20.1