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bh=Kd60isijc7N93R5SBt36LCkpor0G13KGJpP9vjfXfyA=; b=WQzEGohn96wxZmQSYgiOgQR7IDwy5uBkCglM+km5ffjGqiTqAiGZk1xLSRRPRtkGbpTBLt dfzhy5ftSfWnntubrerwGt6N7Rck72qUPK01gsy9+NHtqGnGr5G5wmFIIPYFjtRaDAKBij vPQkyXFRoL8pl0e6yFs2/uZNjEYs9N4= X-MC-Unique: dKprUG8KNtahSmXsp-dHDg-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH 1/9] hw/arm/smmu-common: Factorize some code in smmu_ptw_64() Date: Thu, 21 May 2020 11:10:51 +0200 Message-Id: <20200521091059.9453-2-eric.auger@redhat.com> In-Reply-To: <20200521091059.9453-1-eric.auger@redhat.com> References: <20200521091059.9453-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Page and block PTE decoding can share some code. Let's first handle table PTE and factorize some code shared by page and block PTEs. Signed-off-by: Eric Auger --- hw/arm/smmu-common.c | 51 ++++++++++++++++---------------------------- 1 file changed, 18 insertions(+), 33 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index e13a5f4a7c..f2de2be527 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -186,12 +186,12 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); uint64_t mask =3D subpage_size - 1; uint32_t offset =3D iova_level_offset(iova, inputsize, level, gran= ule_sz); - uint64_t pte; + uint64_t pte, gpa; dma_addr_t pte_addr =3D baseaddr + offset * sizeof(pte); uint8_t ap; =20 if (get_pte(baseaddr, offset, &pte, info)) { - goto error; + break; } trace_smmu_ptw_level(level, iova, subpage_size, baseaddr, offset, pte); @@ -199,58 +199,43 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) { trace_smmu_ptw_invalid_pte(stage, level, baseaddr, pte_addr, offset, pte); - info->type =3D SMMU_PTW_ERR_TRANSLATION; - goto error; + break; } =20 - if (is_page_pte(pte, level)) { - uint64_t gpa =3D get_page_pte_address(pte, granule_sz); + if (is_table_pte(pte, level)) { + ap =3D PTE_APTABLE(pte); =20 - ap =3D PTE_AP(pte); if (is_permission_fault(ap, perm)) { info->type =3D SMMU_PTW_ERR_PERMISSION; goto error; } - - tlbe->translated_addr =3D gpa + (iova & mask); - tlbe->perm =3D PTE_AP_TO_PERM(ap); + baseaddr =3D get_table_pte_address(pte, granule_sz); + level++; + continue; + } else if (is_page_pte(pte, level)) { + gpa =3D get_page_pte_address(pte, granule_sz); trace_smmu_ptw_page_pte(stage, level, iova, baseaddr, pte_addr, pte, gpa); - return 0; - } - if (is_block_pte(pte, level)) { + } else { uint64_t block_size; - hwaddr gpa =3D get_block_pte_address(pte, level, granule_sz, - &block_size); - - ap =3D PTE_AP(pte); - if (is_permission_fault(ap, perm)) { - info->type =3D SMMU_PTW_ERR_PERMISSION; - goto error; - } =20 + gpa =3D get_block_pte_address(pte, level, granule_sz, + &block_size); trace_smmu_ptw_block_pte(stage, level, baseaddr, pte_addr, pte, iova, gpa, block_size >> 20); - - tlbe->translated_addr =3D gpa + (iova & mask); - tlbe->perm =3D PTE_AP_TO_PERM(ap); - return 0; } - - /* table pte */ - ap =3D PTE_APTABLE(pte); - + ap =3D PTE_AP(pte); if (is_permission_fault(ap, perm)) { info->type =3D SMMU_PTW_ERR_PERMISSION; goto error; } - baseaddr =3D get_table_pte_address(pte, granule_sz); - level++; + + tlbe->translated_addr =3D gpa + (iova & mask); + tlbe->perm =3D PTE_AP_TO_PERM(ap); + return 0; } - info->type =3D SMMU_PTW_ERR_TRANSLATION; - error: tlbe->perm =3D IOMMU_NONE; return -EINVAL; --=20 2.20.1 From nobody Sat Apr 20 13:22:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1590052596; cv=none; d=zohomail.com; s=zohoarc; b=GlKTOlcp1z1xddeJ2i0RYDkKclqeciCWM++VFj0TqrXitgSOY15h0jqzdBkqvGteSbSomnvRhgO28E6VzEX4QrsP53HfzdzZHesDwvXpf7gn9C1X1NzrKn6LBln1en8nRNDICl7gkzdSHY9wP3ZYzMEIU6S0IpiLOTyaKSA/qV0= ARC-Message-Signature: i=1; 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Thu, 21 May 2020 09:11:30 +0000 (UTC) Received: from laptop.redhat.com (ovpn-113-56.ams2.redhat.com [10.36.113.56]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1343E5D9C9; Thu, 21 May 2020 09:11:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1590052294; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=88JfQ/V18ykOPEZ1/11XYsmgAaywXOVJDbk3ySzrtNY=; b=R09yxwGAcMoewbjI5PEB4gIg/FZrQkv+dcyNAkEauzLoDO3nWIoyfJtpBFg2M1eIFDmDlb t8tkKnidRfUu2Y6+2c77iZv90MkaD7Fr3Q/r51hJU+FvIrRSYDwCQO+KHomwSBGIblEeiL WKKHvc/PuuBd74JOqo8Gdycckyo5QTQ= X-MC-Unique: nzE6LQzDPIugIT93WW7ASw-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH 2/9] hw/arm/smmu-common: Add IOTLB helpers Date: Thu, 21 May 2020 11:10:52 +0200 Message-Id: <20200521091059.9453-3-eric.auger@redhat.com> In-Reply-To: <20200521091059.9453-1-eric.auger@redhat.com> References: <20200521091059.9453-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Add two helpers to lookup for a given IOTLB entry and an one. We also more the tracing there. Signed-off-by: Eric Auger --- include/hw/arm/smmu-common.h | 2 ++ hw/arm/smmu-common.c | 36 ++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3.c | 26 ++------------------------ hw/arm/trace-events | 5 +++-- 4 files changed, 43 insertions(+), 26 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index ca4a4b1ad1..1dceec5cb1 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -153,6 +153,8 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t= sid); =20 #define SMMU_IOTLB_MAX_SIZE 256 =20 +IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr = iova); +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index f2de2be527..8409de052d 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -32,6 +32,42 @@ =20 /* IOTLB Management */ =20 +IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, + hwaddr iova) +{ + SMMUIOTLBKey key =3D {.asid =3D cfg->asid, .iova =3D iova}; + IOMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); + + if (entry) { + cfg->iotlb_hits++; + trace_smmu_iotlb_lookup_hit(cfg->asid, iova, + cfg->iotlb_hits, cfg->iotlb_misses, + 100 * cfg->iotlb_hits / + (cfg->iotlb_hits + cfg->iotlb_misses)); + } else { + cfg->iotlb_misses++; + trace_smmu_iotlb_lookup_miss(cfg->asid, iova, + cfg->iotlb_hits, cfg->iotlb_misses, + 100 * cfg->iotlb_hits / + (cfg->iotlb_hits + cfg->iotlb_misses)= ); + } + return entry; +} + +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try) +{ + SMMUIOTLBKey *key =3D g_new0(SMMUIOTLBKey, 1); + + if (g_hash_table_size(bs->iotlb) >=3D SMMU_IOTLB_MAX_SIZE) { + smmu_iotlb_inv_all(bs); + } + + key->asid =3D cfg->asid; + key->iova =3D entry->iova; + trace_smmu_iotlb_insert(cfg->asid, entry->iova); + g_hash_table_insert(bs->iotlb, key, entry); +} + inline void smmu_iotlb_inv_all(SMMUState *s) { trace_smmu_iotlb_inv_all(); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 57a79df55b..cd2a2e7e14 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -636,7 +636,6 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, .addr_mask =3D ~(hwaddr)0, .perm =3D IOMMU_NONE, }; - SMMUIOTLBKey key, *new_key; =20 qemu_mutex_lock(&s->mutex); =20 @@ -675,16 +674,8 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, page_mask =3D (1ULL << (tt->granule_sz)) - 1; aligned_addr =3D addr & ~page_mask; =20 - key.asid =3D cfg->asid; - key.iova =3D aligned_addr; - - cached_entry =3D g_hash_table_lookup(bs->iotlb, &key); + cached_entry =3D smmu_iotlb_lookup(bs, cfg, aligned_addr); if (cached_entry) { - cfg->iotlb_hits++; - trace_smmu_iotlb_cache_hit(cfg->asid, aligned_addr, - cfg->iotlb_hits, cfg->iotlb_misses, - 100 * cfg->iotlb_hits / - (cfg->iotlb_hits + cfg->iotlb_misses)); if ((flag & IOMMU_WO) && !(cached_entry->perm & IOMMU_WO)) { status =3D SMMU_TRANS_ERROR; if (event.record_trans_faults) { @@ -698,16 +689,6 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, goto epilogue; } =20 - cfg->iotlb_misses++; - trace_smmu_iotlb_cache_miss(cfg->asid, addr & ~page_mask, - cfg->iotlb_hits, cfg->iotlb_misses, - 100 * cfg->iotlb_hits / - (cfg->iotlb_hits + cfg->iotlb_misses)); - - if (g_hash_table_size(bs->iotlb) >=3D SMMU_IOTLB_MAX_SIZE) { - smmu_iotlb_inv_all(bs); - } - cached_entry =3D g_new0(IOMMUTLBEntry, 1); =20 if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { @@ -753,10 +734,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, } status =3D SMMU_TRANS_ERROR; } else { - new_key =3D g_new0(SMMUIOTLBKey, 1); - new_key->asid =3D cfg->asid; - new_key->iova =3D aligned_addr; - g_hash_table_insert(bs->iotlb, new_key, cached_entry); + smmu_iotlb_insert(bs, cfg, cached_entry); status =3D SMMU_TRANS_SUCCESS; } =20 diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 0acedcedc6..b808a1bfc1 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -14,6 +14,9 @@ smmu_iotlb_inv_all(void) "IOTLB invalidate all" smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=3D%d" smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid= =3D%d addr=3D0x%"PRIx64 smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" +smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t= miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%d m= iss=3D%d hit rate=3D%d" +smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_= t miss, uint32_t p) "IOTLB cache MISS asid=3D%d addr=3D0x%"PRIx64" hit=3D%d= miss=3D%d hit rate=3D%d" +smmu_iotlb_insert(uint16_t asid, uint64_t addr) "IOTLB ++ asid=3D%d addr= =3D0x%"PRIx64 =20 # smmuv3.c smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "= addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" @@ -46,8 +49,6 @@ smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr,= bool leaf) "vmid =3D%d a smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =3D%d addr=3D0x%"PR= Ix64 smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" -smmu_iotlb_cache_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t = miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%d mi= ss=3D%d hit rate=3D%d" -smmu_iotlb_cache_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t= miss, uint32_t p) "IOTLB cache MISS asid=3D%d addr=3D0x%"PRIx64" hit=3D%d = miss=3D%d hit rate=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" --=20 2.20.1 From nobody Sat Apr 20 13:22:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=Xhpy5/KHWu7f7iBNn50umu1Z55N8FKEPXHzp1efxKzw=; b=QpOe7hYtdVQ8phZYlbIEKz4lEzFIZy/tfccJWzocNluPYyvC9dy61dFvbtj7P+7UP47kwJ 6uT4huVXlfSJHjnE4+c4J5tGhCDh1dO4XgH+UoESU3oAXBjcC+le/LkYCh11lNRUoObRax qS34cwvl6kIgMt8S3CWJfK+p9fHfJlI= X-MC-Unique: PCw5C86lNgSEPAipt1THbA-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH 3/9] hw/arm/smmu: Simplify the IOTLB key format Date: Thu, 21 May 2020 11:10:53 +0200 Message-Id: <20200521091059.9453-4-eric.auger@redhat.com> In-Reply-To: <20200521091059.9453-1-eric.auger@redhat.com> References: <20200521091059.9453-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Instead of using a Jenkins hash function to generate the key let's just use a 64 bit unsigned integer that contains the asid and the 40 upper bits of the iova. A maximum of 52-bit IOVA is supported. This change in the key format also prepares for the addition of new fields in subsequent patches (granule and level). Signed-off-by: Eric Auger --- hw/arm/smmu-internal.h | 4 +++ include/hw/arm/smmu-common.h | 6 +--- hw/arm/smmu-common.c | 53 ++++++++++++++---------------------- 3 files changed, 26 insertions(+), 37 deletions(-) diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index 7794d6d394..2ecb6f1dc6 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -96,4 +96,8 @@ uint64_t iova_level_offset(uint64_t iova, int inputsize, MAKE_64BIT_MASK(0, gsz - 3); } =20 +#define SMMU_IOTLB_ASID_SHIFT 40 + +#define SMMU_IOTLB_ASID(key) (((key) >> SMMU_IOTLB_ASID_SHIFT) & 0xFFFF) +#define SMMU_IOTLB_IOVA(key) (((key) & MAKE_64BIT_MASK(0, 40)) << 12) #endif diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 1dceec5cb1..7b9d2f0eb7 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -88,11 +88,6 @@ typedef struct SMMUPciBus { SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc= */ } SMMUPciBus; =20 -typedef struct SMMUIOTLBKey { - uint64_t iova; - uint16_t asid; -} SMMUIOTLBKey; - typedef struct SMMUState { /* */ SysBusDevice dev; @@ -155,6 +150,7 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t= sid); =20 IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr = iova); void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try); +uint64_t smmu_get_iotlb_key(uint16_t asid, uint64_t iova); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 8409de052d..3101043540 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -32,10 +32,25 @@ =20 /* IOTLB Management */ =20 +static guint smmu_iotlb_key_hash(gconstpointer v) +{ + return (guint)*(const uint64_t *)v; +} + +static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2) +{ + return *((const uint64_t *)v1) =3D=3D *((const uint64_t *)v2); +} + +uint64_t smmu_get_iotlb_key(uint16_t asid, uint64_t iova) +{ + return iova >> 12 | (uint64_t)(asid) << SMMU_IOTLB_ASID_SHIFT; +} + IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr iova) { - SMMUIOTLBKey key =3D {.asid =3D cfg->asid, .iova =3D iova}; + uint64_t key =3D smmu_get_iotlb_key(cfg->asid, iova); IOMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); =20 if (entry) { @@ -56,14 +71,13 @@ IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTra= nsCfg *cfg, =20 void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try) { - SMMUIOTLBKey *key =3D g_new0(SMMUIOTLBKey, 1); + uint64_t *key =3D g_new0(uint64_t, 1); =20 if (g_hash_table_size(bs->iotlb) >=3D SMMU_IOTLB_MAX_SIZE) { smmu_iotlb_inv_all(bs); } =20 - key->asid =3D cfg->asid; - key->iova =3D entry->iova; + *key =3D smmu_get_iotlb_key(cfg->asid, entry->iova); trace_smmu_iotlb_insert(cfg->asid, entry->iova); g_hash_table_insert(bs->iotlb, key, entry); } @@ -78,14 +92,14 @@ static gboolean smmu_hash_remove_by_asid(gpointer key, = gpointer value, gpointer user_data) { uint16_t asid =3D *(uint16_t *)user_data; - SMMUIOTLBKey *iotlb_key =3D (SMMUIOTLBKey *)key; + uint64_t *iotlb_key =3D (uint64_t *)key; =20 - return iotlb_key->asid =3D=3D asid; + return SMMU_IOTLB_ASID(*iotlb_key) =3D=3D asid; } =20 inline void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t io= va) { - SMMUIOTLBKey key =3D {.asid =3D asid, .iova =3D iova}; + uint64_t key =3D smmu_get_iotlb_key(asid, iova); =20 trace_smmu_iotlb_inv_iova(asid, iova); g_hash_table_remove(s->iotlb, &key); @@ -382,31 +396,6 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_= t sid) return NULL; } =20 -static guint smmu_iotlb_key_hash(gconstpointer v) -{ - SMMUIOTLBKey *key =3D (SMMUIOTLBKey *)v; - uint32_t a, b, c; - - /* Jenkins hash */ - a =3D b =3D c =3D JHASH_INITVAL + sizeof(*key); - a +=3D key->asid; - b +=3D extract64(key->iova, 0, 32); - c +=3D extract64(key->iova, 32, 32); - - __jhash_mix(a, b, c); - __jhash_final(a, b, c); - - return c; -} - -static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2) -{ - const SMMUIOTLBKey *k1 =3D v1; - const SMMUIOTLBKey *k2 =3D v2; - - return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova); -} - /* Unmap the whole notifier's range */ static void smmu_unmap_notifier_range(IOMMUNotifier *n) { --=20 2.20.1 From nobody Sat Apr 20 13:22:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1590052370; cv=none; d=zohomail.com; s=zohoarc; b=fW6Z6xU46vIxoKY3E/0dccno4g81Xi1iOuZESuO6ZiwCkDoX8QWE6UNvtr1Cymg9Nx9IVTjpgoDWh3q/ivQtsH35lL9K37SFJbCIqsdoOvtkkfmGMevsRVRvz0oVJCn+/QZHwlJDlUboq/WVaaNEko2BlgrbD4f7RVsPKqKzbWY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1590052370; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1590052306; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1czAJ1x/IV6ed1bEr1v7sbxUSM/1M7JNSIvpPOu9AnM=; b=fRO9Hdn9wN8cAZm5yWghbmZXS1qijaRC0FR6r2yGjNV0rjTJQtTAWTWi/O9GO7nD4wTxQr OtaPH/1oKKUchZ9wq1fm1HP33tSrmbWmHA6DYbmzyBovlWbsxnzB307SJRbJnuJsb9HSmC 1vPGiH5ijU7KJabUzkLpjUsbBdiZP2E= X-MC-Unique: vYGYtdXmMUCtSkWSzXc-hQ-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH 4/9] hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value Date: Thu, 21 May 2020 11:10:54 +0200 Message-Id: <20200521091059.9453-5-eric.auger@redhat.com> In-Reply-To: <20200521091059.9453-1-eric.auger@redhat.com> References: <20200521091059.9453-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Introduce a specialized SMMUTLBEntry to store the result of the PTW and cache in the IOTLB. This structure extends the generic IOMMUTLBEntry struct with the level of the entry and the granule size. Those latter will be useful when implementing range invalidation. Signed-off-by: Eric Auger --- include/hw/arm/smmu-common.h | 14 +++++++++++--- hw/arm/smmu-common.c | 30 ++++++++++++++++-------------- hw/arm/smmuv3.c | 10 +++++----- 3 files changed, 32 insertions(+), 22 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 7b9d2f0eb7..f6ee78e16c 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -52,6 +52,14 @@ typedef struct SMMUTransTableInfo { uint8_t granule_sz; /* granule page shift */ } SMMUTransTableInfo; =20 +struct SMMUTLBEntry { + IOMMUTLBEntry entry; + uint8_t level; + uint8_t granule; +}; + +typedef struct SMMUTLBEntry SMMUTLBEntry; + /* * Generic structure populated by derived SMMU devices * after decoding the configuration information and used as @@ -135,7 +143,7 @@ static inline uint16_t smmu_get_sid(SMMUDevice *sdev) * pair, according to @cfg translation config */ int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, - IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); =20 /** * select_tt - compute which translation table shall be used according to @@ -148,8 +156,8 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t= sid); =20 #define SMMU_IOTLB_MAX_SIZE 256 =20 -IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr = iova); -void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try); +SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr i= ova); +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *ent= ry); uint64_t smmu_get_iotlb_key(uint16_t asid, uint64_t iova); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 3101043540..aa88b62efb 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -47,11 +47,11 @@ uint64_t smmu_get_iotlb_key(uint16_t asid, uint64_t iov= a) return iova >> 12 | (uint64_t)(asid) << SMMU_IOTLB_ASID_SHIFT; } =20 -IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, +SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr iova) { uint64_t key =3D smmu_get_iotlb_key(cfg->asid, iova); - IOMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); + SMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); =20 if (entry) { cfg->iotlb_hits++; @@ -69,7 +69,7 @@ IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTrans= Cfg *cfg, return entry; } =20 -void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try) +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new) { uint64_t *key =3D g_new0(uint64_t, 1); =20 @@ -77,9 +77,9 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, = IOMMUTLBEntry *entry) smmu_iotlb_inv_all(bs); } =20 - *key =3D smmu_get_iotlb_key(cfg->asid, entry->iova); - trace_smmu_iotlb_insert(cfg->asid, entry->iova); - g_hash_table_insert(bs->iotlb, key, entry); + *key =3D smmu_get_iotlb_key(cfg->asid, new->entry.iova); + trace_smmu_iotlb_insert(cfg->asid, new->entry.iova); + g_hash_table_insert(bs->iotlb, key, new); } =20 inline void smmu_iotlb_inv_all(SMMUState *s) @@ -199,7 +199,7 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_ad= dr_t iova) * @cfg: translation config * @iova: iova to translate * @perm: access type - * @tlbe: IOMMUTLBEntry (out) + * @tlbe: SMMUTLBEntry (out) * @info: handle to an error info * * Return 0 on success, < 0 on error. In case of error, @info is filled @@ -209,7 +209,7 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_ad= dr_t iova) */ static int smmu_ptw_64(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, - IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { dma_addr_t baseaddr, indexmask; int stage =3D cfg->stage; @@ -229,8 +229,8 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, baseaddr =3D extract64(tt->ttb, 0, 48); baseaddr &=3D ~indexmask; =20 - tlbe->iova =3D iova; - tlbe->addr_mask =3D (1 << granule_sz) - 1; + tlbe->entry.iova =3D iova; + tlbe->entry.addr_mask =3D (1 << granule_sz) - 1; =20 while (level <=3D 3) { uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); @@ -281,13 +281,15 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, goto error; } =20 - tlbe->translated_addr =3D gpa + (iova & mask); - tlbe->perm =3D PTE_AP_TO_PERM(ap); + tlbe->entry.translated_addr =3D gpa + (iova & mask); + tlbe->entry.perm =3D PTE_AP_TO_PERM(ap); + tlbe->level =3D level; + tlbe->granule =3D granule_sz; return 0; } info->type =3D SMMU_PTW_ERR_TRANSLATION; error: - tlbe->perm =3D IOMMU_NONE; + tlbe->entry.perm =3D IOMMU_NONE; return -EINVAL; } =20 @@ -303,7 +305,7 @@ error: * return 0 on success */ inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags p= erm, - IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { if (!cfg->aa64) { /* diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index cd2a2e7e14..db74d27add 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -626,7 +626,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, SMMUTranslationStatus status; SMMUState *bs =3D ARM_SMMU(s); uint64_t page_mask, aligned_addr; - IOMMUTLBEntry *cached_entry =3D NULL; + SMMUTLBEntry *cached_entry =3D NULL; SMMUTransTableInfo *tt; SMMUTransCfg *cfg =3D NULL; IOMMUTLBEntry entry =3D { @@ -676,7 +676,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, =20 cached_entry =3D smmu_iotlb_lookup(bs, cfg, aligned_addr); if (cached_entry) { - if ((flag & IOMMU_WO) && !(cached_entry->perm & IOMMU_WO)) { + if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { status =3D SMMU_TRANS_ERROR; if (event.record_trans_faults) { event.type =3D SMMU_EVT_F_PERMISSION; @@ -689,7 +689,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, goto epilogue; } =20 - cached_entry =3D g_new0(IOMMUTLBEntry, 1); + cached_entry =3D g_new0(SMMUTLBEntry, 1); =20 if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { g_free(cached_entry); @@ -743,9 +743,9 @@ epilogue: switch (status) { case SMMU_TRANS_SUCCESS: entry.perm =3D flag; - entry.translated_addr =3D cached_entry->translated_addr + + entry.translated_addr =3D cached_entry->entry.translated_addr + (addr & page_mask); - entry.addr_mask =3D cached_entry->addr_mask; + entry.addr_mask =3D cached_entry->entry.addr_mask; trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr, entry.translated_addr, entry.perm); break; --=20 2.20.1 From nobody Sat Apr 20 13:22:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=OPtBcos55hsUQYrVViHHdkNlrTJev7hV9hkjAaBxS9A=; b=CqMaJMlhCBqcRMqflv8ke4n+Dbh6lDo46+hkYpSWf//2IsRogS1YZeE+ncbq3bIdnq4hr/ ri+bMIwmeTLdNxBOwwaFwY3mgE/gJA+LPd/8qdqOqDNA3JpamVBTLh5XMqDE0xZUAjLK/w ZBoGUb3G9zij6nzmX1gSZSSFOfEGYxg= X-MC-Unique: KA3lIE9BN8a6pRHpEHxq9w-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH 5/9] hw/arm/smmuv3: Store the starting level in SMMUTransTableInfo Date: Thu, 21 May 2020 11:10:55 +0200 Message-Id: <20200521091059.9453-6-eric.auger@redhat.com> In-Reply-To: <20200521091059.9453-1-eric.auger@redhat.com> References: <20200521091059.9453-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Compute the starting level on CD decoding and store it into SMMUTransTableInfo. We will need this information on IOTLB lookup so let's avoid to recompute it each time. Signed-off-by: Eric Auger --- include/hw/arm/smmu-common.h | 1 + hw/arm/smmu-common.c | 2 +- hw/arm/smmuv3.c | 8 ++++++-- hw/arm/trace-events | 2 +- 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index f6ee78e16c..676e53c086 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -50,6 +50,7 @@ typedef struct SMMUTransTableInfo { uint64_t ttb; /* TT base address */ uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/ uint8_t granule_sz; /* granule page shift */ + uint8_t starting_level; /* starting level */ } SMMUTransTableInfo; =20 struct SMMUTLBEntry { diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index aa88b62efb..c2ed8346fb 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -224,7 +224,7 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, granule_sz =3D tt->granule_sz; stride =3D granule_sz - 3; inputsize =3D 64 - tt->tsz; - level =3D 4 - (inputsize - 4) / stride; + level =3D tt->starting_level; indexmask =3D (1ULL << (inputsize - (stride * (4 - level)))) - 1; baseaddr =3D extract64(tt->ttb, 0, 48); baseaddr &=3D ~indexmask; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index db74d27add..12d3e972d6 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -482,7 +482,7 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEve= ntInfo *event) =20 /* decode data dependent on TT */ for (i =3D 0; i <=3D 1; i++) { - int tg, tsz; + int tg, tsz, input_size, stride; SMMUTransTableInfo *tt =3D &cfg->tt[i]; =20 cfg->tt[i].disabled =3D CD_EPD(cd, i); @@ -502,11 +502,15 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUE= ventInfo *event) } =20 tt->tsz =3D tsz; + input_size =3D 64 - tt->tsz; + stride =3D tt->granule_sz - 3; tt->ttb =3D CD_TTB(cd, i); if (tt->ttb & ~(MAKE_64BIT_MASK(0, cfg->oas))) { goto bad_cd; } - trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz); + tt->starting_level =3D 4 - (input_size - 4) / stride; + trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, + tt->granule_sz, tt->starting_level); } =20 event->record_trans_faults =3D CD_R(cd); diff --git a/hw/arm/trace-events b/hw/arm/trace-events index b808a1bfc1..7263b9c586 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -39,7 +39,7 @@ smmuv3_translate_abort(const char *n, uint16_t sid, uint6= 4_t addr, bool is_write smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint6= 4_t translated, int perm) "%s sid=3D%d iova=3D0x%"PRIx64" translated=3D0x%"= PRIx64" perm=3D0x%x" smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64 smmuv3_decode_cd(uint32_t oas) "oas=3D%d" -smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz= ) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d" +smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz= , uint8_t starting_level) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d star= ting_level=3D%d" smmuv3_cmdq_cfgi_ste(int streamid) "streamid =3D%d" smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D0x%d - end=3D0x%d" smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d" --=20 2.20.1 From nobody Sat Apr 20 13:22:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=0vYMi+kgVnD/ZFNncBOFCqHi5dc2slD8n10tuwHQGQo=; b=OKxtCerIcLUmnQD1fSKqXgE/XjwvGmRQdUTKs3x4cC/NZC7vIsV5lZI5NWv6CBwa/fCJXu Mf0C7Wr7fAYew6jRR4umH63QOs4DNerx3H0oIBFprbRt+8eKqiUhh3k4OXPXJ6FzEwdiXi grTxnVU5VWLfA3x9qBm3mplgZeIJDK4= X-MC-Unique: scbFFwPJPxmNkZgXeJBJeA-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH 6/9] hw/arm/smmu-common: Manage IOTLB block entries Date: Thu, 21 May 2020 11:10:56 +0200 Message-Id: <20200521091059.9453-7-eric.auger@redhat.com> In-Reply-To: <20200521091059.9453-1-eric.auger@redhat.com> References: <20200521091059.9453-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" At the moment each entry in the IOTLB corresponds to a page sized mapping (4K, 16K or 64K), even if the page belongs to a mapped block. In case of block mapping this unefficiently consume IOTLB entries. Change the value of the entry so that it reflects the actual mapping it belongs to (block or page start address and size). Also the level/tg of the entry is encoded in the key. In subsequent patches we will enable range invalidation. This latter is able to provide the level/tg of the entry. Signed-off-by: Eric Auger --- hw/arm/smmu-internal.h | 10 ++++++ include/hw/arm/smmu-common.h | 8 +++-- hw/arm/smmu-common.c | 61 +++++++++++++++++++++++++++--------- hw/arm/smmuv3.c | 6 ++-- hw/arm/trace-events | 2 +- 5 files changed, 66 insertions(+), 21 deletions(-) diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index 2ecb6f1dc6..f60b48dc9b 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -97,7 +97,17 @@ uint64_t iova_level_offset(uint64_t iova, int inputsize, } =20 #define SMMU_IOTLB_ASID_SHIFT 40 +#define SMMU_IOTLB_LEVEL_SHIFT 56 +#define SMMU_IOTLB_TG_SHIFT 58 =20 #define SMMU_IOTLB_ASID(key) (((key) >> SMMU_IOTLB_ASID_SHIFT) & 0xFFFF) #define SMMU_IOTLB_IOVA(key) (((key) & MAKE_64BIT_MASK(0, 40)) << 12) + +struct SMMUIOTLBPageInvInfo { + int asid; + uint64_t iova; + uint64_t mask; +}; +typedef struct SMMUIOTLBPageInvInfo SMMUIOTLBPageInvInfo; + #endif diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 676e53c086..34a13c7cd6 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -157,12 +157,14 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32= _t sid); =20 #define SMMU_IOTLB_MAX_SIZE 256 =20 -SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr i= ova); +SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, + SMMUTransTableInfo *tt, hwaddr iova); void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *ent= ry); -uint64_t smmu_get_iotlb_key(uint16_t asid, uint64_t iova); +uint64_t smmu_get_iotlb_key(uint16_t asid, uint64_t iova, + uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); -void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova); +void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova); =20 /* Unmap the range of all the notifiers registered to any IOMMU mr */ void smmu_inv_notifiers_all(SMMUState *s); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index c2ed8346fb..27804fbb2d 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -42,16 +42,33 @@ static gboolean smmu_iotlb_key_equal(gconstpointer v1, = gconstpointer v2) return *((const uint64_t *)v1) =3D=3D *((const uint64_t *)v2); } =20 -uint64_t smmu_get_iotlb_key(uint16_t asid, uint64_t iova) +uint64_t smmu_get_iotlb_key(uint16_t asid, uint64_t iova, + uint8_t tg, uint8_t level) { - return iova >> 12 | (uint64_t)(asid) << SMMU_IOTLB_ASID_SHIFT; + return iova >> 12 | (uint64_t)(asid) << SMMU_IOTLB_ASID_SHIFT | + (uint64_t)(level) << SMMU_IOTLB_LEVEL_SHIFT | + (uint64_t)(tg) << SMMU_IOTLB_TG_SHIFT; } =20 SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, - hwaddr iova) + SMMUTransTableInfo *tt, hwaddr iova) { - uint64_t key =3D smmu_get_iotlb_key(cfg->asid, iova); - SMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); + uint8_t tg =3D (tt->granule_sz - 10) / 2; + int level =3D tt->starting_level; + SMMUTLBEntry *entry =3D NULL; + + while (level <=3D 3) { + uint64_t subpage_size =3D 1ULL << level_shift(level, tt->granule_s= z); + uint64_t mask =3D subpage_size - 1; + uint64_t key; + + key =3D smmu_get_iotlb_key(cfg->asid, iova & ~mask, tg, level); + entry =3D g_hash_table_lookup(bs->iotlb, &key); + if (entry) { + break; + } + level++; + } =20 if (entry) { cfg->iotlb_hits++; @@ -72,13 +89,14 @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTran= sCfg *cfg, void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new) { uint64_t *key =3D g_new0(uint64_t, 1); + uint8_t tg =3D (new->granule - 10) / 2; =20 if (g_hash_table_size(bs->iotlb) >=3D SMMU_IOTLB_MAX_SIZE) { smmu_iotlb_inv_all(bs); } =20 - *key =3D smmu_get_iotlb_key(cfg->asid, new->entry.iova); - trace_smmu_iotlb_insert(cfg->asid, new->entry.iova); + *key =3D smmu_get_iotlb_key(cfg->asid, new->entry.iova, tg, new->level= ); + trace_smmu_iotlb_insert(cfg->asid, new->entry.iova, tg, new->level); g_hash_table_insert(bs->iotlb, key, new); } =20 @@ -97,12 +115,28 @@ static gboolean smmu_hash_remove_by_asid(gpointer key,= gpointer value, return SMMU_IOTLB_ASID(*iotlb_key) =3D=3D asid; } =20 -inline void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t io= va) +static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value, + gpointer user_data) { - uint64_t key =3D smmu_get_iotlb_key(asid, iova); + SMMUTLBEntry *iter =3D (SMMUTLBEntry *)value; + IOMMUTLBEntry *entry =3D &iter->entry; + SMMUIOTLBPageInvInfo *info =3D (SMMUIOTLBPageInvInfo *)user_data; + uint64_t *iotlb_key =3D (uint64_t *)key; + + if (info->asid >=3D 0) { + return (info->asid =3D=3D SMMU_IOTLB_ASID(*iotlb_key)) && + ((info->iova & ~entry->addr_mask) =3D=3D entry->iova); + } else { + return (info->iova & ~entry->addr_mask) =3D=3D entry->iova; + } +} + +inline void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova) +{ + SMMUIOTLBPageInvInfo info =3D {.asid =3D asid, .iova =3D iova}; =20 trace_smmu_iotlb_inv_iova(asid, iova); - g_hash_table_remove(s->iotlb, &key); + g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid_iova, &= info); } =20 inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) @@ -229,9 +263,6 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, baseaddr =3D extract64(tt->ttb, 0, 48); baseaddr &=3D ~indexmask; =20 - tlbe->entry.iova =3D iova; - tlbe->entry.addr_mask =3D (1 << granule_sz) - 1; - while (level <=3D 3) { uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); uint64_t mask =3D subpage_size - 1; @@ -281,7 +312,9 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, goto error; } =20 - tlbe->entry.translated_addr =3D gpa + (iova & mask); + tlbe->entry.translated_addr =3D gpa; + tlbe->entry.iova =3D iova & ~mask; + tlbe->entry.addr_mask =3D mask; tlbe->entry.perm =3D PTE_AP_TO_PERM(ap); tlbe->level =3D level; tlbe->granule =3D granule_sz; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 12d3e972d6..931a2b6872 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -678,7 +678,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, page_mask =3D (1ULL << (tt->granule_sz)) - 1; aligned_addr =3D addr & ~page_mask; =20 - cached_entry =3D smmu_iotlb_lookup(bs, cfg, aligned_addr); + cached_entry =3D smmu_iotlb_lookup(bs, cfg, tt, aligned_addr); if (cached_entry) { if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { status =3D SMMU_TRANS_ERROR; @@ -748,7 +748,7 @@ epilogue: case SMMU_TRANS_SUCCESS: entry.perm =3D flag; entry.translated_addr =3D cached_entry->entry.translated_addr + - (addr & page_mask); + (addr & cached_entry->entry.addr_mask); entry.addr_mask =3D cached_entry->entry.addr_mask; trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr, entry.translated_addr, entry.perm); @@ -976,7 +976,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) =20 trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr); smmuv3_inv_notifiers_iova(bs, -1, addr); - smmu_iotlb_inv_all(bs); + smmu_iotlb_inv_iova(bs, -1, addr); break; } case SMMU_CMD_TLBI_NH_VA: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 7263b9c586..2d445c99b7 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -16,7 +16,7 @@ smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB = invalidate asid=3D%d addr smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t= miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%d m= iss=3D%d hit rate=3D%d" smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_= t miss, uint32_t p) "IOTLB cache MISS asid=3D%d addr=3D0x%"PRIx64" hit=3D%d= miss=3D%d hit rate=3D%d" -smmu_iotlb_insert(uint16_t asid, uint64_t addr) "IOTLB ++ asid=3D%d addr= =3D0x%"PRIx64 +smmu_iotlb_insert(uint16_t asid, uint64_t addr, uint8_t tg, uint8_t level)= "IOTLB ++ asid=3D%d addr=3D0x%"PRIx64" tg=3D%d level=3D%d" =20 # smmuv3.c smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "= addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" --=20 2.20.1 From nobody Sat Apr 20 13:22:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=ARv8qSDziPHTJvaLmyQIW8b8LLLtOfE1f3+HLmQbobU=; b=J31Tm4jBftk0W4ezRL6PArkLk8bTG4Te1Q2EsUcsGoOH7dGYxq3DiG6kNAh3kMxuxtRVV3 lWHh0FQODiUCxG3J0sCbuWXO+1odEwb8Xg5p9jS9JD9VDKYfkeKNuY1cInUKuWI/JxTKd9 H8LQqosTBOBm50hAW/osdQcuUqqD3VE= X-MC-Unique: TQfVxmaFOqaQ8AUEYaPdmg-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH 7/9] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper Date: Thu, 21 May 2020 11:10:57 +0200 Message-Id: <20200521091059.9453-8-eric.auger@redhat.com> In-Reply-To: <20200521091059.9453-1-eric.auger@redhat.com> References: <20200521091059.9453-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Let's introduce an helper for S1 IOVA range invalidation. This will be used for NH_VA and NH_VAA commands. It decodes the same fields, trace, calls the UNMAP notifiers and invalidate the corresponding IOTLB entries. At the moment, we do not support 3.2 range invalidation yet. So it reduces to a single IOVA invalidation. Signed-off-by: Eric Auger --- hw/arm/smmuv3.c | 36 +++++++++++++++++------------------- hw/arm/trace-events | 3 +-- 2 files changed, 18 insertions(+), 21 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 931a2b6872..4eda16be7b 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -840,6 +840,22 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, in= t asid, dma_addr_t iova) } } =20 +static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) +{ + dma_addr_t addr =3D CMD_ADDR(cmd); + uint8_t type =3D CMD_TYPE(cmd); + uint16_t vmid =3D CMD_VMID(cmd); + bool leaf =3D CMD_LEAF(cmd); + int asid =3D -1; + + if (type =3D=3D SMMU_CMD_TLBI_NH_VA) { + asid =3D CMD_ASID(cmd); + } + trace_smmuv3_s1_range_inval(vmid, asid, addr, leaf); + smmuv3_inv_notifiers_iova(s, asid, addr); + smmu_iotlb_inv_iova(s, asid, addr); +} + static int smmuv3_cmdq_consume(SMMUv3State *s) { SMMUState *bs =3D ARM_SMMU(s); @@ -970,27 +986,9 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) smmu_iotlb_inv_all(bs); break; case SMMU_CMD_TLBI_NH_VAA: - { - dma_addr_t addr =3D CMD_ADDR(&cmd); - uint16_t vmid =3D CMD_VMID(&cmd); - - trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr); - smmuv3_inv_notifiers_iova(bs, -1, addr); - smmu_iotlb_inv_iova(bs, -1, addr); - break; - } case SMMU_CMD_TLBI_NH_VA: - { - uint16_t asid =3D CMD_ASID(&cmd); - uint16_t vmid =3D CMD_VMID(&cmd); - dma_addr_t addr =3D CMD_ADDR(&cmd); - bool leaf =3D CMD_LEAF(&cmd); - - trace_smmuv3_cmdq_tlbi_nh_va(vmid, asid, addr, leaf); - smmuv3_inv_notifiers_iova(bs, asid, addr); - smmu_iotlb_inv_iova(bs, asid, addr); + smmuv3_s1_range_inval(bs, &cmd); break; - } case SMMU_CMD_TLBI_EL3_ALL: case SMMU_CMD_TLBI_EL3_VA: case SMMU_CMD_TLBI_EL2_ALL: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 2d445c99b7..b366973739 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -45,8 +45,7 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D0= x%d - end=3D0x%d" smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" -smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr, bool leaf) "vmid= =3D%d asid =3D%d addr=3D0x%"PRIx64" leaf=3D%d" -smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =3D%d addr=3D0x%"PR= Ix64 +smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, bool leaf) "vmid = =3D%d asid =3D%d addr=3D0x%"PRIx64" leaf=3D%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" --=20 2.20.1 From nobody Sat Apr 20 13:22:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=28JeEQFaQKpR65Fvr4h2OzB54px8vEV5aJWYpQDbyYY=; b=N6InNOKV0TJAeeFba1VKdivgnEodze9s1A4WO/c1f7umqTzsMRecN6MTZ0cTnGqwsqSNlZ wm/ttyEayZxWIi6ANmZwy02pRg5B02Mmx1sQ7fJdLxlan0PH6yp6f6lJzhs++g3ybb2PRJ WHCIdaBj0n7j/5CL0BTrlLyQPsKq0D0= X-MC-Unique: SfmX2BWhNwChuhBrSQN2oA-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH 8/9] hw/arm/smmuv3: Get prepared for range invalidation Date: Thu, 21 May 2020 11:10:58 +0200 Message-Id: <20200521091059.9453-9-eric.auger@redhat.com> In-Reply-To: <20200521091059.9453-1-eric.auger@redhat.com> References: <20200521091059.9453-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Enhance the smmu_iotlb_inv_iova() helper with range invalidation. This uses the new fields passed in the NH_VA and NH_VAA commands: the size of the range, the level and the granule. As NH_VA and NH_VAA both use those fields, their decoding and handling is factorized in a new smmuv3_s1_range_inval() helper. Signed-off-by: Eric Auger --- hw/arm/smmuv3-internal.h | 4 +++ include/hw/arm/smmu-common.h | 3 +- hw/arm/smmu-common.c | 28 ++++++++++++---- hw/arm/smmuv3.c | 64 +++++++++++++++++++++++------------- hw/arm/trace-events | 4 +-- 5 files changed, 71 insertions(+), 32 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 4112394129..5babf72f7d 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -298,6 +298,8 @@ enum { /* Command completion notification */ }; =20 #define CMD_TYPE(x) extract32((x)->word[0], 0 , 8) +#define CMD_NUM(x) extract32((x)->word[0], 12 , 5) +#define CMD_SCALE(x) extract32((x)->word[0], 20 , 5) #define CMD_SSEC(x) extract32((x)->word[0], 10, 1) #define CMD_SSV(x) extract32((x)->word[0], 11, 1) #define CMD_RESUME_AC(x) extract32((x)->word[0], 12, 1) @@ -310,6 +312,8 @@ enum { /* Command completion notification */ #define CMD_RESUME_STAG(x) extract32((x)->word[2], 0 , 16) #define CMD_RESP(x) extract32((x)->word[2], 11, 2) #define CMD_LEAF(x) extract32((x)->word[2], 0 , 1) +#define CMD_TTL(x) extract32((x)->word[2], 8 , 2) +#define CMD_TG(x) extract32((x)->word[2], 10, 2) #define CMD_STE_RANGE(x) extract32((x)->word[2], 0 , 5) #define CMD_ADDR(x) ({ \ uint64_t high =3D (uint64_t)(x)->word[3]; \ diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 34a13c7cd6..6dd638a485 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -164,7 +164,8 @@ uint64_t smmu_get_iotlb_key(uint16_t asid, uint64_t iov= a, uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); -void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova); +void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, + uint8_t tg, uint64_t num_pages, uint8_t ttl); =20 /* Unmap the range of all the notifiers registered to any IOMMU mr */ void smmu_inv_notifiers_all(SMMUState *s); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 27804fbb2d..0a86afe69d 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -125,18 +125,34 @@ static gboolean smmu_hash_remove_by_asid_iova(gpointe= r key, gpointer value, =20 if (info->asid >=3D 0) { return (info->asid =3D=3D SMMU_IOTLB_ASID(*iotlb_key)) && - ((info->iova & ~entry->addr_mask) =3D=3D entry->iova); + (((entry->iova & ~info->mask) =3D=3D info->iova) || + ((info->iova & ~entry->addr_mask) =3D=3D entry->iova)); } else { - return (info->iova & ~entry->addr_mask) =3D=3D entry->iova; + return (((entry->iova & ~info->mask) =3D=3D info->iova) || + ((info->iova & ~entry->addr_mask) =3D=3D entry->iova)); } } =20 -inline void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova) +inline void +smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, + uint8_t tg, uint64_t num_pages, uint8_t ttl) { - SMMUIOTLBPageInvInfo info =3D {.asid =3D asid, .iova =3D iova}; + if (ttl && (num_pages =3D=3D 1)) { + uint64_t key =3D smmu_get_iotlb_key(asid, iova, tg, ttl); =20 - trace_smmu_iotlb_inv_iova(asid, iova); - g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid_iova, &= info); + g_hash_table_remove(s->iotlb, &key); + } else { + /* if tg is not set we use 4KB range invalidation */ + uint8_t granule =3D tg ? tg * 2 + 10 : 12; + + SMMUIOTLBPageInvInfo info =3D { + .asid =3D asid, .iova =3D iova, + .mask =3D (num_pages * 1 << granule) - 1}; + + g_hash_table_foreach_remove(s->iotlb, + smmu_hash_remove_by_asid_iova, + &info); + } } =20 inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 4eda16be7b..4dff438809 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -789,42 +789,49 @@ epilogue: * @n: notifier to be called * @asid: address space ID or negative value if we don't care * @iova: iova + * @tg: translation granule (if communicated through range invalidation) + * @num_pages: number of @granule sized pages (if tg !=3D 0), otherwise 1 */ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, IOMMUNotifier *n, - int asid, - dma_addr_t iova) + int asid, dma_addr_t iova, + uint8_t tg, uint64_t num_pages) { SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); - SMMUEventInfo event =3D {.inval_ste_allowed =3D true}; - SMMUTransTableInfo *tt; - SMMUTransCfg *cfg; IOMMUTLBEntry entry; + uint8_t granule =3D tg; =20 - cfg =3D smmuv3_get_config(sdev, &event); - if (!cfg) { - return; - } + if (!tg) { + SMMUEventInfo event =3D {.inval_ste_allowed =3D true}; + SMMUTransCfg *cfg =3D smmuv3_get_config(sdev, &event); + SMMUTransTableInfo *tt; =20 - if (asid >=3D 0 && cfg->asid !=3D asid) { - return; - } + if (!cfg) { + return; + } =20 - tt =3D select_tt(cfg, iova); - if (!tt) { - return; + if (asid >=3D 0 && cfg->asid !=3D asid) { + return; + } + + tt =3D select_tt(cfg, iova); + if (!tt) { + return; + } + granule =3D tt->granule_sz; } =20 entry.target_as =3D &address_space_memory; entry.iova =3D iova; - entry.addr_mask =3D (1 << tt->granule_sz) - 1; + entry.addr_mask =3D num_pages * (1 << granule) - 1; entry.perm =3D IOMMU_NONE; =20 memory_region_notify_one(n, &entry); } =20 -/* invalidate an asid/iova tuple in all mr's */ -static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t i= ova) +/* invalidate an asid/iova range tuple in all mr's */ +static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t i= ova, + uint8_t tg, uint64_t num_pages) { SMMUDevice *sdev; =20 @@ -832,28 +839,39 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, i= nt asid, dma_addr_t iova) IOMMUMemoryRegion *mr =3D &sdev->iommu; IOMMUNotifier *n; =20 - trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova); + trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova, + tg, num_pages); =20 IOMMU_NOTIFIER_FOREACH(n, mr) { - smmuv3_notify_iova(mr, n, asid, iova); + smmuv3_notify_iova(mr, n, asid, iova, tg, num_pages); } } } =20 static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) { + uint8_t scale =3D 0, num =3D 0, ttl =3D 0; dma_addr_t addr =3D CMD_ADDR(cmd); uint8_t type =3D CMD_TYPE(cmd); uint16_t vmid =3D CMD_VMID(cmd); bool leaf =3D CMD_LEAF(cmd); + uint8_t tg =3D CMD_TG(cmd); + hwaddr num_pages =3D 1; int asid =3D -1; =20 + if (tg) { + scale =3D CMD_SCALE(cmd); + num =3D CMD_NUM(cmd); + ttl =3D CMD_TTL(cmd); + num_pages =3D (num + 1) * (1 << (scale)); + } + if (type =3D=3D SMMU_CMD_TLBI_NH_VA) { asid =3D CMD_ASID(cmd); } - trace_smmuv3_s1_range_inval(vmid, asid, addr, leaf); - smmuv3_inv_notifiers_iova(s, asid, addr); - smmu_iotlb_inv_iova(s, asid, addr); + trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf= ); + smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); + smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl); } =20 static int smmuv3_cmdq_consume(SMMUv3State *s) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index b366973739..c47943f1c7 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -45,11 +45,11 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start= =3D0x%d - end=3D0x%d" smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" -smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, bool leaf) "vmid = =3D%d asid =3D%d addr=3D0x%"PRIx64" leaf=3D%d" +smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint6= 4_t num_pages, uint8_t ttl, bool leaf) "vmid =3D%d asid =3D%d addr=3D0x%"PR= Ix64" tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" -smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova) = "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64 +smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, = uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64 =20 --=20 2.20.1 From nobody Sat Apr 20 13:22:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=b9hGE1kZUZvCbnSbzRYkY+Xwj8Z7keAHPfrl7Jr1YeY=; b=G3bnGAEXiQ9g8IekYf9SUBDWVDKQakrjV0cir2bLPva5yfh2aWlVwJmEii87EvlWW0c4W7 sCjzp96jarRi0TS6lIYntN8TtsRHf7Ce7cHo622ACi7o87nm8tDuslCVEYDKM8tmq3YxO+ o3vcXimjlNcl1MQIvpivoV6tN4bMw7Y= X-MC-Unique: FgeXcZFRPuipx40Q3TG5Tw-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH 9/9] hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation Date: Thu, 21 May 2020 11:10:59 +0200 Message-Id: <20200521091059.9453-10-eric.auger@redhat.com> In-Reply-To: <20200521091059.9453-1-eric.auger@redhat.com> References: <20200521091059.9453-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Expose the RIL bit so that the guest driver uses range invalidation. Signed-off-by: Eric Auger --- hw/arm/smmuv3-internal.h | 1 + hw/arm/smmuv3.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 5babf72f7d..4e7ec252ed 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -54,6 +54,7 @@ REG32(IDR1, 0x4) =20 REG32(IDR2, 0x8) REG32(IDR3, 0xc) + FIELD(IDR3, RIL, 10, 1); REG32(IDR4, 0x10) REG32(IDR5, 0x14) FIELD(IDR5, OAS, 0, 3); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 4dff438809..78920f5158 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -254,6 +254,8 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS); s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS); =20 + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 1); + /* 4K and 64K granule support */ s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); --=20 2.20.1