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That's all we know. X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@syrmia.com, Aleksandar Markovic Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" Use consistently 'l' and 'h' for low and high halves. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic --- target/mips/fpu_helper.c | 62 ++++++++++++++++++++-------------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 56ba49104e..dbb8ca5692 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1059,14 +1059,14 @@ uint32_t helper_float_recip1_s(CPUMIPSState *env, u= int32_t fst0) =20 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) { - uint32_t fst2; + uint32_t fstl2; uint32_t fsth2; =20 - fst2 =3D float32_div(float32_one, fdt0 & 0XFFFFFFFF, - &env->active_fpu.fp_status); + fstl2 =3D float32_div(float32_one, fdt0 & 0XFFFFFFFF, + &env->active_fpu.fp_status); fsth2 =3D float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_sta= tus); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } =20 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) @@ -1091,15 +1091,15 @@ uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, u= int32_t fst0) =20 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) { - uint32_t fst2; + uint32_t fstl2; uint32_t fsth2; =20 - fst2 =3D float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + fstl2 =3D float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 =3D float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); - fst2 =3D float32_div(float32_one, fst2, &env->active_fpu.fp_status); + fstl2 =3D float32_div(float32_one, fstl2, &env->active_fpu.fp_status); fsth2 =3D float32_div(float32_one, fsth2, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } =20 uint64_t helper_float_rint_d(CPUMIPSState *env, uint64_t fs) @@ -1367,19 +1367,19 @@ uint32_t helper_float_recip2_s(CPUMIPSState *env, u= int32_t fst0, uint32_t fst2) =20 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t= fdt2) { - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; + uint32_t fstl0 =3D fdt0 & 0XFFFFFFFF; uint32_t fsth0 =3D fdt0 >> 32; - uint32_t fst2 =3D fdt2 & 0XFFFFFFFF; + uint32_t fstl2 =3D fdt2 & 0XFFFFFFFF; uint32_t fsth2 =3D fdt2 >> 32; =20 - fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fstl2 =3D float32_mul(fstl0, fstl2, &env->active_fpu.fp_status); fsth2 =3D float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_sub(fst2, float32_one, + fstl2 =3D float32_chs(float32_sub(fstl2, float32_one, &env->active_fpu.fp_status)); fsth2 =3D float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } =20 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t = fdt2) @@ -1404,51 +1404,51 @@ uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, u= int32_t fst0, uint32_t fst2) =20 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t= fdt2) { - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; + uint32_t fstl0 =3D fdt0 & 0XFFFFFFFF; uint32_t fsth0 =3D fdt0 >> 32; - uint32_t fst2 =3D fdt2 & 0XFFFFFFFF; + uint32_t fstl2 =3D fdt2 & 0XFFFFFFFF; uint32_t fsth2 =3D fdt2 >> 32; =20 - fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fstl2 =3D float32_mul(fstl0, fstl2, &env->active_fpu.fp_status); fsth2 =3D float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 =3D float32_sub(fst2, float32_one, &env->active_fpu.fp_status); + fstl2 =3D float32_sub(fstl2, float32_one, &env->active_fpu.fp_status); fsth2 =3D float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, + fstl2 =3D float32_chs(float32_div(fstl2, FLOAT_TWO32, &env->active_fpu.fp_status)); fsth2 =3D float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } =20 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t f= dt1) { - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; + uint32_t fstl0 =3D fdt0 & 0XFFFFFFFF; uint32_t fsth0 =3D fdt0 >> 32; - uint32_t fst1 =3D fdt1 & 0XFFFFFFFF; + uint32_t fstl1 =3D fdt1 & 0XFFFFFFFF; uint32_t fsth1 =3D fdt1 >> 32; - uint32_t fst2; + uint32_t fstl2; uint32_t fsth2; =20 - fst2 =3D float32_add(fst0, fsth0, &env->active_fpu.fp_status); - fsth2 =3D float32_add(fst1, fsth1, &env->active_fpu.fp_status); + fstl2 =3D float32_add(fstl0, fsth0, &env->active_fpu.fp_status); + fsth2 =3D float32_add(fstl1, fsth1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } =20 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t f= dt1) { - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; + uint32_t fstl0 =3D fdt0 & 0XFFFFFFFF; uint32_t fsth0 =3D fdt0 >> 32; - uint32_t fst1 =3D fdt1 & 0XFFFFFFFF; + uint32_t fstl1 =3D fdt1 & 0XFFFFFFFF; uint32_t fsth1 =3D fdt1 >> 32; - uint32_t fst2; + uint32_t fstl2; uint32_t fsth2; =20 - fst2 =3D float32_mul(fst0, fsth0, &env->active_fpu.fp_status); - fsth2 =3D float32_mul(fst1, fsth1, &env->active_fpu.fp_status); + fstl2 =3D float32_mul(fstl0, fsth0, &env->active_fpu.fp_status); + fsth2 =3D float32_mul(fstl1, fsth1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } =20 #define FLOAT_MINMAX(name, bits, minmaxfunc) \ --=20 2.20.1