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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x24sm17756487wrd.51.2020.05.18.07.30.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2020 07:30:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=8TBzzcsFazlljQPoOpAMIzgSdLt0n2ByqDt37jz37+s=; b=rD4snTRV3Wwn3W3X1jN40jdKx5l3FCSpwB7/3dBRSKfHRpcCf67NZFaz9DbiLFOE4P t/Vry0Kf3vdMl9+zMMBvFkehxo6KD7umFIltUk5k+APjCnaZ40zGKfyR2ls8KnHgO0Nq J/wUf2498NYLLUYOv+kqe+AiBd3ki/72QyBJcMSEBGFHNyvy15ql7URnbhuPCaT4nEY2 Bl4XNl9de1w1IVCiEpGbCaoVUzLXSQRK0ncL0e4DRlGPrFDck7KJzX5QGMs4MVQdbcjx avPjA0fkwmxgIbzJ2iFbEpa0opGAp7m61ps7OM6Wp1B7mgkjye+1MSUuIDTWN2ouATo9 f39w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=8TBzzcsFazlljQPoOpAMIzgSdLt0n2ByqDt37jz37+s=; b=iSGb9uj4t+rcn9JZbobhXMuW3Ih1XwjSbFDr8emnwmY9haFMJu9PFADs4gXpsL/GnG gb5lXRblWmQyDVnFeetWmuzoGGXXEnIMbkkV5rGmeXiANU7kIV6gWI/G7ABVMQEM6AXM bB2VbgvWsXi/GPM+hRCHURUcbMfwJCBwBSUtfdBBaUfJoeXfxUplsjcQiZzfwpWNy7FA uJYYqUrYG8MI2C4FAAAMbMYGnPpms+Tphl9aawAnX7/WQJ03fNau/j/oj1gbApkLLpxK McqV98uy1usGp7KlV08+9dvJnsHRIgJZFDl1kewL5KOdyZeNeAMJBk85W6520dO4ExMZ JP1Q== X-Gm-Message-State: AOAM533DTvG2aMvUWuNHiblRVJrst+AQrdAJxmTlwCRuCn/seq2t6zvp roZqDZhza/L0hP9tDXumbUpfEQ== X-Google-Smtp-Source: ABdhPJxqb6Cxnd1sG32koSvumhLJM+CoWGxJnefpHXSR3VV+jERTOHAoLjbVfsL4i9HNkXNIk7Nd9Q== X-Received: by 2002:adf:c38c:: with SMTP id p12mr21142380wrf.357.1589812216950; Mon, 18 May 2020 07:30:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 Date: Mon, 18 May 2020 15:30:14 +0100 Message-Id: <20200518143014.20689-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Riku Voipio , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The Arm signal-handling code has some parts ifdeffed with a TARGET_CONFIG_CPU_32, which is always defined. This is a leftover from when this code's structure was based on the Linux kernel signal handling code, where it was intended to support 26-bit Arm CPUs. The kernel dropped its CONFIG_CPU_32 in kernel commit 4da8b8208eded0ba21e3 in 2009. QEMU has never had 26-bit CPU support and is unlikely to ever add it; we certainly aren't going to support 26-bit Linux binaries via linux-user mode. The ifdef is just unhelpful noise, so remove it entirely. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Based-on: <20200518142801.20503-1-peter.maydell@linaro.org> ("[PATCH v2] target/arm: Allow user-mode code to write CPSR.E via MSR") to avoid a textual conflict. linux-user/arm/signal.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index 698985a647e..f21d1535e4d 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -126,8 +126,6 @@ struct rt_sigframe_v2 abi_ulong retcode[4]; }; =20 -#define TARGET_CONFIG_CPU_32 1 - /* * For ARM syscalls, we encode the syscall number into the instruction. */ @@ -187,9 +185,7 @@ setup_sigcontext(struct target_sigcontext *sc, /*struct= _fpstate *fpstate,*/ __put_user(env->regs[13], &sc->arm_sp); __put_user(env->regs[14], &sc->arm_lr); __put_user(env->regs[15], &sc->arm_pc); -#ifdef TARGET_CONFIG_CPU_32 __put_user(cpsr_read(env), &sc->arm_cpsr); -#endif =20 __put_user(/* current->thread.trap_no */ 0, &sc->trap_no); __put_user(/* current->thread.error_code */ 0, &sc->error_code); @@ -549,11 +545,9 @@ restore_sigcontext(CPUARMState *env, struct target_sig= context *sc) __get_user(env->regs[13], &sc->arm_sp); __get_user(env->regs[14], &sc->arm_lr); __get_user(env->regs[15], &sc->arm_pc); -#ifdef TARGET_CONFIG_CPU_32 __get_user(cpsr, &sc->arm_cpsr); cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr); arm_rebuild_hflags(env); -#endif =20 err |=3D !valid_user_regs(env); =20 --=20 2.20.1