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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id s14sm3738327wmh.18.2020.05.15.07.20.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2020 07:20:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YD8Dvuo5pUfHRMo8RpEeRFbdBBgINC3AFc9P3kqEPfY=; b=IL4BxIWVkbgjozh8pyu59eUNZoYCsRxcoX9jcmSXkrX6RP+zFcp5HFQrlD3uBNVEiP LvuBWuQAEBZN20CzSjE8u6TjIZU1B4gau5IfQTqCw6vQ3BmjxTu/+HVEAJO6fKK//MrR JkQ6Uto1eSdpCUOXg1C8/SNW2pN1+UK8MzNq8G3NHIIzwa4/U1IF2SMmNy43+ZwZ6s5J 8t9DrDotDulXrbrEEzgUQpjtbNY12TKcffzDF7TvYlcKT0nciyPGhoRp20uzoTd0f/Wo BQdAfTTTGNn8wkiBxN84EkUbpxJTFsoeI97ENMhxnDeok1UKYslRjDBdB2SntLeAMqYq ZmwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YD8Dvuo5pUfHRMo8RpEeRFbdBBgINC3AFc9P3kqEPfY=; b=rl2EwtHYGq/8FBjcchZb7cB3JTUGm+cd7w0VKnFLNc9JSHE9GnALAjF1UVJr3jDTG9 gTHTOZhLfMEXXoKaQxxD+yo9vUnApTyp93haEujntHBWliIKfUxW/+blYs9Q1eY8e8nf enQPOPgDblXF0yH3IQ+9eeIx9cNC22rMPWIQyUXPkeVxI90V2E17AOneuRGrqzfwRF5N 89/0HIJE8XvbBFWbJcrovib2nhB+x6etwJLNEYWI6xdsmKbBCEq5s8C1LYSY1CJcpPS8 OiFrNSB0bL1bXJs69DLEdvwEelDZHLG3jP5fhXIjBhCgQQGEww4whqqMDvDWrD+RgljQ kK1A== X-Gm-Message-State: AOAM5338JacGWsJWxHSmIsS/8B/H2RF37l/UtMs/FpHGDh2xKegSwPDT 3iVdeJh1q4QJhwQWS2zhB3Vh5wc3CLnqmQ== X-Google-Smtp-Source: ABdhPJwlRkIdrEQ8RGCnh2cceKI7lyF4AwYTEyTGutdK+S7QU/6InZcPPpp+oZJcrtqLsS+ToQPpmw== X-Received: by 2002:adf:80a3:: with SMTP id 32mr4472357wrl.199.1589552459820; Fri, 15 May 2020 07:20:59 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/10] target/arm: Remove unused GEN_NEON_INTEGER_OP macro Date: Fri, 15 May 2020 15:20:47 +0100 Message-Id: <20200515142056.21346-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200515142056.21346-1-peter.maydell@linaro.org> References: <20200515142056.21346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The GEN_NEON_INTEGER_OP macro is no longer used; remove it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Between Richard's cleanup and mine we deleted all the uses of this, but since neither series on its own was sufficient to delete all of them we failed to remove the macro definition when it finally became unused. --- target/arm/translate.c | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4c9bb8b5ac0..c8296116d4b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3034,29 +3034,6 @@ static inline void gen_neon_rsb(int size, TCGv_i32 t= 0, TCGv_i32 t1) default: return 1; \ }} while (0) =20 -#define GEN_NEON_INTEGER_OP(name) do { \ - switch ((size << 1) | u) { \ - case 0: \ - gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \ - break; \ - case 1: \ - gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \ - break; \ - case 2: \ - gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \ - break; \ - case 3: \ - gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \ - break; \ - case 4: \ - gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \ - break; \ - case 5: \ - gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \ - break; \ - default: return 1; \ - }} while (0) - static TCGv_i32 neon_load_scratch(int scratch) { TCGv_i32 tmp =3D tcg_temp_new_i32(); --=20 2.20.1 From nobody Thu May 2 06:10:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1589552533; cv=none; d=zohomail.com; s=zohoarc; b=e8F54oyJJbumyBDQ56GwPxdbzEIaOfVmsZSR6SMmkMgSiyUzQPgzQXH3U8skcR7L+Zic1QhX2q7Qbr4gYSI8PEILnAF9zedTY0UDlDspEi7FcqTbVKu6EvDB3T1gmt26RZDd6u2gDfXjRfWCbUHdKVH9d0tkxdylE2RxGc2qgWs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589552533; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=17miaZnAVR6c8E+5NalM9aupFX47F8Zsgz/tNLlnYGE=; b=JBKsDS+5RsjH5gG4X5xo/FYBYdsr1IIo08KIiYmEkacTso7m1OSPIOA4IqxqB6Qdq83Wlx+YJ6ac0OwS6392e+qYj73IN4AbNaDVAdgypRKVfvH4vgdt4UEjfWn4M2pleAbFjYMpQsgPhxUJx3vGn0gDbJfJ9XgYLLh+qvGi3Og= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589552533818734.9538700468535; Fri, 15 May 2020 07:22:13 -0700 (PDT) Received: from localhost ([::1]:34268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZbE4-0002aP-AV for importer@patchew.org; Fri, 15 May 2020 10:22:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34762) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZbCx-0000eE-Mz for qemu-devel@nongnu.org; Fri, 15 May 2020 10:21:03 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:33781) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jZbCw-0003rm-NT for qemu-devel@nongnu.org; Fri, 15 May 2020 10:21:03 -0400 Received: by mail-wr1-x442.google.com with SMTP id l11so3824882wru.0 for ; Fri, 15 May 2020 07:21:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id s14sm3738327wmh.18.2020.05.15.07.20.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2020 07:21:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=17miaZnAVR6c8E+5NalM9aupFX47F8Zsgz/tNLlnYGE=; b=D0deTJfLmgHltI/6u5Nua2Vfio85SFd+D8DvqxMP5X0NmioFo/1fy4SUyj3hCOZALO nsBC0yFREmmff7lkOcY3z8LqrUzHTuiCvsSZtDd+DJ9aRLoub+VdocB9wAWk24mrghtG 8+h+KBBj5Scm7ti6za1YZAiANvLIyTkrUV5MK3fzRBm92yJuwXkU8ysCOIFYZASEto7j a3MaJCEijnBgwFF7HhwzyYcFPTd1lkamyE1a1lwVuMyMTHfK+QFCMWC0xDuHPUaxiiEL 8UAZ3byOKvn5wR/Jte15lnyPhN/a8lD3cWgSyrP5Us4a9J5s8soP4yjtKxB8/qWFdCmj lAxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=17miaZnAVR6c8E+5NalM9aupFX47F8Zsgz/tNLlnYGE=; b=itgrkBdi4QnYighq/e3y49uh538cwT5zJZk6g/7SK5KkWlMZU0/DqcnNHWh7JBQ+Im cxvwDHrrouGGHJace5KgY+X/3ENmmnQxB0D5JnOpha3G/5ADlWvAjm/PncbHaS3sSUuI P9375klQdNCRZ/wB4mCoQLAYa1ZNUeS0SJaRgHiA9KoL4zPnDGlarDqyCPArYDQqwdNe 3ZIBIkdQYdlPcJeyAck54Tt5vBkRNoi7mUV6QYE5FtECXzXoT5M3AYxKqoJpAJp1HjzI POtmOtLWkbrsc866zmNyMTi7s9vsN3hqc/X3TEE63pEJC7XlDMa54h9Z1nUnPYQtDyxa jiTw== X-Gm-Message-State: AOAM531A6K7Fz2D1y26ubGpFljQ+9twAivlfRQ43ZIDgcgcZUFoI8Z1f 5m6k8J+qvXJPPB6C5W713U4Ghcs/Ak37yw== X-Google-Smtp-Source: ABdhPJypDy2vplkeqU1l0s0iAbzKU5HJoOQeRW4ohDFHcSywPPxzictJYLN9tlRyD5FPwdR1QY1r5A== X-Received: by 2002:a5d:522d:: with SMTP id i13mr4642896wra.306.1589552460990; Fri, 15 May 2020 07:21:00 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/10] target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree Date: Fri, 15 May 2020 15:20:48 +0100 Message-Id: <20200515142056.21346-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200515142056.21346-1-peter.maydell@linaro.org> References: <20200515142056.21346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VSHL and VSLI insns from the Neon 2-registers-and-a-shift group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 27 +++++++++++++++++++++++ target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 18 +++++++--------- 3 files changed, 73 insertions(+), 10 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 8beb1db768b..df7b4798a5a 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -199,3 +199,30 @@ VRECPS_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ...= 1 .... @3same_fp VRSQRTS_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp VMAXNM_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp + +###################################################################### +# 2-reg-and-shift grouping: +# 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4 +###################################################################### +&2reg_shift vm vd q shift size + +@2reg_shift .... ... . . . ...... .... .... . q:1 . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp + +VSHL_2sh 1111 001 0 1 . shift:6 .... 0101 1 . . 1 .... \ + @2reg_shift size=3D3 +VSHL_2sh 1111 001 0 1 . 1 shift:5 .... 0101 0 . . 1 .... \ + @2reg_shift size=3D2 +VSHL_2sh 1111 001 0 1 . 01 shift:4 .... 0101 0 . . 1 .... \ + @2reg_shift size=3D1 +VSHL_2sh 1111 001 0 1 . 001 shift:3 .... 0101 0 . . 1 .... \ + @2reg_shift size=3D0 + +VSLI_2sh 1111 001 1 1 . shift:6 .... 0101 1 . . 1 .... \ + @2reg_shift size=3D3 +VSLI_2sh 1111 001 1 1 . 1 shift:5 .... 0101 0 . . 1 .... \ + @2reg_shift size=3D2 +VSLI_2sh 1111 001 1 1 . 01 shift:4 .... 0101 0 . . 1 .... \ + @2reg_shift size=3D1 +VSLI_2sh 1111 001 1 1 . 001 shift:3 .... 0101 0 . . 1 .... \ + @2reg_shift size=3D0 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 3fe65a0b080..305213fe6d9 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1310,3 +1310,41 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3s= ame *a, VFPGen3OpSPFn *fn) DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds) DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs) DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins) + +static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn = *fn) +{ + /* Handle a 2-reg-shift insn which can be vectorized. */ + int vec_size =3D a->q ? 16 : 8; + int rd_ofs =3D neon_reg_offset(a->vd, 0); + int rm_ofs =3D neon_reg_offset(a->vm, 0); + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fn(a->size, rd_ofs, rm_ofs, a->shift, vec_size, vec_size); + return true; +} + +#define DO_2SH(INSN, FUNC) \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_vector_2sh(s, a, FUNC); \ + } \ + +DO_2SH(VSHL, tcg_gen_gvec_shli) +DO_2SH(VSLI, gen_gvec_sli) diff --git a/target/arm/translate.c b/target/arm/translate.c index c8296116d4b..d0a4a08f6d9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5294,6 +5294,14 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) if ((insn & 0x00380080) !=3D 0) { /* Two registers and shift. */ op =3D (insn >> 8) & 0xf; + + switch (op) { + case 5: /* VSHL, VSLI */ + return 1; /* handled by decodetree */ + default: + break; + } + if (insn & (1 << 7)) { /* 64-bit shift. */ if (op > 7) { @@ -5387,16 +5395,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) gen_gvec_sri(size, rd_ofs, rm_ofs, shift, vec_size, vec_size); return 0; - - case 5: /* VSHL, VSLI */ - if (u) { /* VSLI */ - gen_gvec_sli(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } else { /* VSHL */ - tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; } =20 if (size =3D=3D 3) { --=20 2.20.1 From nobody Thu May 2 06:10:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1589552563; cv=none; d=zohomail.com; s=zohoarc; b=IKoqjTC3GB72hJYiZSZO4DG3AYwsGV6acwxKI89GEFe4wiqr4IWHy0b8O2xmLh/DI3zI61id6aLUXleT2nGxoixk5dKHWS81HzS0DwKyiQMtPN5Wo/+ZaH4IQebuFyD18K1Dub+jNsIMiyiOKd1EsH/h8tk1cEUALSO+BuKv280= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589552563; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hKEL7z4LxXMw8xsvvZqstECIgOw6TAEOPxp9PR9rpGE=; b=IZUlzl9+Y+lsFqGVEhsAe8oQxKI/ZuJzfFpYKiaTrXipE+xHG78Qn8NUvEBCOz7CqkxIXubsxytaWimLX/Ft+IjfEzPa1hkPYyyaD1Fo/QMND+fVdiPRXum0z7SrwtCU3FGvyLsEAAiDlJIy99pL4VFJwYnQk/jZdU3uLf4tfHg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589552563666757.1153805897824; Fri, 15 May 2020 07:22:43 -0700 (PDT) Received: from localhost ([::1]:36208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZbEY-0003Q7-D7 for importer@patchew.org; Fri, 15 May 2020 10:22:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZbCy-0000gO-RX for qemu-devel@nongnu.org; Fri, 15 May 2020 10:21:04 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:53906) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jZbCx-0003s4-NU for qemu-devel@nongnu.org; Fri, 15 May 2020 10:21:04 -0400 Received: by mail-wm1-x341.google.com with SMTP id k12so2506959wmj.3 for ; Fri, 15 May 2020 07:21:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id s14sm3738327wmh.18.2020.05.15.07.21.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2020 07:21:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hKEL7z4LxXMw8xsvvZqstECIgOw6TAEOPxp9PR9rpGE=; b=GX+CpsnhbSVEVmKZ18h/6DwQfYUec0YIsWsoUXMn60OwTssJZJD0ObsjurPS9THSqI Ew668yFwCSigE4OUt8a/oL0/qJKvbAaqLdw9Gr2ncXbu7+QpKtyemXMV8yEhLETXEPe7 KezTYlismGvSo7mgdquj5fRM2gvrDgGeyUFG7IRSu76Ds9IIJEWPyv5iokK2MISo5CrU GLRLAYevukem7yBF6SuqzxTFpg/YlPsQzqHfxQrYLrH/ISeQrd+zW1JomJaGnsYqQ9VO 1HSFSaeJRJeftUuxLsSrJVsYyHnhUy4D86w37wkR0IW6ZKz6OEBs8v3CLchef2orARy2 8tXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hKEL7z4LxXMw8xsvvZqstECIgOw6TAEOPxp9PR9rpGE=; b=CrC30ZiY990DnkQBwR/AGlYHIh5ZlppjKICLSLesRdjJLSjYFTKs33MoFm+lxEB9n+ bYsHNyt6K6Cd1u6EiOUO0NH8b90aFPxYp/413SBuSSfXpmgIveOz+KyYTELMXZY5M2Nd RcfJbzZByhF/LEDJlKlLSCU972Q/fcu5/6Hf+tkjD9nVUz77CSWXjgDE1dstUqDudwx0 ZjHa4YUraA6MzGX1s6w5ztbVDal72bXlMxR7BSgi+PHXZrqw6JEtNyHFnSNysg1C5yGa vd73PYn6tVYigbw/lhKbHtR5piqSgX2ELlRm6sobN25WWluI9XFovSN2xtWkfbGirpyh PGPQ== X-Gm-Message-State: AOAM532hK/HduAIXbHuOkEig4mqJB2fQ6SUsdMkhB7c4xShfQbNWTcUm Qt4pIb2EOeTOADNLxoVjecuQNg== X-Google-Smtp-Source: ABdhPJxvrcXNTizysTpb0HNQBgQBP2kkWN98+gM0Om0kJ5L+Ls8CihYVUPg9ctF2xhD4Vl2nzo12bQ== X-Received: by 2002:a7b:c413:: with SMTP id k19mr4284214wmi.124.1589552462175; Fri, 15 May 2020 07:21:02 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/10] target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree Date: Fri, 15 May 2020 15:20:49 +0100 Message-Id: <20200515142056.21346-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200515142056.21346-1-peter.maydell@linaro.org> References: <20200515142056.21346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VSHR 2-reg-shift insns to decodetree. Note that unlike the legacy decoder, we present the right shift amount to the trans_ function as a positive integer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 24 +++++++++++++++++++ target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 21 +---------------- 3 files changed, 66 insertions(+), 20 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index df7b4798a5a..648812395f1 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -209,6 +209,30 @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ...= 1 .... @3same_fp @2reg_shift .... ... . . . ...... .... .... . q:1 . . .... \ &2reg_shift vm=3D%vm_dp vd=3D%vd_dp =20 +# Right shifts are encoded as N - shift, where N is the element size in bi= ts. +%neon_rshift_i6 16:6 !function=3Drsub_64 +%neon_rshift_i5 16:5 !function=3Drsub_32 +%neon_rshift_i4 16:4 !function=3Drsub_16 +%neon_rshift_i3 16:3 !function=3Drsub_8 + +VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 1 . . 1 .... \ + @2reg_shift size=3D3 shift=3D%neon_rshift_i6 +VSHR_S_2sh 1111 001 0 1 . 1 ..... .... 0000 0 . . 1 .... \ + @2reg_shift size=3D2 shift=3D%neon_rshift_i5 +VSHR_S_2sh 1111 001 0 1 . 01 .... .... 0000 0 . . 1 .... \ + @2reg_shift size=3D1 shift=3D%neon_rshift_i4 +VSHR_S_2sh 1111 001 0 1 . 001 ... .... 0000 0 . . 1 .... \ + @2reg_shift size=3D0 shift=3D%neon_rshift_i3 + +VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 1 . . 1 .... \ + @2reg_shift size=3D3 shift=3D%neon_rshift_i6 +VSHR_U_2sh 1111 001 1 1 . 1 ..... .... 0000 0 . . 1 .... \ + @2reg_shift size=3D2 shift=3D%neon_rshift_i5 +VSHR_U_2sh 1111 001 1 1 . 01 .... .... 0000 0 . . 1 .... \ + @2reg_shift size=3D1 shift=3D%neon_rshift_i4 +VSHR_U_2sh 1111 001 1 1 . 001 ... .... 0000 0 . . 1 .... \ + @2reg_shift size=3D0 shift=3D%neon_rshift_i3 + VSHL_2sh 1111 001 0 1 . shift:6 .... 0101 1 . . 1 .... \ @2reg_shift size=3D3 VSHL_2sh 1111 001 0 1 . 1 shift:5 .... 0101 0 . . 1 .... \ diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 305213fe6d9..0475696835f 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -31,6 +31,24 @@ static inline int plus1(DisasContext *s, int x) return x + 1; } =20 +static inline int rsub_64(DisasContext *s, int x) +{ + return 64 - x; +} + +static inline int rsub_32(DisasContext *s, int x) +{ + return 32 - x; +} +static inline int rsub_16(DisasContext *s, int x) +{ + return 16 - x; +} +static inline int rsub_8(DisasContext *s, int x) +{ + return 8 - x; +} + /* Include the generated Neon decoder */ #include "decode-neon-dp.inc.c" #include "decode-neon-ls.inc.c" @@ -1348,3 +1366,26 @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_= shift *a, GVecGen2iFn *fn) =20 DO_2SH(VSHL, tcg_gen_gvec_shli) DO_2SH(VSLI, gen_gvec_sli) + +static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a) +{ + /* Signed shift out of range results in all-sign-bits */ + a->shift =3D MIN(a->shift, (8 << a->size) - 1); + return do_vector_2sh(s, a, tcg_gen_gvec_sari); +} + +static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_of= s, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0); +} + +static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a) +{ + /* Shift out of range is architecturally valid and results in zero. */ + if (a->shift >=3D (8 << a->size)) { + return do_vector_2sh(s, a, gen_zero_rd_2sh); + } else { + return do_vector_2sh(s, a, tcg_gen_gvec_shri); + } +} diff --git a/target/arm/translate.c b/target/arm/translate.c index d0a4a08f6d9..f2ccab1b21c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5296,6 +5296,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) op =3D (insn >> 8) & 0xf; =20 switch (op) { + case 0: /* VSHR */ case 5: /* VSHL, VSLI */ return 1; /* handled by decodetree */ default: @@ -5330,26 +5331,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) } =20 switch (op) { - case 0: /* VSHR */ - /* Right shift comes here negative. */ - shift =3D -shift; - /* Shifts larger than the element size are architectur= ally - * valid. Unsigned results in all zeros; signed resul= ts - * in all sign bits. - */ - if (!u) { - tcg_gen_gvec_sari(size, rd_ofs, rm_ofs, - MIN(shift, (8 << size) - 1), - vec_size, vec_size); - } else if (shift >=3D 8 << size) { - tcg_gen_gvec_dup_imm(MO_8, rd_ofs, vec_size, - vec_size, 0); - } else { - tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; - case 1: /* VSRA */ /* Right shift comes here negative. */ shift =3D -shift; --=20 2.20.1 From nobody Thu May 2 06:10:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1589552749; cv=none; d=zohomail.com; s=zohoarc; b=YLZ8JnI3EJ0x/IatZCnKQpEMttTxSFOF9YA4Bev5ZSuaZ+ItbbD7OYkxXakyxncstsTJC75KJDJslfcL82DJehGFQGxqu7HBSthYtCCjiMKq/oufz+QrRU+ogi0+GrLfqwL4+2rpZk87kGUnYXiqSV/91u1xkXOsHafWBxY24S4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589552749; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2YJwvw0U8SAAD/UpPFNsjDivgh2d1pwAU2NE+6DTu5Y=; b=n+lMsxJjtqf+JHJeyOEG4nQod0cmB2yc6HH/OLUyrI9aWUb7/5he0QaH3oeHPEO1be0QMu9hMyKtuWj6CAyvOHdyDyesAE55jdtyEDriNR3Rl7gzgvWUIwAE063EBNKwk0HiKl2Cbc4Q0h+IFGHsDIcm3c4owKamBkCERtijvHs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589552749515709.821054143753; Fri, 15 May 2020 07:25:49 -0700 (PDT) Received: from localhost ([::1]:49126 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZbHY-0000Xx-30 for importer@patchew.org; Fri, 15 May 2020 10:25:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZbCz-0000ix-TR for qemu-devel@nongnu.org; Fri, 15 May 2020 10:21:05 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:38142) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jZbCy-0003sG-OU for qemu-devel@nongnu.org; Fri, 15 May 2020 10:21:05 -0400 Received: by mail-wr1-x442.google.com with SMTP id e1so3772914wrt.5 for ; Fri, 15 May 2020 07:21:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id s14sm3738327wmh.18.2020.05.15.07.21.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2020 07:21:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2YJwvw0U8SAAD/UpPFNsjDivgh2d1pwAU2NE+6DTu5Y=; b=vi1slfoeztNGNZ6vyb9td7BdpXMFohwqluyQB7JBMtlYW+unZ4McAgMzqXlwY1HpHI 1KoQKlx01C2TPdV8yr1SoitAe1+3tEUFu0lY9IG9zt0kgyiPupmyvfmpc3H7c7fg96qp nn7Qgg7NaERw9N+7USkjbDlDnAHQXsGHNj30Nbgf6dBGstcJ3Qxt4CxGzwopGB/JE7P7 OitXplZgSxh7s8ua3r2BeMzO2xMER2qpKi+i/QZkGn+M1IsTq+z/ajD/mBciE05RuYlo zpDEP04FlfmjbKAsAJYMVP18vinhKb2uGEzV45TGFQ170YThyvukQva3cSPmmGA0GJ0D Re5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2YJwvw0U8SAAD/UpPFNsjDivgh2d1pwAU2NE+6DTu5Y=; b=Hnw+XBCJ5QVh92e4eW0s9fCtZmkmBAgniFpmdWfht+LAxpDGhkAjBAXNW95op+25hh LOci0CgZeCNH9Wv5Gt8QHvgkMtxlIFVwDJW0W+0LwPD2i52esRxK6v6e5NriaiePWG91 F1eseqsZJU+5VGgLiT6wj6yGhmv5EznrTtEpG8IVKvb2zx07dWsNE9EgUlCDFQJgdDEi korFUqj1SFzhSZqNFw+xOk1BqWZoO9HUUkImKKD5VWmilBy5/j3k3AofG8IN5Cevch1C 5od5JsO9FciZBFmlreYgwMY8lGLL+Abt0RbSG3NUH72cpAdXDSohEd1/Pa1wbHcSnVtk qkHw== X-Gm-Message-State: AOAM532tNUx3SjzjO1jU9olIjZTGwMSMHuSlzI1mVPBZZ4ZPiJMbsyb5 eLGUhrgG+a4ctgbNG8kkZuGGdQ== X-Google-Smtp-Source: ABdhPJydgcfhnHbIwx1fcPmedqQjVWuRYTReR6iOVZdMgugbfb28bTK/dz6IShKslx61TvqIYVAshQ== X-Received: by 2002:adf:dd01:: with SMTP id a1mr4460229wrm.224.1589552463301; Fri, 15 May 2020 07:21:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/10] target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree Date: Fri, 15 May 2020 15:20:50 +0100 Message-Id: <20200515142056.21346-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200515142056.21346-1-peter.maydell@linaro.org> References: <20200515142056.21346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree. (These are the last instructions in the group that are vectorized; the rest all require looping over each element.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 63 +++++++++++++++++++++++++++++++++ target/arm/translate-neon.inc.c | 7 ++++ target/arm/translate.c | 52 +++------------------------ 3 files changed, 74 insertions(+), 48 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 648812395f1..3ed10d1524e 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -233,6 +233,69 @@ VSHR_U_2sh 1111 001 1 1 . 01 .... .... 0000 = 0 . . 1 .... \ VSHR_U_2sh 1111 001 1 1 . 001 ... .... 0000 0 . . 1 .... \ @2reg_shift size=3D0 shift=3D%neon_rshift_i3 =20 +VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 1 . . 1 .... \ + @2reg_shift size=3D3 shift=3D%neon_rshift_i6 +VSRA_S_2sh 1111 001 0 1 . 1 ..... .... 0001 0 . . 1 .... \ + @2reg_shift size=3D2 shift=3D%neon_rshift_i5 +VSRA_S_2sh 1111 001 0 1 . 01 .... .... 0001 0 . . 1 .... \ + @2reg_shift size=3D1 shift=3D%neon_rshift_i4 +VSRA_S_2sh 1111 001 0 1 . 001 ... .... 0001 0 . . 1 .... \ + @2reg_shift size=3D0 shift=3D%neon_rshift_i3 + +VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 1 . . 1 .... \ + @2reg_shift size=3D3 shift=3D%neon_rshift_i6 +VSRA_U_2sh 1111 001 1 1 . 1 ..... .... 0001 0 . . 1 .... \ + @2reg_shift size=3D2 shift=3D%neon_rshift_i5 +VSRA_U_2sh 1111 001 1 1 . 01 .... .... 0001 0 . . 1 .... \ + @2reg_shift size=3D1 shift=3D%neon_rshift_i4 +VSRA_U_2sh 1111 001 1 1 . 001 ... .... 0001 0 . . 1 .... \ + @2reg_shift size=3D0 shift=3D%neon_rshift_i3 + +VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 1 . . 1 .... \ + @2reg_shift size=3D3 shift=3D%neon_rshift_i6 +VRSHR_S_2sh 1111 001 0 1 . 1 ..... .... 0010 0 . . 1 .... \ + @2reg_shift size=3D2 shift=3D%neon_rshift_i5 +VRSHR_S_2sh 1111 001 0 1 . 01 .... .... 0010 0 . . 1 .... \ + @2reg_shift size=3D1 shift=3D%neon_rshift_i4 +VRSHR_S_2sh 1111 001 0 1 . 001 ... .... 0010 0 . . 1 .... \ + @2reg_shift size=3D0 shift=3D%neon_rshift_i3 + +VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 1 . . 1 .... \ + @2reg_shift size=3D3 shift=3D%neon_rshift_i6 +VRSHR_U_2sh 1111 001 1 1 . 1 ..... .... 0010 0 . . 1 .... \ + @2reg_shift size=3D2 shift=3D%neon_rshift_i5 +VRSHR_U_2sh 1111 001 1 1 . 01 .... .... 0010 0 . . 1 .... \ + @2reg_shift size=3D1 shift=3D%neon_rshift_i4 +VRSHR_U_2sh 1111 001 1 1 . 001 ... .... 0010 0 . . 1 .... \ + @2reg_shift size=3D0 shift=3D%neon_rshift_i3 + +VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 1 . . 1 .... \ + @2reg_shift size=3D3 shift=3D%neon_rshift_i6 +VRSRA_S_2sh 1111 001 0 1 . 1 ..... .... 0011 0 . . 1 .... \ + @2reg_shift size=3D2 shift=3D%neon_rshift_i5 +VRSRA_S_2sh 1111 001 0 1 . 01 .... .... 0011 0 . . 1 .... \ + @2reg_shift size=3D1 shift=3D%neon_rshift_i4 +VRSRA_S_2sh 1111 001 0 1 . 001 ... .... 0011 0 . . 1 .... \ + @2reg_shift size=3D0 shift=3D%neon_rshift_i3 + +VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 1 . . 1 .... \ + @2reg_shift size=3D3 shift=3D%neon_rshift_i6 +VRSRA_U_2sh 1111 001 1 1 . 1 ..... .... 0011 0 . . 1 .... \ + @2reg_shift size=3D2 shift=3D%neon_rshift_i5 +VRSRA_U_2sh 1111 001 1 1 . 01 .... .... 0011 0 . . 1 .... \ + @2reg_shift size=3D1 shift=3D%neon_rshift_i4 +VRSRA_U_2sh 1111 001 1 1 . 001 ... .... 0011 0 . . 1 .... \ + @2reg_shift size=3D0 shift=3D%neon_rshift_i3 + +VSRI_2sh 1111 001 1 1 . ...... .... 0100 1 . . 1 .... \ + @2reg_shift size=3D3 shift=3D%neon_rshift_i6 +VSRI_2sh 1111 001 1 1 . 1 ..... .... 0100 0 . . 1 .... \ + @2reg_shift size=3D2 shift=3D%neon_rshift_i5 +VSRI_2sh 1111 001 1 1 . 01 .... .... 0100 0 . . 1 .... \ + @2reg_shift size=3D1 shift=3D%neon_rshift_i4 +VSRI_2sh 1111 001 1 1 . 001 ... .... 0100 0 . . 1 .... \ + @2reg_shift size=3D0 shift=3D%neon_rshift_i3 + VSHL_2sh 1111 001 0 1 . shift:6 .... 0101 1 . . 1 .... \ @2reg_shift size=3D3 VSHL_2sh 1111 001 0 1 . 1 shift:5 .... 0101 0 . . 1 .... \ diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 0475696835f..f4d42683aea 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1366,6 +1366,13 @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_= shift *a, GVecGen2iFn *fn) =20 DO_2SH(VSHL, tcg_gen_gvec_shli) DO_2SH(VSLI, gen_gvec_sli) +DO_2SH(VSRI, gen_gvec_sri) +DO_2SH(VSRA_S, gen_gvec_ssra) +DO_2SH(VSRA_U, gen_gvec_usra) +DO_2SH(VRSHR_S, gen_gvec_srshr) +DO_2SH(VRSHR_U, gen_gvec_urshr) +DO_2SH(VRSRA_S, gen_gvec_srsra) +DO_2SH(VRSRA_U, gen_gvec_ursra) =20 static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a) { diff --git a/target/arm/translate.c b/target/arm/translate.c index f2ccab1b21c..4a55986aad9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5297,6 +5297,10 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) =20 switch (op) { case 0: /* VSHR */ + case 1: /* VSRA */ + case 2: /* VRSHR */ + case 3: /* VRSRA */ + case 4: /* VSRI */ case 5: /* VSHL, VSLI */ return 1; /* handled by decodetree */ default: @@ -5330,54 +5334,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) shift =3D shift - (1 << (size + 3)); } =20 - switch (op) { - case 1: /* VSRA */ - /* Right shift comes here negative. */ - shift =3D -shift; - if (u) { - gen_gvec_usra(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } else { - gen_gvec_ssra(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; - - case 2: /* VRSHR */ - /* Right shift comes here negative. */ - shift =3D -shift; - if (u) { - gen_gvec_urshr(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } else { - gen_gvec_srshr(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; - - case 3: /* VRSRA */ - /* Right shift comes here negative. */ - shift =3D -shift; - if (u) { - gen_gvec_ursra(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } else { - gen_gvec_srsra(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; - - case 4: /* VSRI */ - if (!u) { - return 1; - } - /* Right shift comes here negative. */ - shift =3D -shift; - gen_gvec_sri(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - return 0; - } - if (size =3D=3D 3) { count =3D q + 1; } else { --=20 2.20.1 From nobody Thu May 2 06:10:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1589552648; cv=none; d=zohomail.com; s=zohoarc; b=d+NuJ0lMhTa5yTfaiS9+VytFYB58qOPk0i8kAllEEOWiqePIEUJAM0F6sM5wsLV/LvXVe66uddDeyKIPjrYXkfsrea7Ns3J2nqtcK9m3iSlm2XRvwUFw0FCBC+hhx0etwfdDM6ox7P2XbR9vGfrB7E/Vg+pi1sYF7hUoZWCvO2E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589552648; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id s14sm3738327wmh.18.2020.05.15.07.21.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2020 07:21:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x52pOoMber5KmhMhzO3xI4c0KAd3lEJy8+iCRYC1x2A=; b=VtlPPzAih767yq3Y8RV70qVVoeaymVRKbvQOBxcT+/q79vdBjL7kaQcl7H49Yd4q7o Z7ESJ4meGeaNdu60JFYrydg/VKQClAFZJCu0RDf0vVAdJK2UVXsGIh1ZuSabtQMgAV8N qYCzL7a+U+S+ZINtHM2ZX2G/5YV2evDoj22lgG1nEfAjTKpP1Lg/adt4KQnYwS1mj6O6 Kq1A9ru1vDBgeHYN4n88i67ybaeEn9i787cjdP1k0TdGO5plB9hRQ+uVn8UbupfGZ72O gUsuVskH7jpcw4gHDZWiMI9g8w7lcHfrQ7bJOu7yOFBXczjDaoL0WKB6YLRWfaeM6RWD H5BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x52pOoMber5KmhMhzO3xI4c0KAd3lEJy8+iCRYC1x2A=; b=Ya3n3ecPeEPG11piQOh1iZGRMSDQslIacBsJj6TSCQOygJAwM+P4rRBsT+sXTw/fCO 023Yswt08h7UyLWf91ETJgXf5zEQjbOQRDLn2D7vP6VxC+arPy/181oreIHv1e6IGxI+ xKxn26fl+X/3rG1keeO7jMhDd72w4OGBYVxYrND8PfU1Z/2Ce/erT54t3gOgnY70kY1G wIMBOatDQfDJNO7efxFiBUSTTc920NxiqDSuVnILHaMZ6pg3LUXboSpFvb04kiKZExcw E8NBQRw0EBbghIrGrAO/djpLJMJt+nCK/Cm/MARRPLWFHH6IPyOsg2YacJihPxbWAHpn S47g== X-Gm-Message-State: AOAM530Z2dgATyQJ95OeMiZoOZdJ90EANW8IZW7fkArDQ4kpYvt086mT DHdZxX7U5WV+0ZWR7wSOHu41nQ== X-Google-Smtp-Source: ABdhPJwz36FbbIwmvzbU47nskFvKHEn5CxiMkDYeDAaVD9cIa0BW3/4Ds4n3KpIv5i45nHzFBvmwFQ== X-Received: by 2002:a1c:7d93:: with SMTP id y141mr4417191wmc.34.1589552464513; Fri, 15 May 2020 07:21:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/10] target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree Date: Fri, 15 May 2020 15:20:51 +0100 Message-Id: <20200515142056.21346-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200515142056.21346-1-peter.maydell@linaro.org> References: <20200515142056.21346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VQSHLU and QVSHL 2-reg-shift insns to decodetree. These are the last of the simple shift-by-immediate insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 27 ++++++++ target/arm/translate-neon.inc.c | 108 +++++++++++++++++++++++++++++++ target/arm/translate.c | 110 +------------------------------- 3 files changed, 138 insertions(+), 107 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 3ed10d1524e..6456b53a690 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -313,3 +313,30 @@ VSLI_2sh 1111 001 1 1 . 01 shift:4 .... 0101 = 0 . . 1 .... \ @2reg_shift size=3D1 VSLI_2sh 1111 001 1 1 . 001 shift:3 .... 0101 0 . . 1 .... \ @2reg_shift size=3D0 + +VQSHLU_64_2sh 1111 001 1 1 . shift:6 .... 0110 1 . . 1 .... \ + @2reg_shift size=3D3 +VQSHLU_2sh 1111 001 1 1 . 1 shift:5 .... 0110 0 . . 1 .... \ + @2reg_shift size=3D2 +VQSHLU_2sh 1111 001 1 1 . 01 shift:4 .... 0110 0 . . 1 .... \ + @2reg_shift size=3D1 +VQSHLU_2sh 1111 001 1 1 . 001 shift:3 .... 0110 0 . . 1 .... \ + @2reg_shift size=3D0 + +VQSHL_S_64_2sh 1111 001 0 1 . shift:6 .... 0111 1 . . 1 .... \ + @2reg_shift size=3D3 +VQSHL_S_2sh 1111 001 0 1 . 1 shift:5 .... 0111 0 . . 1 .... \ + @2reg_shift size=3D2 +VQSHL_S_2sh 1111 001 0 1 . 01 shift:4 .... 0111 0 . . 1 .... \ + @2reg_shift size=3D1 +VQSHL_S_2sh 1111 001 0 1 . 001 shift:3 .... 0111 0 . . 1 .... \ + @2reg_shift size=3D0 + +VQSHL_U_64_2sh 1111 001 1 1 . shift:6 .... 0111 1 . . 1 .... \ + @2reg_shift size=3D3 +VQSHL_U_2sh 1111 001 1 1 . 1 shift:5 .... 0111 0 . . 1 .... \ + @2reg_shift size=3D2 +VQSHL_U_2sh 1111 001 1 1 . 01 shift:4 .... 0111 0 . . 1 .... \ + @2reg_shift size=3D1 +VQSHL_U_2sh 1111 001 1 1 . 001 shift:3 .... 0111 0 . . 1 .... \ + @2reg_shift size=3D0 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index f4d42683aea..396db55565f 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1396,3 +1396,111 @@ static bool trans_VSHR_U_2sh(DisasContext *s, arg_2= reg_shift *a) return do_vector_2sh(s, a, tcg_gen_gvec_shri); } } + +static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a, + NeonGenTwo64OpEnvFn *fn) +{ + /* + * 2-reg-and-shift operations, size =3D=3D 3 case, where the + * function needs to be passed cpu_env. + */ + TCGv_i64 constimm; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * To avoid excessive duplication of ops we implement shift + * by immediate using the variable shift operations. + */ + constimm =3D tcg_const_i64(dup_const(a->size, a->shift)); + + for (pass =3D 0; pass < a->q + 1; pass++) { + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + neon_load_reg64(tmp, a->vm + pass); + fn(tmp, cpu_env, tmp, constimm); + neon_store_reg64(tmp, a->vd + pass); + } + tcg_temp_free_i64(constimm); + return true; +} + +static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, + NeonGenTwoOpEnvFn *fn) +{ + /* + * 2-reg-and-shift operations, size < 3 case, where the + * helper needs to be passed cpu_env. + */ + TCGv_i32 constimm; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * To avoid excessive duplication of ops we implement shift + * by immediate using the variable shift operations. + */ + constimm =3D tcg_const_i32(dup_const(a->size, a->shift)); + + for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { + TCGv_i32 tmp =3D neon_load_reg(a->vm, pass); + fn(tmp, cpu_env, tmp, constimm); + neon_store_reg(a->vd, pass, tmp); + } + tcg_temp_free_i32(constimm); + return true; +} + +#define DO_2SHIFT_ENV(INSN, FUNC) \ + static bool trans_##INSN##_64_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64); \ + } \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + static NeonGenTwoOpEnvFn * const fns[] =3D { \ + gen_helper_neon_##FUNC##8, \ + gen_helper_neon_##FUNC##16, \ + gen_helper_neon_##FUNC##32, \ + }; \ + assert(a->size < ARRAY_SIZE(fns)); \ + return do_2shift_env_32(s, a, fns[a->size]); \ + } + +DO_2SHIFT_ENV(VQSHLU, qshlu_s) +DO_2SHIFT_ENV(VQSHL_U, qshl_u) +DO_2SHIFT_ENV(VQSHL_S, qshl_s) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4a55986aad9..d711d39eb9d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3011,29 +3011,6 @@ static inline void gen_neon_rsb(int size, TCGv_i32 t= 0, TCGv_i32 t1) } } =20 -#define GEN_NEON_INTEGER_OP_ENV(name) do { \ - switch ((size << 1) | u) { \ - case 0: \ - gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \ - break; \ - case 1: \ - gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \ - break; \ - case 2: \ - gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \ - break; \ - case 3: \ - gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \ - break; \ - case 4: \ - gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \ - break; \ - case 5: \ - gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \ - break; \ - default: return 1; \ - }} while (0) - static TCGv_i32 neon_load_scratch(int scratch) { TCGv_i32 tmp =3D tcg_temp_new_i32(); @@ -5252,7 +5229,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) int size; int shift; int pass; - int count; int u; int vec_size; uint32_t imm; @@ -5302,6 +5278,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case 3: /* VRSRA */ case 4: /* VSRI */ case 5: /* VSHL, VSLI */ + case 6: /* VQSHLU */ + case 7: /* VQSHL */ return 1; /* handled by decodetree */ default: break; @@ -5319,89 +5297,7 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) size--; } shift =3D (insn >> 16) & ((1 << (3 + size)) - 1); - if (op < 8) { - /* Shift by immediate: - VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */ - if (q && ((rd | rm) & 1)) { - return 1; - } - if (!u && (op =3D=3D 4 || op =3D=3D 6)) { - return 1; - } - /* Right shifts are encoded as N - shift, where N is the - element size in bits. */ - if (op <=3D 4) { - shift =3D shift - (1 << (size + 3)); - } - - if (size =3D=3D 3) { - count =3D q + 1; - } else { - count =3D q ? 4: 2; - } - - /* To avoid excessive duplication of ops we implement shift - * by immediate using the variable shift operations. - */ - imm =3D dup_const(size, shift); - - for (pass =3D 0; pass < count; pass++) { - if (size =3D=3D 3) { - neon_load_reg64(cpu_V0, rm + pass); - tcg_gen_movi_i64(cpu_V1, imm); - switch (op) { - case 6: /* VQSHLU */ - gen_helper_neon_qshlu_s64(cpu_V0, cpu_env, - cpu_V0, cpu_V1); - break; - case 7: /* VQSHL */ - if (u) { - gen_helper_neon_qshl_u64(cpu_V0, cpu_env, - cpu_V0, cpu_V1); - } else { - gen_helper_neon_qshl_s64(cpu_V0, cpu_env, - cpu_V0, cpu_V1); - } - break; - default: - g_assert_not_reached(); - } - neon_store_reg64(cpu_V0, rd + pass); - } else { /* size < 3 */ - /* Operands in T0 and T1. */ - tmp =3D neon_load_reg(rm, pass); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, imm); - switch (op) { - case 6: /* VQSHLU */ - switch (size) { - case 0: - gen_helper_neon_qshlu_s8(tmp, cpu_env, - tmp, tmp2); - break; - case 1: - gen_helper_neon_qshlu_s16(tmp, cpu_env, - tmp, tmp2); - break; - case 2: - gen_helper_neon_qshlu_s32(tmp, cpu_env, - tmp, tmp2); - break; - default: - abort(); - } - break; - case 7: /* VQSHL */ - GEN_NEON_INTEGER_OP_ENV(qshl); - break; - default: - g_assert_not_reached(); - } - tcg_temp_free_i32(tmp2); - neon_store_reg(rd, pass, tmp); - } - } /* for pass */ - } else if (op < 10) { + if (op < 10) { /* Shift by immediate and narrow: VSHRN, VRSHRN, VQSHRN, VQRSHRN. */ int input_unsigned =3D (op =3D=3D 8) ? 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id s14sm3738327wmh.18.2020.05.15.07.21.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2020 07:21:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6WUuBCvwQjl4vjtsPhISoEx1Syp1mmE1uHgxZQrBY4A=; b=pN2qeP0xbN7eA6I//8+tBnfZdYkDiREPMMUAKyYVgoZPlxhOwEmRf/LlXM7D+tP4c1 JAROSdxHPfpu60jz8k+axPhfHtH7EPzQx20QFPP9PTfYMt0VqEGa9ggmqACVfys/XPSs xEbOyoCXM3ZzCmUSt2e2HgovCtZvnynBbv9spE5NpNYBdFd2m1ua3GnhS7xQOnn+QH2S +CHNw1Q0AfUJVy9ftc8nRnwTPBZA+5s0AQiico5MtxijJjVYhVAeCwJYZ77rDVpTvdXN celcf/EJLIfWfl9T4nnQ3SFUVL5trs/w/iPPtFwvLQfpH8DPq0zJRbCooLOULHyXoEer iIsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6WUuBCvwQjl4vjtsPhISoEx1Syp1mmE1uHgxZQrBY4A=; b=d0IGe1O1gWHv5mUtIOYHpnVgJ9H2nFbu+lv5v3cpafH9HC1O2zhm54KucMaabP4FWK 1YtmId6JPLcLGFOHVlL/2j7sqTb0dkJ2dHtxQNBAMeFaE2frUWtYcJ7Wnh2v6dOAg9JD ZPNtFltRAbv8MEPLx81sSNPMiCrgJXh8q467oHxZnT5MLU4QLzzO/ZGEdQcEIim4o7LN s5xZkekGO8Gw2/uBRJTO3VpkWcxnw4+I8YrPOk0K2O9OGWURdR0YFH8p5dkURtE522mK BDa1ZflNwvVZWozlcg/51B5/5R0nK2Eg1KGJ3F+x29rOFHvCvjRLx6uIyLZtUqQQ08RV rZGA== X-Gm-Message-State: AOAM532wku5Q2voZuPKn9DwshZlNhuWMbBGDBJjMvFJPelmk1OfwtMzn /S2RL8/bgokB3ltVOioo+Me8sC0Za3ijkQ== X-Google-Smtp-Source: ABdhPJzIyXF6lxulg4O0m/wZxheQak7SZFgs7GlNedMgoJHxak5tTvWmdTPPuIx4Ml1XrGdgn4ncPQ== X-Received: by 2002:a1c:27c2:: with SMTP id n185mr3508422wmn.68.1589552465562; Fri, 15 May 2020 07:21:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/10] target/arm: Convert Neon narrowing shifts with op==8 to decodetree Date: Fri, 15 May 2020 15:20:52 +0100 Message-Id: <20200515142056.21346-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200515142056.21346-1-peter.maydell@linaro.org> References: <20200515142056.21346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the Neon narrowing shifts where op=3D=3D8 to decodetree: * VSHRN * VRSHRN * VQSHRUN * VQRSHRUN Signed-off-by: Peter Maydell --- target/arm/neon-dp.decode | 32 ++++++ target/arm/translate-neon.inc.c | 168 ++++++++++++++++++++++++++++++++ target/arm/translate.c | 1 + 3 files changed, 201 insertions(+) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 6456b53a690..f8d19c5819c 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -208,6 +208,10 @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ...= 1 .... @3same_fp =20 @2reg_shift .... ... . . . ...... .... .... . q:1 . . .... \ &2reg_shift vm=3D%vm_dp vd=3D%vd_dp +@2reg_shift_q0 .... ... . . . ...... .... .... . 0 . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp q=3D0 +@2reg_shift_q1 .... ... . . . ...... .... .... . 1 . . .... \ + &2reg_shift vm=3D%vm_dp vd=3D%vd_dp q=3D1 =20 # Right shifts are encoded as N - shift, where N is the element size in bi= ts. %neon_rshift_i6 16:6 !function=3Drsub_64 @@ -340,3 +344,31 @@ VQSHL_U_2sh 1111 001 1 1 . 01 shift:4 .... 0111 = 0 . . 1 .... \ @2reg_shift size=3D1 VQSHL_U_2sh 1111 001 1 1 . 001 shift:3 .... 0111 0 . . 1 .... \ @2reg_shift size=3D0 + +VSHRN_64_2sh 1111 001 0 1 . 1 ..... .... 1000 0 . . 1 .... \ + @2reg_shift_q0 size=3D3 shift=3D%neon_rshift_i5 +VSHRN_32_2sh 1111 001 0 1 . 01 .... .... 1000 0 . . 1 .... \ + @2reg_shift_q0 size=3D2 shift=3D%neon_rshift_i4 +VSHRN_16_2sh 1111 001 0 1 . 001 ... .... 1000 0 . . 1 .... \ + @2reg_shift_q0 size=3D1 shift=3D%neon_rshift_i3 + +VRSHRN_64_2sh 1111 001 0 1 . 1 ..... .... 1000 0 . . 1 .... \ + @2reg_shift_q1 size=3D3 shift=3D%neon_rshift_i5 +VRSHRN_32_2sh 1111 001 0 1 . 01 .... .... 1000 0 . . 1 .... \ + @2reg_shift_q1 size=3D2 shift=3D%neon_rshift_i4 +VRSHRN_16_2sh 1111 001 0 1 . 001 ... .... 1000 0 . . 1 .... \ + @2reg_shift_q1 size=3D1 shift=3D%neon_rshift_i3 + +VQSHRUN_64_2sh 1111 001 1 1 . 1 ..... .... 1000 0 . . 1 .... \ + @2reg_shift_q0 size=3D3 shift=3D%neon_rshift_i5 +VQSHRUN_32_2sh 1111 001 1 1 . 01 .... .... 1000 0 . . 1 .... \ + @2reg_shift_q0 size=3D2 shift=3D%neon_rshift_i4 +VQSHRUN_16_2sh 1111 001 1 1 . 001 ... .... 1000 0 . . 1 .... \ + @2reg_shift_q0 size=3D1 shift=3D%neon_rshift_i3 + +VQRSHRUN_64_2sh 1111 001 1 1 . 1 ..... .... 1000 0 . . 1 .... \ + @2reg_shift_q1 size=3D3 shift=3D%neon_rshift_i5 +VQRSHRUN_32_2sh 1111 001 1 1 . 01 .... .... 1000 0 . . 1 .... \ + @2reg_shift_q1 size=3D2 shift=3D%neon_rshift_i4 +VQRSHRUN_16_2sh 1111 001 1 1 . 001 ... .... 1000 0 . . 1 .... \ + @2reg_shift_q1 size=3D1 shift=3D%neon_rshift_i3 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 396db55565f..18ea7255e38 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1504,3 +1504,171 @@ static bool do_2shift_env_32(DisasContext *s, arg_2= reg_shift *a, DO_2SHIFT_ENV(VQSHLU, qshlu_s) DO_2SHIFT_ENV(VQSHL_U, qshl_u) DO_2SHIFT_ENV(VQSHL_S, qshl_s) + +static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, + NeonGenTwo64OpFn *shiftfn, + NeonGenNarrowEnvFn *narrowfn) +{ + /* 2-reg-and-shift narrowing-shift operations, size =3D=3D 3 case */ + TCGv_i64 constimm, rm1, rm2; + TCGv_i32 rd; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vm & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * This is always a right shift, and the shiftfn is always a + * left-shift helper, which thus needs the negated shift count. + */ + constimm =3D tcg_const_i64(-a->shift); + rm1 =3D tcg_temp_new_i64(); + rm2 =3D tcg_temp_new_i64(); + + /* Load both inputs first to avoid potential overwrite if rm =3D=3D rd= */ + neon_load_reg64(rm1, a->vm); + neon_load_reg64(rm2, a->vm + 1); + + shiftfn(rm1, rm1, constimm); + rd =3D tcg_temp_new_i32(); + narrowfn(rd, cpu_env, rm1); + neon_store_reg(a->vd, 0, rd); + + shiftfn(rm2, rm2, constimm); + rd =3D tcg_temp_new_i32(); + narrowfn(rd, cpu_env, rm2); + neon_store_reg(a->vd, 1, rd); + + tcg_temp_free_i64(rm1); + tcg_temp_free_i64(rm2); + tcg_temp_free_i64(constimm); + + return true; +} + +static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, + NeonGenTwoOpFn *shiftfn, + NeonGenNarrowEnvFn *narrowfn) +{ + /* 2-reg-and-shift narrowing-shift operations, size < 3 case */ + TCGv_i32 constimm, rm1, rm2, rm3, rm4; + TCGv_i64 rtmp; + uint32_t imm; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vm & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * This is always a right shift, and the shiftfn is always a + * left-shift helper, which thus needs the negated shift count + * duplicated into each lane of the immediate value. + */ + if (a->size =3D=3D 1) { + imm =3D (uint16_t)(-a->shift); + imm |=3D imm << 16; + } else { + /* size =3D=3D 2 */ + imm =3D -a->shift; + } + constimm =3D tcg_const_i32(imm); + + /* Load all inputs first to avoid potential overwrite */ + rm1 =3D neon_load_reg(a->vm, 0); + rm2 =3D neon_load_reg(a->vm, 1); + rm3 =3D neon_load_reg(a->vm + 1, 0); + rm4 =3D neon_load_reg(a->vm + 1, 1); + rtmp =3D tcg_temp_new_i64(); + + // todo expand out the shift-narrow and the narrow-op + shiftfn(rm1, rm1, constimm); + shiftfn(rm2, rm2, constimm); + + tcg_gen_concat_i32_i64(rtmp, rm1, rm2); + tcg_temp_free_i32(rm2); + + narrowfn(rm1, cpu_env, rtmp); + neon_store_reg(a->vd, 0, rm1); + + shiftfn(rm3, rm3, constimm); + shiftfn(rm4, rm4, constimm); + tcg_temp_free_i32(constimm); + + tcg_gen_concat_i32_i64(rtmp, rm3, rm4); + tcg_temp_free_i32(rm4); + + narrowfn(rm3, cpu_env, rtmp); + tcg_temp_free_i64(rtmp); + neon_store_reg(a->vd, 1, rm3); + return true; +} + +#define DO_2SN_64(INSN, FUNC, NARROWFUNC) \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_2shift_narrow_64(s, a, FUNC, NARROWFUNC); \ + } +#define DO_2SN_32(INSN, FUNC, NARROWFUNC) \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC); \ + } + +static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) +{ + tcg_gen_extrl_i64_i32(dest, src); +} + +static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) +{ + gen_helper_neon_narrow_u16(dest, src); +} + +static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) +{ + gen_helper_neon_narrow_u8(dest, src); +} + +DO_2SN_64(VSHRN_64, gen_ushl_i64, gen_neon_narrow_u32) +DO_2SN_32(VSHRN_32, gen_ushl_i32, gen_neon_narrow_u16) +DO_2SN_32(VSHRN_16, gen_helper_neon_shl_u16, gen_neon_narrow_u8) + +DO_2SN_64(VRSHRN_64, gen_helper_neon_rshl_u64, gen_neon_narrow_u32) +DO_2SN_32(VRSHRN_32, gen_helper_neon_rshl_u32, gen_neon_narrow_u16) +DO_2SN_32(VRSHRN_16, gen_helper_neon_rshl_u16, gen_neon_narrow_u8) + +DO_2SN_64(VQSHRUN_64, gen_sshl_i64, gen_helper_neon_unarrow_sat32) +DO_2SN_32(VQSHRUN_32, gen_sshl_i32, gen_helper_neon_unarrow_sat16) +DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat= 8) + +DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_s= at32) +DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_s= at16) +DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_s= at8) diff --git a/target/arm/translate.c b/target/arm/translate.c index d711d39eb9d..f884db535b4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5280,6 +5280,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case 5: /* VSHL, VSLI */ case 6: /* VQSHLU */ case 7: /* VQSHL */ + case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */ return 1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id s14sm3738327wmh.18.2020.05.15.07.21.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2020 07:21:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c8QnJPR4e5CrzI56PlTXE4px0fnMWNVyL5clfFDkQxI=; b=FnK6mW7Hs+yENpbeJgKPfn/6OaYR3a0T+EDo97QXkvy+nPAtkPOBK9WZEsLa50oblW xeI78A81soy36c84l2mijikk/3XXq+vMnLBxo0GZxKyx5T+/f1eQyWCAoH++A6DhoUi1 SSeg4JeBH+4KDZE8tCx24G24Bxe0yFQ6TXo+g0WsWLG6XhuxZPudwXDw2BeJdZbUY+K9 Uk/t6Q6PR60+f4lJRpSaxMmQ/mOU7YB9ABDMx+9MlRBA1lVKP5SPMUD/pmpXssm2gMx3 gXMsLo+KTwQ+1NVQXMc74MtSegNRmvGZpP+hPnNiQHn3zeWK7aCvwgK3Nu2ZltXBklBs Ui5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c8QnJPR4e5CrzI56PlTXE4px0fnMWNVyL5clfFDkQxI=; b=lJ+3oHHYmmHuFRxO6hgrxTbyD5KwoPyEJwihYT0O1mJ31Y3Aizt7Z1ovXzbbUAtOHz 9rK2+aUkF6nV1l1EVMB9+2Fl+Lxnju4ZIVmLeD4x74/f4D6Csgp56m6Hrev6344lM+xt 9Uc4pm8GEneiIEVQ4TXIFGBDsnBX2uRzeRAyXeNiJPQuRnnz1d8VIumCSB4psqfE8591 fWiIRbWoegMY8mJaD4z+ophRCkLfAyOEC+8C/w7KmR5zzTtu17oP8RnWKE3Z1d5MeHGb Vd929+4HKvnwjq/PZBpxUpEwxW5yaFkRBgnQc6CBkv7/EonOkKYY2kxR3IUT9eRWE0kC wCIg== X-Gm-Message-State: AOAM533BCiGkZH/VMnC0u0hrW3wUTWvkqkGoazzje7R249gi3dHDLJm0 xZ3YN0JLlroS7uIAwRY6Yx+VvAF8yh25Jg== X-Google-Smtp-Source: ABdhPJwraKBeLSiclF44DaE6MNhr7DYjeEUvPAlLqWBB8Q79WClQMtKr7/jXJDA/OOjSwEUJEmbWcA== X-Received: by 2002:a1c:ed04:: with SMTP id l4mr4356995wmh.93.1589552466680; Fri, 15 May 2020 07:21:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/10] target/arm: Convert Neon narrowing shifts with op==9 to decodetree Date: Fri, 15 May 2020 15:20:53 +0100 Message-Id: <20200515142056.21346-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200515142056.21346-1-peter.maydell@linaro.org> References: <20200515142056.21346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the remaining Neon narrowing shifts to decodetree: * VQSHRN * VQRSHRN Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 32 ++++++++++ target/arm/translate-neon.inc.c | 15 +++++ target/arm/translate.c | 110 +------------------------------- 3 files changed, 49 insertions(+), 108 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index f8d19c5819c..bf4ef8c555f 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -372,3 +372,35 @@ VQRSHRUN_32_2sh 1111 001 1 1 . 01 .... .... 1000 = 0 . . 1 .... \ @2reg_shift_q1 size=3D2 shift=3D%neon_rshift_i4 VQRSHRUN_16_2sh 1111 001 1 1 . 001 ... .... 1000 0 . . 1 .... \ @2reg_shift_q1 size=3D1 shift=3D%neon_rshift_i3 + +# VQSHRN with signed input +VQSHRN_S64_2sh 1111 001 0 1 . 1 ..... .... 1001 0 . . 1 .... \ + @2reg_shift_q0 size=3D3 shift=3D%neon_rshift_i5 +VQSHRN_S32_2sh 1111 001 0 1 . 01 .... .... 1001 0 . . 1 .... \ + @2reg_shift_q0 size=3D2 shift=3D%neon_rshift_i4 +VQSHRN_S16_2sh 1111 001 0 1 . 001 ... .... 1001 0 . . 1 .... \ + @2reg_shift_q0 size=3D1 shift=3D%neon_rshift_i3 + +# VQRSHRN with signed input +VQRSHRN_S64_2sh 1111 001 0 1 . 1 ..... .... 1001 0 . . 1 .... \ + @2reg_shift_q1 size=3D3 shift=3D%neon_rshift_i5 +VQRSHRN_S32_2sh 1111 001 0 1 . 01 .... .... 1001 0 . . 1 .... \ + @2reg_shift_q1 size=3D2 shift=3D%neon_rshift_i4 +VQRSHRN_S16_2sh 1111 001 0 1 . 001 ... .... 1001 0 . . 1 .... \ + @2reg_shift_q1 size=3D1 shift=3D%neon_rshift_i3 + +# VQSHRN with unsigned input +VQSHRN_U64_2sh 1111 001 1 1 . 1 ..... .... 1001 0 . . 1 .... \ + @2reg_shift_q0 size=3D3 shift=3D%neon_rshift_i5 +VQSHRN_U32_2sh 1111 001 1 1 . 01 .... .... 1001 0 . . 1 .... \ + @2reg_shift_q0 size=3D2 shift=3D%neon_rshift_i4 +VQSHRN_U16_2sh 1111 001 1 1 . 001 ... .... 1001 0 . . 1 .... \ + @2reg_shift_q0 size=3D1 shift=3D%neon_rshift_i3 + +# VQRSHRN with unsigned input +VQRSHRN_U64_2sh 1111 001 1 1 . 1 ..... .... 1001 0 . . 1 .... \ + @2reg_shift_q1 size=3D3 shift=3D%neon_rshift_i5 +VQRSHRN_U32_2sh 1111 001 1 1 . 01 .... .... 1001 0 . . 1 .... \ + @2reg_shift_q1 size=3D2 shift=3D%neon_rshift_i4 +VQRSHRN_U16_2sh 1111 001 1 1 . 001 ... .... 1001 0 . . 1 .... \ + @2reg_shift_q1 size=3D1 shift=3D%neon_rshift_i3 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 18ea7255e38..9a75a69a4f5 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1672,3 +1672,18 @@ DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_h= elper_neon_unarrow_sat8) DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_s= at32) DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_s= at16) DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_s= at8) +DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32) +DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16) +DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_= s8) + +DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64, gen_helper_neon_narrow_sa= t_s32) +DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32, gen_helper_neon_narrow_sa= t_s16) +DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sa= t_s8) + +DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32) +DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16) +DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_= u8) + +DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sa= t_u32) +DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sa= t_u16) +DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sa= t_u8) diff --git a/target/arm/translate.c b/target/arm/translate.c index f884db535b4..f728231b198 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3201,40 +3201,6 @@ static inline void gen_neon_unarrow_sats(int size, T= CGv_i32 dest, TCGv_i64 src) } } =20 -static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32 = shift, - int q, int u) -{ - if (q) { - if (u) { - switch (size) { - case 1: gen_helper_neon_rshl_u16(var, var, shift); break; - case 2: gen_helper_neon_rshl_u32(var, var, shift); break; - default: abort(); - } - } else { - switch (size) { - case 1: gen_helper_neon_rshl_s16(var, var, shift); break; - case 2: gen_helper_neon_rshl_s32(var, var, shift); break; - default: abort(); - } - } - } else { - if (u) { - switch (size) { - case 1: gen_helper_neon_shl_u16(var, var, shift); break; - case 2: gen_ushl_i32(var, var, shift); break; - default: abort(); - } - } else { - switch (size) { - case 1: gen_helper_neon_shl_s16(var, var, shift); break; - case 2: gen_sshl_i32(var, var, shift); break; - default: abort(); - } - } - } -} - static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, i= nt u) { if (u) { @@ -5281,6 +5247,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case 6: /* VQSHLU */ case 7: /* VQSHL */ case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */ + case 9: /* VQSHRN, VQRSHRN */ return 1; /* handled by decodetree */ default: break; @@ -5298,80 +5265,7 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) size--; } shift =3D (insn >> 16) & ((1 << (3 + size)) - 1); - if (op < 10) { - /* Shift by immediate and narrow: - VSHRN, VRSHRN, VQSHRN, VQRSHRN. */ - int input_unsigned =3D (op =3D=3D 8) ? !u : u; - if (rm & 1) { - return 1; - } - shift =3D shift - (1 << (size + 3)); - size++; - if (size =3D=3D 3) { - tmp64 =3D tcg_const_i64(shift); - neon_load_reg64(cpu_V0, rm); - neon_load_reg64(cpu_V1, rm + 1); - for (pass =3D 0; pass < 2; pass++) { - TCGv_i64 in; - if (pass =3D=3D 0) { - in =3D cpu_V0; - } else { - in =3D cpu_V1; - } - if (q) { - if (input_unsigned) { - gen_helper_neon_rshl_u64(cpu_V0, in, tmp64= ); - } else { - gen_helper_neon_rshl_s64(cpu_V0, in, tmp64= ); - } - } else { - if (input_unsigned) { - gen_ushl_i64(cpu_V0, in, tmp64); - } else { - gen_sshl_i64(cpu_V0, in, tmp64); - } - } - tmp =3D tcg_temp_new_i32(); - gen_neon_narrow_op(op =3D=3D 8, u, size - 1, tmp, = cpu_V0); - neon_store_reg(rd, pass, tmp); - } /* for pass */ - tcg_temp_free_i64(tmp64); - } else { - if (size =3D=3D 1) { - imm =3D (uint16_t)shift; - imm |=3D imm << 16; - } else { - /* size =3D=3D 2 */ - imm =3D (uint32_t)shift; - } - tmp2 =3D tcg_const_i32(imm); - tmp4 =3D neon_load_reg(rm + 1, 0); - tmp5 =3D neon_load_reg(rm + 1, 1); - for (pass =3D 0; pass < 2; pass++) { - if (pass =3D=3D 0) { - tmp =3D neon_load_reg(rm, 0); - } else { - tmp =3D tmp4; - } - gen_neon_shift_narrow(size, tmp, tmp2, q, - input_unsigned); - if (pass =3D=3D 0) { - tmp3 =3D neon_load_reg(rm, 1); - } else { - tmp3 =3D tmp5; - } - gen_neon_shift_narrow(size, tmp3, tmp2, q, - input_unsigned); - tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp3); - tmp =3D tcg_temp_new_i32(); - gen_neon_narrow_op(op =3D=3D 8, u, size - 1, tmp, = cpu_V0); - neon_store_reg(rd, pass, tmp); - } /* for pass */ - tcg_temp_free_i32(tmp2); - } - } else if (op =3D=3D 10) { + if (op =3D=3D 10) { /* VSHLL, VMOVL */ if (q || (rd & 1)) { return 1; --=20 2.20.1 From nobody Thu May 2 06:10:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id s14sm3738327wmh.18.2020.05.15.07.21.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2020 07:21:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t3k1YQ3YiPwjNYyBRfLq+hISGgzCVFU8auqRb6w56y0=; b=l+QqZYzCRr4nLEcvxPdjVOcUe+AmZvJMVlwv1eegUJSgpEiV0ddzolUhCwsNp1caIy 4Ggg8u4OQRgHjltGvee35g0Lo2nz2hvcRi6rz5XQKN79KoStIV6UKsdk36FSrxOUYCoe h3X6vHgetEq9HiUcMDm+O4Q+hvWt29bSpkDc9km/3EZGU2sACcLw1EWeEf+xvtY5D+rn JftWx53MtYyzHY7lt+2tQpDpC0rIc40xhZ2/ngPH4kt7bujzxZxsXcGP+e+hoIlkRsGA d4Gm+K29/cmPJsTwVrzVRx/sTGvJXFZedJfFuyo9IkCoOswiOuyZAfmVwPDxsVk/PrCb I7LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t3k1YQ3YiPwjNYyBRfLq+hISGgzCVFU8auqRb6w56y0=; b=npqUjLH4aTgPyCh/qyvn4a1Pq8mM00Ujt1yBR32ZSautbGYL29Mena44uot7nkNrHJ fykIswWDt7vimnOIdENPPDH2oovY4yW9QeaCUVaFPQi3bl8/WMf571qZuUeY4dmk0ceF xWsioBA6T82Q0eiQCZjNtHdeYpl1Tfks0wTGeA10mlUk/LtgCYpplUNS/yM9SyIAVgvI yKA0YoLN0Jbhh7INJ0SLtVaqQbVATGLLBoeadmYq1vk3L83VTvmZ3UBh3Qe7dvrs/cS+ 6CnIav5gArWAYdJ1t0D+cvB+2rx2M0/TENhwmbOCxQCAFWd0KE/D4iYYH9Isozz9SuUJ +9hQ== X-Gm-Message-State: AOAM530u1BJDWADwOgn1XwASDTljrmdeg9uP8iKxsP0wFNTx0DjpmSTZ JCairNyWbpB7+gObUpDl8cf2rw== X-Google-Smtp-Source: ABdhPJzOmWOjMnaik0TPqiDzqwTgPG1DsgK7bB0+C4pxzn4ibawFND08mWp8d/wiaQRpjPtkPirSjg== X-Received: by 2002:a1c:dd09:: with SMTP id u9mr4384418wmg.77.1589552467889; Fri, 15 May 2020 07:21:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/10] target/arm: Convert Neon VSHLL, VMOVL to decodetree Date: Fri, 15 May 2020 15:20:54 +0100 Message-Id: <20200515142056.21346-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200515142056.21346-1-peter.maydell@linaro.org> References: <20200515142056.21346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VSHLL and VMOVL insns from the 2-reg-shift group to decodetree. Since the loop always has two passes, we unroll it to avoid the awkward reassignment of one TCGv to another. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 14 ++++++ target/arm/translate-neon.inc.c | 81 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 46 +------------------ 3 files changed, 97 insertions(+), 44 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index bf4ef8c555f..4438c1c8728 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -404,3 +404,17 @@ VQRSHRN_U32_2sh 1111 001 1 1 . 01 .... .... 1001 = 0 . . 1 .... \ @2reg_shift_q1 size=3D2 shift=3D%neon_rshift_i4 VQRSHRN_U16_2sh 1111 001 1 1 . 001 ... .... 1001 0 . . 1 .... \ @2reg_shift_q1 size=3D1 shift=3D%neon_rshift_i3 + +VSHLL_S_2sh 1111 001 0 1 . 1 shift:5 .... 1010 0 . . 1 .... \ + @2reg_shift_q0 size=3D2 +VSHLL_S_2sh 1111 001 0 1 . 01 shift:4 .... 1010 0 . . 1 .... \ + @2reg_shift_q0 size=3D1 +VSHLL_S_2sh 1111 001 0 1 . 001 shift:3 .... 1010 0 . . 1 .... \ + @2reg_shift_q0 size=3D0 + +VSHLL_U_2sh 1111 001 1 1 . 1 shift:5 .... 1010 0 . . 1 .... \ + @2reg_shift_q0 size=3D2 +VSHLL_U_2sh 1111 001 1 1 . 01 shift:4 .... 1010 0 . . 1 .... \ + @2reg_shift_q0 size=3D1 +VSHLL_U_2sh 1111 001 1 1 . 001 shift:3 .... 1010 0 . . 1 .... \ + @2reg_shift_q0 size=3D0 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 9a75a69a4f5..5678bfd0d4d 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1687,3 +1687,84 @@ DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_h= elper_neon_narrow_sat_u8) DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sa= t_u32) DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sa= t_u16) DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sa= t_u8) + +static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, + NeonGenWidenFn *widenfn, bool u) +{ + TCGv_i64 tmp; + TCGv_i32 rm0, rm1; + uint64_t widen_mask =3D 0; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vd & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * This is a widen-and-shift operation. The shift is always less + * than the width of the source type, so after widening the input + * vector we can simply shift the whole 64-bit widened register, + * and then clear the potential overflow bits resulting from left + * bits of the narrow input appearing as right bits of the left + * neighbour narrow input. Calculate a mask of bits to clear. + */ + if ((a->shift !=3D 0) && (a->size < 2 || u)) { + int esize =3D 8 << a->size; + widen_mask =3D MAKE_64BIT_MASK(0, esize); + widen_mask >>=3D esize - a->shift; + widen_mask =3D dup_const(a->size + 1, widen_mask); + } + + rm0 =3D neon_load_reg(a->vm, 0); + rm1 =3D neon_load_reg(a->vm, 1); + tmp =3D tcg_temp_new_i64(); + + widenfn(tmp, rm0); + if (a->shift !=3D 0) { + tcg_gen_shli_i64(tmp, tmp, a->shift); + tcg_gen_andi_i64(tmp, tmp, ~widen_mask); + } + neon_store_reg64(tmp, a->vd); + + widenfn(tmp, rm1); + if (a->shift !=3D 0) { + tcg_gen_shli_i64(tmp, tmp, a->shift); + tcg_gen_andi_i64(tmp, tmp, ~widen_mask); + } + neon_store_reg64(tmp, a->vd + 1); + tcg_temp_free_i64(tmp); + return true; +} + +static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a) +{ + NeonGenWidenFn *widenfn[] =3D { + gen_helper_neon_widen_s8, + gen_helper_neon_widen_s16, + tcg_gen_ext_i32_i64, + }; + return do_vshll_2sh(s, a, widenfn[a->size], false); +} + +static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a) +{ + NeonGenWidenFn *widenfn[] =3D { + gen_helper_neon_widen_u8, + gen_helper_neon_widen_u16, + tcg_gen_extu_i32_i64, + }; + return do_vshll_2sh(s, a, widenfn[a->size], true); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index f728231b198..ef39c89f10a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5248,6 +5248,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case 7: /* VQSHL */ case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */ case 9: /* VQSHRN, VQRSHRN */ + case 10: /* VSHLL, including VMOVL */ return 1; /* handled by decodetree */ default: break; @@ -5265,50 +5266,7 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) size--; } shift =3D (insn >> 16) & ((1 << (3 + size)) - 1); - if (op =3D=3D 10) { - /* VSHLL, VMOVL */ - if (q || (rd & 1)) { - return 1; - } - tmp =3D neon_load_reg(rm, 0); - tmp2 =3D neon_load_reg(rm, 1); - for (pass =3D 0; pass < 2; pass++) { - if (pass =3D=3D 1) - tmp =3D tmp2; - - gen_neon_widen(cpu_V0, tmp, size, u); - - if (shift !=3D 0) { - /* The shift is less than the width of the source - type, so we can just shift the whole register. = */ - tcg_gen_shli_i64(cpu_V0, cpu_V0, shift); - /* Widen the result of shift: we need to clear - * the potential overflow bits resulting from - * left bits of the narrow input appearing as - * right bits of left the neighbour narrow - * input. */ - if (size < 2 || !u) { - uint64_t imm64; - if (size =3D=3D 0) { - imm =3D (0xffu >> (8 - shift)); - imm |=3D imm << 16; - } else if (size =3D=3D 1) { - imm =3D 0xffff >> (16 - shift); - } else { - /* size =3D=3D 2 */ - imm =3D 0xffffffff >> (32 - shift); - } - if (size < 2) { - imm64 =3D imm | (((uint64_t)imm) << 32); - } else { - imm64 =3D imm; - } - tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64); - } - } - neon_store_reg64(cpu_V0, rd + pass); - } - } else if (op >=3D 14) { + if (op >=3D 14) { /* VCVT fixed-point. */ TCGv_ptr fpst; TCGv_i32 shiftv; --=20 2.20.1 From nobody Thu May 2 06:10:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id s14sm3738327wmh.18.2020.05.15.07.21.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2020 07:21:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wdYDE6D4f41OSyQDXa/yslAI5HysUIzYcX5Y5tAHexk=; b=qHYVBo/vibTvYrFIG9tPYKO9V3WJvlChV3Jz2ZtZtdJ0n1zWWiRJd6YDaZaByPlh+5 WWX9ilQGJ4qxPI1tDRdYF84TaSjSLAB9DZgVLwBktv/PNMEo4FiAEI6OgiQTf/oLL6wb txq2yyDKmeWkVt9fSmXVIBeoKedeQKmkubANV8zdgW32umW32MBHyV4R4QPwh6Nst1Lg 5LBUstFGWxF5c1HoSH+luYEDevZ1G9ZQlnvm63+MXC9OIx7+C2mSDO03Q9amjpH9yqdd gBZ16VluYNNvpwSrt+FPaN9V2Gi3RFmLxxgn9zktU5x+wIFupoYubaOvzHT/GlXuStOA UZ6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wdYDE6D4f41OSyQDXa/yslAI5HysUIzYcX5Y5tAHexk=; b=gPWfBJcTt/FYUgCryvX0uIaQvmDIyqIwlJoP9mvJooLDLLbmAWRxqBK41C6/pgWqRI MPL4iCaRkmqdmPEGcNeEJ4D7y98STWzvVtvepY7FPF/fyOTymwRh7gw9+ZH64KfBWrK7 pDClRHTO0XWjNaNR0//G1bNMwAR+j2ts1mpICWLLxPFcP+rqr9yjRgqRQqfTuwr3oqJ7 mbBIxAsiKst1nc4YsbFclNOquycX0zFHMK0N4Bz/IqNc1YhQ9KzeHjKUsFmAvz4l9klf b7bpYlUeyzcY94KD6yS9Krm2egHgV9IJF+MPaPseuC//WS6xIiYXfCJLltp08V2QY70V vzMA== X-Gm-Message-State: AOAM531fyBpe4Zd1QORRBPYUnlyNqWMjd30sIGHsvMoCML9r0BlOc/nr Xet9T8abJ2pnh8cSNgzzXeUCew== X-Google-Smtp-Source: ABdhPJyyLYygQwg3T0rGrZbw8AczQjz5canHjgzh+gOn+5cHZUXAmlVS0Dp4cqT+b5pSQkEYLTFVrg== X-Received: by 2002:a1c:a3c1:: with SMTP id m184mr4592450wme.91.1589552469153; Fri, 15 May 2020 07:21:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/10] target/arm: Convert VCVT fixed-point ops to decodetree Date: Fri, 15 May 2020 15:20:55 +0100 Message-Id: <20200515142056.21346-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200515142056.21346-1-peter.maydell@linaro.org> References: <20200515142056.21346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the VCVT fixed-point conversion operations in the Neon 2-regs-and-shift group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 12 ++++++ target/arm/translate-neon.inc.c | 53 +++++++++++++++++++++++ target/arm/translate.c | 75 +-------------------------------- 3 files changed, 67 insertions(+), 73 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 4438c1c8728..bce4043746e 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -418,3 +418,15 @@ VSHLL_U_2sh 1111 001 1 1 . 01 shift:4 .... 1010 = 0 . . 1 .... \ @2reg_shift_q0 size=3D1 VSHLL_U_2sh 1111 001 1 1 . 001 shift:3 .... 1010 0 . . 1 .... \ @2reg_shift_q0 size=3D0 + +# VCVT fixed<->float conversions +# TODO: FP16 fixed<->float conversions are opc=3D=3D0b1100 and 0b1101 +# We use size=3D0 for fp32 and size=3D1 for fp16 to match the 3-same encod= ings. +VCVT_SF_2sh 1111 001 0 1 . 1 shift:5 .... 1110 0 . . 1 .... \ + @2reg_shift size=3D0 +VCVT_UF_2sh 1111 001 1 1 . 1 shift:5 .... 1110 0 . . 1 .... \ + @2reg_shift size=3D0 +VCVT_FS_2sh 1111 001 0 1 . 1 shift:5 .... 1111 0 . . 1 .... \ + @2reg_shift size=3D0 +VCVT_FU_2sh 1111 001 1 1 . 1 shift:5 .... 1111 0 . . 1 .... \ + @2reg_shift size=3D0 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index 5678bfd0d4d..f27fe769f85 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1768,3 +1768,56 @@ static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2= reg_shift *a) }; return do_vshll_2sh(s, a, widenfn[a->size], true); } + +static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, + NeonGenTwoSingleOPFn *fn) +{ + /* FP operations in 2-reg-and-shift group */ + TCGv_i32 tmp, shiftv; + TCGv_ptr fpstatus; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpstatus =3D get_fpstatus_ptr(1); + /* + * The decode doesn't include the must-be-1 top bit of imm6 in a->shif= t, + * hence this 32-shift where the ARM ARM has 64-imm6. + */ + shiftv =3D tcg_const_i32(32 - a->shift); + for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { + tmp =3D neon_load_reg(a->vm, pass); + fn(tmp, tmp, shiftv, fpstatus); + neon_store_reg(a->vd, pass, tmp); + } + tcg_temp_free_ptr(fpstatus); + tcg_temp_free_i32(shiftv); + return true; +} + +#define DO_FP_2SH(INSN, FUNC) \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_fp_2sh(s, a, FUNC); \ + } + +DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos) +DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos) +DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero) +DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero) diff --git a/target/arm/translate.c b/target/arm/translate.c index ef39c89f10a..9cc44e6258e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5193,7 +5193,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) int q; int rd, rn, rm, rd_ofs, rn_ofs, rm_ofs; int size; - int shift; int pass; int u; int vec_size; @@ -5234,78 +5233,8 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) return 1; } else if (insn & (1 << 4)) { if ((insn & 0x00380080) !=3D 0) { - /* Two registers and shift. */ - op =3D (insn >> 8) & 0xf; - - switch (op) { - case 0: /* VSHR */ - case 1: /* VSRA */ - case 2: /* VRSHR */ - case 3: /* VRSRA */ - case 4: /* VSRI */ - case 5: /* VSHL, VSLI */ - case 6: /* VQSHLU */ - case 7: /* VQSHL */ - case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */ - case 9: /* VQSHRN, VQRSHRN */ - case 10: /* VSHLL, including VMOVL */ - return 1; /* handled by decodetree */ - default: - break; - } - - if (insn & (1 << 7)) { - /* 64-bit shift. */ - if (op > 7) { - return 1; - } - size =3D 3; - } else { - size =3D 2; - while ((insn & (1 << (size + 19))) =3D=3D 0) - size--; - } - shift =3D (insn >> 16) & ((1 << (3 + size)) - 1); - if (op >=3D 14) { - /* VCVT fixed-point. */ - TCGv_ptr fpst; - TCGv_i32 shiftv; - VFPGenFixPointFn *fn; - - if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) { - return 1; - } - - if (!(op & 1)) { - if (u) { - fn =3D gen_helper_vfp_ultos; - } else { - fn =3D gen_helper_vfp_sltos; - } - } else { - if (u) { - fn =3D gen_helper_vfp_touls_round_to_zero; - } else { - fn =3D gen_helper_vfp_tosls_round_to_zero; - } - } - - /* We have already masked out the must-be-1 top bit of imm= 6, - * hence this 32-shift where the ARM ARM has 64-imm6. - */ - shift =3D 32 - shift; - fpst =3D get_fpstatus_ptr(1); - shiftv =3D tcg_const_i32(shift); - for (pass =3D 0; pass < (q ? 4 : 2); pass++) { - TCGv_i32 tmpf =3D neon_load_reg(rm, pass); - fn(tmpf, tmpf, shiftv, fpst); - neon_store_reg(rd, pass, tmpf); - } - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(shiftv); - } else { - return 1; - } + /* Two registers and shift: handled by decodetree */ + return 1; } else { /* (insn & 0x00380080) =3D=3D 0 */ int invert, reg_ofs, vec_size; =20 --=20 2.20.1 From nobody Thu May 2 06:10:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1589552952; cv=none; d=zohomail.com; s=zohoarc; b=JPMJg4muDqFtGk6l5pDeIZ9Htj1Zh1XrlOU2sCojguT9a7gb97k/DZ368V5544ifJiHIokuQRxi54Hy83gt/Ou7KiVkeqfKeoVgLTjNoYT9F/H7EmKV7w1oPu2U1EtbIZ/IRKywbAELpLRYlGzl7uEKF4s8RG9VaEW5wESTdy28= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589552952; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nNsSGVGF8y4So1qak3dO7LfQL9H2lgAJXftV4QL0Yx8=; b=IvR6VbobqM0LzCllQ9crTBth5OnH+Uy5W4Xjl15+xZdtc1YW3IS+GPW9n4ev26Rl6GgdtUfY5Gh+nm3n41GKed4xbz1qIeM3Mns7d6udxNqOM5xFK+NCqncR4F7RCTI2gUwpgvzWclZbXQPP8xEsPle1qJqKfGJujKVSXaMCxgI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589552952840420.8897709171574; Fri, 15 May 2020 07:29:12 -0700 (PDT) Received: from localhost ([::1]:57940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZbKp-0006Mv-9p for importer@patchew.org; Fri, 15 May 2020 10:29:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34876) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZbD7-000157-Ca for qemu-devel@nongnu.org; Fri, 15 May 2020 10:21:13 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:55536) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jZbD6-0003vL-2R for qemu-devel@nongnu.org; Fri, 15 May 2020 10:21:13 -0400 Received: by mail-wm1-x342.google.com with SMTP id f13so2490755wmc.5 for ; Fri, 15 May 2020 07:21:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id s14sm3738327wmh.18.2020.05.15.07.21.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2020 07:21:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nNsSGVGF8y4So1qak3dO7LfQL9H2lgAJXftV4QL0Yx8=; b=mum9kL3ByrWhU8A0oiXiqltR/TJV+/8rb+bTO6xaOd+63TBUwim7fr5ZezQCdAfGrn JyyRmas30Dvkpjh7YkTmcyNKIEZeCX0Fa158jd3iOp/SIqJwSM6i/aX2xbe953yKDvGb b8R4Ix0DREr2evxvOHFke0Cz82gDo1TTe3BeqVUMi06hEHmqhuaaBFE3HfanvrTKDnIK 88/zixazkxeQN84xBEfr9KsRovjzTDtEWZwdSPXZlFKl/PqYVVvfkqTJ2lYogrmDyvJU +xzCcfYc1JXr8bYRnnORskGzRlE4t1KKYaGokFSzEG3eFKf6t6r9QleMCUyAgfD9slYQ F3qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nNsSGVGF8y4So1qak3dO7LfQL9H2lgAJXftV4QL0Yx8=; b=gqYp8VsAXAiXUOkmUodiRhn5qIl5+5vGh71dEVvlQuCmZNFsl/dpFwxvsR1ees484h om3w4Zb+a1LWr3v4iaXdEo+Uh7lEOXjRNeNU5heEuKV4DewoDGsUD8gOeYbst/eIBx9N n8gT9wZu0yKTpW37a0kpXUMyOVYXp2QXOGuBvEDTQ7om3dBHWS/3BGu0iaLa8sPP85oj SlljnqvuTB6Wujf6EfkG+J+fYFUTq4AKLpQ43iUEgJy+zbyCl28Ge/r3uTiQMmjY5HX7 1ZTS2XSfoWi0VibeqDP77ZPRicJf7qcYgGARciDVVHho7TEYi5YF5mQvyt8fOIXFQpJx 1e2w== X-Gm-Message-State: AOAM5337/kln0d7XFpvTAuxyH2/aZ/rddTBIXlitHeaJhTD4CpR73zpF gWqOe91KB+P8AFzWhfAoQoo3lA== X-Google-Smtp-Source: ABdhPJzMUA5mK/DGYFshKV2Snad8Vl/Jsy0AAPzzEWscgloPDKWqUiCIj1sQ6c59edE/XZC67xWjUg== X-Received: by 2002:a05:600c:22c9:: with SMTP id 9mr4247016wmg.162.1589552470479; Fri, 15 May 2020 07:21:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/10] target/arm: Convert Neon one-register-and-immediate insns to decodetree Date: Fri, 15 May 2020 15:20:56 +0100 Message-Id: <20200515142056.21346-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200515142056.21346-1-peter.maydell@linaro.org> References: <20200515142056.21346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the insns in the one-register-and-immediate group to decodetree. Signed-off-by: Peter Maydell --- target/arm/neon-dp.decode | 49 +++++++++++ target/arm/translate-neon.inc.c | 151 ++++++++++++++++++++++++++++++++ target/arm/translate.c | 101 +-------------------- 3 files changed, 202 insertions(+), 99 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index bce4043746e..39d2217a9c8 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -430,3 +430,52 @@ VCVT_FS_2sh 1111 001 0 1 . 1 shift:5 .... 1111 = 0 . . 1 .... \ @2reg_shift size=3D0 VCVT_FU_2sh 1111 001 1 1 . 1 shift:5 .... 1111 0 . . 1 .... \ @2reg_shift size=3D0 + +###################################################################### +# 1-reg-and-modified-immediate grouping: +# 1111 001 i 1 D 000 imm:3 Vd:4 cmode:4 0 Q op 1 Vm:4 +###################################################################### + +&1reg_imm vd q imm cmode op + +%asimd_imm_value 24:1 16:3 0:4 + +@1reg_imm .... ... . . . ... ... .... .... . q:1 . . .... \ + &1reg_imm imm=3D%asimd_imm_value vd=3D%vd_dp + +{ + # Logic operations, ie not VMOV or VMVN: (cmode & 1) && cmode < 12 + VORR_1r 1111 001 . 1 . 000 ... .... 0001 0 . 0 1 .... \ + @1reg_imm cmode=3D1 op=3D0 + VORR_1r 1111 001 . 1 . 000 ... .... 0011 0 . 0 1 .... \ + @1reg_imm cmode=3D3 op=3D0 + VORR_1r 1111 001 . 1 . 000 ... .... 0101 0 . 0 1 .... \ + @1reg_imm cmode=3D5 op=3D0 + VORR_1r 1111 001 . 1 . 000 ... .... 0111 0 . 0 1 .... \ + @1reg_imm cmode=3D7 op=3D0 + VORR_1r 1111 001 . 1 . 000 ... .... 1001 0 . 0 1 .... \ + @1reg_imm cmode=3D9 op=3D0 + VORR_1r 1111 001 . 1 . 000 ... .... 1011 0 . 0 1 .... \ + @1reg_imm cmode=3D11 op=3D0 + + VBIC_1r 1111 001 . 1 . 000 ... .... 0001 0 . 1 1 .... \ + @1reg_imm cmode=3D1 op=3D1 + VBIC_1r 1111 001 . 1 . 000 ... .... 0011 0 . 1 1 .... \ + @1reg_imm cmode=3D3 op=3D1 + VBIC_1r 1111 001 . 1 . 000 ... .... 0101 0 . 1 1 .... \ + @1reg_imm cmode=3D5 op=3D1 + VBIC_1r 1111 001 . 1 . 000 ... .... 0111 0 . 1 1 .... \ + @1reg_imm cmode=3D7 op=3D1 + VBIC_1r 1111 001 . 1 . 000 ... .... 1001 0 . 1 1 .... \ + @1reg_imm cmode=3D9 op=3D1 + VBIC_1r 1111 001 . 1 . 000 ... .... 1011 0 . 1 1 .... \ + @1reg_imm cmode=3D11 op=3D1 + + # A VMVN special case: cmode =3D=3D 14 op =3D=3D 1 + VMVN_14_1r 1111 001 . 1 . 000 ... .... 1110 0 . 1 1 .... \ + @1reg_imm cmode=3D14 op=3D1 + + # VMOV, VMVN: all other cmode/op combinations + VMOV_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... \ + @1reg_imm +} diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index f27fe769f85..f4eeb84541f 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1821,3 +1821,154 @@ DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos) DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos) DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero) DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero) + +static uint32_t asimd_imm_const(uint32_t imm, int cmode, int op) +{ + /* + * Expand the encoded constant. + * Note that cmode =3D 2,3,4,5,6,7,10,11,12,13 imm=3D0 is UNPREDICTABL= E. + * We choose to not special-case this and will behave as if a + * valid constant encoding of 0 had been given. + * cmode =3D 15 op =3D 1 must UNDEF; we assume decode has handled that. + */ + switch (cmode) { + case 0: case 1: + /* no-op */ + break; + case 2: case 3: + imm <<=3D 8; + break; + case 4: case 5: + imm <<=3D 16; + break; + case 6: case 7: + imm <<=3D 24; + break; + case 8: case 9: + imm |=3D imm << 16; + break; + case 10: case 11: + imm =3D (imm << 8) | (imm << 24); + break; + case 12: + imm =3D (imm << 8) | 0xff; + break; + case 13: + imm =3D (imm << 16) | 0xffff; + break; + case 14: + imm |=3D (imm << 8) | (imm << 16) | (imm << 24); + if (op) { + imm =3D ~imm; + } + break; + case 15: + imm =3D ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) + | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); + break; + } + if (op) { + imm =3D ~imm; + } + return imm; +} + +static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, + GVecGen2iFn *fn) +{ + uint32_t imm; + int reg_ofs, vec_size; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + return false; + } + + if (a->vd & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + reg_ofs =3D neon_reg_offset(a->vd, 0); + vec_size =3D a->q ? 16 : 8; + imm =3D asimd_imm_const(a->imm, a->cmode, a->op); + + fn(MO_32, reg_ofs, reg_ofs, imm, vec_size, vec_size); + return true; +} + +static bool trans_VORR_1r(DisasContext *s, arg_1reg_imm *a) +{ + return do_1reg_imm(s, a, tcg_gen_gvec_ori); +} + +static bool trans_VBIC_1r(DisasContext *s, arg_1reg_imm *a) +{ + /* The immediate value will be inverted, so BIC becomes AND. */ + return do_1reg_imm(s, a, tcg_gen_gvec_andi); +} + +static bool trans_VMVN_14_1r(DisasContext *s, arg_1reg_imm *a) +{ + /* The cmode=3D=3D14 op=3D=3D1 special case isn't vectorized */ + uint32_t imm; + TCGv_i64 t64; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + return false; + } + + if (a->vd & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + imm =3D asimd_imm_const(a->imm, a->cmode, a->op); + + t64 =3D tcg_temp_new_i64(); + for (pass =3D 0; pass <=3D a->q; ++pass) { + uint64_t val =3D 0; + int n; + + for (n =3D 0; n < 8; n++) { + if (imm & (1 << (n + pass * 8))) { + val |=3D 0xffull << (n * 8); + } + } + tcg_gen_movi_i64(t64, val); + neon_store_reg64(t64, a->vd + pass); + } + tcg_temp_free_i64(t64); + return true; +} + +static void gen_VMOV_1r(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_dup_imm(MO_32, dofs, oprsz, maxsz, c); +} + +static bool trans_VMOV_1r(DisasContext *s, arg_1reg_imm *a) +{ + /* There is one unallocated cmode/op combination in this space */ + if (a->cmode =3D=3D 15 && a->op =3D=3D 1) { + return false; + } + return do_1reg_imm(s, a, gen_VMOV_1r); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 9cc44e6258e..20d07e99053 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5232,105 +5232,8 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) /* Three register same length: handled by decodetree */ return 1; } else if (insn & (1 << 4)) { - if ((insn & 0x00380080) !=3D 0) { - /* Two registers and shift: handled by decodetree */ - return 1; - } else { /* (insn & 0x00380080) =3D=3D 0 */ - int invert, reg_ofs, vec_size; - - if (q && (rd & 1)) { - return 1; - } - - op =3D (insn >> 8) & 0xf; - /* One register and immediate. */ - imm =3D (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf); - invert =3D (insn & (1 << 5)) !=3D 0; - /* Note that op =3D 2,3,4,5,6,7,10,11,12,13 imm=3D0 is UNPREDI= CTABLE. - * We choose to not special-case this and will behave as if a - * valid constant encoding of 0 had been given. - */ - switch (op) { - case 0: case 1: - /* no-op */ - break; - case 2: case 3: - imm <<=3D 8; - break; - case 4: case 5: - imm <<=3D 16; - break; - case 6: case 7: - imm <<=3D 24; - break; - case 8: case 9: - imm |=3D imm << 16; - break; - case 10: case 11: - imm =3D (imm << 8) | (imm << 24); - break; - case 12: - imm =3D (imm << 8) | 0xff; - break; - case 13: - imm =3D (imm << 16) | 0xffff; - break; - case 14: - imm |=3D (imm << 8) | (imm << 16) | (imm << 24); - if (invert) { - imm =3D ~imm; - } - break; - case 15: - if (invert) { - return 1; - } - imm =3D ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) - | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); - break; - } - if (invert) { - imm =3D ~imm; - } - - reg_ofs =3D neon_reg_offset(rd, 0); - vec_size =3D q ? 16 : 8; - - if (op & 1 && op < 12) { - if (invert) { - /* The immediate value has already been inverted, - * so BIC becomes AND. - */ - tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm, - vec_size, vec_size); - } else { - tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm, - vec_size, vec_size); - } - } else { - /* VMOV, VMVN. */ - if (op =3D=3D 14 && invert) { - TCGv_i64 t64 =3D tcg_temp_new_i64(); - - for (pass =3D 0; pass <=3D q; ++pass) { - uint64_t val =3D 0; - int n; - - for (n =3D 0; n < 8; n++) { - if (imm & (1 << (n + pass * 8))) { - val |=3D 0xffull << (n * 8); - } - } - tcg_gen_movi_i64(t64, val); - neon_store_reg64(t64, rd + pass); - } - tcg_temp_free_i64(t64); - } else { - tcg_gen_gvec_dup_imm(MO_32, reg_ofs, vec_size, - vec_size, imm); - } - } - } + /* Two registers and shift or reg and imm: handled by decodetree */ + return 1; } else { /* (insn & 0x00800010 =3D=3D 0x00800000) */ if (size !=3D 3) { op =3D (insn >> 8) & 0xf; --=20 2.20.1