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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id i7sm4986pjj.33.2020.05.14.14.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 May 2020 14:28:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QtavOgtJbqCDtFoMyh2yfPlecYMuCnzasezS0T2jFho=; b=Nrm1EtpZVTExEUl3ZJBZibMZF9mY+G7rJeCITqTr1OD6vv+8KVGcgFHxmPQnSVWjbJ vBCCweGupVA5Oqy2OlgU+zDforbVZE4ElCoORNLbeLyUG146wSxo/vJfScRvdYUl3uCy b8zMS5fVXXh9wnFa97u+lZ+AZIvZZ9WNggv6SXCNnZeikEZ2dlT4qQrD9bvJjW81yzcm Vi5Dk19qefQBMRQM/LJY3Tp14wwU7xvxlx0+mtdlOX47JNiPSCEuOWp3rgtaBxM9b6wc RqVK6ne74Sz58zJhhuaAToZFFpd8oOvsCmCWDw5ArZp0AAxnJn638ctNQFyZ4hGJ+EwV PyNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QtavOgtJbqCDtFoMyh2yfPlecYMuCnzasezS0T2jFho=; b=uEc8gsPHrSZkA/G5yZGXtq2LdDZ+jT16EKIeoMuqFA1LDCmUGwjCDMa+OX31G7XSPZ /VW4S1JcgwRH1LixgJlDpOKANOS7tuZYB4MveRI2L5oqxKBad0x3eMRxoG24KAtI5XoU wCru6L/H9Op252K9O/J/E0BXTsjJoS1hfqzbDMf5sGL2mssZQdE6C8CbHGeQ84VRCh0c LCbysQ26bwhtq1DfIbwyMeg3oy19C0t8ry4HuP2lSdmavLE/BwHaGxlgcE47SuyNvBAE hh4UylPCmQXlFER5ZiK+6auQd8psny6vBvbHYvVACQs0maoCX/MDZLPFBXtGz58Wp+/4 hP+Q== X-Gm-Message-State: AOAM531We2SSSkFLyLo8vjpMHDt3CUgo35EpYWuXIL0YJV65e5oaZxp5 wuhyfWzyN6NTmGvmmDaP+JyXadF1bNQ= X-Google-Smtp-Source: ABdhPJxidZQcqfERxf9H1XAUhqKmcs43rjnLzqqmTEMvPFc1QZ1JLed17g9gumignU1VSKkpNfhoIw== X-Received: by 2002:aa7:9096:: with SMTP id i22mr555981pfa.250.1589491716065; Thu, 14 May 2020 14:28:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/6] target/arm: Convert rax1 to gvec helpers Date: Thu, 14 May 2020 14:28:27 -0700 Message-Id: <20200514212831.31248-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200514212831.31248-1-richard.henderson@linaro.org> References: <20200514212831.31248-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" With this conversion, we will be able to use the same helpers with sve. This also fixes a bug in which we failed to clear the high bits of the SVE register after an AdvSIMD operation. Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 ++ target/arm/translate-a64.h | 3 ++ target/arm/crypto_helper.c | 11 +++++++ target/arm/translate-a64.c | 59 ++++++++++++++++++++------------------ 4 files changed, 47 insertions(+), 28 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 42759f82aa..6c4eb9befb 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -534,6 +534,8 @@ DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, v= oid, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) =20 +DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) =20 diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index f02fbb63a4..da0f59a2ce 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -115,4 +115,7 @@ static inline int vec_full_reg_size(DisasContext *s) =20 bool disas_sve(DisasContext *, uint32_t); =20 +void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, + uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); + #endif /* TARGET_ARM_TRANSLATE_A64_H */ diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c index 6bd5a3d2d0..372d8350e4 100644 --- a/target/arm/crypto_helper.c +++ b/target/arm/crypto_helper.c @@ -725,3 +725,14 @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* = vm, uint32_t desc) } clear_tail(vd, opr_sz, simd_maxsz(desc)); } + +void HELPER(crypto_rax1)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 8; ++i) { + d[i] =3D n[i] ^ rol64(m[i], 1); + } + clear_tail(vd, opr_sz, simd_maxsz(desc)); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1e511529b8..4d7a8fd2bb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13579,6 +13579,32 @@ static void disas_crypto_two_reg_sha(DisasContext = *s, uint32_t insn) tcg_temp_free_ptr(tcg_rn_ptr); } =20 +static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) +{ + tcg_gen_rotli_i64(d, m, 1); + tcg_gen_xor_i64(d, d, n); +} + +static void gen_rax1_vec(unsigned vece, TCGv_vec d, TCGv_vec n, TCGv_vec m) +{ + tcg_gen_rotli_vec(vece, d, m, 1); + tcg_gen_xor_vec(vece, d, d, n); +} + +void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, + uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_rotli_vec, 0 }; + static const GVecGen3 op =3D { + .fni8 =3D gen_rax1_i64, + .fniv =3D gen_rax1_vec, + .opt_opc =3D vecop_list, + .fno =3D gen_helper_crypto_rax1, + .vece =3D MO_64, + }; + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &op); +} + /* Crypto three-reg SHA512 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 * +-----------------------+------+---+---+-----+--------+------+------+ @@ -13595,6 +13621,7 @@ static void disas_crypto_three_reg_sha512(DisasCont= ext *s, uint32_t insn) bool feature; CryptoThreeOpFn *genfn =3D NULL; gen_helper_gvec_3 *oolfn =3D NULL; + GVecGen3Fn *gvecfn =3D NULL; =20 if (o =3D=3D 0) { switch (opcode) { @@ -13612,7 +13639,7 @@ static void disas_crypto_three_reg_sha512(DisasCont= ext *s, uint32_t insn) break; case 3: /* RAX1 */ feature =3D dc_isar_feature(aa64_sha3, s); - genfn =3D NULL; + gvecfn =3D gen_gvec_rax1; break; default: g_assert_not_reached(); @@ -13648,10 +13675,9 @@ static void disas_crypto_three_reg_sha512(DisasCon= text *s, uint32_t insn) =20 if (oolfn) { gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn); - return; - } - - if (genfn) { + } else if (gvecfn) { + gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64); + } else { TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; =20 tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); @@ -13663,29 +13689,6 @@ static void disas_crypto_three_reg_sha512(DisasCon= text *s, uint32_t insn) tcg_temp_free_ptr(tcg_rd_ptr); tcg_temp_free_ptr(tcg_rn_ptr); tcg_temp_free_ptr(tcg_rm_ptr); - } else { - TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; - int pass; - - tcg_op1 =3D tcg_temp_new_i64(); - tcg_op2 =3D tcg_temp_new_i64(); - tcg_res[0] =3D tcg_temp_new_i64(); - tcg_res[1] =3D tcg_temp_new_i64(); - - for (pass =3D 0; pass < 2; pass++) { - read_vec_element(s, tcg_op1, rn, pass, MO_64); - read_vec_element(s, tcg_op2, rm, pass, MO_64); - - tcg_gen_rotli_i64(tcg_res[pass], tcg_op2, 1); - tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); - } - write_vec_element(s, tcg_res[0], rd, 0, MO_64); - write_vec_element(s, tcg_res[1], rd, 1, MO_64); - - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); - tcg_temp_free_i64(tcg_res[0]); - tcg_temp_free_i64(tcg_res[1]); } } =20 --=20 2.20.1