From nobody Fri Nov 14 19:39:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1589484653; cv=none; d=zohomail.com; s=zohoarc; b=eCgkxXU2n5iF6vMI7PXgvc6tdzvjB1dSlG1OW7VAAhVRM+tpG0ngXAalwIHpOjWcrkgnTt8623FW5brCXqKIiMEsCT4yluVEMspAjKMrUCkIdmVC2TyP3M//sd0L/rFSg8CUgrqbtNBwEGjki1Cjs3D0ZGgr1FIrF5Fk4UQKq2A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589484653; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bFeqPWm2QsPGoTt7fEQgUrf7uzCq2N6hwh31edqpp1E=; b=FtVnPah2O/iVhUBf0hH7dtsu6GYCRSZbva6NBuQKGA0L/WiREDfBZjRzytavSSjsxAPtFbwdUD12Zut7bSH2Ie8aeRDvNSjMU4bOuD/zvQUdXgavT7r+Sn3wdtrq3C7gwPIm2a2t592eoC2+v59EoY/KAdj+rt/q3AlS7rUzUzs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589484653047546.6840000532288; Thu, 14 May 2020 12:30:53 -0700 (PDT) Received: from localhost ([::1]:37836 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZJZD-0004Uj-Ic for importer@patchew.org; Thu, 14 May 2020 15:30:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58194) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZJQE-0007UO-Fv for qemu-devel@nongnu.org; Thu, 14 May 2020 15:21:35 -0400 Received: from mail-lj1-x244.google.com ([2a00:1450:4864:20::244]:34160) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jZJQA-0007OM-5D for qemu-devel@nongnu.org; Thu, 14 May 2020 15:21:33 -0400 Received: by mail-lj1-x244.google.com with SMTP id b6so4843337ljj.1 for ; Thu, 14 May 2020 12:21:29 -0700 (PDT) Received: from localhost.localdomain ([109.245.227.98]) by smtp.gmail.com with ESMTPSA id h3sm2427257lfk.3.2020.05.14.12.21.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 May 2020 12:21:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bFeqPWm2QsPGoTt7fEQgUrf7uzCq2N6hwh31edqpp1E=; b=pILZZOe1QivWpiOyJAz3ngJqVvoGu3hY7oz6bGBQG4LuZcQgDnpeH497rKikbhFKDg j4dYAAu1F7T2Dz1C/M3WURQpHH1iTU+SC9r8kHRjjg1wA9y0iWBl0UjjPgvE278Q87HW VvFDTCpmiu/wfGsY3X73HuAqzIF2FAPEjEvVs4Brb9o67M5+Pw5tU9WQs+IRElieGbol T3rrJe1O74RBW9AS05OkkvknV2ul/8ienihlsVeEGzTxbvTUYldbSeCt6yujXrqRvd5I musFKSH05drCiBvNrKSoM+JyWTE5ro/mU0xsmYONB77lQ2uKu8a+uM6GgcpxTKslQzbc pc7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bFeqPWm2QsPGoTt7fEQgUrf7uzCq2N6hwh31edqpp1E=; b=fxmESP6T1XpHWmgwSHVDFpeo07NHnv7YcraW5PaPB/bM8BCHW7mMlyZIp8w2EvidVq 0XnghsOfqB+U07mYZWV6sDRgKD6mFf6W8nXYXGiw4dirEMr6M2oNnOcRP/+AvLFipS8u Ubu3u8ZxJYF21vQqAFPa2duWefr+KZ4RYw85dJsyBVvSFkhaaPkJxSbNuuP9jEPoKObP PfxbTx+ye/kUniaEpiE7jrLD9Ga8/jC+V0M9yt1JX8SGpuMR0w6i8Mmm61SIxyynVD0R S6/nzUHJslikagahnbP5Qwc3aApIN5MaH4oVmVxNb22CGHumivRc8UdjWnjxj85wHcVa nWtg== X-Gm-Message-State: AOAM5325j0Ed6ESmzX0BvMySESp0huIsjSmWzc3SdxQrvCzEFdso17bs YWzT2jo0Ie9CcyhPInpWVLOvzPMnNuk= X-Google-Smtp-Source: ABdhPJwyiwZ2yMk+Eo91RFph+cMYjHaamcfW4iY8K3OHj0BWTRfENuEPXVyamo4Xnl4RUdKg9MuoDA== X-Received: by 2002:a2e:3517:: with SMTP id z23mr3720080ljz.147.1589484088402; Thu, 14 May 2020 12:21:28 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH v2 15/17] target/mips: fpu: Name better paired-single variables Date: Thu, 14 May 2020 21:20:45 +0200 Message-Id: <20200514192047.5297-16-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200514192047.5297-1-aleksandar.qemu.devel@gmail.com> References: <20200514192047.5297-1-aleksandar.qemu.devel@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::244; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-lj1-x244.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@rt-rk.com, Aleksandar Markovic Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" Use consistently 'l' and 'h' for low and high halves. Signed-off-by: Aleksandar Markovic --- target/mips/fpu_helper.c | 62 ++++++++++++++++++++-------------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 56ba49104e..dbb8ca5692 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1059,14 +1059,14 @@ uint32_t helper_float_recip1_s(CPUMIPSState *env, u= int32_t fst0) =20 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) { - uint32_t fst2; + uint32_t fstl2; uint32_t fsth2; =20 - fst2 =3D float32_div(float32_one, fdt0 & 0XFFFFFFFF, - &env->active_fpu.fp_status); + fstl2 =3D float32_div(float32_one, fdt0 & 0XFFFFFFFF, + &env->active_fpu.fp_status); fsth2 =3D float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_sta= tus); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } =20 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) @@ -1091,15 +1091,15 @@ uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, u= int32_t fst0) =20 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) { - uint32_t fst2; + uint32_t fstl2; uint32_t fsth2; =20 - fst2 =3D float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + fstl2 =3D float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 =3D float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); - fst2 =3D float32_div(float32_one, fst2, &env->active_fpu.fp_status); + fstl2 =3D float32_div(float32_one, fstl2, &env->active_fpu.fp_status); fsth2 =3D float32_div(float32_one, fsth2, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } =20 uint64_t helper_float_rint_d(CPUMIPSState *env, uint64_t fs) @@ -1367,19 +1367,19 @@ uint32_t helper_float_recip2_s(CPUMIPSState *env, u= int32_t fst0, uint32_t fst2) =20 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t= fdt2) { - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; + uint32_t fstl0 =3D fdt0 & 0XFFFFFFFF; uint32_t fsth0 =3D fdt0 >> 32; - uint32_t fst2 =3D fdt2 & 0XFFFFFFFF; + uint32_t fstl2 =3D fdt2 & 0XFFFFFFFF; uint32_t fsth2 =3D fdt2 >> 32; =20 - fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fstl2 =3D float32_mul(fstl0, fstl2, &env->active_fpu.fp_status); fsth2 =3D float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_sub(fst2, float32_one, + fstl2 =3D float32_chs(float32_sub(fstl2, float32_one, &env->active_fpu.fp_status)); fsth2 =3D float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } =20 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t = fdt2) @@ -1404,51 +1404,51 @@ uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, u= int32_t fst0, uint32_t fst2) =20 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t= fdt2) { - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; + uint32_t fstl0 =3D fdt0 & 0XFFFFFFFF; uint32_t fsth0 =3D fdt0 >> 32; - uint32_t fst2 =3D fdt2 & 0XFFFFFFFF; + uint32_t fstl2 =3D fdt2 & 0XFFFFFFFF; uint32_t fsth2 =3D fdt2 >> 32; =20 - fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fstl2 =3D float32_mul(fstl0, fstl2, &env->active_fpu.fp_status); fsth2 =3D float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 =3D float32_sub(fst2, float32_one, &env->active_fpu.fp_status); + fstl2 =3D float32_sub(fstl2, float32_one, &env->active_fpu.fp_status); fsth2 =3D float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, + fstl2 =3D float32_chs(float32_div(fstl2, FLOAT_TWO32, &env->active_fpu.fp_status)); fsth2 =3D float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } =20 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t f= dt1) { - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; + uint32_t fstl0 =3D fdt0 & 0XFFFFFFFF; uint32_t fsth0 =3D fdt0 >> 32; - uint32_t fst1 =3D fdt1 & 0XFFFFFFFF; + uint32_t fstl1 =3D fdt1 & 0XFFFFFFFF; uint32_t fsth1 =3D fdt1 >> 32; - uint32_t fst2; + uint32_t fstl2; uint32_t fsth2; =20 - fst2 =3D float32_add(fst0, fsth0, &env->active_fpu.fp_status); - fsth2 =3D float32_add(fst1, fsth1, &env->active_fpu.fp_status); + fstl2 =3D float32_add(fstl0, fsth0, &env->active_fpu.fp_status); + fsth2 =3D float32_add(fstl1, fsth1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } =20 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t f= dt1) { - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; + uint32_t fstl0 =3D fdt0 & 0XFFFFFFFF; uint32_t fsth0 =3D fdt0 >> 32; - uint32_t fst1 =3D fdt1 & 0XFFFFFFFF; + uint32_t fstl1 =3D fdt1 & 0XFFFFFFFF; uint32_t fsth1 =3D fdt1 >> 32; - uint32_t fst2; + uint32_t fstl2; uint32_t fsth2; =20 - fst2 =3D float32_mul(fst0, fsth0, &env->active_fpu.fp_status); - fsth2 =3D float32_mul(fst1, fsth1, &env->active_fpu.fp_status); + fstl2 =3D float32_mul(fstl0, fsth0, &env->active_fpu.fp_status); + fsth2 =3D float32_mul(fstl1, fsth1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } =20 #define FLOAT_MINMAX(name, bits, minmaxfunc) \ --=20 2.20.1