From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589431680; cv=none; d=zohomail.com; s=zohoarc; b=YRpKHsrR4+pwxqGQlRNUJO1Whuuh5PcTBxlKeYKvhG92I9ZIwYmghpaF6AtWPx6JQCMxblL+icD2ybAXIo0H+o8QQ44EN/xjy8sC7uRCUzChBYB0xwzgddD1hunyxGK5niYOBp7iqryJF4zSpTIiGLSiAYIwbC5qpojF/tnyt/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589431680; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dCGDM3AbEhnk1L7eBBVSGCUEeRNpyHuneyEcKP/dUgs=; b=ApbqLBhGj0BWmpSf81E1z0uzAhBEpBTbcUojWr54TP5eh/IWYZ7463MF1J1TzS5HBZ/Ko9zGEJUMFZYBS4tt+3nPqRZpknwjRrQK8WbIkfPSkmRLI9m3QYEjb63bJX7S5i6q6ftP3fAw8IBoN1ayKrhoMwnQfm6PlKA6ZMjoE9s= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589431680541498.26569109689535; Wed, 13 May 2020 21:48:00 -0700 (PDT) Received: from localhost ([::1]:34444 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZ5mp-0002qk-5F for importer@patchew.org; Thu, 14 May 2020 00:47:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56668) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lT-0000S1-Sm; Thu, 14 May 2020 00:46:35 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43720) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lR-0003jh-Vt; Thu, 14 May 2020 00:46:35 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 31367BFDA3; Thu, 14 May 2020 04:46:30 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 01/20] hw/block/nvme: fix pci doorbell size calculation Date: Thu, 14 May 2020 06:45:52 +0200 Message-Id: <20200514044611.734782-2-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen The size of the BAR is 0x1000 (main registers) + 8 bytes for each queue. Currently, the size of the BAR is calculated like so: n->reg_size =3D pow2ceil(0x1004 + 2 * (n->num_queues + 1) * 4); Since the 'num_queues' parameter already accounts for the admin queue, this should in any case not need to be incremented by one. Also, the size should be initialized to (0x1000). n->reg_size =3D pow2ceil(0x1000 + 2 * n->num_queues * 4); This, with the default value of num_queues (64), we will set aside room for 1 admin queue and 63 I/O queues (4 bytes per doorbell, 2 doorbells per queue). Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 9b453423cf2c..1d7d7fb3c67a 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -54,6 +54,9 @@ #include "trace.h" #include "nvme.h" =20 +#define NVME_REG_SIZE 0x1000 +#define NVME_DB_SIZE 4 + #define NVME_GUEST_ERR(trace, fmt, ...) \ do { \ (trace_##trace)(__VA_ARGS__); \ @@ -1403,7 +1406,9 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) pcie_endpoint_cap_init(pci_dev, 0x80); =20 n->num_namespaces =3D 1; - n->reg_size =3D pow2ceil(0x1004 + 2 * (n->num_queues + 1) * 4); + + /* num_queues is really number of pairs, so each has two doorbells */ + n->reg_size =3D pow2ceil(NVME_REG_SIZE + 2 * n->num_queues * NVME_DB_S= IZE); n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; =20 n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589431768; cv=none; d=zohomail.com; s=zohoarc; b=bSwiEwNqqED/qO6Tf0FoSTHpU/aiNBGdOt1tzXD72VqSFVhBMpz95OwGsuGhKfU5Xpn4lBXlvqRDTVAHBDl6t4ODIllztRKbrnRnXb+f3WRDP6z4HHQepx3uWAW42oV1CrjbOLBEx6rfXfUYWRkizfZXIPPuB3GrYYh6TYw5MSA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589431768; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=n6P7b3TUhajMvyqDh8rCSqfhMP8va+ED5enrbw3yGVQ=; b=hufObjdLWUz5n/EZEe/HpeW1IlVBBU18O5KkP1fsgTPUZOy4fMoFt8+ISLz0aYiWFpq4RrlMkvGNRbt2ZJnd0IhXh7dIBoUHB2SfGfUZi1+hvtrLd746x2i8wrOmTenONTOQltNW2LGwgah9Z1RRHdDvMgw2JrbjQdMXE1Ki2BU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589431768166407.1826724671016; Wed, 13 May 2020 21:49:28 -0700 (PDT) Received: from localhost ([::1]:42710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZ5oE-0006NS-JS for importer@patchew.org; Thu, 14 May 2020 00:49:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56686) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lW-0000U6-6g; Thu, 14 May 2020 00:46:38 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43724) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lR-0003jk-Uw; Thu, 14 May 2020 00:46:37 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id A8661BFDAD; Thu, 14 May 2020 04:46:30 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 02/20] hw/block/nvme: rename trace events to pci_nvme Date: Thu, 14 May 2020 06:45:53 +0200 Message-Id: <20200514044611.734782-3-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Change the prefix of all nvme device related trace events to 'pci_nvme' to not clash with trace events from the nvme block driver. Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 198 +++++++++++++++++++++--------------------- hw/block/trace-events | 180 +++++++++++++++++++------------------- 2 files changed, 188 insertions(+), 190 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 1d7d7fb3c67a..6702812ecdd1 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -126,16 +126,16 @@ static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *= cq) { if (cq->irq_enabled) { if (msix_enabled(&(n->parent_obj))) { - trace_nvme_irq_msix(cq->vector); + trace_pci_nvme_irq_msix(cq->vector); msix_notify(&(n->parent_obj), cq->vector); } else { - trace_nvme_irq_pin(); + trace_pci_nvme_irq_pin(); assert(cq->cqid < 64); n->irq_status |=3D 1 << cq->cqid; nvme_irq_check(n); } } else { - trace_nvme_irq_masked(); + trace_pci_nvme_irq_masked(); } } =20 @@ -160,7 +160,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, int num_prps =3D (len >> n->page_bits) + 1; =20 if (unlikely(!prp1)) { - trace_nvme_err_invalid_prp(); + trace_pci_nvme_err_invalid_prp(); return NVME_INVALID_FIELD | NVME_DNR; } else if (n->cmbsz && prp1 >=3D n->ctrl_mem.addr && prp1 < n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size)) { @@ -174,7 +174,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, len -=3D trans_len; if (len) { if (unlikely(!prp2)) { - trace_nvme_err_invalid_prp2_missing(); + trace_pci_nvme_err_invalid_prp2_missing(); goto unmap; } if (len > n->page_size) { @@ -190,7 +190,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, =20 if (i =3D=3D n->max_prp_ents - 1 && len > n->page_size) { if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))= ) { - trace_nvme_err_invalid_prplist_ent(prp_ent); + trace_pci_nvme_err_invalid_prplist_ent(prp_ent); goto unmap; } =20 @@ -203,7 +203,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, } =20 if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) { - trace_nvme_err_invalid_prplist_ent(prp_ent); + trace_pci_nvme_err_invalid_prplist_ent(prp_ent); goto unmap; } =20 @@ -218,7 +218,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, } } else { if (unlikely(prp2 & (n->page_size - 1))) { - trace_nvme_err_invalid_prp2_align(prp2); + trace_pci_nvme_err_invalid_prp2_align(prp2); goto unmap; } if (qsg->nsg) { @@ -266,20 +266,20 @@ static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_= t *ptr, uint32_t len, QEMUIOVector iov; uint16_t status =3D NVME_SUCCESS; =20 - trace_nvme_dma_read(prp1, prp2); + trace_pci_nvme_dma_read(prp1, prp2); =20 if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) { return NVME_INVALID_FIELD | NVME_DNR; } if (qsg.nsg > 0) { if (unlikely(dma_buf_read(ptr, len, &qsg))) { - trace_nvme_err_invalid_dma(); + trace_pci_nvme_err_invalid_dma(); status =3D NVME_INVALID_FIELD | NVME_DNR; } qemu_sglist_destroy(&qsg); } else { if (unlikely(qemu_iovec_from_buf(&iov, 0, ptr, len) !=3D len)) { - trace_nvme_err_invalid_dma(); + trace_pci_nvme_err_invalid_dma(); status =3D NVME_INVALID_FIELD | NVME_DNR; } qemu_iovec_destroy(&iov); @@ -368,7 +368,7 @@ static uint16_t nvme_write_zeros(NvmeCtrl *n, NvmeNames= pace *ns, NvmeCmd *cmd, uint32_t count =3D nlb << data_shift; =20 if (unlikely(slba + nlb > ns->id_ns.nsze)) { - trace_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); + trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); return NVME_LBA_RANGE | NVME_DNR; } =20 @@ -396,11 +396,11 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *n= s, NvmeCmd *cmd, int is_write =3D rw->opcode =3D=3D NVME_CMD_WRITE ? 1 : 0; enum BlockAcctType acct =3D is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_R= EAD; =20 - trace_nvme_rw(is_write ? "write" : "read", nlb, data_size, slba); + trace_pci_nvme_rw(is_write ? "write" : "read", nlb, data_size, slba); =20 if (unlikely((slba + nlb) > ns->id_ns.nsze)) { block_acct_invalid(blk_get_stats(n->conf.blk), acct); - trace_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); + trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); return NVME_LBA_RANGE | NVME_DNR; } =20 @@ -435,7 +435,7 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, = NvmeRequest *req) uint32_t nsid =3D le32_to_cpu(cmd->nsid); =20 if (unlikely(nsid =3D=3D 0 || nsid > n->num_namespaces)) { - trace_nvme_err_invalid_ns(nsid, n->num_namespaces); + trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces); return NVME_INVALID_NSID | NVME_DNR; } =20 @@ -449,7 +449,7 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, = NvmeRequest *req) case NVME_CMD_READ: return nvme_rw(n, ns, cmd, req); default: - trace_nvme_err_invalid_opc(cmd->opcode); + trace_pci_nvme_err_invalid_opc(cmd->opcode); return NVME_INVALID_OPCODE | NVME_DNR; } } @@ -474,11 +474,11 @@ static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeCmd *cmd) uint16_t qid =3D le16_to_cpu(c->qid); =20 if (unlikely(!qid || nvme_check_sqid(n, qid))) { - trace_nvme_err_invalid_del_sq(qid); + trace_pci_nvme_err_invalid_del_sq(qid); return NVME_INVALID_QID | NVME_DNR; } =20 - trace_nvme_del_sq(qid); + trace_pci_nvme_del_sq(qid); =20 sq =3D n->sq[qid]; while (!QTAILQ_EMPTY(&sq->out_req_list)) { @@ -542,26 +542,26 @@ static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeCmd *= cmd) uint16_t qflags =3D le16_to_cpu(c->sq_flags); uint64_t prp1 =3D le64_to_cpu(c->prp1); =20 - trace_nvme_create_sq(prp1, sqid, cqid, qsize, qflags); + trace_pci_nvme_create_sq(prp1, sqid, cqid, qsize, qflags); =20 if (unlikely(!cqid || nvme_check_cqid(n, cqid))) { - trace_nvme_err_invalid_create_sq_cqid(cqid); + trace_pci_nvme_err_invalid_create_sq_cqid(cqid); return NVME_INVALID_CQID | NVME_DNR; } if (unlikely(!sqid || !nvme_check_sqid(n, sqid))) { - trace_nvme_err_invalid_create_sq_sqid(sqid); + trace_pci_nvme_err_invalid_create_sq_sqid(sqid); return NVME_INVALID_QID | NVME_DNR; } if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) { - trace_nvme_err_invalid_create_sq_size(qsize); + trace_pci_nvme_err_invalid_create_sq_size(qsize); return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR; } if (unlikely(!prp1 || prp1 & (n->page_size - 1))) { - trace_nvme_err_invalid_create_sq_addr(prp1); + trace_pci_nvme_err_invalid_create_sq_addr(prp1); return NVME_INVALID_FIELD | NVME_DNR; } if (unlikely(!(NVME_SQ_FLAGS_PC(qflags)))) { - trace_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflags)); + trace_pci_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflag= s)); return NVME_INVALID_FIELD | NVME_DNR; } sq =3D g_malloc0(sizeof(*sq)); @@ -587,17 +587,17 @@ static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeCmd *cmd) uint16_t qid =3D le16_to_cpu(c->qid); =20 if (unlikely(!qid || nvme_check_cqid(n, qid))) { - trace_nvme_err_invalid_del_cq_cqid(qid); + trace_pci_nvme_err_invalid_del_cq_cqid(qid); return NVME_INVALID_CQID | NVME_DNR; } =20 cq =3D n->cq[qid]; if (unlikely(!QTAILQ_EMPTY(&cq->sq_list))) { - trace_nvme_err_invalid_del_cq_notempty(qid); + trace_pci_nvme_err_invalid_del_cq_notempty(qid); return NVME_INVALID_QUEUE_DEL; } nvme_irq_deassert(n, cq); - trace_nvme_del_cq(qid); + trace_pci_nvme_del_cq(qid); nvme_free_cq(cq, n); return NVME_SUCCESS; } @@ -630,27 +630,27 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *= cmd) uint16_t qflags =3D le16_to_cpu(c->cq_flags); uint64_t prp1 =3D le64_to_cpu(c->prp1); =20 - trace_nvme_create_cq(prp1, cqid, vector, qsize, qflags, - NVME_CQ_FLAGS_IEN(qflags) !=3D 0); + trace_pci_nvme_create_cq(prp1, cqid, vector, qsize, qflags, + NVME_CQ_FLAGS_IEN(qflags) !=3D 0); =20 if (unlikely(!cqid || !nvme_check_cqid(n, cqid))) { - trace_nvme_err_invalid_create_cq_cqid(cqid); + trace_pci_nvme_err_invalid_create_cq_cqid(cqid); return NVME_INVALID_CQID | NVME_DNR; } if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) { - trace_nvme_err_invalid_create_cq_size(qsize); + trace_pci_nvme_err_invalid_create_cq_size(qsize); return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR; } if (unlikely(!prp1)) { - trace_nvme_err_invalid_create_cq_addr(prp1); + trace_pci_nvme_err_invalid_create_cq_addr(prp1); return NVME_INVALID_FIELD | NVME_DNR; } if (unlikely(vector > n->num_queues)) { - trace_nvme_err_invalid_create_cq_vector(vector); + trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } if (unlikely(!(NVME_CQ_FLAGS_PC(qflags)))) { - trace_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflags)); + trace_pci_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflag= s)); return NVME_INVALID_FIELD | NVME_DNR; } =20 @@ -665,7 +665,7 @@ static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeIde= ntify *c) uint64_t prp1 =3D le64_to_cpu(c->prp1); uint64_t prp2 =3D le64_to_cpu(c->prp2); =20 - trace_nvme_identify_ctrl(); + trace_pci_nvme_identify_ctrl(); =20 return nvme_dma_read_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl), prp1, prp2); @@ -678,10 +678,10 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIde= ntify *c) uint64_t prp1 =3D le64_to_cpu(c->prp1); uint64_t prp2 =3D le64_to_cpu(c->prp2); =20 - trace_nvme_identify_ns(nsid); + trace_pci_nvme_identify_ns(nsid); =20 if (unlikely(nsid =3D=3D 0 || nsid > n->num_namespaces)) { - trace_nvme_err_invalid_ns(nsid, n->num_namespaces); + trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces); return NVME_INVALID_NSID | NVME_DNR; } =20 @@ -701,7 +701,7 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeI= dentify *c) uint16_t ret; int i, j =3D 0; =20 - trace_nvme_identify_nslist(min_nsid); + trace_pci_nvme_identify_nslist(min_nsid); =20 list =3D g_malloc0(data_len); for (i =3D 0; i < n->num_namespaces; i++) { @@ -730,14 +730,14 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *c= md) case 0x02: return nvme_identify_nslist(n, c); default: - trace_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns)); + trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns)); return NVME_INVALID_FIELD | NVME_DNR; } } =20 static inline void nvme_set_timestamp(NvmeCtrl *n, uint64_t ts) { - trace_nvme_setfeat_timestamp(ts); + trace_pci_nvme_setfeat_timestamp(ts); =20 n->host_timestamp =3D le64_to_cpu(ts); n->timestamp_set_qemu_clock_ms =3D qemu_clock_get_ms(QEMU_CLOCK_VIRTUA= L); @@ -770,7 +770,7 @@ static inline uint64_t nvme_get_timestamp(const NvmeCtr= l *n) /* If the host timestamp is non-zero, set the timestamp origin */ ts.origin =3D n->host_timestamp ? 0x01 : 0x00; =20 - trace_nvme_getfeat_timestamp(ts.all); + trace_pci_nvme_getfeat_timestamp(ts.all); =20 return cpu_to_le64(ts.all); } @@ -794,17 +794,17 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd= *cmd, NvmeRequest *req) switch (dw10) { case NVME_VOLATILE_WRITE_CACHE: result =3D blk_enable_write_cache(n->conf.blk); - trace_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); + trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); break; case NVME_NUMBER_OF_QUEUES: result =3D cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) = << 16)); - trace_nvme_getfeat_numq(result); + trace_pci_nvme_getfeat_numq(result); break; case NVME_TIMESTAMP: return nvme_get_feature_timestamp(n, cmd); break; default: - trace_nvme_err_invalid_getfeat(dw10); + trace_pci_nvme_err_invalid_getfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; } =20 @@ -840,9 +840,9 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) blk_set_enable_write_cache(n->conf.blk, dw11 & 1); break; case NVME_NUMBER_OF_QUEUES: - trace_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, - ((dw11 >> 16) & 0xFFFF) + 1, - n->num_queues - 1, n->num_queues - 1); + trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, + ((dw11 >> 16) & 0xFFFF) + 1, + n->num_queues - 1, n->num_queues - 1); req->cqe.result =3D cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16)); break; @@ -852,7 +852,7 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) break; =20 default: - trace_nvme_err_invalid_setfeat(dw10); + trace_pci_nvme_err_invalid_setfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; } return NVME_SUCCESS; @@ -876,7 +876,7 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *cm= d, NvmeRequest *req) case NVME_ADM_CMD_GET_FEATURES: return nvme_get_feature(n, cmd, req); default: - trace_nvme_err_invalid_admin_opc(cmd->opcode); + trace_pci_nvme_err_invalid_admin_opc(cmd->opcode); return NVME_INVALID_OPCODE | NVME_DNR; } } @@ -939,77 +939,77 @@ static int nvme_start_ctrl(NvmeCtrl *n) uint32_t page_size =3D 1 << page_bits; =20 if (unlikely(n->cq[0])) { - trace_nvme_err_startfail_cq(); + trace_pci_nvme_err_startfail_cq(); return -1; } if (unlikely(n->sq[0])) { - trace_nvme_err_startfail_sq(); + trace_pci_nvme_err_startfail_sq(); return -1; } if (unlikely(!n->bar.asq)) { - trace_nvme_err_startfail_nbarasq(); + trace_pci_nvme_err_startfail_nbarasq(); return -1; } if (unlikely(!n->bar.acq)) { - trace_nvme_err_startfail_nbaracq(); + trace_pci_nvme_err_startfail_nbaracq(); return -1; } if (unlikely(n->bar.asq & (page_size - 1))) { - trace_nvme_err_startfail_asq_misaligned(n->bar.asq); + trace_pci_nvme_err_startfail_asq_misaligned(n->bar.asq); return -1; } if (unlikely(n->bar.acq & (page_size - 1))) { - trace_nvme_err_startfail_acq_misaligned(n->bar.acq); + trace_pci_nvme_err_startfail_acq_misaligned(n->bar.acq); return -1; } if (unlikely(NVME_CC_MPS(n->bar.cc) < NVME_CAP_MPSMIN(n->bar.cap))) { - trace_nvme_err_startfail_page_too_small( + trace_pci_nvme_err_startfail_page_too_small( NVME_CC_MPS(n->bar.cc), NVME_CAP_MPSMIN(n->bar.cap)); return -1; } if (unlikely(NVME_CC_MPS(n->bar.cc) > NVME_CAP_MPSMAX(n->bar.cap))) { - trace_nvme_err_startfail_page_too_large( + trace_pci_nvme_err_startfail_page_too_large( NVME_CC_MPS(n->bar.cc), NVME_CAP_MPSMAX(n->bar.cap)); return -1; } if (unlikely(NVME_CC_IOCQES(n->bar.cc) < NVME_CTRL_CQES_MIN(n->id_ctrl.cqes))) { - trace_nvme_err_startfail_cqent_too_small( + trace_pci_nvme_err_startfail_cqent_too_small( NVME_CC_IOCQES(n->bar.cc), NVME_CTRL_CQES_MIN(n->bar.cap)); return -1; } if (unlikely(NVME_CC_IOCQES(n->bar.cc) > NVME_CTRL_CQES_MAX(n->id_ctrl.cqes))) { - trace_nvme_err_startfail_cqent_too_large( + trace_pci_nvme_err_startfail_cqent_too_large( NVME_CC_IOCQES(n->bar.cc), NVME_CTRL_CQES_MAX(n->bar.cap)); return -1; } if (unlikely(NVME_CC_IOSQES(n->bar.cc) < NVME_CTRL_SQES_MIN(n->id_ctrl.sqes))) { - trace_nvme_err_startfail_sqent_too_small( + trace_pci_nvme_err_startfail_sqent_too_small( NVME_CC_IOSQES(n->bar.cc), NVME_CTRL_SQES_MIN(n->bar.cap)); return -1; } if (unlikely(NVME_CC_IOSQES(n->bar.cc) > NVME_CTRL_SQES_MAX(n->id_ctrl.sqes))) { - trace_nvme_err_startfail_sqent_too_large( + trace_pci_nvme_err_startfail_sqent_too_large( NVME_CC_IOSQES(n->bar.cc), NVME_CTRL_SQES_MAX(n->bar.cap)); return -1; } if (unlikely(!NVME_AQA_ASQS(n->bar.aqa))) { - trace_nvme_err_startfail_asqent_sz_zero(); + trace_pci_nvme_err_startfail_asqent_sz_zero(); return -1; } if (unlikely(!NVME_AQA_ACQS(n->bar.aqa))) { - trace_nvme_err_startfail_acqent_sz_zero(); + trace_pci_nvme_err_startfail_acqent_sz_zero(); return -1; } =20 @@ -1032,14 +1032,14 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, unsigned size) { if (unlikely(offset & (sizeof(uint32_t) - 1))) { - NVME_GUEST_ERR(nvme_ub_mmiowr_misaligned32, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_misaligned32, "MMIO write not 32-bit aligned," " offset=3D0x%"PRIx64"", offset); /* should be ignored, fall through for now */ } =20 if (unlikely(size < sizeof(uint32_t))) { - NVME_GUEST_ERR(nvme_ub_mmiowr_toosmall, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_toosmall, "MMIO write smaller than 32-bits," " offset=3D0x%"PRIx64", size=3D%u", offset, size); @@ -1049,32 +1049,30 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, switch (offset) { case 0xc: /* INTMS */ if (unlikely(msix_enabled(&(n->parent_obj)))) { - NVME_GUEST_ERR(nvme_ub_mmiowr_intmask_with_msix, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix, "undefined access to interrupt mask set" " when MSI-X is enabled"); /* should be ignored, fall through for now */ } n->bar.intms |=3D data & 0xffffffff; n->bar.intmc =3D n->bar.intms; - trace_nvme_mmio_intm_set(data & 0xffffffff, - n->bar.intmc); + trace_pci_nvme_mmio_intm_set(data & 0xffffffff, n->bar.intmc); nvme_irq_check(n); break; case 0x10: /* INTMC */ if (unlikely(msix_enabled(&(n->parent_obj)))) { - NVME_GUEST_ERR(nvme_ub_mmiowr_intmask_with_msix, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix, "undefined access to interrupt mask clr" " when MSI-X is enabled"); /* should be ignored, fall through for now */ } n->bar.intms &=3D ~(data & 0xffffffff); n->bar.intmc =3D n->bar.intms; - trace_nvme_mmio_intm_clr(data & 0xffffffff, - n->bar.intmc); + trace_pci_nvme_mmio_intm_clr(data & 0xffffffff, n->bar.intmc); nvme_irq_check(n); break; case 0x14: /* CC */ - trace_nvme_mmio_cfg(data & 0xffffffff); + trace_pci_nvme_mmio_cfg(data & 0xffffffff); /* Windows first sends data, then sends enable bit */ if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) && !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc)) @@ -1085,42 +1083,42 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, if (NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc)) { n->bar.cc =3D data; if (unlikely(nvme_start_ctrl(n))) { - trace_nvme_err_startfail(); + trace_pci_nvme_err_startfail(); n->bar.csts =3D NVME_CSTS_FAILED; } else { - trace_nvme_mmio_start_success(); + trace_pci_nvme_mmio_start_success(); n->bar.csts =3D NVME_CSTS_READY; } } else if (!NVME_CC_EN(data) && NVME_CC_EN(n->bar.cc)) { - trace_nvme_mmio_stopped(); + trace_pci_nvme_mmio_stopped(); nvme_clear_ctrl(n); n->bar.csts &=3D ~NVME_CSTS_READY; } if (NVME_CC_SHN(data) && !(NVME_CC_SHN(n->bar.cc))) { - trace_nvme_mmio_shutdown_set(); + trace_pci_nvme_mmio_shutdown_set(); nvme_clear_ctrl(n); n->bar.cc =3D data; n->bar.csts |=3D NVME_CSTS_SHST_COMPLETE; } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(n->bar.cc)) { - trace_nvme_mmio_shutdown_cleared(); + trace_pci_nvme_mmio_shutdown_cleared(); n->bar.csts &=3D ~NVME_CSTS_SHST_COMPLETE; n->bar.cc =3D data; } break; case 0x1C: /* CSTS */ if (data & (1 << 4)) { - NVME_GUEST_ERR(nvme_ub_mmiowr_ssreset_w1c_unsupported, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported, "attempted to W1C CSTS.NSSRO" " but CAP.NSSRS is zero (not supported)"); } else if (data !=3D 0) { - NVME_GUEST_ERR(nvme_ub_mmiowr_ro_csts, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ro_csts, "attempted to set a read only bit" " of controller status"); } break; case 0x20: /* NSSR */ if (data =3D=3D 0x4E564D65) { - trace_nvme_ub_mmiowr_ssreset_unsupported(); + trace_pci_nvme_ub_mmiowr_ssreset_unsupported(); } else { /* The spec says that writes of other values have no effect */ return; @@ -1128,55 +1126,55 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, break; case 0x24: /* AQA */ n->bar.aqa =3D data & 0xffffffff; - trace_nvme_mmio_aqattr(data & 0xffffffff); + trace_pci_nvme_mmio_aqattr(data & 0xffffffff); break; case 0x28: /* ASQ */ n->bar.asq =3D data; - trace_nvme_mmio_asqaddr(data); + trace_pci_nvme_mmio_asqaddr(data); break; case 0x2c: /* ASQ hi */ n->bar.asq |=3D data << 32; - trace_nvme_mmio_asqaddr_hi(data, n->bar.asq); + trace_pci_nvme_mmio_asqaddr_hi(data, n->bar.asq); break; case 0x30: /* ACQ */ - trace_nvme_mmio_acqaddr(data); + trace_pci_nvme_mmio_acqaddr(data); n->bar.acq =3D data; break; case 0x34: /* ACQ hi */ n->bar.acq |=3D data << 32; - trace_nvme_mmio_acqaddr_hi(data, n->bar.acq); + trace_pci_nvme_mmio_acqaddr_hi(data, n->bar.acq); break; case 0x38: /* CMBLOC */ - NVME_GUEST_ERR(nvme_ub_mmiowr_cmbloc_reserved, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbloc_reserved, "invalid write to reserved CMBLOC" " when CMBSZ is zero, ignored"); return; case 0x3C: /* CMBSZ */ - NVME_GUEST_ERR(nvme_ub_mmiowr_cmbsz_readonly, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly, "invalid write to read only CMBSZ, ignored"); return; case 0xE00: /* PMRCAP */ - NVME_GUEST_ERR(nvme_ub_mmiowr_pmrcap_readonly, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly, "invalid write to PMRCAP register, ignored"); return; case 0xE04: /* TODO PMRCTL */ break; case 0xE08: /* PMRSTS */ - NVME_GUEST_ERR(nvme_ub_mmiowr_pmrsts_readonly, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrsts_readonly, "invalid write to PMRSTS register, ignored"); return; case 0xE0C: /* PMREBS */ - NVME_GUEST_ERR(nvme_ub_mmiowr_pmrebs_readonly, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrebs_readonly, "invalid write to PMREBS register, ignored"); return; case 0xE10: /* PMRSWTP */ - NVME_GUEST_ERR(nvme_ub_mmiowr_pmrswtp_readonly, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly, "invalid write to PMRSWTP register, ignored"); return; case 0xE14: /* TODO PMRMSC */ break; default: - NVME_GUEST_ERR(nvme_ub_mmiowr_invalid, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid, "invalid MMIO write," " offset=3D0x%"PRIx64", data=3D%"PRIx64"", offset, data); @@ -1191,12 +1189,12 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr= addr, unsigned size) uint64_t val =3D 0; =20 if (unlikely(addr & (sizeof(uint32_t) - 1))) { - NVME_GUEST_ERR(nvme_ub_mmiord_misaligned32, + NVME_GUEST_ERR(pci_nvme_ub_mmiord_misaligned32, "MMIO read not 32-bit aligned," " offset=3D0x%"PRIx64"", addr); /* should RAZ, fall through for now */ } else if (unlikely(size < sizeof(uint32_t))) { - NVME_GUEST_ERR(nvme_ub_mmiord_toosmall, + NVME_GUEST_ERR(pci_nvme_ub_mmiord_toosmall, "MMIO read smaller than 32-bits," " offset=3D0x%"PRIx64"", addr); /* should RAZ, fall through for now */ @@ -1215,7 +1213,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr a= ddr, unsigned size) } memcpy(&val, ptr + addr, size); } else { - NVME_GUEST_ERR(nvme_ub_mmiord_invalid_ofs, + NVME_GUEST_ERR(pci_nvme_ub_mmiord_invalid_ofs, "MMIO read beyond last register," " offset=3D0x%"PRIx64", returning 0", addr); } @@ -1228,7 +1226,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) uint32_t qid; =20 if (unlikely(addr & ((1 << 2) - 1))) { - NVME_GUEST_ERR(nvme_ub_db_wr_misaligned, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned, "doorbell write not 32-bit aligned," " offset=3D0x%"PRIx64", ignoring", addr); return; @@ -1243,7 +1241,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 qid =3D (addr - (0x1000 + (1 << 2))) >> 3; if (unlikely(nvme_check_cqid(n, qid))) { - NVME_GUEST_ERR(nvme_ub_db_wr_invalid_cq, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cq, "completion queue doorbell write" " for nonexistent queue," " sqid=3D%"PRIu32", ignoring", qid); @@ -1252,7 +1250,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 cq =3D n->cq[qid]; if (unlikely(new_head >=3D cq->size)) { - NVME_GUEST_ERR(nvme_ub_db_wr_invalid_cqhead, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cqhead, "completion queue doorbell write value" " beyond queue size, sqid=3D%"PRIu32"," " new_head=3D%"PRIu16", ignoring", @@ -1281,7 +1279,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 qid =3D (addr - 0x1000) >> 3; if (unlikely(nvme_check_sqid(n, qid))) { - NVME_GUEST_ERR(nvme_ub_db_wr_invalid_sq, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sq, "submission queue doorbell write" " for nonexistent queue," " sqid=3D%"PRIu32", ignoring", qid); @@ -1290,7 +1288,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 sq =3D n->sq[qid]; if (unlikely(new_tail >=3D sq->size)) { - NVME_GUEST_ERR(nvme_ub_db_wr_invalid_sqtail, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sqtail, "submission queue doorbell write value" " beyond queue size, sqid=3D%"PRIu32"," " new_tail=3D%"PRIu16", ignoring", diff --git a/hw/block/trace-events b/hw/block/trace-events index aca54bda1423..958fcc5508d1 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -29,100 +29,100 @@ hd_geometry_guess(void *blk, uint32_t cyls, uint32_t = heads, uint32_t secs, int t =20 # nvme.c # nvme traces for successful events -nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u" -nvme_irq_pin(void) "pulsing IRQ pin" -nvme_irq_masked(void) "IRQ is masked" -nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=3D0x%"PRIx64" = prp2=3D0x%"PRIx64"" -nvme_rw(const char *verb, uint32_t blk_count, uint64_t byte_count, uint64_= t lba) "%s %"PRIu32" blocks (%"PRIu64" bytes) from LBA %"PRIu64"" -nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t qsize= , uint16_t qflags) "create submission queue, addr=3D0x%"PRIx64", sqid=3D%"P= RIu16", cqid=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRIu16"" -nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t siz= e, uint16_t qflags, int ien) "create completion queue, addr=3D0x%"PRIx64", = cqid=3D%"PRIu16", vector=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRIu16"= , ien=3D%d" -nvme_del_sq(uint16_t qid) "deleting submission queue sqid=3D%"PRIu16"" -nvme_del_cq(uint16_t cqid) "deleted completion queue, cqid=3D%"PRIu16"" -nvme_identify_ctrl(void) "identify controller" -nvme_identify_ns(uint16_t ns) "identify namespace, nsid=3D%"PRIu16"" -nvme_identify_nslist(uint16_t ns) "identify namespace list, nsid=3D%"PRIu1= 6"" -nvme_getfeat_vwcache(const char* result) "get feature volatile write cache= , result=3D%s" -nvme_getfeat_numq(int result) "get feature number of queues, result=3D%d" -nvme_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "requested c= q_count=3D%d sq_count=3D%d, responding with cq_count=3D%d sq_count=3D%d" -nvme_setfeat_timestamp(uint64_t ts) "set feature timestamp =3D 0x%"PRIx64"" -nvme_getfeat_timestamp(uint64_t ts) "get feature timestamp =3D 0x%"PRIx64"" -nvme_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, interrup= t mask set, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" -nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, interrup= t mask clr, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" -nvme_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=3D0x%"P= RIx64"" -nvme_mmio_aqattr(uint64_t data) "wrote MMIO, admin queue attributes=3D0x%"= PRIx64"" -nvme_mmio_asqaddr(uint64_t data) "wrote MMIO, admin submission queue addre= ss=3D0x%"PRIx64"" -nvme_mmio_acqaddr(uint64_t data) "wrote MMIO, admin completion queue addre= ss=3D0x%"PRIx64"" -nvme_mmio_asqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, admin = submission queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" -nvme_mmio_acqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, admin = completion queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" -nvme_mmio_start_success(void) "setting controller enable bit succeeded" -nvme_mmio_stopped(void) "cleared controller enable bit" -nvme_mmio_shutdown_set(void) "shutdown bit set" -nvme_mmio_shutdown_cleared(void) "shutdown bit cleared" +pci_nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u" +pci_nvme_irq_pin(void) "pulsing IRQ pin" +pci_nvme_irq_masked(void) "IRQ is masked" +pci_nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=3D0x%"PRIx= 64" prp2=3D0x%"PRIx64"" +pci_nvme_rw(const char *verb, uint32_t blk_count, uint64_t byte_count, uin= t64_t lba) "%s %"PRIu32" blocks (%"PRIu64" bytes) from LBA %"PRIu64"" +pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t q= size, uint16_t qflags) "create submission queue, addr=3D0x%"PRIx64", sqid= =3D%"PRIu16", cqid=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRIu16"" +pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t= size, uint16_t qflags, int ien) "create completion queue, addr=3D0x%"PRIx6= 4", cqid=3D%"PRIu16", vector=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRI= u16", ien=3D%d" +pci_nvme_del_sq(uint16_t qid) "deleting submission queue sqid=3D%"PRIu16"" +pci_nvme_del_cq(uint16_t cqid) "deleted completion queue, cqid=3D%"PRIu16"" +pci_nvme_identify_ctrl(void) "identify controller" +pci_nvme_identify_ns(uint16_t ns) "identify namespace, nsid=3D%"PRIu16"" +pci_nvme_identify_nslist(uint16_t ns) "identify namespace list, nsid=3D%"P= RIu16"" +pci_nvme_getfeat_vwcache(const char* result) "get feature volatile write c= ache, result=3D%s" +pci_nvme_getfeat_numq(int result) "get feature number of queues, result=3D= %d" +pci_nvme_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "request= ed cq_count=3D%d sq_count=3D%d, responding with cq_count=3D%d sq_count=3D%d" +pci_nvme_setfeat_timestamp(uint64_t ts) "set feature timestamp =3D 0x%"PRI= x64"" +pci_nvme_getfeat_timestamp(uint64_t ts) "get feature timestamp =3D 0x%"PRI= x64"" +pci_nvme_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, inte= rrupt mask set, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" +pci_nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, inte= rrupt mask clr, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" +pci_nvme_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=3D0= x%"PRIx64"" +pci_nvme_mmio_aqattr(uint64_t data) "wrote MMIO, admin queue attributes=3D= 0x%"PRIx64"" +pci_nvme_mmio_asqaddr(uint64_t data) "wrote MMIO, admin submission queue a= ddress=3D0x%"PRIx64"" +pci_nvme_mmio_acqaddr(uint64_t data) "wrote MMIO, admin completion queue a= ddress=3D0x%"PRIx64"" +pci_nvme_mmio_asqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, ad= min submission queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" +pci_nvme_mmio_acqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, ad= min completion queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" +pci_nvme_mmio_start_success(void) "setting controller enable bit succeeded" +pci_nvme_mmio_stopped(void) "cleared controller enable bit" +pci_nvme_mmio_shutdown_set(void) "shutdown bit set" +pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared" =20 # nvme traces for error conditions -nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size" -nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null or = not page aligned: 0x%"PRIx64"" -nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: 0x%"= PRIx64"" -nvme_err_invalid_prp2_missing(void) "PRP2 is null and more data to be tran= sferred" -nvme_err_invalid_prp(void) "invalid PRP" -nvme_err_invalid_ns(uint32_t ns, uint32_t limit) "invalid namespace %u not= within 1-%u" -nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" -nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx8"" -nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limit) "= Invalid LBA start=3D%"PRIu64" len=3D%"PRIu64" limit=3D%"PRIu64"" -nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deletion, = sid=3D%"PRIu16"" -nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submission= queue, invalid cqid=3D%"PRIu16"" -nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating submission= queue, invalid sqid=3D%"PRIu16"" -nvme_err_invalid_create_sq_size(uint16_t qsize) "failed creating submissio= n queue, invalid qsize=3D%"PRIu16"" -nvme_err_invalid_create_sq_addr(uint64_t addr) "failed creating submission= queue, addr=3D0x%"PRIx64"" -nvme_err_invalid_create_sq_qflags(uint16_t qflags) "failed creating submis= sion queue, qflags=3D%"PRIu16"" -nvme_err_invalid_del_cq_cqid(uint16_t cqid) "failed deleting completion qu= eue, cqid=3D%"PRIu16"" -nvme_err_invalid_del_cq_notempty(uint16_t cqid) "failed deleting completio= n queue, it is not empty, cqid=3D%"PRIu16"" -nvme_err_invalid_create_cq_cqid(uint16_t cqid) "failed creating completion= queue, cqid=3D%"PRIu16"" -nvme_err_invalid_create_cq_size(uint16_t size) "failed creating completion= queue, size=3D%"PRIu16"" -nvme_err_invalid_create_cq_addr(uint64_t addr) "failed creating completion= queue, addr=3D0x%"PRIx64"" -nvme_err_invalid_create_cq_vector(uint16_t vector) "failed creating comple= tion queue, vector=3D%"PRIu16"" -nvme_err_invalid_create_cq_qflags(uint16_t qflags) "failed creating comple= tion queue, qflags=3D%"PRIu16"" -nvme_err_invalid_identify_cns(uint16_t cns) "identify, invalid cns=3D0x%"P= RIx16"" -nvme_err_invalid_getfeat(int dw10) "invalid get features, dw10=3D0x%"PRIx3= 2"" -nvme_err_invalid_setfeat(uint32_t dw10) "invalid set features, dw10=3D0x%"= PRIx32"" -nvme_err_startfail_cq(void) "nvme_start_ctrl failed because there are non-= admin completion queues" -nvme_err_startfail_sq(void) "nvme_start_ctrl failed because there are non-= admin submission queues" -nvme_err_startfail_nbarasq(void) "nvme_start_ctrl failed because the admin= submission queue address is null" -nvme_err_startfail_nbaracq(void) "nvme_start_ctrl failed because the admin= completion queue address is null" -nvme_err_startfail_asq_misaligned(uint64_t addr) "nvme_start_ctrl failed b= ecause the admin submission queue address is misaligned: 0x%"PRIx64"" -nvme_err_startfail_acq_misaligned(uint64_t addr) "nvme_start_ctrl failed b= ecause the admin completion queue address is misaligned: 0x%"PRIx64"" -nvme_err_startfail_page_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvme= _start_ctrl failed because the page size is too small: log2size=3D%u, min= =3D%u" -nvme_err_startfail_page_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvme= _start_ctrl failed because the page size is too large: log2size=3D%u, max= =3D%u" -nvme_err_startfail_cqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvm= e_start_ctrl failed because the completion queue entry size is too small: l= og2size=3D%u, min=3D%u" -nvme_err_startfail_cqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvm= e_start_ctrl failed because the completion queue entry size is too large: l= og2size=3D%u, max=3D%u" -nvme_err_startfail_sqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvm= e_start_ctrl failed because the submission queue entry size is too small: l= og2size=3D%u, min=3D%u" -nvme_err_startfail_sqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvm= e_start_ctrl failed because the submission queue entry size is too large: l= og2size=3D%u, max=3D%u" -nvme_err_startfail_asqent_sz_zero(void) "nvme_start_ctrl failed because th= e admin submission queue size is zero" -nvme_err_startfail_acqent_sz_zero(void) "nvme_start_ctrl failed because th= e admin completion queue size is zero" -nvme_err_startfail(void) "setting controller enable bit failed" +pci_nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size" +pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null= or not page aligned: 0x%"PRIx64"" +pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: = 0x%"PRIx64"" +pci_nvme_err_invalid_prp2_missing(void) "PRP2 is null and more data to be = transferred" +pci_nvme_err_invalid_prp(void) "invalid PRP" +pci_nvme_err_invalid_ns(uint32_t ns, uint32_t limit) "invalid namespace %u= not within 1-%u" +pci_nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" +pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx= 8"" +pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limi= t) "Invalid LBA start=3D%"PRIu64" len=3D%"PRIu64" limit=3D%"PRIu64"" +pci_nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deleti= on, sid=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submis= sion queue, invalid cqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating submis= sion queue, invalid sqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_size(uint16_t qsize) "failed creating submi= ssion queue, invalid qsize=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_addr(uint64_t addr) "failed creating submis= sion queue, addr=3D0x%"PRIx64"" +pci_nvme_err_invalid_create_sq_qflags(uint16_t qflags) "failed creating su= bmission queue, qflags=3D%"PRIu16"" +pci_nvme_err_invalid_del_cq_cqid(uint16_t cqid) "failed deleting completio= n queue, cqid=3D%"PRIu16"" +pci_nvme_err_invalid_del_cq_notempty(uint16_t cqid) "failed deleting compl= etion queue, it is not empty, cqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_cqid(uint16_t cqid) "failed creating comple= tion queue, cqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_size(uint16_t size) "failed creating comple= tion queue, size=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_addr(uint64_t addr) "failed creating comple= tion queue, addr=3D0x%"PRIx64"" +pci_nvme_err_invalid_create_cq_vector(uint16_t vector) "failed creating co= mpletion queue, vector=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_qflags(uint16_t qflags) "failed creating co= mpletion queue, qflags=3D%"PRIu16"" +pci_nvme_err_invalid_identify_cns(uint16_t cns) "identify, invalid cns=3D0= x%"PRIx16"" +pci_nvme_err_invalid_getfeat(int dw10) "invalid get features, dw10=3D0x%"P= RIx32"" +pci_nvme_err_invalid_setfeat(uint32_t dw10) "invalid set features, dw10=3D= 0x%"PRIx32"" +pci_nvme_err_startfail_cq(void) "nvme_start_ctrl failed because there are = non-admin completion queues" +pci_nvme_err_startfail_sq(void) "nvme_start_ctrl failed because there are = non-admin submission queues" +pci_nvme_err_startfail_nbarasq(void) "nvme_start_ctrl failed because the a= dmin submission queue address is null" +pci_nvme_err_startfail_nbaracq(void) "nvme_start_ctrl failed because the a= dmin completion queue address is null" +pci_nvme_err_startfail_asq_misaligned(uint64_t addr) "nvme_start_ctrl fail= ed because the admin submission queue address is misaligned: 0x%"PRIx64"" +pci_nvme_err_startfail_acq_misaligned(uint64_t addr) "nvme_start_ctrl fail= ed because the admin completion queue address is misaligned: 0x%"PRIx64"" +pci_nvme_err_startfail_page_too_small(uint8_t log2ps, uint8_t maxlog2ps) "= nvme_start_ctrl failed because the page size is too small: log2size=3D%u, m= in=3D%u" +pci_nvme_err_startfail_page_too_large(uint8_t log2ps, uint8_t maxlog2ps) "= nvme_start_ctrl failed because the page size is too large: log2size=3D%u, m= ax=3D%u" +pci_nvme_err_startfail_cqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the completion queue entry size is too smal= l: log2size=3D%u, min=3D%u" +pci_nvme_err_startfail_cqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the completion queue entry size is too larg= e: log2size=3D%u, max=3D%u" +pci_nvme_err_startfail_sqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the submission queue entry size is too smal= l: log2size=3D%u, min=3D%u" +pci_nvme_err_startfail_sqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the submission queue entry size is too larg= e: log2size=3D%u, max=3D%u" +pci_nvme_err_startfail_asqent_sz_zero(void) "nvme_start_ctrl failed becaus= e the admin submission queue size is zero" +pci_nvme_err_startfail_acqent_sz_zero(void) "nvme_start_ctrl failed becaus= e the admin completion queue size is zero" +pci_nvme_err_startfail(void) "setting controller enable bit failed" =20 # Traces for undefined behavior -nvme_ub_mmiowr_misaligned32(uint64_t offset) "MMIO write not 32-bit aligne= d, offset=3D0x%"PRIx64"" -nvme_ub_mmiowr_toosmall(uint64_t offset, unsigned size) "MMIO write smalle= r than 32 bits, offset=3D0x%"PRIx64", size=3D%u" -nvme_ub_mmiowr_intmask_with_msix(void) "undefined access to interrupt mask= set when MSI-X is enabled" -nvme_ub_mmiowr_ro_csts(void) "attempted to set a read only bit of controll= er status" -nvme_ub_mmiowr_ssreset_w1c_unsupported(void) "attempted to W1C CSTS.NSSRO = but CAP.NSSRS is zero (not supported)" -nvme_ub_mmiowr_ssreset_unsupported(void) "attempted NVM subsystem reset bu= t CAP.NSSRS is zero (not supported)" -nvme_ub_mmiowr_cmbloc_reserved(void) "invalid write to reserved CMBLOC whe= n CMBSZ is zero, ignored" -nvme_ub_mmiowr_cmbsz_readonly(void) "invalid write to read only CMBSZ, ign= ored" -nvme_ub_mmiowr_pmrcap_readonly(void) "invalid write to read only PMRCAP, i= gnored" -nvme_ub_mmiowr_pmrsts_readonly(void) "invalid write to read only PMRSTS, i= gnored" -nvme_ub_mmiowr_pmrebs_readonly(void) "invalid write to read only PMREBS, i= gnored" -nvme_ub_mmiowr_pmrswtp_readonly(void) "invalid write to read only PMRSWTP,= ignored" -nvme_ub_mmiowr_invalid(uint64_t offset, uint64_t data) "invalid MMIO write= , offset=3D0x%"PRIx64", data=3D0x%"PRIx64"" -nvme_ub_mmiord_misaligned32(uint64_t offset) "MMIO read not 32-bit aligned= , offset=3D0x%"PRIx64"" -nvme_ub_mmiord_toosmall(uint64_t offset) "MMIO read smaller than 32-bits, = offset=3D0x%"PRIx64"" -nvme_ub_mmiord_invalid_ofs(uint64_t offset) "MMIO read beyond last registe= r, offset=3D0x%"PRIx64", returning 0" -nvme_ub_db_wr_misaligned(uint64_t offset) "doorbell write not 32-bit align= ed, offset=3D0x%"PRIx64", ignoring" -nvme_ub_db_wr_invalid_cq(uint32_t qid) "completion queue doorbell write fo= r nonexistent queue, cqid=3D%"PRIu32", ignoring" -nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t new_head) "completion = queue doorbell write value beyond queue size, cqid=3D%"PRIu32", new_head=3D= %"PRIu16", ignoring" -nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell write fo= r nonexistent queue, sqid=3D%"PRIu32", ignoring" -nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail) "submission = queue doorbell write value beyond queue size, sqid=3D%"PRIu32", new_head=3D= %"PRIu16", ignoring" +pci_nvme_ub_mmiowr_misaligned32(uint64_t offset) "MMIO write not 32-bit al= igned, offset=3D0x%"PRIx64"" +pci_nvme_ub_mmiowr_toosmall(uint64_t offset, unsigned size) "MMIO write sm= aller than 32 bits, offset=3D0x%"PRIx64", size=3D%u" +pci_nvme_ub_mmiowr_intmask_with_msix(void) "undefined access to interrupt = mask set when MSI-X is enabled" +pci_nvme_ub_mmiowr_ro_csts(void) "attempted to set a read only bit of cont= roller status" +pci_nvme_ub_mmiowr_ssreset_w1c_unsupported(void) "attempted to W1C CSTS.NS= SRO but CAP.NSSRS is zero (not supported)" +pci_nvme_ub_mmiowr_ssreset_unsupported(void) "attempted NVM subsystem rese= t but CAP.NSSRS is zero (not supported)" +pci_nvme_ub_mmiowr_cmbloc_reserved(void) "invalid write to reserved CMBLOC= when CMBSZ is zero, ignored" +pci_nvme_ub_mmiowr_cmbsz_readonly(void) "invalid write to read only CMBSZ,= ignored" +pci_nvme_ub_mmiowr_pmrcap_readonly(void) "invalid write to read only PMRCA= P, ignored" +pci_nvme_ub_mmiowr_pmrsts_readonly(void) "invalid write to read only PMRST= S, ignored" +pci_nvme_ub_mmiowr_pmrebs_readonly(void) "invalid write to read only PMREB= S, ignored" +pci_nvme_ub_mmiowr_pmrswtp_readonly(void) "invalid write to read only PMRS= WTP, ignored" +pci_nvme_ub_mmiowr_invalid(uint64_t offset, uint64_t data) "invalid MMIO w= rite, offset=3D0x%"PRIx64", data=3D0x%"PRIx64"" +pci_nvme_ub_mmiord_misaligned32(uint64_t offset) "MMIO read not 32-bit ali= gned, offset=3D0x%"PRIx64"" +pci_nvme_ub_mmiord_toosmall(uint64_t offset) "MMIO read smaller than 32-bi= ts, offset=3D0x%"PRIx64"" +pci_nvme_ub_mmiord_invalid_ofs(uint64_t offset) "MMIO read beyond last reg= ister, offset=3D0x%"PRIx64", returning 0" +pci_nvme_ub_db_wr_misaligned(uint64_t offset) "doorbell write not 32-bit a= ligned, offset=3D0x%"PRIx64", ignoring" +pci_nvme_ub_db_wr_invalid_cq(uint32_t qid) "completion queue doorbell writ= e for nonexistent queue, cqid=3D%"PRIu32", ignoring" +pci_nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t new_head) "complet= ion queue doorbell write value beyond queue size, cqid=3D%"PRIu32", new_hea= d=3D%"PRIu16", ignoring" +pci_nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell writ= e for nonexistent queue, sqid=3D%"PRIu32", ignoring" +pci_nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail) "submiss= ion queue doorbell write value beyond queue size, sqid=3D%"PRIu32", new_hea= d=3D%"PRIu16", ignoring" =20 # xen-block.c xen_block_realize(const char *type, uint32_t disk, uint32_t partition) "%s= d%up%u" --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589431676; cv=none; d=zohomail.com; s=zohoarc; b=EQXSRznol14/XKKa48qIGqFMVWXhdzTpNmEMQKnqKpVtUpc5j4kinfGKYwQ4aUSyBaCAXB0tKGLJ1YA8w9oQ9d0l2b28Z8uTBuj4P8RXW4vK6YDbEGb5ORY6EJPE6NwEQteGTVaFk9RK+QySNDRNnWu22VEs/tUP1i+1Xrm5Tr4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589431676; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zHxqzvvMJ7RxZfYkagKk2nOjtJ1N06XByFt3MACfKR4=; b=S24TmH0f1CePW2+NU1FKOLKPQWs//DfJieW3qHEi321SHwDXGN9jIv8X9uZ0cPsQ6l6bRaGIXsme6kls/33rtUfBHS+fedwiA+32hG0TrQIMSbsuAXsmf/CBOwE11Vqg352Cww0QZKL+I9KKKcM/2i4D6Kn81fTh5xNfbruVIlM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589431676363299.09807536883795; Wed, 13 May 2020 21:47:56 -0700 (PDT) Received: from localhost ([::1]:33840 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZ5mj-0002ZL-JQ for importer@patchew.org; Thu, 14 May 2020 00:47:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56672) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lU-0000SA-6h; Thu, 14 May 2020 00:46:36 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43736) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lR-0003jq-VR; Thu, 14 May 2020 00:46:35 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 3B93ABFDAE; Thu, 14 May 2020 04:46:31 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 03/20] hw/block/nvme: remove superfluous breaks Date: Thu, 14 May 2020 06:45:54 +0200 Message-Id: <20200514044611.734782-4-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen These break statements was left over when commit 3036a626e9ef ("nvme: add Get/Set Feature Timestamp support") was merged. Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Keith Busch --- hw/block/nvme.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 6702812ecdd1..f67499d85f3a 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -802,7 +802,6 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) break; case NVME_TIMESTAMP: return nvme_get_feature_timestamp(n, cmd); - break; default: trace_pci_nvme_err_invalid_getfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; @@ -846,11 +845,8 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd = *cmd, NvmeRequest *req) req->cqe.result =3D cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16)); break; - case NVME_TIMESTAMP: return nvme_set_feature_timestamp(n, cmd); - break; - default: trace_pci_nvme_err_invalid_setfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589431687; cv=none; d=zohomail.com; s=zohoarc; b=XmFXsNtZu44UCk8TqQTE11B0yBz/WsqqV3Xpx2uZMIgJ75iW6WcnUY1w6jm/AFLHjst6qHx+YU2gdVcz2YzpP7MJlAtCBre4aUAT+Z9JzhkJoKYxGknRytWctcBLijMp9cj/lHyek/jj6dTPt4dIHZIQCzv2yeX88LBByfkY2iE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589431687; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8Tt9P1sB40S7nVsH8HMKl38hY8RIq+4IacqHTkiR4FM=; b=FNdf9qZRPM3MhGp/6MxFsGOkfRqAiqWCvRsBdj3upFyUeW1NXX7f4JyKPFtcJwMZiYSh6TzU4VhNmElI2H5t67DtVdKu95LtkpX4Ou8UIvENsh89+dzuu3LYleVP+WdcDQorYSvYgLYicDheBNHreyCcHHwSY7fu6GrzXEskWqo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589431687361289.28710123610927; Wed, 13 May 2020 21:48:07 -0700 (PDT) Received: from localhost ([::1]:35296 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZ5mw-0003CP-2Y for importer@patchew.org; Thu, 14 May 2020 00:48:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56676) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lV-0000SV-Ax; Thu, 14 May 2020 00:46:37 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43744) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lS-0003jv-92; Thu, 14 May 2020 00:46:37 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 99B5BBFE23; Thu, 14 May 2020 04:46:31 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 04/20] hw/block/nvme: move device parameters to separate struct Date: Thu, 14 May 2020 06:45:55 +0200 Message-Id: <20200514044611.734782-5-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Move device configuration parameters to separate struct to make it explicit what is configurable and what is set internally. Signed-off-by: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky --- hw/block/nvme.c | 49 ++++++++++++++++++++++++++----------------------- hw/block/nvme.h | 11 ++++++++--- 2 files changed, 34 insertions(+), 26 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index f67499d85f3a..e26db7591574 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -78,12 +78,12 @@ static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, vo= id *buf, int size) =20 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) { - return sqid < n->num_queues && n->sq[sqid] !=3D NULL ? 0 : -1; + return sqid < n->params.num_queues && n->sq[sqid] !=3D NULL ? 0 : -1; } =20 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid) { - return cqid < n->num_queues && n->cq[cqid] !=3D NULL ? 0 : -1; + return cqid < n->params.num_queues && n->cq[cqid] !=3D NULL ? 0 : -1; } =20 static void nvme_inc_cq_tail(NvmeCQueue *cq) @@ -645,7 +645,7 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cm= d) trace_pci_nvme_err_invalid_create_cq_addr(prp1); return NVME_INVALID_FIELD | NVME_DNR; } - if (unlikely(vector > n->num_queues)) { + if (unlikely(vector > n->params.num_queues)) { trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } @@ -797,7 +797,8 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); break; case NVME_NUMBER_OF_QUEUES: - result =3D cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) = << 16)); + result =3D cpu_to_le32((n->params.num_queues - 2) | + ((n->params.num_queues - 2) << 16)); trace_pci_nvme_getfeat_numq(result); break; case NVME_TIMESTAMP: @@ -841,9 +842,10 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd = *cmd, NvmeRequest *req) case NVME_NUMBER_OF_QUEUES: trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, ((dw11 >> 16) & 0xFFFF) + 1, - n->num_queues - 1, n->num_queues - 1); - req->cqe.result =3D - cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16)); + n->params.num_queues - 1, + n->params.num_queues - 1); + req->cqe.result =3D cpu_to_le32((n->params.num_queues - 2) | + ((n->params.num_queues - 2) << 16)); break; case NVME_TIMESTAMP: return nvme_set_feature_timestamp(n, cmd); @@ -914,12 +916,12 @@ static void nvme_clear_ctrl(NvmeCtrl *n) =20 blk_drain(n->conf.blk); =20 - for (i =3D 0; i < n->num_queues; i++) { + for (i =3D 0; i < n->params.num_queues; i++) { if (n->sq[i] !=3D NULL) { nvme_free_sq(n->sq[i], n); } } - for (i =3D 0; i < n->num_queues; i++) { + for (i =3D 0; i < n->params.num_queues; i++) { if (n->cq[i] !=3D NULL) { nvme_free_cq(n->cq[i], n); } @@ -1350,7 +1352,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) int64_t bs_size; uint8_t *pci_conf; =20 - if (!n->num_queues) { + if (!n->params.num_queues) { error_setg(errp, "num_queues can't be zero"); return; } @@ -1366,12 +1368,12 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) return; } =20 - if (!n->serial) { + if (!n->params.serial) { error_setg(errp, "serial property not set"); return; } =20 - if (!n->cmb_size_mb && n->pmrdev) { + if (!n->params.cmb_size_mb && n->pmrdev) { if (host_memory_backend_is_mapped(n->pmrdev)) { char *path =3D object_get_canonical_path_component(OBJECT(n->p= mrdev)); error_setg(errp, "can't use already busy memdev: %s", path); @@ -1402,25 +1404,26 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) n->num_namespaces =3D 1; =20 /* num_queues is really number of pairs, so each has two doorbells */ - n->reg_size =3D pow2ceil(NVME_REG_SIZE + 2 * n->num_queues * NVME_DB_S= IZE); + n->reg_size =3D pow2ceil(NVME_REG_SIZE + + 2 * n->params.num_queues * NVME_DB_SIZE); n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; =20 n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); - n->sq =3D g_new0(NvmeSQueue *, n->num_queues); - n->cq =3D g_new0(NvmeCQueue *, n->num_queues); + n->sq =3D g_new0(NvmeSQueue *, n->params.num_queues); + n->cq =3D g_new0(NvmeCQueue *, n->params.num_queues); =20 memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); - msix_init_exclusive_bar(pci_dev, n->num_queues, 4, NULL); + msix_init_exclusive_bar(pci_dev, n->params.num_queues, 4, NULL); =20 id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' '); - strpadcpy((char *)id->sn, sizeof(id->sn), n->serial, ' '); + strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' '); id->rab =3D 6; id->ieee[0] =3D 0x00; id->ieee[1] =3D 0x02; @@ -1449,7 +1452,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) n->bar.vs =3D 0x00010200; n->bar.intmc =3D n->bar.intms =3D 0; =20 - if (n->cmb_size_mb) { + if (n->params.cmb_size_mb) { =20 NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2); NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); @@ -1460,7 +1463,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1); NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ - NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->cmb_size_mb); + NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); =20 n->cmbloc =3D n->bar.cmbloc; n->cmbsz =3D n->bar.cmbsz; @@ -1544,7 +1547,7 @@ static void nvme_exit(PCIDevice *pci_dev) g_free(n->cq); g_free(n->sq); =20 - if (n->cmb_size_mb) { + if (n->params.cmb_size_mb) { g_free(n->cmbuf); } =20 @@ -1558,9 +1561,9 @@ static Property nvme_props[] =3D { DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf), DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmrdev, TYPE_MEMORY_BACKEND, HostMemoryBackend *), - DEFINE_PROP_STRING("serial", NvmeCtrl, serial), - DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, cmb_size_mb, 0), - DEFINE_PROP_UINT32("num_queues", NvmeCtrl, num_queues, 64), + DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial), + DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, params.cmb_size_mb, 0), + DEFINE_PROP_UINT32("num_queues", NvmeCtrl, params.num_queues, 64), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 6520a9f0bead..9df244c93c02 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -1,7 +1,14 @@ #ifndef HW_NVME_H #define HW_NVME_H + #include "block/nvme.h" =20 +typedef struct NvmeParams { + char *serial; + uint32_t num_queues; + uint32_t cmb_size_mb; +} NvmeParams; + typedef struct NvmeAsyncEvent { QSIMPLEQ_ENTRY(NvmeAsyncEvent) entry; NvmeAerResult result; @@ -63,6 +70,7 @@ typedef struct NvmeCtrl { MemoryRegion ctrl_mem; NvmeBar bar; BlockConf conf; + NvmeParams params; =20 uint32_t page_size; uint16_t page_bits; @@ -71,10 +79,8 @@ typedef struct NvmeCtrl { uint16_t sqe_size; uint32_t reg_size; uint32_t num_namespaces; - uint32_t num_queues; uint32_t max_q_ents; uint64_t ns_size; - uint32_t cmb_size_mb; uint32_t cmbsz; uint32_t cmbloc; uint8_t *cmbuf; @@ -82,7 +88,6 @@ typedef struct NvmeCtrl { uint64_t host_timestamp; /* Timestamp sent by the h= ost */ uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */ =20 - char *serial; HostMemoryBackend *pmrdev; =20 NvmeNamespace *namespaces; --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Wed, 13 May 2020 21:49:40 -0700 (PDT) Received: from localhost ([::1]:43872 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZ5oR-0006pe-Iu for importer@patchew.org; Thu, 14 May 2020 00:49:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lq-0001TP-B4; Thu, 14 May 2020 00:46:58 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43804) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lp-0003kT-Fy; Thu, 14 May 2020 00:46:58 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 02EE5BFE24; Thu, 14 May 2020 04:46:31 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 05/20] hw/block/nvme: use constants in identify Date: Thu, 14 May 2020 06:45:56 +0200 Message-Id: <20200514044611.734782-6-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Keith Busch --- hw/block/nvme.c | 8 ++++---- include/block/nvme.h | 8 ++++++++ 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index e26db7591574..4058f2c79796 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -693,7 +693,7 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdent= ify *c) =20 static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c) { - static const int data_len =3D 4 * KiB; + static const int data_len =3D NVME_IDENTIFY_DATA_SIZE; uint32_t min_nsid =3D le32_to_cpu(c->nsid); uint64_t prp1 =3D le64_to_cpu(c->prp1); uint64_t prp2 =3D le64_to_cpu(c->prp2); @@ -723,11 +723,11 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *c= md) NvmeIdentify *c =3D (NvmeIdentify *)cmd; =20 switch (le32_to_cpu(c->cns)) { - case 0x00: + case NVME_ID_CNS_NS: return nvme_identify_ns(n, c); - case 0x01: + case NVME_ID_CNS_CTRL: return nvme_identify_ctrl(n, c); - case 0x02: + case NVME_ID_CNS_NS_ACTIVE_LIST: return nvme_identify_nslist(n, c); default: trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns)); diff --git a/include/block/nvme.h b/include/block/nvme.h index 5525c8e34308..1720ee1d5158 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -705,6 +705,14 @@ typedef struct NvmePSD { uint8_t resv[16]; } NvmePSD; =20 +#define NVME_IDENTIFY_DATA_SIZE 4096 + +enum { + NVME_ID_CNS_NS =3D 0x0, + NVME_ID_CNS_CTRL =3D 0x1, + NVME_ID_CNS_NS_ACTIVE_LIST =3D 0x2, +}; + typedef struct NvmeIdCtrl { uint16_t vid; uint16_t ssvid; --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589432055; cv=none; d=zohomail.com; s=zohoarc; b=jtDSuwTCMSeHMy1yiuVE/dJ6aYL9fb3x22uEESzyFZC5nJ2lqz2K1wi3HukAF/Rr+8i7s1prAFBiFVYKTeUtvqwV8VWFYwBktxZl8wX3LJQ812sBrS7VBT11DpSkW2bxb7ehTApIp7Y4savJggLubW3C0rRGTDme77U33zhOlwo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589432055; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=818MT6mdBbxbfRtl5dPO9AHqWGxkt6GAGt8pkB6mpjU=; b=R9WEHOp2m2TrWgbZPAVTGELSXrtCi65CYn7JGJDNCfXq4KEWh25iKI+IeyQlqmAShVOGntTmlwW26fAYG+27BwS0120Z2iWVOXF1MDtkQly3t1n9SODOsPMpRZbMosgFgjaQx3DbReF0/y16rgvVpG0rUZk4Kus6HOe0iaL+a3Q= ARC-Authentication-Results: i=1; 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Thu, 14 May 2020 04:46:32 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 06/20] hw/block/nvme: refactor nvme_addr_read Date: Thu, 14 May 2020 06:45:57 +0200 Message-Id: <20200514044611.734782-7-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Pull the controller memory buffer check to its own function. The check will be used on its own in later patches. Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 4058f2c79796..623a88be93dc 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -66,14 +66,22 @@ =20 static void nvme_process_sq(void *opaque); =20 +static bool nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr) +{ + hwaddr low =3D n->ctrl_mem.addr; + hwaddr hi =3D n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size); + + return addr >=3D low && addr < hi; +} + static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size) { - if (n->cmbsz && addr >=3D n->ctrl_mem.addr && - addr < (n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size))= ) { + if (n->cmbsz && nvme_addr_is_cmb(n, addr)) { memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size); - } else { - pci_dma_read(&n->parent_obj, addr, buf, size); + return; } + + pci_dma_read(&n->parent_obj, addr, buf, size); } =20 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589431896; cv=none; d=zohomail.com; s=zohoarc; b=RSA61ioBsPGluYCyUS4aNfei28NtHkkKbkrWU2QMjLM28WQHCLmT5JNqRmqVO97OL09CcKgPp2s7gyAKUzDkOiQ+nHZ4pmPu+5SfiWr7vBgKGWaGI61q+Y/qB6HhZPnjtvS0BCCcH53uQH0DU7shcgrlpftUYOkehrzQgevHiX8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589431896; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uPTMinsehKv5Efvwzr/DbihCJ+0j/NS1LM2JkXyXa30=; b=ZdNL7f8lQSUJYOJgfQozs9hRmbrPnVz0ip6LZu7o6Qi2KahGZXGptojzLpnpfvIM9p3eLhoYC+CcPfNoHdRj63urTyHyYKap5K4P4aTCUIk+7NR1lyPdpYpiHJhMiplReasq5APFxWgH6HH5oZiQ4i4HX4OdACwm29f2dZ58Ny0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589431896745586.7953106462382; Wed, 13 May 2020 21:51:36 -0700 (PDT) Received: from localhost ([::1]:52076 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZ5qJ-0001lS-Cb for importer@patchew.org; Thu, 14 May 2020 00:51:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56694) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lX-0000Xd-CM; Thu, 14 May 2020 00:46:39 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43812) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lV-0003kX-40; Thu, 14 May 2020 00:46:39 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id C5BADBFE2D; Thu, 14 May 2020 04:46:32 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 07/20] hw/block/nvme: fix pin-based interrupt behavior Date: Thu, 14 May 2020 06:45:58 +0200 Message-Id: <20200514044611.734782-8-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , "Michael S. Tsirkin" , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen First, since the device only supports MSI-X or pin-based interrupt, if MSI-X is not enabled, it should not accept interrupt vectors different from 0 when creating completion queues. Secondly, the irq_status NvmeCtrl member is meant to be compared to the INTMS register, so it should only be 32 bits wide. And it is really only useful when used with multi-message MSI. Third, since we do not force a 1-to-1 correspondence between cqid and interrupt vector, the irq_status register should not have bits set according to cqid, but according to the associated interrupt vector. Fix these issues, but keep irq_status available so we can easily support multi-message MSI down the line. Fixes: 5e9aa92eb1a5 ("hw/block: Fix pin-based interrupt behaviour of NVMe") Cc: "Michael S. Tsirkin" Cc: Marcel Apfelbaum Signed-off-by: Klaus Jensen Reviewed-by: Keith Busch --- hw/block/nvme.c | 12 ++++++++---- hw/block/nvme.h | 2 +- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 623a88be93dc..c9d10df1f763 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -138,8 +138,8 @@ static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq) msix_notify(&(n->parent_obj), cq->vector); } else { trace_pci_nvme_irq_pin(); - assert(cq->cqid < 64); - n->irq_status |=3D 1 << cq->cqid; + assert(cq->vector < 32); + n->irq_status |=3D 1 << cq->vector; nvme_irq_check(n); } } else { @@ -153,8 +153,8 @@ static void nvme_irq_deassert(NvmeCtrl *n, NvmeCQueue *= cq) if (msix_enabled(&(n->parent_obj))) { return; } else { - assert(cq->cqid < 64); - n->irq_status &=3D ~(1 << cq->cqid); + assert(cq->vector < 32); + n->irq_status &=3D ~(1 << cq->vector); nvme_irq_check(n); } } @@ -653,6 +653,10 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *c= md) trace_pci_nvme_err_invalid_create_cq_addr(prp1); return NVME_INVALID_FIELD | NVME_DNR; } + if (unlikely(!msix_enabled(&n->parent_obj) && vector)) { + trace_pci_nvme_err_invalid_create_cq_vector(vector); + return NVME_INVALID_IRQ_VECTOR | NVME_DNR; + } if (unlikely(vector > n->params.num_queues)) { trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 9df244c93c02..91f16c812582 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -84,7 +84,7 @@ typedef struct NvmeCtrl { uint32_t cmbsz; uint32_t cmbloc; uint8_t *cmbuf; - uint64_t irq_status; + uint32_t irq_status; uint64_t host_timestamp; /* Timestamp sent by the h= ost */ uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */ =20 --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Wed, 13 May 2020 21:49:51 -0700 (PDT) Received: from localhost ([::1]:44946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZ5oc-0007G1-46 for importer@patchew.org; Thu, 14 May 2020 00:49:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lW-0000VG-L6; Thu, 14 May 2020 00:46:38 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43814) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lV-0003ka-5v; Thu, 14 May 2020 00:46:38 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 3EFC5BFE2F; Thu, 14 May 2020 04:46:33 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 08/20] hw/block/nvme: allow use of any valid msix vector Date: Thu, 14 May 2020 06:45:59 +0200 Message-Id: <20200514044611.734782-9-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , "Michael S. Tsirkin" , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen If the device uses MSI-X, any of the 2048 MSI-X interrupt vectors are valid. If the device is not using MSI-X, vector will and can only be zero at this point. Cc: "Michael S. Tsirkin" Cc: Marcel Apfelbaum Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/nvme.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index c9d10df1f763..a2e6734c7a25 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -657,7 +657,7 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cm= d) trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } - if (unlikely(vector > n->params.num_queues)) { + if (unlikely(vector > PCI_MSIX_FLAGS_QSIZE)) { trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589431920; cv=none; d=zohomail.com; s=zohoarc; b=cZmRsYUhiSrA7Ju9YybvoilmmUA1Gi4ih2xfB+6a3UmfmdXheGjIn8Vg6zCONEwCvgTcWsFOKJcgzLRkLz95+fp52fL8GpCzXb/dNKWt7klzBJcV3cyYvEcHfmKZY8PPNxyNezsbI6kKykFjt3xe9e/GbV9dHavYLkKR/UYc0z8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589431920; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KEK92dTIg9Ff/8LItIoDW3xRmft7mO8PaUUD5y1OgAc=; b=FOkvpphB5+3LWQHjFsRy9v6vHn0Ki/IwG30hH6biZxXe9Nebk1/m5R6rR63DbKnASkqdNXyq6hhRNsN4qXKSTS59AQhgKtPxhl2nHbd54ePxXXGwqFDjMsj3NmU7jruRaPjtZ8AUZunsVyTKFWnLguW++IJYoZP3dGrGiL7moq4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589431920330138.91950524457638; Wed, 13 May 2020 21:52:00 -0700 (PDT) Received: from localhost ([::1]:54100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZ5qh-0002Zw-0L for importer@patchew.org; Thu, 14 May 2020 00:51:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lX-0000X3-6G; Thu, 14 May 2020 00:46:39 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43816) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lV-0003kf-9g; Thu, 14 May 2020 00:46:38 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id A9A0DBFE39; Thu, 14 May 2020 04:46:33 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 09/20] hw/block/nvme: add max_ioqpairs device parameter Date: Thu, 14 May 2020 06:46:00 +0200 Message-Id: <20200514044611.734782-10-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen The num_queues device paramater has a slightly confusing meaning because it accounts for the admin queue pair which is not really optional. Secondly, it is really a maximum value of queues allowed. Add a new max_ioqpairs parameter that only accounts for I/O queue pairs, but keep num_queues for compatibility. Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Keith Busch --- hw/block/nvme.c | 49 ++++++++++++++++++++++++++++++------------------- hw/block/nvme.h | 3 ++- 2 files changed, 32 insertions(+), 20 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index a2e6734c7a25..88ab5d55b8c9 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -20,7 +20,7 @@ * -device nvme,drive=3D,serial=3D,id=3D, \ * cmb_size_mb=3D, \ * [pmrdev=3D,] \ - * num_queues=3D + * max_ioqpairs=3D * * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at * offset 0 in BAR2 and supports only WDS, RDS and SQS for now. @@ -36,6 +36,7 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/error-report.h" #include "hw/block/block.h" #include "hw/pci/msix.h" #include "hw/pci/pci.h" @@ -86,12 +87,12 @@ static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, vo= id *buf, int size) =20 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) { - return sqid < n->params.num_queues && n->sq[sqid] !=3D NULL ? 0 : -1; + return sqid < n->params.max_ioqpairs + 1 && n->sq[sqid] !=3D NULL ? 0 = : -1; } =20 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid) { - return cqid < n->params.num_queues && n->cq[cqid] !=3D NULL ? 0 : -1; + return cqid < n->params.max_ioqpairs + 1 && n->cq[cqid] !=3D NULL ? 0 = : -1; } =20 static void nvme_inc_cq_tail(NvmeCQueue *cq) @@ -809,8 +810,8 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); break; case NVME_NUMBER_OF_QUEUES: - result =3D cpu_to_le32((n->params.num_queues - 2) | - ((n->params.num_queues - 2) << 16)); + result =3D cpu_to_le32((n->params.max_ioqpairs - 1) | + ((n->params.max_ioqpairs - 1) << 16)); trace_pci_nvme_getfeat_numq(result); break; case NVME_TIMESTAMP: @@ -854,10 +855,10 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd= *cmd, NvmeRequest *req) case NVME_NUMBER_OF_QUEUES: trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, ((dw11 >> 16) & 0xFFFF) + 1, - n->params.num_queues - 1, - n->params.num_queues - 1); - req->cqe.result =3D cpu_to_le32((n->params.num_queues - 2) | - ((n->params.num_queues - 2) << 16)); + n->params.max_ioqpairs, + n->params.max_ioqpairs); + req->cqe.result =3D cpu_to_le32((n->params.max_ioqpairs - 1) | + ((n->params.max_ioqpairs - 1) << 16)= ); break; case NVME_TIMESTAMP: return nvme_set_feature_timestamp(n, cmd); @@ -928,12 +929,12 @@ static void nvme_clear_ctrl(NvmeCtrl *n) =20 blk_drain(n->conf.blk); =20 - for (i =3D 0; i < n->params.num_queues; i++) { + for (i =3D 0; i < n->params.max_ioqpairs + 1; i++) { if (n->sq[i] !=3D NULL) { nvme_free_sq(n->sq[i], n); } } - for (i =3D 0; i < n->params.num_queues; i++) { + for (i =3D 0; i < n->params.max_ioqpairs + 1; i++) { if (n->cq[i] !=3D NULL) { nvme_free_cq(n->cq[i], n); } @@ -1364,8 +1365,17 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) int64_t bs_size; uint8_t *pci_conf; =20 - if (!n->params.num_queues) { - error_setg(errp, "num_queues can't be zero"); + if (n->params.num_queues) { + warn_report("num_queues is deprecated; please use max_ioqpairs " + "instead"); + + n->params.max_ioqpairs =3D n->params.num_queues - 1; + } + + if (n->params.max_ioqpairs < 1 || + n->params.max_ioqpairs > PCI_MSIX_FLAGS_QSIZE) { + error_setg(errp, "max_ioqpairs must be between 1 and %d", + PCI_MSIX_FLAGS_QSIZE); return; } =20 @@ -1415,21 +1425,21 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) =20 n->num_namespaces =3D 1; =20 - /* num_queues is really number of pairs, so each has two doorbells */ + /* add one to max_ioqpairs to account for the admin queue pair */ n->reg_size =3D pow2ceil(NVME_REG_SIZE + - 2 * n->params.num_queues * NVME_DB_SIZE); + 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; =20 n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); - n->sq =3D g_new0(NvmeSQueue *, n->params.num_queues); - n->cq =3D g_new0(NvmeCQueue *, n->params.num_queues); + n->sq =3D g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); + n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); =20 memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); - msix_init_exclusive_bar(pci_dev, n->params.num_queues, 4, NULL); + msix_init_exclusive_bar(pci_dev, n->params.max_ioqpairs + 1, 4, NULL); =20 id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); @@ -1575,7 +1585,8 @@ static Property nvme_props[] =3D { HostMemoryBackend *), DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial), DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, params.cmb_size_mb, 0), - DEFINE_PROP_UINT32("num_queues", NvmeCtrl, params.num_queues, 64), + DEFINE_PROP_UINT32("num_queues", NvmeCtrl, params.num_queues, 0), + DEFINE_PROP_UINT32("max_ioqpairs", NvmeCtrl, params.max_ioqpairs, 64), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 91f16c812582..26c38bd913be 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -5,7 +5,8 @@ =20 typedef struct NvmeParams { char *serial; - uint32_t num_queues; + uint32_t num_queues; /* deprecated since 5.1 */ + uint32_t max_ioqpairs; uint32_t cmb_size_mb; } NvmeParams; =20 --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Wed, 13 May 2020 21:49:29 -0700 (PDT) Received: from localhost ([::1]:42956 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZ5oF-0006Tb-Mw for importer@patchew.org; Thu, 14 May 2020 00:49:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56690) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lW-0000WC-SH; Thu, 14 May 2020 00:46:38 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43818) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lV-0003kg-B5; Thu, 14 May 2020 00:46:38 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 2E811BFE30; Thu, 14 May 2020 04:46:34 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 10/20] hw/block/nvme: remove redundant cmbloc/cmbsz members Date: Thu, 14 May 2020 06:46:01 +0200 Message-Id: <20200514044611.734782-11-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 7 ++----- hw/block/nvme.h | 2 -- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 88ab5d55b8c9..e93ed729aef5 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -77,7 +77,7 @@ static bool nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr) =20 static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size) { - if (n->cmbsz && nvme_addr_is_cmb(n, addr)) { + if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr)) { memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size); return; } @@ -171,7 +171,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, if (unlikely(!prp1)) { trace_pci_nvme_err_invalid_prp(); return NVME_INVALID_FIELD | NVME_DNR; - } else if (n->cmbsz && prp1 >=3D n->ctrl_mem.addr && + } else if (n->bar.cmbsz && prp1 >=3D n->ctrl_mem.addr && prp1 < n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size)) { qsg->nsg =3D 0; qemu_iovec_init(iov, num_prps); @@ -1487,9 +1487,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); =20 - n->cmbloc =3D n->bar.cmbloc; - n->cmbsz =3D n->bar.cmbsz; - n->cmbuf =3D g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n, "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz)= ); diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 26c38bd913be..cedc8022dbb3 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -82,8 +82,6 @@ typedef struct NvmeCtrl { uint32_t num_namespaces; uint32_t max_q_ents; uint64_t ns_size; - uint32_t cmbsz; - uint32_t cmbloc; uint8_t *cmbuf; uint32_t irq_status; uint64_t host_timestamp; /* Timestamp sent by the h= ost */ --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589432197; cv=none; d=zohomail.com; s=zohoarc; b=CaY2/b52vfO0We+7Ca5YwTD5mh1aTiDKrlv7r3VFx4OLA4ceyjFTpvo9yznc0azRqflxaU7k+wGlBQH96cohgrHJK6Ky3bENJCwO2VyaW1kt7rqAvt2cNYE/5zkY/dV5L/GLF7Alp6dDKZjItkpsb2cA9jin+YSeU447bTOi4Mw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589432197; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 14 May 2020 00:46:59 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 8D6B5BFE3B; Thu, 14 May 2020 04:46:34 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 11/20] hw/block/nvme: factor out property/constraint checks Date: Thu, 14 May 2020 06:46:02 +0200 Message-Id: <20200514044611.734782-12-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 48 ++++++++++++++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 18 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index e93ed729aef5..1d4fbba9c5da 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1356,24 +1356,19 @@ static const MemoryRegionOps nvme_cmb_ops =3D { }, }; =20 -static void nvme_realize(PCIDevice *pci_dev, Error **errp) +static void nvme_check_constraints(NvmeCtrl *n, Error **errp) { - NvmeCtrl *n =3D NVME(pci_dev); - NvmeIdCtrl *id =3D &n->id_ctrl; + NvmeParams *params =3D &n->params; =20 - int i; - int64_t bs_size; - uint8_t *pci_conf; - - if (n->params.num_queues) { + if (params->num_queues) { warn_report("num_queues is deprecated; please use max_ioqpairs " "instead"); =20 - n->params.max_ioqpairs =3D n->params.num_queues - 1; + params->max_ioqpairs =3D params->num_queues - 1; } =20 - if (n->params.max_ioqpairs < 1 || - n->params.max_ioqpairs > PCI_MSIX_FLAGS_QSIZE) { + if (params->max_ioqpairs < 1 || + params->max_ioqpairs > PCI_MSIX_FLAGS_QSIZE) { error_setg(errp, "max_ioqpairs must be between 1 and %d", PCI_MSIX_FLAGS_QSIZE); return; @@ -1384,13 +1379,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) return; } =20 - bs_size =3D blk_getlength(n->conf.blk); - if (bs_size < 0) { - error_setg(errp, "could not get backing file size"); - return; - } - - if (!n->params.serial) { + if (!params->serial) { error_setg(errp, "serial property not set"); return; } @@ -1410,6 +1399,29 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) =20 host_memory_backend_set_mapped(n->pmrdev, true); } +} + +static void nvme_realize(PCIDevice *pci_dev, Error **errp) +{ + NvmeCtrl *n =3D NVME(pci_dev); + NvmeIdCtrl *id =3D &n->id_ctrl; + Error *local_err =3D NULL; + + int i; + int64_t bs_size; + uint8_t *pci_conf; + + nvme_check_constraints(n, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + bs_size =3D blk_getlength(n->conf.blk); + if (bs_size < 0) { + error_setg(errp, "could not get backing file size"); + return; + } =20 blkconf_blocksizes(&n->conf); if (!blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.= blk), --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Wed, 13 May 2020 21:53:50 -0700 (PDT) Received: from localhost ([::1]:32990 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZ5sS-0005X4-4e for importer@patchew.org; Thu, 14 May 2020 00:53:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56722) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lr-0001XR-Jr; Thu, 14 May 2020 00:46:59 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43832) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lq-0003lC-KJ; Thu, 14 May 2020 00:46:59 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id EBBD3BFE3D; Thu, 14 May 2020 04:46:34 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 12/20] hw/block/nvme: factor out device state setup Date: Thu, 14 May 2020 06:46:03 +0200 Message-Id: <20200514044611.734782-13-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 1d4fbba9c5da..617b2f0005df 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1401,6 +1401,17 @@ static void nvme_check_constraints(NvmeCtrl *n, Erro= r **errp) } } =20 +static void nvme_init_state(NvmeCtrl *n) +{ + n->num_namespaces =3D 1; + /* add one to max_ioqpairs to account for the admin queue pair */ + n->reg_size =3D pow2ceil(NVME_REG_SIZE + + 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); + n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); + n->sq =3D g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); + n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); +} + static void nvme_realize(PCIDevice *pci_dev, Error **errp) { NvmeCtrl *n =3D NVME(pci_dev); @@ -1417,6 +1428,8 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) return; } =20 + nvme_init_state(n); + bs_size =3D blk_getlength(n->conf.blk); if (bs_size < 0) { error_setg(errp, "could not get backing file size"); @@ -1435,17 +1448,8 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS); pcie_endpoint_cap_init(pci_dev, 0x80); =20 - n->num_namespaces =3D 1; - - /* add one to max_ioqpairs to account for the admin queue pair */ - n->reg_size =3D pow2ceil(NVME_REG_SIZE + - 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; =20 - n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); - n->sq =3D g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); - n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); - memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); pci_register_bar(pci_dev, 0, --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589432291; cv=none; d=zohomail.com; s=zohoarc; b=l5TTzBY5H3vKcQhMlQcZnwUFSExTS1+cXiRlDA+PwdW6XdZkF4IXgJdh+9wFRpRw4mXEW6nJxzNC1EU1J9duSbgP1EIjZ2ZdOXrzPzaC4RLKQgiKu4zu4MC8aikwETtR2rx9qRhMis570Arg27ZDAvDz6se8m9pgrs/GDS+PYqw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589432291; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 14 May 2020 00:47:01 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 55004BFE43; Thu, 14 May 2020 04:46:35 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 13/20] hw/block/nvme: factor out block backend setup Date: Thu, 14 May 2020 06:46:04 +0200 Message-Id: <20200514044611.734782-14-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 617b2f0005df..c83f0bb1ab20 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1412,6 +1412,13 @@ static void nvme_init_state(NvmeCtrl *n) n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); } =20 +static void nvme_init_blk(NvmeCtrl *n, Error **errp) +{ + blkconf_blocksizes(&n->conf); + blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.blk), + false, errp); +} + static void nvme_realize(PCIDevice *pci_dev, Error **errp) { NvmeCtrl *n =3D NVME(pci_dev); @@ -1436,9 +1443,9 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) return; } =20 - blkconf_blocksizes(&n->conf); - if (!blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.= blk), - false, errp)) { + nvme_init_blk(n, &local_err); + if (local_err) { + error_propagate(errp, local_err); return; } =20 --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589432161; cv=none; d=zohomail.com; s=zohoarc; b=T/eKov+wUUl8ODskzru9zrT/Gta6NXmb4kUPxL5Gft2fxiMz5eX3nWjn4Ms9ZFuouXkDjtjTFzUoAKjoXpcVN2ZzkTVaYvGED855kodtO0S/nB2C9vMu72zHiBT74OwhYi23uYh0+5GMwYCBDroh8l7Mjr7cI8nVKOMKgOIHP2w= ARC-Message-Signature: i=1; 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Thu, 14 May 2020 00:55:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56738) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5ls-0001ZX-Ab; Thu, 14 May 2020 00:47:00 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43852) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lr-0003lM-D7; Thu, 14 May 2020 00:46:59 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id AED66BFDA3; Thu, 14 May 2020 04:46:35 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 14/20] hw/block/nvme: add namespace helpers Date: Thu, 14 May 2020 06:46:05 +0200 Message-Id: <20200514044611.734782-15-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Introduce some small helpers to make the next patches easier on the eye. Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 3 +-- hw/block/nvme.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index c83f0bb1ab20..e24d376b0d71 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1575,8 +1575,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) id_ns->dps =3D 0; id_ns->lbaf[0].ds =3D BDRV_SECTOR_BITS; id_ns->ncap =3D id_ns->nuse =3D id_ns->nsze =3D - cpu_to_le64(n->ns_size >> - id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas)].ds); + cpu_to_le64(nvme_ns_nlbas(n, ns)); } } =20 diff --git a/hw/block/nvme.h b/hw/block/nvme.h index cedc8022dbb3..61dd9b23b81d 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -61,6 +61,17 @@ typedef struct NvmeNamespace { NvmeIdNs id_ns; } NvmeNamespace; =20 +static inline NvmeLBAF *nvme_ns_lbaf(NvmeNamespace *ns) +{ + NvmeIdNs *id_ns =3D &ns->id_ns; + return &id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)]; +} + +static inline uint8_t nvme_ns_lbads(NvmeNamespace *ns) +{ + return nvme_ns_lbaf(ns)->ds; +} + #define TYPE_NVME "nvme" #define NVME(obj) \ OBJECT_CHECK(NvmeCtrl, (obj), TYPE_NVME) @@ -97,4 +108,10 @@ typedef struct NvmeCtrl { NvmeIdCtrl id_ctrl; } NvmeCtrl; =20 +/* calculate the number of LBAs that the namespace can accomodate */ +static inline uint64_t nvme_ns_nlbas(NvmeCtrl *n, NvmeNamespace *ns) +{ + return n->ns_size >> nvme_ns_lbads(ns); +} + #endif /* HW_NVME_H */ --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589432304; cv=none; d=zohomail.com; s=zohoarc; b=bYwkM5hXgGO/c8oHN0/OvOslZk32MTn1EvgqkBIry86nf+ckZ5U3e4c6K/jBcIesb+rKZWZE10Huxew5zIXijz04PJEJhsKNbyS6uKQdnEcmc1EpvLO3LY1hSsQVJVXGcIm7nxAskqsKoUGBSxiYor+vbbPEQgzocJY8lrxrqvg= ARC-Message-Signature: i=1; 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Thu, 14 May 2020 00:58:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56748) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lt-0001c3-34; Thu, 14 May 2020 00:47:01 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43870) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lr-0003lU-MY; Thu, 14 May 2020 00:47:00 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 17D75BF647; Thu, 14 May 2020 04:46:36 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 15/20] hw/block/nvme: factor out namespace setup Date: Thu, 14 May 2020 06:46:06 +0200 Message-Id: <20200514044611.734782-16-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 46 ++++++++++++++++++++++++++-------------------- 1 file changed, 26 insertions(+), 20 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index e24d376b0d71..8e9312534fcd 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1419,6 +1419,27 @@ static void nvme_init_blk(NvmeCtrl *n, Error **errp) false, errp); } =20 +static void nvme_init_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **er= rp) +{ + int64_t bs_size; + NvmeIdNs *id_ns =3D &ns->id_ns; + + bs_size =3D blk_getlength(n->conf.blk); + if (bs_size < 0) { + error_setg_errno(errp, -bs_size, "could not get backing file size"= ); + return; + } + + n->ns_size =3D bs_size; + + id_ns->lbaf[0].ds =3D BDRV_SECTOR_BITS; + id_ns->nsze =3D cpu_to_le64(nvme_ns_nlbas(n, ns)); + + /* no thin provisioning */ + id_ns->ncap =3D id_ns->nsze; + id_ns->nuse =3D id_ns->ncap; +} + static void nvme_realize(PCIDevice *pci_dev, Error **errp) { NvmeCtrl *n =3D NVME(pci_dev); @@ -1426,7 +1447,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) Error *local_err =3D NULL; =20 int i; - int64_t bs_size; uint8_t *pci_conf; =20 nvme_check_constraints(n, &local_err); @@ -1437,12 +1457,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) =20 nvme_init_state(n); =20 - bs_size =3D blk_getlength(n->conf.blk); - if (bs_size < 0) { - error_setg(errp, "could not get backing file size"); - return; - } - nvme_init_blk(n, &local_err); if (local_err) { error_propagate(errp, local_err); @@ -1455,8 +1469,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS); pcie_endpoint_cap_init(pci_dev, 0x80); =20 - n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; - memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); pci_register_bar(pci_dev, 0, @@ -1565,17 +1577,11 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) } =20 for (i =3D 0; i < n->num_namespaces; i++) { - NvmeNamespace *ns =3D &n->namespaces[i]; - NvmeIdNs *id_ns =3D &ns->id_ns; - id_ns->nsfeat =3D 0; - id_ns->nlbaf =3D 0; - id_ns->flbas =3D 0; - id_ns->mc =3D 0; - id_ns->dpc =3D 0; - id_ns->dps =3D 0; - id_ns->lbaf[0].ds =3D BDRV_SECTOR_BITS; - id_ns->ncap =3D id_ns->nuse =3D id_ns->nsze =3D - cpu_to_le64(nvme_ns_nlbas(n, ns)); + nvme_init_namespace(n, &n->namespaces[i], &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } } } =20 --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589431904; cv=none; d=zohomail.com; s=zohoarc; b=JjYDPUznJojWH1s+x9zTPy+lKVVwJvsMZMLEVkDQ1qpOmwxI7Fazpivd78HCiWwYOK2xlNtkfunnjyWNImN+KOmOXeRrMWWlzkaiZo1/Mkh1bEWNsTc20lgGvBZw4YoUtjOMZmp4ZbfcHvumY041Y8bTidhhWN5NrbBYm+sWNi4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589431904; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yeUPvhRWSofXTjRNLZZlKQAnQ83AxuA4tHuwP/zBTs4=; b=FUaccTf1a8jUsrpIUPCZSW7EcFBZmJlpT7u53ZmcyoqsOTcxDP74M4qJgyRZZ8KC1DcMJIYIfUBXaA/9sgte2+AWYz7fYPEb6I1nXMDt41stkncBg0i5vNMIv8byLBe6WwCqkRTuMEk3+fksXBxQ12Cfhre1wSH+1D6TC40gp3M= ARC-Authentication-Results: i=1; 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Thu, 14 May 2020 04:46:36 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 16/20] hw/block/nvme: factor out pci setup Date: Thu, 14 May 2020 06:46:07 +0200 Message-Id: <20200514044611.734782-17-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 8e9312534fcd..2fcab706c759 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1440,6 +1440,22 @@ static void nvme_init_namespace(NvmeCtrl *n, NvmeNam= espace *ns, Error **errp) id_ns->nuse =3D id_ns->ncap; } =20 +static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev) +{ + uint8_t *pci_conf =3D pci_dev->config; + + pci_conf[PCI_INTERRUPT_PIN] =3D 1; + pci_config_set_prog_interface(pci_conf, 0x2); + pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS); + pcie_endpoint_cap_init(pci_dev, 0x80); + + memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", + n->reg_size); + pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); + msix_init_exclusive_bar(pci_dev, n->params.max_ioqpairs + 1, 4, NULL); +} + static void nvme_realize(PCIDevice *pci_dev, Error **errp) { NvmeCtrl *n =3D NVME(pci_dev); @@ -1463,19 +1479,9 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) return; } =20 + nvme_init_pci(n, pci_dev); + pci_conf =3D pci_dev->config; - pci_conf[PCI_INTERRUPT_PIN] =3D 1; - pci_config_set_prog_interface(pci_dev->config, 0x2); - pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS); - pcie_endpoint_cap_init(pci_dev, 0x80); - - memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, - "nvme", n->reg_size); - pci_register_bar(pci_dev, 0, - PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, - &n->iomem); - msix_init_exclusive_bar(pci_dev, n->params.max_ioqpairs + 1, 4, NULL); - id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589432071; cv=none; d=zohomail.com; s=zohoarc; b=jRck2hfnQs96ndD2QYBSLdZv1O49Bp0lV8wzJBhO5wUTh2R8YVvIKgymaM1xo1/qaV3L92uDWIWlbGE197TuQWEXNLyVUz4/Md/8TS/Xa/mX/qNFNmCtE+50eWGFlUtcXsAhIerrdJj8bTdy0Ux2IUz0W0VA6sdojcg7JWPR7vw= ARC-Message-Signature: i=1; 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Thu, 14 May 2020 00:54:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lv-0001jo-6v; Thu, 14 May 2020 00:47:03 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43878) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lr-0003ld-UO; Thu, 14 May 2020 00:47:02 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id E9488BFE49; Thu, 14 May 2020 04:46:36 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 17/20] hw/block/nvme: factor out cmb setup Date: Thu, 14 May 2020 06:46:08 +0200 Message-Id: <20200514044611.734782-18-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 43 ++++++++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 2fcab706c759..d71a5f142d51 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -57,6 +57,7 @@ =20 #define NVME_REG_SIZE 0x1000 #define NVME_DB_SIZE 4 +#define NVME_CMB_BIR 2 =20 #define NVME_GUEST_ERR(trace, fmt, ...) \ do { \ @@ -1440,6 +1441,28 @@ static void nvme_init_namespace(NvmeCtrl *n, NvmeNam= espace *ns, Error **errp) id_ns->nuse =3D id_ns->ncap; } =20 +static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev) +{ + NVME_CMBLOC_SET_BIR(n->bar.cmbloc, NVME_CMB_BIR); + NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); + + NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1); + NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0); + NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 0); + NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); + NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1); + NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ + NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); + + n->cmbuf =3D g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); + memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n, + "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); + pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc), + PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64 | + PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem); +} + static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev) { uint8_t *pci_conf =3D pci_dev->config; @@ -1516,25 +1539,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) n->bar.intmc =3D n->bar.intms =3D 0; =20 if (n->params.cmb_size_mb) { - - NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2); - NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); - - NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0); - NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 0); - NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ - NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); - - n->cmbuf =3D g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); - memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n, - "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz)= ); - pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc), - PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 | - PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem); - + nvme_init_cmb(n, pci_dev); } else if (n->pmrdev) { /* Controller Capabilities register */ NVME_CAP_SET_PMRS(n->bar.cap, 1); --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 13 May 2020 21:56:36 -0700 (PDT) Received: from localhost ([::1]:42914 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jZ5v9-00022o-Dd for importer@patchew.org; Thu, 14 May 2020 00:56:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lu-0001fj-4X; Thu, 14 May 2020 00:47:02 -0400 Received: from charlie.dont.surf ([128.199.63.193]:43880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZ5lr-0003le-Vy; Thu, 14 May 2020 00:47:01 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 52562BFE52; Thu, 14 May 2020 04:46:37 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 18/20] hw/block/nvme: factor out pmr setup Date: Thu, 14 May 2020 06:46:09 +0200 Message-Id: <20200514044611.734782-19-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/nvme.c | 95 ++++++++++++++++++++++++++----------------------- 1 file changed, 51 insertions(+), 44 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index d71a5f142d51..7254b66ae199 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -58,6 +58,7 @@ #define NVME_REG_SIZE 0x1000 #define NVME_DB_SIZE 4 #define NVME_CMB_BIR 2 +#define NVME_PMR_BIR 2 =20 #define NVME_GUEST_ERR(trace, fmt, ...) \ do { \ @@ -1463,6 +1464,55 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pc= i_dev) PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem); } =20 +static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev) +{ + /* Controller Capabilities register */ + NVME_CAP_SET_PMRS(n->bar.cap, 1); + + /* PMR Capabities register */ + n->bar.pmrcap =3D 0; + NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0); + NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0); + NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR); + NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0); + /* Turn on bit 1 support */ + NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02); + NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0); + NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0); + + /* PMR Control register */ + n->bar.pmrctl =3D 0; + NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0); + + /* PMR Status register */ + n->bar.pmrsts =3D 0; + NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0); + NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0); + NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0); + NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0); + + /* PMR Elasticity Buffer Size register */ + n->bar.pmrebs =3D 0; + NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0); + NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0); + NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0); + + /* PMR Sustained Write Throughput register */ + n->bar.pmrswtp =3D 0; + NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0); + NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0); + + /* PMR Memory Space Control register */ + n->bar.pmrmsc =3D 0; + NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0); + NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0); + + pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap), + PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64 | + PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr); +} + static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev) { uint8_t *pci_conf =3D pci_dev->config; @@ -1541,50 +1591,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) if (n->params.cmb_size_mb) { nvme_init_cmb(n, pci_dev); } else if (n->pmrdev) { - /* Controller Capabilities register */ - NVME_CAP_SET_PMRS(n->bar.cap, 1); - - /* PMR Capabities register */ - n->bar.pmrcap =3D 0; - NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0); - NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0); - NVME_PMRCAP_SET_BIR(n->bar.pmrcap, 2); - NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0); - /* Turn on bit 1 support */ - NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02); - NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0); - NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0); - - /* PMR Control register */ - n->bar.pmrctl =3D 0; - NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0); - - /* PMR Status register */ - n->bar.pmrsts =3D 0; - NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0); - NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0); - NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0); - NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0); - - /* PMR Elasticity Buffer Size register */ - n->bar.pmrebs =3D 0; - NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0); - NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0); - NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0); - - /* PMR Sustained Write Throughput register */ - n->bar.pmrswtp =3D 0; - NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0); - NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0); - - /* PMR Memory Space Control register */ - n->bar.pmrmsc =3D 0; - NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0); - NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0); - - pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap), - PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 | - PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr); + nvme_init_pmr(n, pci_dev); } =20 for (i =3D 0; i < n->num_namespaces; i++) { --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589431919; cv=none; d=zohomail.com; s=zohoarc; b=kErpNzEc2GbyWz1mad1w5Hk6EPKXOgU/vx9+4/+eCjfNl4Ronj/5kF1AXxIRLQkK72O8mMLqeICwti9wNk11TSpIe+0vydUw0MgXxijNgsZSW3HhXITVMroT2wO7ZZp4A4ThR0EPyNoz8dYPNqFsx87jS202xnfjDh6wlLfceS4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589431919; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 14 May 2020 00:47:01 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id B042EBFE5B; Thu, 14 May 2020 04:46:37 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 19/20] hw/block/nvme: do cmb/pmr init as part of pci init Date: Thu, 14 May 2020 06:46:10 +0200 Message-Id: <20200514044611.734782-20-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/nvme.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 7254b66ae199..2addcc86034a 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1527,6 +1527,12 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pc= i_dev) pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); msix_init_exclusive_bar(pci_dev, n->params.max_ioqpairs + 1, 4, NULL); + + if (n->params.cmb_size_mb) { + nvme_init_cmb(n, pci_dev); + } else if (n->pmrdev) { + nvme_init_pmr(n, pci_dev); + } } =20 static void nvme_realize(PCIDevice *pci_dev, Error **errp) @@ -1588,12 +1594,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) n->bar.vs =3D 0x00010200; n->bar.intmc =3D n->bar.intms =3D 0; =20 - if (n->params.cmb_size_mb) { - nvme_init_cmb(n, pci_dev); - } else if (n->pmrdev) { - nvme_init_pmr(n, pci_dev); - } - for (i =3D 0; i < n->num_namespaces; i++) { nvme_init_namespace(n, &n->namespaces[i], &local_err); if (local_err) { --=20 2.26.2 From nobody Sun Feb 8 18:43:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589432053; cv=none; d=zohomail.com; s=zohoarc; b=GrzBjFp28ykku7KJxXVg+53GzzW+aVsE097EsTSSLISo5N9akjKfFH4LGoFU6HiyMn56/yFgu3a98h+n2Hco6fLOGS/EuVKeCjiCueQCzZBGGXVifJj+qiLn+lglxJpI3XqeGOEOw8Dom2AcTbd1TD38ivq5G/39NDBSTPh3POk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589432053; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 14 May 2020 00:47:01 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 18F1BBFDAD; Thu, 14 May 2020 04:46:38 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v6 20/20] hw/block/nvme: factor out controller identify setup Date: Thu, 14 May 2020 06:46:11 +0200 Message-Id: <20200514044611.734782-21-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514044611.734782-1-its@irrelevant.dk> References: <20200514044611.734782-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/14 00:46:30 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 49 ++++++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 23 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 2addcc86034a..149abef497c4 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1535,32 +1535,11 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *p= ci_dev) } } =20 -static void nvme_realize(PCIDevice *pci_dev, Error **errp) +static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev) { - NvmeCtrl *n =3D NVME(pci_dev); NvmeIdCtrl *id =3D &n->id_ctrl; - Error *local_err =3D NULL; + uint8_t *pci_conf =3D pci_dev->config; =20 - int i; - uint8_t *pci_conf; - - nvme_check_constraints(n, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - nvme_init_state(n); - - nvme_init_blk(n, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - nvme_init_pci(n, pci_dev); - - pci_conf =3D pci_dev->config; id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); @@ -1593,6 +1572,30 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) =20 n->bar.vs =3D 0x00010200; n->bar.intmc =3D n->bar.intms =3D 0; +} + +static void nvme_realize(PCIDevice *pci_dev, Error **errp) +{ + NvmeCtrl *n =3D NVME(pci_dev); + Error *local_err =3D NULL; + + int i; + + nvme_check_constraints(n, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + nvme_init_state(n); + nvme_init_blk(n, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + nvme_init_pci(n, pci_dev); + nvme_init_ctrl(n, pci_dev); =20 for (i =3D 0; i < n->num_namespaces; i++) { nvme_init_namespace(n, &n->namespaces[i], &local_err); --=20 2.26.2