From nobody Mon Feb 9 23:57:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1589383016; cv=none; d=zohomail.com; s=zohoarc; b=gWcmtDrlB3b1bCamZNcMuqK6b/ESP2BrLQTj1y/B7/0C0qYeBJfTw2OgmS/HCxosf4g0nE0NBgjBkW906TdOm/fGKSK2UGbDkWZRuhH7iiHQiGSRblDcSo9lGTYjO80RJiG1pIVxhm6qMdarkQbT8bDU1tccYFcH6NLvsmutqxE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589383016; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=svaXlTQ3XRmbJolGhQhGp6jiY6kXRusLaNYnNbSCCDs=; b=SfzMgeNHUToX0AWtnSk9vIPOfgdoruELPLP00aI26aGesoR0dA3bHhGYRHg2o2HYO7zheYL63fdDgaL1QkqR+c7dkCJDAs2YQw/ThG+y7OuKsJBu6cavqsmYYM412q7IST03QYbJ4VScpWCBnNgkmcHvhu+hSTuGi9v0klQ1BRY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589383016675468.4449268807532; Wed, 13 May 2020 08:16:56 -0700 (PDT) Received: from localhost ([::1]:36746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jYt7v-0003vB-9x for importer@patchew.org; Wed, 13 May 2020 11:16:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34130) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jYt3c-0004Vt-A6 for qemu-devel@nongnu.org; Wed, 13 May 2020 11:12:28 -0400 Received: from 14.mo7.mail-out.ovh.net ([178.33.251.19]:48359) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jYt3a-0005Tt-Q0 for qemu-devel@nongnu.org; Wed, 13 May 2020 11:12:27 -0400 Received: from player791.ha.ovh.net (unknown [10.108.35.211]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 96CE7163A36 for ; Wed, 13 May 2020 17:12:24 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player791.ha.ovh.net (Postfix) with ESMTPSA id 41FC11244BEA3; Wed, 13 May 2020 15:12:19 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Subject: [PATCH 8/9] ppc/pnv: Add model for POWER9 PHB5 PCIe Host bridge Date: Wed, 13 May 2020 17:11:08 +0200 Message-Id: <20200513151109.453530-9-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200513151109.453530-1-clg@kaod.org> References: <20200513151109.453530-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 1033576114966662118 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrleeggdekhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepgfeitedvfedugeehvdevjeduiefhieetffejteejueekhffggfevudegudegudfgnecukfhppedtrddtrddtrddtpdekvddrieegrddvhedtrddujedtnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepphhlrgihvghrjeeluddrhhgrrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehqvghmuhdquggvvhgvlhesnhhonhhgnhhurdhorhhg Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.33.251.19; envelope-from=clg@kaod.org; helo=14.mo7.mail-out.ovh.net X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/13 11:12:24 X-ACL-Warn: Detected OS = Linux 3.11 and newer X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" PHB4 and PHB5 are very similar. Use the PHB4 models with some minor adjustements in a subclass for P10. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/pci-host/pnv_phb4.h | 11 ++++ include/hw/ppc/pnv.h | 3 + include/hw/ppc/pnv_xscom.h | 6 ++ hw/pci-host/pnv_phb4_pec.c | 44 ++++++++++++++ hw/ppc/pnv.c | 101 +++++++++++++++++++++++++++++++++ 5 files changed, 165 insertions(+) diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index c882bfd0aa23..ea3810f74066 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -227,4 +227,15 @@ typedef struct PnvPhb4PecClass { int stk_compat_size; } PnvPhb4PecClass; =20 +/* + * POWER10 definitions + */ + +#define PNV_PHB5_VERSION 0x000000a500000001ull +#define PNV_PHB5_DEVICE_ID 0x0652 + +#define TYPE_PNV_PHB5_PEC "pnv-phb5-pec" +#define PNV_PHB5_PEC(obj) \ + OBJECT_CHECK(PnvPhb4PecState, (obj), TYPE_PNV_PHB5_PEC) + #endif /* PCI_HOST_PNV_PHB4_H */ diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 86bfa2107a8c..516229a51e7b 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -127,6 +127,9 @@ typedef struct Pnv10Chip { uint32_t nr_quads; PnvQuad *quads; =20 +#define PNV10_CHIP_MAX_PEC 2 + PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; + } Pnv10Chip; =20 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index f26c5217764d..433c7b878af4 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -139,6 +139,12 @@ typedef struct PnvXScomInterfaceClass { #define PNV10_XSCOM_XIVE2_BASE 0x2010800 #define PNV10_XSCOM_XIVE2_SIZE 0x400 =20 +#define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */ +#define PNV10_XSCOM_PEC_NEST_SIZE 0x100 + +#define PNV10_XSCOM_PEC_PCI_BASE 0x8010800 /* index goes upwards ... */ +#define PNV10_XSCOM_PEC_PCI_SIZE 0x200 + void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, uint64_t xscom_base, uint64_t xscom_size, diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 911d147ffd7d..869fd77b62cc 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -586,9 +586,53 @@ static const TypeInfo pnv_pec_stk_type_info =3D { } }; =20 +/* + * POWER10 definitions + */ + +static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec) +{ + return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index; +} + +static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec) +{ + /* index goes down ... */ + return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index; +} + +static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data) +{ + PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_CLASS(klass); + static const char compat[] =3D "ibm,power10-pbcq"; + static const char stk_compat[] =3D "ibm,power10-phb-stack"; + + pecc->xscom_nest_base =3D pnv_phb5_pec_xscom_nest_base; + pecc->xscom_pci_base =3D pnv_phb5_pec_xscom_pci_base; + pecc->xscom_nest_size =3D PNV10_XSCOM_PEC_NEST_SIZE; + pecc->xscom_pci_size =3D PNV10_XSCOM_PEC_PCI_SIZE; + pecc->compat =3D compat; + pecc->compat_size =3D sizeof(compat); + pecc->stk_compat =3D stk_compat; + pecc->stk_compat_size =3D sizeof(stk_compat); +} + +static const TypeInfo pnv_phb5_pec_type_info =3D { + .name =3D TYPE_PNV_PHB5_PEC, + .parent =3D TYPE_PNV_PHB4_PEC, + .instance_size =3D sizeof(PnvPhb4PecState), + .class_init =3D pnv_phb5_pec_class_init, + .class_size =3D sizeof(PnvPhb4PecClass), + .interfaces =3D (InterfaceInfo[]) { + { TYPE_PNV_XSCOM_INTERFACE }, + { } + } +}; + static void pnv_pec_register_types(void) { type_register_static(&pnv_pec_type_info); + type_register_static(&pnv_phb5_pec_type_info); type_register_static(&pnv_pec_stk_type_info); } =20 diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index fc751dd575d4..ac4bd2a17a9e 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -705,9 +705,17 @@ static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc= , uint32_t irq) static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) { Pnv10Chip *chip10 =3D PNV10_CHIP(chip); + int i, j; =20 pnv_xive2_pic_print_info(&chip10->xive, mon); pnv_psi_pic_print_info(&chip10->psi, mon); + + for (i =3D 0; i < PNV10_CHIP_MAX_PEC; i++) { + PnvPhb4PecState *pec =3D &chip10->pecs[i]; + for (j =3D 0; j < pec->num_stacks; j++) { + pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); + } + } } =20 static void pnv_init(MachineState *machine) @@ -1607,7 +1615,10 @@ static void pnv_chip_power9_class_init(ObjectClass *= klass, void *data) =20 static void pnv_chip_power10_instance_init(Object *obj) { + PnvChip *chip =3D PNV_CHIP(obj); Pnv10Chip *chip10 =3D PNV10_CHIP(obj); + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(obj); + int i; =20 object_initialize_child(obj, "xive", &chip10->xive, sizeof(chip10->xiv= e), TYPE_PNV_XIVE2, &error_abort, NULL); @@ -1619,6 +1630,17 @@ static void pnv_chip_power10_instance_init(Object *o= bj) TYPE_PNV10_LPC, &error_abort, NULL); object_initialize_child(obj, "occ", &chip10->occ, sizeof(chip10->occ), TYPE_PNV10_OCC, &error_abort, NULL); + + for (i =3D 0; i < PNV10_CHIP_MAX_PEC; i++) { + object_initialize_child(obj, "pec[*]", &chip10->pecs[i], + sizeof(chip10->pecs[i]), TYPE_PNV_PHB5_PEC, + &error_abort, NULL); + } + + /* + * Number of PHBs is the chip default + */ + chip->num_phbs =3D pcc->num_phbs; } =20 =20 @@ -1648,6 +1670,77 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip = *chip10, Error **errp) } } =20 +static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) +{ + Pnv10Chip *chip10 =3D PNV10_CHIP(chip); + Error *local_err =3D NULL; + int i, j; + int phb_id =3D 0; + + for (i =3D 0; i < PNV10_CHIP_MAX_PEC; i++) { + PnvPhb4PecState *pec =3D &chip10->pecs[i]; + PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec); + uint32_t pec_nest_base; + uint32_t pec_pci_base; + + object_property_set_int(OBJECT(pec), i, "index", &error_fatal); + /* + * PEC0 -> 3 stacks + * PEC1 -> 3 stacks + */ + object_property_set_int(OBJECT(pec), 3, "num-stacks", + &error_fatal); + object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id", + &error_fatal); + object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()), + "system-memory", &error_abort); + object_property_set_bool(OBJECT(pec), true, "realized", &local_err= ); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + pec_nest_base =3D pecc->xscom_nest_base(pec); + pec_pci_base =3D pecc->xscom_pci_base(pec); + + pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); + pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); + + for (j =3D 0; j < pec->num_stacks && phb_id < chip->num_phbs; + j++, phb_id++) { + PnvPhb4PecStack *stack =3D &pec->stacks[j]; + Object *obj =3D OBJECT(&stack->phb); + + object_property_set_int(obj, phb_id, "index", &error_fatal); + object_property_set_int(obj, chip->chip_id, "chip-id", + &error_fatal); + object_property_set_int(obj, PNV_PHB5_VERSION, "version", + &error_fatal); + object_property_set_int(obj, PNV_PHB5_DEVICE_ID, "device-id", + &error_fatal); + object_property_set_link(obj, OBJECT(stack), "stack", &error_a= bort); + object_property_set_bool(obj, true, "realized", &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + qdev_set_parent_bus(DEVICE(obj), sysbus_get_default()); + + /* Populate the XSCOM address space. */ + pnv_xscom_add_subregion(chip, + pec_nest_base + 0x40 * (stack->stack_no= + 1), + &stack->nest_regs_mr); + pnv_xscom_add_subregion(chip, + pec_pci_base + 0x40 * (stack->stack_no= + 1), + &stack->pci_regs_mr); + pnv_xscom_add_subregion(chip, + pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0= + + 0x40 * stack->stack_no, + &stack->phb_regs_mr); + } + } +} + static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); @@ -1737,6 +1830,13 @@ static void pnv_chip_power10_realize(DeviceState *de= v, Error **errp) } pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, &chip10->occ.xscom_regs); + + /* PHBs */ + pnv_chip_power10_phb_realize(chip, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } } =20 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) @@ -1763,6 +1863,7 @@ static void pnv_chip_power10_class_init(ObjectClass *= klass, void *data) k->xscom_core_base =3D pnv_chip_power10_xscom_core_base; k->xscom_pcba =3D pnv_chip_power10_xscom_pcba; dc->desc =3D "PowerNV Chip POWER10"; + k->num_phbs =3D 6; =20 device_class_set_parent_realize(dc, pnv_chip_power10_realize, &k->parent_realize); --=20 2.25.4