From nobody Fri Dec 19 04:33:02 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1589204469; cv=none; d=zohomail.com; s=zohoarc; b=PontO9suxxEzgg9vR++b/XH6iP0KXEJH59FB0JcbaUM7dV+gD+SgN2/ozJ9mzezREW2IOft6PiAideHQdiqu/qM2Qz6fS1QGsv1l3IbvL8Hm3n0xxBIOX7VMhfvwUfS3/aowvhHNqTcaqUMyDA0TLGjaxYyeBvp6PrmaxYXcAmY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589204469; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zAWAHddUEw4C2UEsSfPl55AqQD5kSZuypfZNPPCY+D0=; b=gI06gr9L6RJwx/KWWwl11kbBoB9TYV/LvG0iJa1QsnOHizyScYXmKAFTHIPCPNN/zYTms5IaGeNnL9HCVhG+5IC1UipgZ5j2VXr1oNMNNsLRHDcgwGTw81+gXS+3mmpZTjTs6AHXxQF97/Z/bGQDWuy3EqPhouBvCC/qrhB69fg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589204469899743.9429606706409; Mon, 11 May 2020 06:41:09 -0700 (PDT) Received: from localhost ([::1]:42148 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jY8g8-00072T-IB for importer@patchew.org; Mon, 11 May 2020 09:41:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49002) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jY8Zg-00022a-EZ for qemu-devel@nongnu.org; Mon, 11 May 2020 09:34:28 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:38143) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jY8Ze-00074I-Vv for qemu-devel@nongnu.org; Mon, 11 May 2020 09:34:28 -0400 Received: by mail-wm1-x32f.google.com with SMTP id g12so19266643wmh.3 for ; Mon, 11 May 2020 06:34:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m3sm2154818wrn.96.2020.05.11.06.34.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2020 06:34:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zAWAHddUEw4C2UEsSfPl55AqQD5kSZuypfZNPPCY+D0=; b=e2YW8y5DvyDy3CJtt5i2a9URGSSPcPGxrP+a6eVkOe3fvv4KEImYzvKKZ4UO6uoHJJ QwRXi0GOoVAcECn2/NjI6RVZYzAY5iaIxYOVFdw7buohwL7vcwsrcxFYTyHhMRNp8aTj Em4TN/IdOFtNPo5pVVB2253liCV5u39lLkpqlSqLRtdwj90h8KrFG01hSPuA0eNJHk9N vRWYnyOETccugy3LH3IT5IE6SwTOJmF184Cc6M+NxY9tbJJ1qRGPQTY7X27Rmy8+E5Lz iVycgdpf2YZ8YiaTcp94OKYvZ4tWClXl5ZgXBe3xlgM5CEdCrgJszCyPyZJ/Kz5XIfXW +86A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zAWAHddUEw4C2UEsSfPl55AqQD5kSZuypfZNPPCY+D0=; b=awwqGY/hhy4aUQbo0oXyVSzvoUGita6ddPOIeP0nHDplsJ77+4F/cgAS0NvoKKhKJ0 Hwbfq33wCZu84EIqbKah0BxCxblntAQPLw1IcTgRijM7VlGu20RKU77av0wPmalddtpV 0T3JUyNENNEGTbUONpgVtofwuuN3bfaB3Y52m8q+jknOurudmbFJEZ+dtvU2iHgWSDFi 9IjnqSBexJhFsRbhhmspAN67uzcIbvdSUwRUhgak0d/bNrnsedpviPk7CpCwK41Hwbq6 QvvLFe1HdEOs7vsvTEKNt7L2vTWPEGJfDiv/WXuLjI9VDY2rpURcpEocRLwE/ifNH2OF LDYA== X-Gm-Message-State: AGi0PuZNsVr4tb9UY4ZuPRz/LP78QjlO8fAUOijo9Rb+4xEUvQep00YM MJuA7u1fjJ4KgvwrW7LfbRTHKnHM1pn3kw== X-Google-Smtp-Source: APiQypIPihQaz3XN9cQClfu3aWaeJ9BhdbHg8e5ThXnw75eFs95gHkIva7AYsm41wuL/HxIL8lJKVA== X-Received: by 2002:a7b:c846:: with SMTP id c6mr1649543wml.62.1589204065090; Mon, 11 May 2020 06:34:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/34] target/arm: Drop manual handling of set/clear_helper_retaddr Date: Mon, 11 May 2020 14:33:46 +0100 Message-Id: <20200511133405.5275-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200511133405.5275-1-peter.maydell@linaro.org> References: <20200511133405.5275-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Since we converted back to cpu_*_data_ra, we do not need to do this ourselves. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200508154359.7494-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/sve_helper.c | 38 -------------------------------------- 1 file changed, 38 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 655bc9476f4..aad2c8c2371 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4133,12 +4133,6 @@ static intptr_t max_for_page(target_ulong base, intp= tr_t mem_off, return MIN(split, mem_max - mem_off) + mem_off; } =20 -#ifndef CONFIG_USER_ONLY -/* These are normally defined only for CONFIG_USER_ONLY in */ -static inline void set_helper_retaddr(uintptr_t ra) { } -static inline void clear_helper_retaddr(void) { } -#endif - /* * The result of tlb_vaddr_to_host for user-only is just g2h(x), * which is always non-null. Elide the useless test. @@ -4180,7 +4174,6 @@ static void sve_ld1_r(CPUARMState *env, void *vg, con= st target_ulong addr, return; } mem_off =3D reg_off >> diffsz; - set_helper_retaddr(retaddr); =20 /* * If the (remaining) load is entirely within a single page, then: @@ -4195,7 +4188,6 @@ static void sve_ld1_r(CPUARMState *env, void *vg, con= st target_ulong addr, if (test_host_page(host)) { mem_off =3D host_fn(vd, vg, host - mem_off, mem_off, mem_max); tcg_debug_assert(mem_off =3D=3D mem_max); - clear_helper_retaddr(); /* After having taken any fault, zero leading inactive element= s. */ swap_memzero(vd, reg_off); return; @@ -4246,7 +4238,6 @@ static void sve_ld1_r(CPUARMState *env, void *vg, con= st target_ulong addr, } #endif =20 - clear_helper_retaddr(); memcpy(vd, &scratch, reg_max); } =20 @@ -4306,7 +4297,6 @@ static void sve_ld2_r(CPUARMState *env, void *vg, tar= get_ulong addr, intptr_t i, oprsz =3D simd_oprsz(desc); ARMVectorReg scratch[2] =3D { }; =20 - set_helper_retaddr(ra); for (i =3D 0; i < oprsz; ) { uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { @@ -4318,7 +4308,6 @@ static void sve_ld2_r(CPUARMState *env, void *vg, tar= get_ulong addr, addr +=3D 2 * size; } while (i & 15); } - clear_helper_retaddr(); =20 /* Wait until all exceptions have been raised to write back. */ memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz); @@ -4333,7 +4322,6 @@ static void sve_ld3_r(CPUARMState *env, void *vg, tar= get_ulong addr, intptr_t i, oprsz =3D simd_oprsz(desc); ARMVectorReg scratch[3] =3D { }; =20 - set_helper_retaddr(ra); for (i =3D 0; i < oprsz; ) { uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { @@ -4346,7 +4334,6 @@ static void sve_ld3_r(CPUARMState *env, void *vg, tar= get_ulong addr, addr +=3D 3 * size; } while (i & 15); } - clear_helper_retaddr(); =20 /* Wait until all exceptions have been raised to write back. */ memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz); @@ -4362,7 +4349,6 @@ static void sve_ld4_r(CPUARMState *env, void *vg, tar= get_ulong addr, intptr_t i, oprsz =3D simd_oprsz(desc); ARMVectorReg scratch[4] =3D { }; =20 - set_helper_retaddr(ra); for (i =3D 0; i < oprsz; ) { uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { @@ -4376,7 +4362,6 @@ static void sve_ld4_r(CPUARMState *env, void *vg, tar= get_ulong addr, addr +=3D 4 * size; } while (i & 15); } - clear_helper_retaddr(); =20 /* Wait until all exceptions have been raised to write back. */ memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz); @@ -4483,7 +4468,6 @@ static void sve_ldff1_r(CPUARMState *env, void *vg, c= onst target_ulong addr, return; } mem_off =3D reg_off >> diffsz; - set_helper_retaddr(retaddr); =20 /* * If the (remaining) load is entirely within a single page, then: @@ -4498,7 +4482,6 @@ static void sve_ldff1_r(CPUARMState *env, void *vg, c= onst target_ulong addr, if (test_host_page(host)) { mem_off =3D host_fn(vd, vg, host - mem_off, mem_off, mem_max); tcg_debug_assert(mem_off =3D=3D mem_max); - clear_helper_retaddr(); /* After any fault, zero any leading inactive elements. */ swap_memzero(vd, reg_off); return; @@ -4541,7 +4524,6 @@ static void sve_ldff1_r(CPUARMState *env, void *vg, c= onst target_ulong addr, } #endif =20 - clear_helper_retaddr(); record_fault(env, reg_off, reg_max); } =20 @@ -4687,7 +4669,6 @@ static void sve_st1_r(CPUARMState *env, void *vg, tar= get_ulong addr, intptr_t i, oprsz =3D simd_oprsz(desc); void *vd =3D &env->vfp.zregs[rd]; =20 - set_helper_retaddr(ra); for (i =3D 0; i < oprsz; ) { uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { @@ -4698,7 +4679,6 @@ static void sve_st1_r(CPUARMState *env, void *vg, tar= get_ulong addr, addr +=3D msize; } while (i & 15); } - clear_helper_retaddr(); } =20 static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr, @@ -4711,7 +4691,6 @@ static void sve_st2_r(CPUARMState *env, void *vg, tar= get_ulong addr, void *d1 =3D &env->vfp.zregs[rd]; void *d2 =3D &env->vfp.zregs[(rd + 1) & 31]; =20 - set_helper_retaddr(ra); for (i =3D 0; i < oprsz; ) { uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { @@ -4723,7 +4702,6 @@ static void sve_st2_r(CPUARMState *env, void *vg, tar= get_ulong addr, addr +=3D 2 * msize; } while (i & 15); } - clear_helper_retaddr(); } =20 static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr, @@ -4737,7 +4715,6 @@ static void sve_st3_r(CPUARMState *env, void *vg, tar= get_ulong addr, void *d2 =3D &env->vfp.zregs[(rd + 1) & 31]; void *d3 =3D &env->vfp.zregs[(rd + 2) & 31]; =20 - set_helper_retaddr(ra); for (i =3D 0; i < oprsz; ) { uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { @@ -4750,7 +4727,6 @@ static void sve_st3_r(CPUARMState *env, void *vg, tar= get_ulong addr, addr +=3D 3 * msize; } while (i & 15); } - clear_helper_retaddr(); } =20 static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr, @@ -4765,7 +4741,6 @@ static void sve_st4_r(CPUARMState *env, void *vg, tar= get_ulong addr, void *d3 =3D &env->vfp.zregs[(rd + 2) & 31]; void *d4 =3D &env->vfp.zregs[(rd + 3) & 31]; =20 - set_helper_retaddr(ra); for (i =3D 0; i < oprsz; ) { uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { @@ -4779,7 +4754,6 @@ static void sve_st4_r(CPUARMState *env, void *vg, tar= get_ulong addr, addr +=3D 4 * msize; } while (i & 15); } - clear_helper_retaddr(); } =20 #define DO_STN_1(N, NAME, ESIZE) \ @@ -4875,7 +4849,6 @@ static void sve_ld1_zs(CPUARMState *env, void *vd, vo= id *vg, void *vm, intptr_t i, oprsz =3D simd_oprsz(desc); ARMVectorReg scratch =3D { }; =20 - set_helper_retaddr(ra); for (i =3D 0; i < oprsz; ) { uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { @@ -4886,7 +4859,6 @@ static void sve_ld1_zs(CPUARMState *env, void *vd, vo= id *vg, void *vm, i +=3D 4, pg >>=3D 4; } while (i & 15); } - clear_helper_retaddr(); =20 /* Wait until all exceptions have been raised to write back. */ memcpy(vd, &scratch, oprsz); @@ -4900,7 +4872,6 @@ static void sve_ld1_zd(CPUARMState *env, void *vd, vo= id *vg, void *vm, intptr_t i, oprsz =3D simd_oprsz(desc) / 8; ARMVectorReg scratch =3D { }; =20 - set_helper_retaddr(ra); for (i =3D 0; i < oprsz; i++) { uint8_t pg =3D *(uint8_t *)(vg + H1(i)); if (likely(pg & 1)) { @@ -4908,7 +4879,6 @@ static void sve_ld1_zd(CPUARMState *env, void *vd, vo= id *vg, void *vm, tlb_fn(env, &scratch, i * 8, base + (off << scale), ra); } } - clear_helper_retaddr(); =20 /* Wait until all exceptions have been raised to write back. */ memcpy(vd, &scratch, oprsz * 8); @@ -5080,13 +5050,11 @@ static inline void sve_ldff1_zs(CPUARMState *env, v= oid *vd, void *vg, void *vm, reg_off =3D find_next_active(vg, 0, reg_max, MO_32); if (likely(reg_off < reg_max)) { /* Perform one normal read, which will fault or not. */ - set_helper_retaddr(ra); addr =3D off_fn(vm, reg_off); addr =3D base + (addr << scale); tlb_fn(env, vd, reg_off, addr, ra); =20 /* The rest of the reads will be non-faulting. */ - clear_helper_retaddr(); } =20 /* After any fault, zero the leading predicated false elements. */ @@ -5122,13 +5090,11 @@ static inline void sve_ldff1_zd(CPUARMState *env, v= oid *vd, void *vg, void *vm, reg_off =3D find_next_active(vg, 0, reg_max, MO_64); if (likely(reg_off < reg_max)) { /* Perform one normal read, which will fault or not. */ - set_helper_retaddr(ra); addr =3D off_fn(vm, reg_off); addr =3D base + (addr << scale); tlb_fn(env, vd, reg_off, addr, ra); =20 /* The rest of the reads will be non-faulting. */ - clear_helper_retaddr(); } =20 /* After any fault, zero the leading predicated false elements. */ @@ -5240,7 +5206,6 @@ static void sve_st1_zs(CPUARMState *env, void *vd, vo= id *vg, void *vm, const int scale =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, = 2); intptr_t i, oprsz =3D simd_oprsz(desc); =20 - set_helper_retaddr(ra); for (i =3D 0; i < oprsz; ) { uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { @@ -5251,7 +5216,6 @@ static void sve_st1_zs(CPUARMState *env, void *vd, vo= id *vg, void *vm, i +=3D 4, pg >>=3D 4; } while (i & 15); } - clear_helper_retaddr(); } =20 static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm, @@ -5261,7 +5225,6 @@ static void sve_st1_zd(CPUARMState *env, void *vd, vo= id *vg, void *vm, const int scale =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, = 2); intptr_t i, oprsz =3D simd_oprsz(desc) / 8; =20 - set_helper_retaddr(ra); for (i =3D 0; i < oprsz; i++) { uint8_t pg =3D *(uint8_t *)(vg + H1(i)); if (likely(pg & 1)) { @@ -5269,7 +5232,6 @@ static void sve_st1_zd(CPUARMState *env, void *vd, vo= id *vg, void *vm, tlb_fn(env, vd, i * 8, base + (off << scale), ra); } } - clear_helper_retaddr(); } =20 #define DO_ST1_ZPZ_S(MEM, OFS) \ --=20 2.20.1