From nobody Mon Feb 9 16:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1589075076; cv=none; d=zohomail.com; s=zohoarc; b=M5z/lXEpk+sPwN7/yKoszymd6TYMZEGkHUquO6fkMRQ1asF13Hzto6GOJqRDnrBQYP6hUT7p03Bg7Q8uGUq6DB8Q9jeM07vXdeTJxZ6ZJq8o+hGe0hxvmjXRE7P74kv0Jft4yPyToTflqdYd4jJuB9ODsjEJukBmQ+IW2nyGoyU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589075076; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=+WSXt+3GRyE758ZJguBL8JMwtCGzyZ/25NFbuKrBe14=; b=QSHtxihMss4RYHQnNOz1PHryyRfjikohGWtobd0Y5SwslQN13DBv48lx3M2xhVk04QWVkMdi24A4RrMddnhh3F0g+OZtK7DRW25rYbcycur3kRA7VkGImxfj1E4qS9jCIZc/nizQ5zyd/TvbRVqIjX+YlJCSbazOnjYBUNcglDU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589075076570509.3329549662177; Sat, 9 May 2020 18:44:36 -0700 (PDT) Received: from localhost ([::1]:35726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jXb19-0000JS-Ag for importer@patchew.org; Sat, 09 May 2020 21:44:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jXayA-0003rN-LW for qemu-devel@nongnu.org; Sat, 09 May 2020 21:41:31 -0400 Received: from mga09.intel.com ([134.134.136.24]:59850) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jXay8-0006hs-IC for qemu-devel@nongnu.org; Sat, 09 May 2020 21:41:30 -0400 Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2020 18:41:22 -0700 Received: from unknown (HELO local-michael-cet-test.sh.intel.com) ([10.239.159.128]) by orsmga006.jf.intel.com with ESMTP; 09 May 2020 18:41:21 -0700 IronPort-SDR: 9EHYVJ1jEEVoCadK9dN91NZLlORhO99c1zQenOikJn+bgq0nIgKU5s8hk6HlUrAnrZigg5qVAE TE+bSMP1xmUA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False IronPort-SDR: 4vKevsnqgDQPWk+jAmYKdwa6wRzyRFbSAKMv8VhSoIE2bUuo5I8hK+E2YAV6jVTKrArRaLcljM 8lwpN2lJgu8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,373,1583222400"; d="scan'208";a="264783141" From: Yang Weijiang To: qemu-devel@nongnu.org, pbonzini@redhat.com Subject: [Qemu-devel][PATCH v5 4/4] x86/cpu: Add user space access interface for CET MSRs Date: Sun, 10 May 2020 09:42:50 +0800 Message-Id: <20200510014250.28111-5-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20200510014250.28111-1-weijiang.yang@intel.com> References: <20200510014250.28111-1-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.24; envelope-from=weijiang.yang@intel.com; helo=mga09.intel.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/09 21:41:17 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Added interface for CET MSR_IA32_{U,S}_CET, MSR_IA32_PL{0,1,2,3}_SSP, MSR_IA32_INTR_SSP_TBL and MSR_KVM_GUEST_SSP save/restore. Check if corresponding CET features are available before access the MSRs. Signed-off-by: Yang Weijiang --- target/i386/cpu.h | 18 +++++ target/i386/kvm.c | 73 +++++++++++++++++++ target/i386/machine.c | 161 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 252 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ed03cd1760..51577a04ca 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -480,6 +480,15 @@ typedef enum X86Seg { #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 #define MSR_IA32_VMX_VMFUNC 0x00000491 =20 +#define MSR_IA32_U_CET 0x6a0 +#define MSR_IA32_S_CET 0x6a2 +#define MSR_IA32_PL0_SSP 0x6a4 +#define MSR_IA32_PL1_SSP 0x6a5 +#define MSR_IA32_PL2_SSP 0x6a6 +#define MSR_IA32_PL3_SSP 0x6a7 +#define MSR_IA32_SSP_TBL 0x6a8 +#define MSR_KVM_GUEST_SSP 0x4b564d06 + #define XSTATE_FP_BIT 0 #define XSTATE_SSE_BIT 1 #define XSTATE_YMM_BIT 2 @@ -1567,6 +1576,15 @@ typedef struct CPUX86State { =20 uintptr_t retaddr; =20 + uint64_t u_cet; + uint64_t s_cet; + uint64_t pl0_ssp; + uint64_t pl1_ssp; + uint64_t pl2_ssp; + uint64_t pl3_ssp; + uint64_t ssp_tbl; + uint64_t guest_ssp; + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 4901c6dd74..0735981558 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -2979,6 +2979,31 @@ static int kvm_put_msrs(X86CPU *cpu, int level) } } =20 + if (((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) || + (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)) && + (env->features[FEAT_XSAVES_LO] & XSTATE_CET_U_MASK)) { + kvm_msr_entry_add(cpu, MSR_IA32_U_CET, env->u_cet); + kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, env->pl3_ssp); + } + + if (env->features[FEAT_XSAVES_LO] & XSTATE_CET_S_MASK) { + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) { + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, env->pl0_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, env->pl1_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, env->pl2_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_SSP_TBL, env->ssp_tbl); + } + + if (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT) { + kvm_msr_entry_add(cpu, MSR_IA32_S_CET, env->s_cet); + } + } + + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) && + (env->features[FEAT_XSAVES_LO] & (XSTATE_CET_U_MASK | + XSTATE_CET_S_MASK))) + kvm_msr_entry_add(cpu, MSR_KVM_GUEST_SSP, env->guest_ssp); + return kvm_buf_set_msrs(cpu); } =20 @@ -3295,6 +3320,30 @@ static int kvm_get_msrs(X86CPU *cpu) } } =20 + if (((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) || + (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)) && + (env->features[FEAT_XSAVES_LO] & XSTATE_CET_U_MASK)) { + kvm_msr_entry_add(cpu, MSR_IA32_U_CET, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, 0); + } + + if (env->features[FEAT_XSAVES_LO] & XSTATE_CET_S_MASK) { + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) { + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_SSP_TBL, 0); + } + + if (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT) { + kvm_msr_entry_add(cpu, MSR_IA32_S_CET, 0); + } + } + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) && + (env->features[FEAT_XSAVES_LO] & (XSTATE_CET_U_MASK | + XSTATE_CET_S_MASK))) + kvm_msr_entry_add(cpu, MSR_KVM_GUEST_SSP, 0); + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; @@ -3578,6 +3627,30 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] =3D msrs[i]= .data; break; + case MSR_IA32_U_CET: + env->u_cet =3D msrs[i].data; + break; + case MSR_IA32_S_CET: + env->s_cet =3D msrs[i].data; + break; + case MSR_IA32_PL0_SSP: + env->pl0_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL1_SSP: + env->pl1_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL2_SSP: + env->pl2_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL3_SSP: + env->pl3_ssp =3D msrs[i].data; + break; + case MSR_IA32_SSP_TBL: + env->ssp_tbl =3D msrs[i].data; + break; + case MSR_KVM_GUEST_SSP: + env->guest_ssp =3D msrs[i].data; + break; } } =20 diff --git a/target/i386/machine.c b/target/i386/machine.c index 0c96531a56..3e1d8b6eb9 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -962,6 +962,159 @@ static const VMStateDescription vmstate_umwait =3D { } }; =20 +static bool u_cet_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->u_cet !=3D 0; +} + +static const VMStateDescription vmstate_u_cet =3D { + .name =3D "cpu/u_cet", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D u_cet_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.u_cet, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool s_cet_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->s_cet !=3D 0; +} + +static const VMStateDescription vmstate_s_cet =3D { + .name =3D "cpu/s_cet", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D s_cet_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.s_cet, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool pl0_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->pl0_ssp !=3D 0; +} + +static const VMStateDescription vmstate_pl0_ssp =3D { + .name =3D "cpu/pl0_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pl0_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.pl0_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool pl1_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->pl1_ssp !=3D 0; +} + +static const VMStateDescription vmstate_pl1_ssp =3D { + .name =3D "cpu/pl1_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pl1_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.pl1_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool pl2_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->pl2_ssp !=3D 0; +} + +static const VMStateDescription vmstate_pl2_ssp =3D { + .name =3D "cpu/pl2_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pl2_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.pl2_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + + +static bool pl3_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->pl3_ssp !=3D 0; +} + +static const VMStateDescription vmstate_pl3_ssp =3D { + .name =3D "cpu/pl3_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pl3_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.pl3_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool ssp_tbl_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->ssp_tbl !=3D 0; +} + +static const VMStateDescription vmstate_ssp_tbl =3D { + .name =3D "cpu/ssp_tbl", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D ssp_tbl_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.ssp_tbl, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool guest_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->guest_ssp !=3D 0; +} + +static const VMStateDescription vmstate_guest_ssp =3D { + .name =3D "cpu/guest_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D guest_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.guest_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + #ifdef TARGET_X86_64 static bool pkru_needed(void *opaque) { @@ -1447,6 +1600,14 @@ VMStateDescription vmstate_x86_cpu =3D { &vmstate_nested_state, #endif &vmstate_msr_tsx_ctrl, + &vmstate_u_cet, + &vmstate_s_cet, + &vmstate_pl0_ssp, + &vmstate_pl1_ssp, + &vmstate_pl2_ssp, + &vmstate_pl3_ssp, + &vmstate_ssp_tbl, + &vmstate_guest_ssp, NULL } }; --=20 2.17.2