From nobody Mon Feb 9 12:24:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1589074954; cv=none; d=zohomail.com; s=zohoarc; b=XiYAMWVWqTKGMKHCzvl2dNDgvEY7f5lQtIfsKBNG602vd5ecprFm6rvEvOeiU4wnQqreMzTI4YqJxPpn84qmCX0f0D/1XQ3dmJzU/MVcR4b86SNHoOPfeDv0/bERA/jxP9FdbEwflEA3zJhKv7wj9ExC0KYe+hxL7CMw8LGgwjo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589074954; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=2VabBNblU3337V1upHf20ydfUsPzXyBMNSLHXKzumos=; b=PnS1do3YCM+OCc37jIZsC1r2SbNa8Rumcc+52Q2DrBn6+NaJYGV1SFqf9BJUjD3GIIM9msBibhh6c6l+KETIPds99fskgqXEcs7VRDr4mepTPxQmTceqxaWQzLMngRLRuSCl1KGsvgCqy5xmFJFRwxcEDgz9sizZUgF738PU3nE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1589074954577776.8270972173854; Sat, 9 May 2020 18:42:34 -0700 (PDT) Received: from localhost ([::1]:57374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jXazB-0005rL-2f for importer@patchew.org; Sat, 09 May 2020 21:42:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36698) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jXay8-0003nO-8g for qemu-devel@nongnu.org; Sat, 09 May 2020 21:41:28 -0400 Received: from mga09.intel.com ([134.134.136.24]:59850) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jXay6-0006hs-Im for qemu-devel@nongnu.org; Sat, 09 May 2020 21:41:27 -0400 Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2020 18:41:18 -0700 Received: from unknown (HELO local-michael-cet-test.sh.intel.com) ([10.239.159.128]) by orsmga006.jf.intel.com with ESMTP; 09 May 2020 18:41:17 -0700 IronPort-SDR: Jxyti4Q41eN8YU1ZXNwb067kdL9dLHNaOzd72/a1G/w1keHRVVUVkMpVl5v5YJRjE5vfIBK2g9 VKSZNJSJfLMg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False IronPort-SDR: AJS9Qroqc1PVnpajeL7JYlnbSd/7zEEZRNhBS4l+345dhhPihUI3Su0cl/c/i4dAoNbuoF5XS9 C+JNTKKDrEBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,373,1583222400"; d="scan'208";a="264783113" From: Yang Weijiang To: qemu-devel@nongnu.org, pbonzini@redhat.com Subject: [Qemu-devel][PATCH v5 1/4] x86/cpu: Add CET CPUID/XSAVES flags and data structures Date: Sun, 10 May 2020 09:42:47 +0800 Message-Id: <20200510014250.28111-2-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20200510014250.28111-1-weijiang.yang@intel.com> References: <20200510014250.28111-1-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.24; envelope-from=weijiang.yang@intel.com; helo=mga09.intel.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/09 21:41:17 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" CET feature SHSTK and IBT are enumerated via CPUID(EAX=3D0x7,0):ECX[bit 7] and EDX[bit 20] respectively. Two CET bits (bit 11 and 12) are defined in MSR_IA32_XSS to support XSAVES/XRSTORS. CPUID(EAX=3D0xd, 1):ECX[bit 11] and ECX[bit 12] correspond to CET states in user and supervisor mode respective= ly. Signed-off-by: Zhang Yi Signed-off-by: Yang Weijiang --- target/i386/cpu.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e818fc712a..ed03cd1760 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -489,6 +489,9 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_BIT 6 #define XSTATE_Hi16_ZMM_BIT 7 #define XSTATE_PKRU_BIT 9 +#define XSTATE_RESERVED_BIT 10 +#define XSTATE_CET_U_BIT 11 +#define XSTATE_CET_S_BIT 12 =20 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) @@ -499,6 +502,19 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) +#define XSTATE_RESERVED_MASK (1ULL << XSTATE_RESERVED_BIT) +#define XSTATE_CET_U_MASK (1ULL << XSTATE_CET_U_BIT) +#define XSTATE_CET_S_MASK (1ULL << XSTATE_CET_S_BIT) + +/* CPUID feature bits available in XCR0 */ +#define CPUID_XSTATE_USER_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \ + XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \ + XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK |= \ + XSTATE_ZMM_Hi256_MASK | \ + XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK) + +/* CPUID feature bits available in XSS */ +#define CPUID_XSTATE_KERNEL_MASK (XSTATE_CET_U_MASK) =20 /* CPUID feature words */ typedef enum FeatureWord { @@ -536,6 +552,8 @@ typedef enum FeatureWord { FEAT_VMX_EPT_VPID_CAPS, FEAT_VMX_BASIC, FEAT_VMX_VMFUNC, + FEAT_XSAVES_LO, /* CPUID[EAX=3D0xd,ECX=3D1].ECX */ + FEAT_XSAVES_HI, /* CPUID[EAX=3D0xd,ECX=3D1].EDX */ FEATURE_WORDS, } FeatureWord; =20 @@ -743,6 +761,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_WAITPKG (1U << 5) /* Additional AVX-512 Vector Byte Manipulation Instruction */ #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) +/* CET SHSTK feature */ +#define CPUID_7_0_ECX_CET_SHSTK (1U << 7) /* Galois Field New Instructions */ #define CPUID_7_0_ECX_GFNI (1U << 8) /* Vector AES Instructions */ @@ -770,6 +790,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) +/* CET IBT feature */ +#define CPUID_7_0_EDX_CET_IBT (1U << 20) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Single Thread Indirect Branch Predictors */ @@ -1260,6 +1282,19 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; =20 +/* Ext. save area 11: User mode CET state */ +typedef struct XSavesCETU { + uint64_t u_cet; + uint64_t user_ssp; +} XSavesCETU; + +/* Ext. save area 12: Supervisor mode CET state */ +typedef struct XSavesCETS { + uint64_t kernel_ssp; + uint64_t pl1_ssp; + uint64_t pl2_ssp; +} XSavesCETS; + typedef struct X86XSaveArea { X86LegacyXSaveArea legacy; X86XSaveHeader header; --=20 2.17.2