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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id o99sm2727662pjo.8.2020.05.08.08.44.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2020 08:44:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2NrE6foXFUL+vDhzqPi3FsUrqKV9Hi7b6uhKwfiWAO8=; b=qThkNysgvv0/1IFy+pWmlJZTAC565QVDItkGqIoYbBaM2gVPfHeJS/UHsRRRIfxCCg Etr5cfJIYeJ3tQY8cJfHhCXudo9lgNOWhPsiaPDGfBnKUZkLZuG3vBuifwm5NpeZirKS vzC8e74brDK46kS0K+bW3m76RU/pSmO5NhaKDBDnjtoGAPY7vfWGzjmjf0hcaIXk4Etf a7holUHZ82MLyGAXiYD+unQE6xjS/l8seWi1d/W/pJ/S53vx3+WIzXt6r07KeCS+6Ryd hWAjNyYU80QF5jI3LlrkG97tWIg1CaNx7/LmlFSrv12OeUIPTIGgSYHsBu9BxioCjqJA Z9og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2NrE6foXFUL+vDhzqPi3FsUrqKV9Hi7b6uhKwfiWAO8=; b=tBztZwL+qBOyN8WkjYA8Ry7lxqg52/C2t2qoE3ZKgqGqAFuKjHXZwjldaHL6zwNMaO uz5CzPjlluUjFRQ+RymXln+mA/P8kveAKh2sigTcgPZkuIO6opnQMHWCdh/wRHYvu+Wa jlhAQ7tFsEfgBf8a0zRYsyXq/2BHppc4hOs7LPvkl5W/RMhQm6ko9nUdftUGZ6pL8wNp 1uFrvtRf0EeIx+63XruY2yZUsr0YzWTCNqMOtrIMd3ucXrT06p+hODB6C27DaOPQXe7e y3lcGiII9W8NKzt5jZGcdHQQz3emAw8/i19xK4o8thZOPPMi2lcOYm4JCSN5i+Ejdg1r uFLQ== X-Gm-Message-State: AGi0PuZT0bilNCkGublMaOg2v8yncOtvazsU9lG6bpQgINnTG/4gSb70 6NarAzFbRmBFPEdbjNnuvGkQsBIhyb4= X-Google-Smtp-Source: APiQypJja2HeRXt2NPiClQfATSZXTYvLplldmKX62El93Tj9XckrnOFVGVuScQBLKdfScUM4zohwWQ== X-Received: by 2002:a17:90a:36a7:: with SMTP id t36mr6630249pjb.232.1588952668055; Fri, 08 May 2020 08:44:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 17/19] target/arm: Reuse sve_probe_page for scatter stores Date: Fri, 8 May 2020 08:43:57 -0700 Message-Id: <20200508154359.7494-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200508154359.7494-1-richard.henderson@linaro.org> References: <20200508154359.7494-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 182 ++++++++++++++++++++++++---------------- 1 file changed, 111 insertions(+), 71 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 1560129b08..ad7e10f1e7 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5413,94 +5413,134 @@ DO_LDFF1_ZPZ_D(dd_be, zd, MO_64) =20 /* Stores with a vector index. */ =20 -static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm, - target_ulong base, uint32_t desc, uintptr_t ra, - zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn) +static inline QEMU_ALWAYS_INLINE +void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, + target_ulong base, uint32_t desc, uintptr_t retaddr, + int esize, int msize, zreg_off_fn *off_fn, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) { const int scale =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, = 2); - intptr_t i, oprsz =3D simd_oprsz(desc); + const int mmu_idx =3D cpu_mmu_index(env, false); + const intptr_t reg_max =3D simd_oprsz(desc); + void *host[ARM_MAX_VQ * 4]; + intptr_t reg_off, i; + SVEHostPage info, info2; =20 - for (i =3D 0; i < oprsz; ) { - uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); + /* + * Probe all of the elements for host addresses and flags. + */ + i =3D reg_off =3D 0; + do { + uint64_t pg =3D vg[reg_off >> 6]; do { - if (likely(pg & 1)) { - target_ulong off =3D off_fn(vm, i); - tlb_fn(env, vd, i, base + (off << scale), ra); + target_ulong addr =3D base + (off_fn(vm, reg_off) << scale); + target_ulong in_page =3D -(addr | TARGET_PAGE_MASK); + + host[i] =3D NULL; + if (likely((pg >> (reg_off & 63)) & 1)) { + if (likely(in_page >=3D msize)) { + sve_probe_page(&info, false, env, addr, 0, MMU_DATA_ST= ORE, + mmu_idx, retaddr); + host[i] =3D info.host; + } else { + /* + * Element crosses the page boundary. + * Probe both pages, but do not record the host addres= s, + * so that we use the slow path. + */ + sve_probe_page(&info, false, env, addr, 0, + MMU_DATA_STORE, mmu_idx, retaddr); + sve_probe_page(&info2, false, env, addr + in_page, 0, + MMU_DATA_STORE, mmu_idx, retaddr); + info.flags |=3D info2.flags; + } + + if (unlikely(info.flags & TLB_WATCHPOINT)) { + cpu_check_watchpoint(env_cpu(env), addr, msize, + info.attrs, BP_MEM_WRITE, retaddr= ); + } + /* TODO: MTE check. */ } - i +=3D 4, pg >>=3D 4; - } while (i & 15); - } -} + i +=3D 1; + reg_off +=3D esize; + } while (reg_off & 63); + } while (reg_off < reg_max); =20 -static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm, - target_ulong base, uint32_t desc, uintptr_t ra, - zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn) -{ - const int scale =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, = 2); - intptr_t i, oprsz =3D simd_oprsz(desc) / 8; - - for (i =3D 0; i < oprsz; i++) { - uint8_t pg =3D *(uint8_t *)(vg + H1(i)); - if (likely(pg & 1)) { - target_ulong off =3D off_fn(vm, i * 8); - tlb_fn(env, vd, i * 8, base + (off << scale), ra); + /* + * Now that we have recognized all exceptions except SyncExternal + * (from TLB_MMIO), which we cannot avoid, perform all of the stores. + * + * Note for the common case of an element in RAM, not crossing a page + * boundary, we have stored the host address in host[]. This doubles + * as a first-level check against the predicate, since only enabled + * elements have non-null host addresses. + */ + i =3D reg_off =3D 0; + do { + void *h =3D host[i]; + if (likely(h !=3D NULL)) { + host_fn(vd, reg_off, h); + } else if ((vg[reg_off >> 6] >> (reg_off & 63)) & 1) { + target_ulong addr =3D base + (off_fn(vm, reg_off) << scale); + tlb_fn(env, vd, reg_off, addr, retaddr); } - } + i +=3D 1; + reg_off +=3D esize; + } while (reg_off < reg_max); } =20 -#define DO_ST1_ZPZ_S(MEM, OFS) \ -void QEMU_FLATTEN HELPER(sve_st##MEM##_##OFS) \ - (CPUARMState *env, void *vd, void *vg, void *vm, \ - target_ulong base, uint32_t desc) \ -{ \ - sve_st1_zs(env, vd, vg, vm, base, desc, GETPC(), \ - off_##OFS##_s, sve_st1##MEM##_tlb); \ +#define DO_ST1_ZPZ_S(MEM, OFS, MSZ) \ +void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, = \ + void *vm, target_ulong base, uint32_t des= c) \ +{ = \ + sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, = \ + off_##OFS##_s, sve_st1##MEM##_host, sve_st1##MEM##_tlb); = \ } =20 -#define DO_ST1_ZPZ_D(MEM, OFS) \ -void QEMU_FLATTEN HELPER(sve_st##MEM##_##OFS) \ - (CPUARMState *env, void *vd, void *vg, void *vm, \ - target_ulong base, uint32_t desc) \ -{ \ - sve_st1_zd(env, vd, vg, vm, base, desc, GETPC(), \ - off_##OFS##_d, sve_st1##MEM##_tlb); \ +#define DO_ST1_ZPZ_D(MEM, OFS, MSZ) \ +void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, = \ + void *vm, target_ulong base, uint32_t des= c) \ +{ = \ + sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, = \ + off_##OFS##_d, sve_st1##MEM##_host, sve_st1##MEM##_tlb); = \ } =20 -DO_ST1_ZPZ_S(bs, zsu) -DO_ST1_ZPZ_S(hs_le, zsu) -DO_ST1_ZPZ_S(hs_be, zsu) -DO_ST1_ZPZ_S(ss_le, zsu) -DO_ST1_ZPZ_S(ss_be, zsu) +DO_ST1_ZPZ_S(bs, zsu, MO_8) +DO_ST1_ZPZ_S(hs_le, zsu, MO_16) +DO_ST1_ZPZ_S(hs_be, zsu, MO_16) +DO_ST1_ZPZ_S(ss_le, zsu, MO_32) +DO_ST1_ZPZ_S(ss_be, zsu, MO_32) =20 -DO_ST1_ZPZ_S(bs, zss) -DO_ST1_ZPZ_S(hs_le, zss) -DO_ST1_ZPZ_S(hs_be, zss) -DO_ST1_ZPZ_S(ss_le, zss) -DO_ST1_ZPZ_S(ss_be, zss) +DO_ST1_ZPZ_S(bs, zss, MO_8) +DO_ST1_ZPZ_S(hs_le, zss, MO_16) +DO_ST1_ZPZ_S(hs_be, zss, MO_16) +DO_ST1_ZPZ_S(ss_le, zss, MO_32) +DO_ST1_ZPZ_S(ss_be, zss, MO_32) =20 -DO_ST1_ZPZ_D(bd, zsu) -DO_ST1_ZPZ_D(hd_le, zsu) -DO_ST1_ZPZ_D(hd_be, zsu) -DO_ST1_ZPZ_D(sd_le, zsu) -DO_ST1_ZPZ_D(sd_be, zsu) -DO_ST1_ZPZ_D(dd_le, zsu) -DO_ST1_ZPZ_D(dd_be, zsu) +DO_ST1_ZPZ_D(bd, zsu, MO_8) +DO_ST1_ZPZ_D(hd_le, zsu, MO_16) +DO_ST1_ZPZ_D(hd_be, zsu, MO_16) +DO_ST1_ZPZ_D(sd_le, zsu, MO_32) +DO_ST1_ZPZ_D(sd_be, zsu, MO_32) +DO_ST1_ZPZ_D(dd_le, zsu, MO_64) +DO_ST1_ZPZ_D(dd_be, zsu, MO_64) =20 -DO_ST1_ZPZ_D(bd, zss) -DO_ST1_ZPZ_D(hd_le, zss) -DO_ST1_ZPZ_D(hd_be, zss) -DO_ST1_ZPZ_D(sd_le, zss) -DO_ST1_ZPZ_D(sd_be, zss) -DO_ST1_ZPZ_D(dd_le, zss) -DO_ST1_ZPZ_D(dd_be, zss) +DO_ST1_ZPZ_D(bd, zss, MO_8) +DO_ST1_ZPZ_D(hd_le, zss, MO_16) +DO_ST1_ZPZ_D(hd_be, zss, MO_16) +DO_ST1_ZPZ_D(sd_le, zss, MO_32) +DO_ST1_ZPZ_D(sd_be, zss, MO_32) +DO_ST1_ZPZ_D(dd_le, zss, MO_64) +DO_ST1_ZPZ_D(dd_be, zss, MO_64) =20 -DO_ST1_ZPZ_D(bd, zd) -DO_ST1_ZPZ_D(hd_le, zd) -DO_ST1_ZPZ_D(hd_be, zd) -DO_ST1_ZPZ_D(sd_le, zd) -DO_ST1_ZPZ_D(sd_be, zd) -DO_ST1_ZPZ_D(dd_le, zd) -DO_ST1_ZPZ_D(dd_be, zd) +DO_ST1_ZPZ_D(bd, zd, MO_8) +DO_ST1_ZPZ_D(hd_le, zd, MO_16) +DO_ST1_ZPZ_D(hd_be, zd, MO_16) +DO_ST1_ZPZ_D(sd_le, zd, MO_32) +DO_ST1_ZPZ_D(sd_be, zd, MO_32) +DO_ST1_ZPZ_D(dd_le, zd, MO_64) +DO_ST1_ZPZ_D(dd_be, zd, MO_64) =20 #undef DO_ST1_ZPZ_S #undef DO_ST1_ZPZ_D --=20 2.20.1