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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id d13sm1557562pga.64.2020.05.08.08.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2020 08:10:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FEyxrWFoyeGNVThGA6JH36MoAeh6ACp73rWPvPfMc8w=; b=AwJP1jhsrvJnwHurTU5MisG9KS6+ZRuGR7c77zDBFNNRdlWtVI0AdwR3VncE+PjFif dJO593/YBrJA/A8hZB3+4oP9hblo376uInQVsXDZ/OBK5F5MR6temvXqaLuV5fLVCB6V HzjIAH3G+oVOwt7DxgHrW6FCghkpsYhKbYWGb4O7WV5Syl+vcJPadxfK4v+hprLE/ryP xYXkk0gMu8S17c0X8TJMSVdNq8ONebVqs6j8c/otqZIN0IDsZcPY5hq54ss6vkwR27yL 3e6BCEVBod4ezHsyusctTmfc9xO+qJLNCFHjeIycQ2qzBY32hhigtK2t1PKitCYmeCoR fesQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FEyxrWFoyeGNVThGA6JH36MoAeh6ACp73rWPvPfMc8w=; b=f+4SGolSD/rVagX5TQekTq5PTwyXzR7QsXmCYgl4laBslI3sj+uuvigj4cYcYrVJ/T 2kKXF8um5bJiOQ3MrtfK42pyJUwm76KJU7bY0jjQPylgIpsJN3XMbtug3Zt5ZJXyxXLq hgt7DcJJy4sgvwQzoxso8suC/SnGQKUX/8FAlbNMPbl/3+vahZyALM1+TcqhVnKXzzN5 kes5TtCRFAOPBSIqjpZzCp5MnB9UKRSe3qfn+nv8G8lpr/TLMLyE24L1b8kidhBMn2yz gXkcOysqMG/KoFjbK58eS5so1fNfN0/Efgev/MCl1lh01NBcwxMHs4OsjrgEqmKJXtIX GgvQ== X-Gm-Message-State: AGi0PubkeLPhODNdvyb/YN0d46KcDXthriCUZ+/oafdBQ9/VNZW5HO0n udIv5/7ZGMjAix22OZzIWI94uNGp6cM= X-Google-Smtp-Source: APiQypKmEMF5wsp9czDMEVjZeMUTPlECUQGnC2D9oBs4HWjcwjbxsHkkH14xmvvnGZ67FIQ6fzj22A== X-Received: by 2002:a65:5b84:: with SMTP id i4mr2645121pgr.263.1588950658476; Fri, 08 May 2020 08:10:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 01/10] tcg: Implement gvec support for rotate by immediate Date: Fri, 8 May 2020 08:10:46 -0700 Message-Id: <20200508151055.5832-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200508151055.5832-1-richard.henderson@linaro.org> References: <20200508151055.5832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) No host backend support yet, but the interfaces for rotli are in place. Canonicalize immediate rotate to the left, based on a survey of architectures, but provide both left and right shift interfaces to the translators. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 5 +++ include/tcg/tcg-op-gvec.h | 6 ++++ include/tcg/tcg-op.h | 2 ++ include/tcg/tcg-opc.h | 1 + include/tcg/tcg.h | 1 + tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + accel/tcg/tcg-runtime-gvec.c | 48 +++++++++++++++++++++++++ tcg/tcg-op-gvec.c | 68 ++++++++++++++++++++++++++++++++++++ tcg/tcg-op-vec.c | 12 +++++++ tcg/tcg.c | 2 ++ tcg/README | 3 +- 13 files changed, 150 insertions(+), 1 deletion(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 4fa61b49b4..cf10c8361e 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -259,6 +259,11 @@ DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void,= ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_3(gvec_rotl8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_rotl16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_rotl32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_rotl64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(gvec_shl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_shl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_shl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index cea6497341..1afc3ebf03 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -334,6 +334,10 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, u= int32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); =20 void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); @@ -388,5 +392,7 @@ void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int6= 4_t); void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); +void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); =20 #endif diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index e3399d6a5e..848d91ce74 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -999,6 +999,8 @@ void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_v= ec a, TCGv_vec b); void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); =20 void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 9288a04946..a6ab4a147f 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -248,6 +248,7 @@ DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not= _vec)) DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) +DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec)) =20 DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index c48bd76b0a..56bedbd03b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -182,6 +182,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_not_vec 0 #define TCG_TARGET_HAS_andc_vec 0 #define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index ca214f6909..225a597f84 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -133,6 +133,7 @@ typedef enum { #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 1 +#define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index bfb3f5f6e9..23aabde992 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -183,6 +183,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_not_vec 0 #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_abs_vec 1 +#define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 4fa21f0e71..e57b891aa5 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -161,6 +161,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec have_isa_3_00 #define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index ca449702e6..34b1030365 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -716,6 +716,54 @@ void HELPER(gvec_sar64i)(void *d, void *a, uint32_t de= sc) clear_high(d, oprsz, desc); } =20 +void HELPER(gvec_rotl8i)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + int shift =3D simd_data(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint8_t)) { + *(uint8_t *)(d + i) =3D rol8(*(uint8_t *)(a + i), shift); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl16i)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + int shift =3D simd_data(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint16_t)) { + *(uint16_t *)(d + i) =3D rol16(*(uint16_t *)(a + i), shift); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl32i)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + int shift =3D simd_data(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + *(uint32_t *)(d + i) =3D rol32(*(uint32_t *)(a + i), shift); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl64i)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + int shift =3D simd_data(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + *(uint64_t *)(d + i) =3D rol64(*(uint64_t *)(a + i), shift); + } + clear_high(d, oprsz, desc); +} + void HELPER(gvec_shl8v)(void *d, void *a, void *b, uint32_t desc) { intptr_t oprsz =3D simd_oprsz(desc); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 049a55e700..25300b1577 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2694,6 +2694,74 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs,= uint32_t aofs, } } =20 +void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) +{ + uint64_t mask =3D dup_const(MO_8, 0xff << c); + + tcg_gen_shli_i64(d, a, c); + tcg_gen_shri_i64(a, a, 8 - c); + tcg_gen_andi_i64(d, d, mask); + tcg_gen_andi_i64(a, a, ~mask); + tcg_gen_or_i64(d, d, a); +} + +void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) +{ + uint64_t mask =3D dup_const(MO_16, 0xffff << c); + + tcg_gen_shli_i64(d, a, c); + tcg_gen_shri_i64(a, a, 16 - c); + tcg_gen_andi_i64(d, d, mask); + tcg_gen_andi_i64(a, a, ~mask); + tcg_gen_or_i64(d, d, a); +} + +void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_rotli_vec, 0 }; + static const GVecGen2i g[4] =3D { + { .fni8 =3D tcg_gen_vec_rotl8i_i64, + .fniv =3D tcg_gen_rotli_vec, + .fno =3D gen_helper_gvec_rotl8i, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fni8 =3D tcg_gen_vec_rotl16i_i64, + .fniv =3D tcg_gen_rotli_vec, + .fno =3D gen_helper_gvec_rotl16i, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_rotli_i32, + .fniv =3D tcg_gen_rotli_vec, + .fno =3D gen_helper_gvec_rotl32i, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_rotli_i64, + .fniv =3D tcg_gen_rotli_vec, + .fno =3D gen_helper_gvec_rotl64i, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_debug_assert(shift >=3D 0 && shift < (8 << vece)); + if (shift =3D=3D 0) { + tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + } else { + tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); + } +} + +void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_debug_assert(vece <=3D MO_64); + tcg_debug_assert(shift >=3D 0 && shift < (8 << vece)); + tcg_gen_gvec_rotli(vece, dofs, aofs, -shift & ((8 << vece) - 1), + oprsz, maxsz); +} + /* * Specialized generation vector shifts by a non-constant scalar. */ diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index b6937e8d64..660ad9be88 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -545,6 +545,18 @@ void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, int64_t i) do_shifti(INDEX_op_sari_vec, vece, r, a, i); } =20 +void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) +{ + do_shifti(INDEX_op_rotli_vec, vece, r, a, i); +} + +void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) +{ + int bits =3D 8 << vece; + tcg_debug_assert(i >=3D 0 && i < bits); + do_shifti(INDEX_op_rotli_vec, vece, r, a, -i & (bits - 1)); +} + void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { diff --git a/tcg/tcg.c b/tcg/tcg.c index dd4b3d7684..d420a14eef 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1661,6 +1661,8 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: return have_vec && TCG_TARGET_HAS_shv_vec; + case INDEX_op_rotli_vec: + return have_vec && TCG_TARGET_HAS_roti_vec; case INDEX_op_ssadd_vec: case INDEX_op_usadd_vec: case INDEX_op_sssub_vec: diff --git a/tcg/README b/tcg/README index bfa2e4ed24..1e3e4654f4 100644 --- a/tcg/README +++ b/tcg/README @@ -605,10 +605,11 @@ E.g. VECL=3D1 -> 64 << 1 -> v128, and VECE=3D2 -> 1 <= < 2 -> i32. =20 * shri_vec v0, v1, i2 * sari_vec v0, v1, i2 +* rotli_vec v0, v1, i2 * shrs_vec v0, v1, s2 * sars_vec v0, v1, s2 =20 - Similarly for logical and arithmetic right shift. + Similarly for logical and arithmetic right shift, and left rotate. =20 * shlv_vec v0, v1, v2 =20 --=20 2.20.1 From nobody Sun May 19 15:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588950839; cv=none; d=zohomail.com; s=zohoarc; b=YyM1OD1Kd2Alu5C2ldcT7DOZl8J9PDiJfFQsvtWLMAEkA14/ZxOqP80oUgkT/qO2G3xBqJOOOjIXq8lmcw7C+BDrXHyME8M8WQ6Hu7XNmqNzvjJc67uKiHydAru9v3eJ7tjjkrK62m3jtZ/KJURknt//7UipcGPxjln1GY9Xjsk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588950839; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=L7KZRH5MhIg6dGlgPmbd2AYUCrU1CGrjk5/JTatPG/s=; b=F81wBhPXWx3vy4aBB2As1K+aULDqYLhxaieCrjAk1WHSc9BiaPG9VY597sEKTWuv7UIF9S3PbBMITBMYf0aNTfbjVciW6o7la7wvc823bD7drSuwch6YDeNWCJ83xjUOM7+jLCrFmEyuABYeSqrV/KNta9fwj6AVlXmTZ8tEkU0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588950839747165.2225713978038; Fri, 8 May 2020 08:13:59 -0700 (PDT) Received: from localhost ([::1]:46730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jX4hK-0006zn-7l for importer@patchew.org; Fri, 08 May 2020 11:13:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59968) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jX4eV-0002RX-9H for qemu-devel@nongnu.org; Fri, 08 May 2020 11:11:03 -0400 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:39197) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jX4eT-0003zb-PD for qemu-devel@nongnu.org; Fri, 08 May 2020 11:11:02 -0400 Received: by mail-pj1-x1041.google.com with SMTP id e6so4359778pjt.4 for ; Fri, 08 May 2020 08:11:01 -0700 (PDT) Received: from localhost.localdomain (174-21-149-226.tukw.qwest.net. [174.21.149.226]) by smtp.gmail.com with ESMTPSA id d13sm1557562pga.64.2020.05.08.08.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2020 08:10:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L7KZRH5MhIg6dGlgPmbd2AYUCrU1CGrjk5/JTatPG/s=; b=e1bdIxVmm1lfgdAg9VQxeCtUX8kaDAyVpCtbVdYoHj7TB6P3nFDz+1vOalvLiGuPul fsKDPu9d1ox2vB9p28Q/5YdAql7ma5979F0eLKK3looGmEZ64u2rjZG2hhibj6IPfG5C Y7ji4RmrdDnUDa8W8hO9FI6WMq9l6aQTg5IgJjprxerFs1tZEfaSo147rTk23tDCfKoG vlrvVMVChwXl3CjYeHaEQaKEdNnmvWY+ncaqsxIB/Td47OMCYXILgzKqNOhXBpmfB0+f js0fKI3Uayozu7RvwT1NMEnmn3tjYVpfBReIHTNuEQ7Da+ZPqQpkjntmSExylHq6utUz cJdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L7KZRH5MhIg6dGlgPmbd2AYUCrU1CGrjk5/JTatPG/s=; b=KWJcryJyOD3SogvyvPJhyD2CNAjmD7jqrdgdAYU9CP1YqzZyDYg20T54JUdURWqISA mU/JG3MxwSiGtxfH8L/Q8NK30rYFimjv8Hd6G136A1aUNf4bkVJVFBawD/QaKkwRTcdd N2z+nXCdzsDC+O2fGLVovSmEKfnMb8hgI/QTC/IadWlXh+Qn6W1iakKXUOa1orC/qJhm dHcM2RQvkCfWspaFAodcbS//lt8DsBBZWmDeAELsB6CCS1ZxHaHdmP0NhJgSqsj8HUbu VDwyxaEaK75pGucv0DuJ6RDjB3d8RfuNWQwASlIxqs61ME5O3tiHf81ZbfJSaRnYOWoR 1aHA== X-Gm-Message-State: AGi0PubXF1WscN8oVyF5zVPKoTqgYgv3zwak7TTEfkhFqABTpywa/my4 nyxYQIpd/XWBnOtyvx8xqarOxKDvrZs= X-Google-Smtp-Source: APiQypJS3gMr63NstB5JLAEnxPs4PMv32I+tslDhMpqUeql7u1r0EbTmC48Rsty7AuB9jZsF0zqQhg== X-Received: by 2002:a17:90a:8a06:: with SMTP id w6mr6867603pjn.191.1588950659616; Fri, 08 May 2020 08:10:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 02/10] tcg: Implement gvec support for rotate by vector Date: Fri, 8 May 2020 08:10:47 -0700 Message-Id: <20200508151055.5832-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200508151055.5832-1-richard.henderson@linaro.org> References: <20200508151055.5832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) No host backend support yet, but the interfaces for rotlv and rotrv are in place. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- v3: Drop the generic expansion from rot to shift; we can do better for each backend, and then this code becomes unused. --- accel/tcg/tcg-runtime.h | 10 +++ include/tcg/tcg-op-gvec.h | 4 ++ include/tcg/tcg-op.h | 2 + include/tcg/tcg-opc.h | 2 + include/tcg/tcg.h | 1 + tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + accel/tcg/tcg-runtime-gvec.c | 96 +++++++++++++++++++++++++++ tcg/tcg-op-gvec.c | 122 +++++++++++++++++++++++++++++++++++ tcg/tcg-op-vec.c | 10 +++ tcg/tcg.c | 3 + tcg/README | 4 +- 13 files changed, 256 insertions(+), 1 deletion(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index cf10c8361e..4eda24e63a 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -279,6 +279,16 @@ DEF_HELPER_FLAGS_4(gvec_sar16v, TCG_CALL_NO_RWG, void,= ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_sar32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_sar64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(gvec_rotl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotl64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_rotr8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotr16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotr32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotr64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index 1afc3ebf03..2d768f1160 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -356,6 +356,10 @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, u= int32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); =20 void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 848d91ce74..5523ee7810 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -1009,6 +1009,8 @@ void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv= _vec a, TCGv_i32 s); void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); =20 void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index a6ab4a147f..69f98d6523 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -257,6 +257,8 @@ DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sh= s_vec)) DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) +DEF(rotlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) +DEF(rotrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) =20 DEF(cmp_vec, 1, 2, 1, IMPLVEC) =20 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 56bedbd03b..b2cb30305c 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -183,6 +183,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_andc_vec 0 #define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 225a597f84..a5477bbc07 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -134,6 +134,7 @@ typedef enum { #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 23aabde992..4c806c97db 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -184,6 +184,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index e57b891aa5..7993422526 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -162,6 +162,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_neg_vec have_isa_3_00 #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 34b1030365..521da4a813 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -908,6 +908,102 @@ void HELPER(gvec_sar64v)(void *d, void *a, void *b, u= int32_t desc) clear_high(d, oprsz, desc); } =20 +void HELPER(gvec_rotl8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint8_t)) { + uint8_t sh =3D *(uint8_t *)(b + i) & 7; + *(uint8_t *)(d + i) =3D rol8(*(uint8_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint16_t)) { + uint8_t sh =3D *(uint16_t *)(b + i) & 15; + *(uint16_t *)(d + i) =3D rol16(*(uint16_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + uint8_t sh =3D *(uint32_t *)(b + i) & 31; + *(uint32_t *)(d + i) =3D rol32(*(uint32_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + uint8_t sh =3D *(uint64_t *)(b + i) & 63; + *(uint64_t *)(d + i) =3D rol64(*(uint64_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotr8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint8_t)) { + uint8_t sh =3D *(uint8_t *)(b + i) & 7; + *(uint8_t *)(d + i) =3D ror8(*(uint8_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotr16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint16_t)) { + uint8_t sh =3D *(uint16_t *)(b + i) & 15; + *(uint16_t *)(d + i) =3D ror16(*(uint16_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotr32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + uint8_t sh =3D *(uint32_t *)(b + i) & 31; + *(uint32_t *)(d + i) =3D ror32(*(uint32_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotr64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + uint8_t sh =3D *(uint64_t *)(b + i) & 63; + *(uint64_t *)(d + i) =3D ror64(*(uint64_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + #define DO_CMP1(NAME, TYPE, OP) = \ void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) = \ { = \ diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 25300b1577..2b71725883 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -3171,6 +3171,128 @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs= , uint32_t aofs, tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); } =20 +/* + * Similarly for rotates. + */ + +static void tcg_gen_rotlv_mod_vec(unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t =3D tcg_temp_new_vec_matching(d); + + tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); + tcg_gen_and_vec(vece, t, t, b); + tcg_gen_rotlv_vec(vece, d, a, t); + tcg_temp_free_vec(t); +} + +static void tcg_gen_rotl_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_andi_i32(t, b, 31); + tcg_gen_rotl_i32(d, a, t); + tcg_temp_free_i32(t); +} + +static void tcg_gen_rotl_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(t, b, 63); + tcg_gen_rotl_i64(d, a, t); + tcg_temp_free_i64(t); +} + +void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_rotlv_vec, 0 }; + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_rotlv_mod_vec, + .fno =3D gen_helper_gvec_rotl8v, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_rotlv_mod_vec, + .fno =3D gen_helper_gvec_rotl16v, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_rotl_mod_i32, + .fniv =3D tcg_gen_rotlv_mod_vec, + .fno =3D gen_helper_gvec_rotl32v, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_rotl_mod_i64, + .fniv =3D tcg_gen_rotlv_mod_vec, + .fno =3D gen_helper_gvec_rotl64v, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + +static void tcg_gen_rotrv_mod_vec(unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t =3D tcg_temp_new_vec_matching(d); + + tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); + tcg_gen_and_vec(vece, t, t, b); + tcg_gen_rotrv_vec(vece, d, a, t); + tcg_temp_free_vec(t); +} + +static void tcg_gen_rotr_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_andi_i32(t, b, 31); + tcg_gen_rotr_i32(d, a, t); + tcg_temp_free_i32(t); +} + +static void tcg_gen_rotr_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(t, b, 63); + tcg_gen_rotr_i64(d, a, t); + tcg_temp_free_i64(t); +} + +void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_rotrv_vec, 0 }; + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_rotrv_mod_vec, + .fno =3D gen_helper_gvec_rotr8v, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_rotrv_mod_vec, + .fno =3D gen_helper_gvec_rotr16v, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_rotr_mod_i32, + .fniv =3D tcg_gen_rotrv_mod_vec, + .fno =3D gen_helper_gvec_rotr32v, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_rotr_mod_i64, + .fniv =3D tcg_gen_rotrv_mod_vec, + .fno =3D gen_helper_gvec_rotr64v, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + /* Expand OPSZ bytes worth of three-operand operations using i32 elements.= */ static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, TCGCond cond) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 660ad9be88..488f9bd27b 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -696,6 +696,16 @@ void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_vec b) do_op3_nofail(vece, r, a, b, INDEX_op_sarv_vec); } =20 +void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3_nofail(vece, r, a, b, INDEX_op_rotlv_vec); +} + +void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3_nofail(vece, r, a, b, INDEX_op_rotrv_vec); +} + static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v) { diff --git a/tcg/tcg.c b/tcg/tcg.c index d420a14eef..01539afc48 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1663,6 +1663,9 @@ bool tcg_op_supported(TCGOpcode op) return have_vec && TCG_TARGET_HAS_shv_vec; case INDEX_op_rotli_vec: return have_vec && TCG_TARGET_HAS_roti_vec; + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + return have_vec && TCG_TARGET_HAS_rotv_vec; case INDEX_op_ssadd_vec: case INDEX_op_usadd_vec: case INDEX_op_sssub_vec: diff --git a/tcg/README b/tcg/README index 1e3e4654f4..a64f67809b 100644 --- a/tcg/README +++ b/tcg/README @@ -621,8 +621,10 @@ E.g. VECL=3D1 -> 64 << 1 -> v128, and VECE=3D2 -> 1 <<= 2 -> i32. =20 * shrv_vec v0, v1, v2 * sarv_vec v0, v1, v2 +* rotlv_vec v0, v1, v2 +* rotrv_vec v0, v1, v2 =20 - Similarly for logical and arithmetic right shift. + Similarly for logical and arithmetic right shift, and rotates. =20 * cmp_vec v0, v1, v2, cond =20 --=20 2.20.1 From nobody Sun May 19 15:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588950971; cv=none; d=zohomail.com; s=zohoarc; b=Y+sgHPj3vuQ0oC2O/K3tHIrFWWxKbaGTIG/PxC19kfFlT8CyU7YRoOwj7KH+NX3VsjR56ZqoRD+3N2F2fQWysMMU3MzUVObWh4/k7vaphnE5aGySDbdw9uahEpGDG2cmvxVYoB4nt0RzzLwaLR256mQWcpCCk+11WBl3GXxeh30= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588950971; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/K1ycY1z79VZy1TG8t7nnh9EG9pxzEbf4Elb16Ela3g=; b=nJCBBLHAg/hdZS3QM/3XKVuGGLiRhCHoS8W+6G3v9bkTBv9F+jOCjaZGXskRwClTq3GNqD0bQxzkOQ2Tb8ZVnKVZ6yFddgws2jj+Pmj3D/OHUqH+SnDWCtHwMiEdCbyRTJ6o7R1lDjUnZ+/THxEaB/RNiCuMcypig6e92ebqYTA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158895097101464.59784263969368; Fri, 8 May 2020 08:16:11 -0700 (PDT) Received: from localhost ([::1]:55414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jX4jR-0002BS-Kk for importer@patchew.org; Fri, 08 May 2020 11:16:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59974) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jX4eV-0002S0-Hd for qemu-devel@nongnu.org; Fri, 08 May 2020 11:11:03 -0400 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:51388) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jX4eU-00040i-FN for qemu-devel@nongnu.org; Fri, 08 May 2020 11:11:03 -0400 Received: by mail-pj1-x1041.google.com with SMTP id mq3so4390403pjb.1 for ; Fri, 08 May 2020 08:11:02 -0700 (PDT) Received: from localhost.localdomain (174-21-149-226.tukw.qwest.net. [174.21.149.226]) by smtp.gmail.com with ESMTPSA id d13sm1557562pga.64.2020.05.08.08.10.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2020 08:11:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/K1ycY1z79VZy1TG8t7nnh9EG9pxzEbf4Elb16Ela3g=; b=AE8E3+zNPcgfJoWKOALOSXXGsU2ya883IeASEzmfjiB7d7y9oT53m5aGyFk20VipUh DagXrJreD6sRv0uqtkfxsVNa/j4kHPWdsMGeij7VraSHl+ZHTYc2xjiRY1+Hb402LTeN jv+CrEITpe8s3E9O2iid5klqLQGtEnfAfOqusBMZsqQU9XgWpW8zDaurns3iQJTiMIs8 5pLoFmXYMlybI59/HgRJDXEMepM5SaV8P7PMlPNs7dGoGr2ripkgHEiXXwVCmFVR0EI7 5E4oa3cXSBxA/9hvDol6Z7dXjMS+uaH6iiaz5bEN3OPjlvjivR1suhK6Q/O4iH2/IdCX /fBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/K1ycY1z79VZy1TG8t7nnh9EG9pxzEbf4Elb16Ela3g=; b=UuRJh9/r/P4nl6ECGBbE+dges5EPlJw9v3KxRCcWK27ViBp+KEl2a8jfJzwCLEoiYg j6YrTr1PghIyyJZM4sjDE2tTxfrmBDFR5agyRonhBgobZGOCiEWxujORC/zRQwzFkifh FasFybhXCNF+yiTpZsF2Czyfq4seMawhYFbYDZa+KMEcaT5eYwyUqD6+3GohcjfKCWHR vzJrR9AApSAijUJ22g7pps6CgaxHaeRFgoyFcy1sZSrtcwrfOaLE9L3+oCkDNuFxKZFH h6KMw63PtDltL4BYkrlxKH4tpw0a70C8dBtR9RRCDq00ouykJb9DybGG8rCuG1DOrolV Q6iw== X-Gm-Message-State: AGi0PuZ6HjDsgEVFQZ0E+PtB7F7kvsuBxRseKZhB2IyIPa8i5I3leZ+N WWU66gIyxofKuENYHLT8mqHO2M46bII= X-Google-Smtp-Source: APiQypIFon/p3UT2dVOmmVq/8gtNhAXVxrrnBxe/ERQbY1X+u0wAd2MnBvobseg7EJCkj2/pvjj+tA== X-Received: by 2002:a17:90a:12c3:: with SMTP id b3mr6714772pjg.57.1588950660718; Fri, 08 May 2020 08:11:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 03/10] tcg: Remove expansion to shift by vector from do_shifts Date: Fri, 8 May 2020 08:10:48 -0700 Message-Id: <20200508151055.5832-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200508151055.5832-1-richard.henderson@linaro.org> References: <20200508151055.5832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We do not reflect this expansion in tcg_can_emit_vecop_list, so it is unused and unusable. However, we actually perform the same expansion in do_gvec_shifts, so it is also unneeded. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 35 +++++++++++------------------------ 1 file changed, 11 insertions(+), 24 deletions(-) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 488f9bd27b..fb1250fee6 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -707,7 +707,7 @@ void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_vec b) } =20 static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a, - TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v) + TCGv_i32 s, TCGOpcode opc) { TCGTemp *rt =3D tcgv_vec_temp(r); TCGTemp *at =3D tcgv_vec_temp(a); @@ -716,48 +716,35 @@ static void do_shifts(unsigned vece, TCGv_vec r, TCGv= _vec a, TCGArg ai =3D temp_arg(at); TCGArg si =3D temp_arg(st); TCGType type =3D rt->base_type; - const TCGOpcode *hold_list; int can; =20 tcg_debug_assert(at->base_type >=3D type); - tcg_assert_listed_vecop(opc_s); - hold_list =3D tcg_swap_vecop_list(NULL); - - can =3D tcg_can_emit_vec_op(opc_s, type, vece); + tcg_assert_listed_vecop(opc); + can =3D tcg_can_emit_vec_op(opc, type, vece); if (can > 0) { - vec_gen_3(opc_s, type, vece, ri, ai, si); + vec_gen_3(opc, type, vece, ri, ai, si); } else if (can < 0) { - tcg_expand_vec_op(opc_s, type, vece, ri, ai, si); + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); + tcg_expand_vec_op(opc, type, vece, ri, ai, si); + tcg_swap_vecop_list(hold_list); } else { - TCGv_vec vec_s =3D tcg_temp_new_vec(type); - - if (vece =3D=3D MO_64) { - TCGv_i64 s64 =3D tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(s64, s); - tcg_gen_dup_i64_vec(MO_64, vec_s, s64); - tcg_temp_free_i64(s64); - } else { - tcg_gen_dup_i32_vec(vece, vec_s, s); - } - do_op3_nofail(vece, r, a, vec_s, opc_v); - tcg_temp_free_vec(vec_s); + g_assert_not_reached(); } - tcg_swap_vecop_list(hold_list); } =20 void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) { - do_shifts(vece, r, a, b, INDEX_op_shls_vec, INDEX_op_shlv_vec); + do_shifts(vece, r, a, b, INDEX_op_shls_vec); } =20 void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) { - do_shifts(vece, r, a, b, INDEX_op_shrs_vec, INDEX_op_shrv_vec); + do_shifts(vece, r, a, b, INDEX_op_shrs_vec); } =20 void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) { - do_shifts(vece, r, a, b, INDEX_op_sars_vec, INDEX_op_sarv_vec); + do_shifts(vece, r, a, b, INDEX_op_sars_vec); } =20 void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, --=20 2.20.1 From nobody Sun May 19 15:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588950862; cv=none; d=zohomail.com; s=zohoarc; b=jQTIOiTDZvW+5LWlwP6qftVVG6+onUikuWxOSTm3RFLneeIWEtkQYGVY3kWhf6ytKa6quHIFWyBUMFmzzplwpNTSnirGmc0oMWwvyOc6JHXbfdGACis6lasVSG2XvPzP+4meUG5CMafLl8HNTxRvPIybnfOO8BuSNgETo8gYlFc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588950862; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3Fbt/6l9Hxl8kYjgwSTdv1G3b/885S3FgOMa21hXJs0=; b=OIsVOw7xavyp8zUv2i0giW3dSbUE1TOZF85vq9T654SBKHwfNfWGWvNgFWdClH3iPyw48MIvfuNjnU0QE36QgxHhTbhMvex8cUy2rit1GMiyVHSs62CUtH6Zabs246DFGYlQfb3y5Xbj8Uo+ulR9vdVm9x0M/1bMBb2dqvXEcKM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588950862596829.9461068973311; Fri, 8 May 2020 08:14:22 -0700 (PDT) Received: from localhost ([::1]:48602 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jX4hh-0007qB-62 for importer@patchew.org; Fri, 08 May 2020 11:14:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59984) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jX4eX-0002VT-0Z for qemu-devel@nongnu.org; Fri, 08 May 2020 11:11:05 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:34343) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jX4eV-00041H-SH for qemu-devel@nongnu.org; Fri, 08 May 2020 11:11:04 -0400 Received: by mail-pl1-x643.google.com with SMTP id s10so846822plr.1 for ; Fri, 08 May 2020 08:11:03 -0700 (PDT) Received: from localhost.localdomain (174-21-149-226.tukw.qwest.net. [174.21.149.226]) by smtp.gmail.com with ESMTPSA id d13sm1557562pga.64.2020.05.08.08.11.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2020 08:11:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3Fbt/6l9Hxl8kYjgwSTdv1G3b/885S3FgOMa21hXJs0=; b=bvBd1jTWJZvhI6T6AIajvlnijjUmGEc+vPUKY46GX59F5UFtkEU+VVfi6BvBUl+PdS XDbOq15pTaAMCAXwUEklCFtRIc64yRSmN/8aBbsj6IXtc/pc3+ucWfmj9YbRr7xgsXuj 7PdkIoB0dFY1Ttahrt4K2w0v4SCQcS25zq7vVyG5kjx5DH8U5bwWB/uFszXzzkNVoTl5 IUkXSOZxub0S5oqw7kNu2/yd3DQG5fv9jQSEUKe4AcBHuR5c4dADOA8Br48mgj0cOIVG u5cF/mOPmqYXGWgxnjoH2i8x9rEMTqcbTe2kADM10QTST4+qs0d+Xgbi6HNSke9VcYFc wRpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3Fbt/6l9Hxl8kYjgwSTdv1G3b/885S3FgOMa21hXJs0=; b=mcXtoVO51dieU/385tP/PDdPPBVNo6+8gym3DtsgwlDSMt/CAUH1bN5DQc8KWQdsGS otQg19ZUSswrcbqx2r86+AoGEXKWuUP5sU+TRKCRR4hXVH6wPtz59KL2WL1lCAkRHCrq qPb1nK1gAWKUYrCzAwKC4QvQh0aJ6f/nV38hwPLc2gNppQlxnsU6cUvZCnRowdDS8e+u QoWc7NXUlOyc8x2MVltGWD1nrX14DYdFx0wILB3EE4N+P9l2wfWJp3jkPdw4fNo1AnxM BaX0CwBmoyUlpje45Di7+v5ZjoLAxaF6sTQJaptm7p1cs7KEXnJWI49iGK0NwhtUdLeO szRg== X-Gm-Message-State: AGi0Pub6JcvgaCMQzouoE+SAeogtVGQlBpo0rqJPGRbhLc4vvE4ubJ6k txWacu2bC0t3dVxBOYqesMlHOx5cdUE= X-Google-Smtp-Source: APiQypJ7VEXDDuIpH7eHX9vNODiY4/CqmyEDW7tXdwOuVZTqT4t6mJdPpvF5tTjjBp/uEF2KsROWlQ== X-Received: by 2002:a17:90a:37ea:: with SMTP id v97mr6915700pjb.206.1588950661983; Fri, 08 May 2020 08:11:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 04/10] tcg: Implement gvec support for rotate by scalar Date: Fri, 8 May 2020 08:10:49 -0700 Message-Id: <20200508151055.5832-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200508151055.5832-1-richard.henderson@linaro.org> References: <20200508151055.5832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) No host backend support yet, but the interfaces for rotls are in place. Only implement left-rotate for now, as the only known use of vector rotate by scalar is s390x, so any right-rotate would be unused and untestable. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 2 ++ include/tcg/tcg-op.h | 1 + include/tcg/tcg-opc.h | 1 + include/tcg/tcg.h | 1 + tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/tcg-op-gvec.c | 22 ++++++++++++++++++++++ tcg/tcg-op-vec.c | 5 +++++ tcg/tcg.c | 2 ++ 10 files changed, 37 insertions(+) diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index 2d768f1160..c69a7de984 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -345,6 +345,8 @@ void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, ui= nt32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); =20 /* * Perform vector shift by vector element, modulo the element size. diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 5523ee7810..5abf17fecc 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -1005,6 +1005,7 @@ void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCG= v_vec a, int64_t i); void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); =20 void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 69f98d6523..e3929b80d2 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -253,6 +253,7 @@ DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_r= oti_vec)) DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) +DEF(rotls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rots_vec)) =20 DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index b2cb30305c..380014ed80 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -183,6 +183,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_andc_vec 0 #define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index a5477bbc07..9bc2a5ecbe 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -134,6 +134,7 @@ typedef enum { #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 4c806c97db..99ac1e3958 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -184,6 +184,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 7993422526..4a17aebc5a 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -162,6 +162,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_neg_vec have_isa_3_00 #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 2b71725883..3707c0effb 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2976,6 +2976,28 @@ void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs,= uint32_t aofs, do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); } =20 +void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen2sh g =3D { + .fni4 =3D tcg_gen_rotl_i32, + .fni8 =3D tcg_gen_rotl_i64, + .fniv_s =3D tcg_gen_rotls_vec, + .fniv_v =3D tcg_gen_rotlv_vec, + .fno =3D { + gen_helper_gvec_rotl8i, + gen_helper_gvec_rotl16i, + gen_helper_gvec_rotl32i, + gen_helper_gvec_rotl64i, + }, + .s_list =3D { INDEX_op_rotls_vec, 0 }, + .v_list =3D { INDEX_op_rotlv_vec, 0 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); +} + /* * Expand D =3D A << (B % element bits) * diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index fb1250fee6..f784517d84 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -747,6 +747,11 @@ void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_i32 b) do_shifts(vece, r, a, b, INDEX_op_sars_vec); } =20 +void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s) +{ + do_shifts(vece, r, a, s, INDEX_op_rotls_vec); +} + void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b, TCGv_vec c) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 01539afc48..aa13158999 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1663,6 +1663,8 @@ bool tcg_op_supported(TCGOpcode op) return have_vec && TCG_TARGET_HAS_shv_vec; case INDEX_op_rotli_vec: return have_vec && TCG_TARGET_HAS_roti_vec; + case INDEX_op_rotls_vec: + return have_vec && TCG_TARGET_HAS_rots_vec; case INDEX_op_rotlv_vec: case INDEX_op_rotrv_vec: return have_vec && TCG_TARGET_HAS_rotv_vec; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For immediates, we must continue the special casing of 8-bit elements. The other element sizes and shift types are trivially implemented with shifts. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 116 ++++++++++++++++++++++++++++++++------ 1 file changed, 100 insertions(+), 16 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index ec083bddcf..ae0228238b 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -3233,6 +3233,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_shls_vec: case INDEX_op_shrs_vec: case INDEX_op_sars_vec: + case INDEX_op_rotls_vec: case INDEX_op_cmp_vec: case INDEX_op_x86_shufps_vec: case INDEX_op_x86_blend_vec: @@ -3271,6 +3272,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_xor_vec: case INDEX_op_andc_vec: return 1; + case INDEX_op_rotli_vec: case INDEX_op_cmp_vec: case INDEX_op_cmpsel_vec: return -1; @@ -3297,12 +3299,17 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type= , unsigned vece) return vece >=3D MO_16; case INDEX_op_sars_vec: return vece >=3D MO_16 && vece <=3D MO_32; + case INDEX_op_rotls_vec: + return vece >=3D MO_16 ? -1 : 0; =20 case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: return have_avx2 && vece >=3D MO_32; case INDEX_op_sarv_vec: return have_avx2 && vece =3D=3D MO_32; + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + return have_avx2 && vece >=3D MO_32 ? -1 : 0; =20 case INDEX_op_mul_vec: if (vece =3D=3D MO_8) { @@ -3331,7 +3338,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) } } =20 -static void expand_vec_shi(TCGType type, unsigned vece, bool shr, +static void expand_vec_shi(TCGType type, unsigned vece, TCGOpcode opc, TCGv_vec v0, TCGv_vec v1, TCGArg imm) { TCGv_vec t1, t2; @@ -3341,26 +3348,31 @@ static void expand_vec_shi(TCGType type, unsigned v= ece, bool shr, t1 =3D tcg_temp_new_vec(type); t2 =3D tcg_temp_new_vec(type); =20 - /* Unpack to W, shift, and repack. Tricky bits: - (1) Use punpck*bw x,x to produce DDCCBBAA, - i.e. duplicate in other half of the 16-bit lane. - (2) For right-shift, add 8 so that the high half of - the lane becomes zero. For left-shift, we must - shift up and down again. - (3) Step 2 leaves high half zero such that PACKUSWB - (pack with unsigned saturation) does not modify - the quantity. */ + /* + * Unpack to W, shift, and repack. Tricky bits: + * (1) Use punpck*bw x,x to produce DDCCBBAA, + * i.e. duplicate in other half of the 16-bit lane. + * (2) For right-shift, add 8 so that the high half of the lane + * becomes zero. For left-shift, and left-rotate, we must + * shift up and down again. + * (3) Step 2 leaves high half zero such that PACKUSWB + * (pack with unsigned saturation) does not modify + * the quantity. + */ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); =20 - if (shr) { - tcg_gen_shri_vec(MO_16, t1, t1, imm + 8); - tcg_gen_shri_vec(MO_16, t2, t2, imm + 8); + if (opc !=3D INDEX_op_rotli_vec) { + imm +=3D 8; + } + if (opc =3D=3D INDEX_op_shri_vec) { + tcg_gen_shri_vec(MO_16, t1, t1, imm); + tcg_gen_shri_vec(MO_16, t2, t2, imm); } else { - tcg_gen_shli_vec(MO_16, t1, t1, imm + 8); - tcg_gen_shli_vec(MO_16, t2, t2, imm + 8); + tcg_gen_shli_vec(MO_16, t1, t1, imm); + tcg_gen_shli_vec(MO_16, t2, t2, imm); tcg_gen_shri_vec(MO_16, t1, t1, 8); tcg_gen_shri_vec(MO_16, t2, t2, 8); } @@ -3427,6 +3439,61 @@ static void expand_vec_sari(TCGType type, unsigned v= ece, } } =20 +static void expand_vec_rotli(TCGType type, unsigned vece, + TCGv_vec v0, TCGv_vec v1, TCGArg imm) +{ + TCGv_vec t; + + if (vece =3D=3D MO_8) { + expand_vec_shi(type, vece, INDEX_op_rotli_vec, v0, v1, imm); + return; + } + + t =3D tcg_temp_new_vec(type); + tcg_gen_shli_vec(vece, t, v1, imm); + tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm); + tcg_gen_or_vec(vece, v0, v0, t); + tcg_temp_free_vec(t); +} + +static void expand_vec_rotls(TCGType type, unsigned vece, + TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh) +{ + TCGv_i32 rsh; + TCGv_vec t; + + tcg_debug_assert(vece !=3D MO_8); + + t =3D tcg_temp_new_vec(type); + rsh =3D tcg_temp_new_i32(); + + tcg_gen_neg_i32(rsh, lsh); + tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1); + tcg_gen_shls_vec(vece, t, v1, lsh); + tcg_gen_shrs_vec(vece, v0, v1, rsh); + tcg_gen_or_vec(vece, v0, v0, t); + tcg_temp_free_vec(t); + tcg_temp_free_i32(rsh); +} + +static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec sh, bool right) +{ + TCGv_vec t =3D tcg_temp_new_vec(type); + + tcg_gen_dupi_vec(vece, t, 8 << vece); + tcg_gen_sub_vec(vece, t, t, sh); + if (right) { + tcg_gen_shlv_vec(vece, t, v1, t); + tcg_gen_shrv_vec(vece, v0, v1, sh); + } else { + tcg_gen_shrv_vec(vece, t, v1, t); + tcg_gen_shlv_vec(vece, v0, v1, sh); + } + tcg_gen_or_vec(vece, v0, v0, t); + tcg_temp_free_vec(t); +} + static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) { @@ -3636,13 +3703,30 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, switch (opc) { case INDEX_op_shli_vec: case INDEX_op_shri_vec: - expand_vec_shi(type, vece, opc =3D=3D INDEX_op_shri_vec, v0, v1, a= 2); + expand_vec_shi(type, vece, opc, v0, v1, a2); break; =20 case INDEX_op_sari_vec: expand_vec_sari(type, vece, v0, v1, a2); break; =20 + case INDEX_op_rotli_vec: + expand_vec_rotli(type, vece, v0, v1, a2); + break; + + case INDEX_op_rotls_vec: + expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2))); + break; + + case INDEX_op_rotlv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + expand_vec_rotv(type, vece, v0, v1, v2, false); + break; + case INDEX_op_rotrv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + expand_vec_rotv(type, vece, v0, v1, v2, true); + break; + case INDEX_op_mul_vec: v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_mul(type, vece, v0, v1, v2); --=20 2.20.1 From nobody Sun May 19 15:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588950999; cv=none; d=zohomail.com; s=zohoarc; b=W+u0tne8vZE0SOdVxathhO/zqbi9q7Fj4s0hJ+K2JoprxjxGn/gFrmZ3oPfwqArbgGtck9KWimgP8B4I+bt9VUfBVr3WaSU6UHnGacEcjj++qwkbbmyVGm1X+qnmLUqeG+0vRwsfiXjy38XzHyO6Wr8JlwAbSyuxG1jK44xBVBE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588950999; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id d13sm1557562pga.64.2020.05.08.08.11.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2020 08:11:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ttVl6jOSw63HNdDDKNW/a5GZXc6b0Nu+B39Nrdhmmqk=; b=nIhHJCebSLcm7z5/g0cfooKLlp3XHQGAgAk/W5Lhq234u8TQgs0XdPtdpCekanGBD3 2rpXjBSi6nCtenXzcF6xvMsC4xkJw2kOpYjYPut8IziLgTcfsJv+9V8xCFCl/J26CuG/ ikwBojyyiBUE+Kqb4BHO9OMV+T24VHkIOQvd0i/PojvJ2UOjpq9+fJ3c4SPkn68emmoi c6OPf+vmtwdsYaCTteiOVL8TcPh3gzFsLjbdkvdYCLthsmbtNV2g6sVnmbPB7NA5LjIa lKgc4UMUtF2WsG+WSFUGjEp0o4hCstXxvh1XS7yFkmswomnaXs+wdhZi24UYGBGKKvJ6 MeLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ttVl6jOSw63HNdDDKNW/a5GZXc6b0Nu+B39Nrdhmmqk=; b=kFH2a8LR2Ne2pGq3O3zQjWAmKHdUSUTFSmCH5ex5by9NTuBDhqVCoBSrDlHVcQrYgp EE5DnTzE3zzlnSzyhIdQWbn69eGtMa5NrXG2rLw3IDfRGLF8QiaHuJXZ1ldfwv9w+QyB ZX0RjxiIu3s/KuOwrqNd38BSOjl+G6XAhl2pqbdgmz1HQyDmq8QhDwo3G5NlrY0IAIYb O6/5MF2SYgzs0jDrZ5kvgpk+ri8wO+LHlw/aN3oMVM5wqNmbVLVzX7Br8x3hAJukQSW3 GW6IXFJ59U5+PYNlqoQmqDpI4GXBPDexZu8s9pJfry2M1owuwLzjtfaxiZj1suTwwRv5 +WLw== X-Gm-Message-State: AGi0PuZn3xL6+CRVHMna3D5iP7ofmdQG4LFLHGIMnpdGHRZhHZoEg6O4 zQC5cta9vSKx3OYFoHHW2E8g8LIfo9w= X-Google-Smtp-Source: APiQypI7GvTfzGY+2a6SLmvulF+U/peuJmsgHimN+Yz+ngo9IPYLrEuWiHF3VDluqOm3WNmA+RP1mw== X-Received: by 2002:a17:90a:258a:: with SMTP id k10mr6510947pje.231.1588950664455; Fri, 08 May 2020 08:11:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 06/10] tcg/aarch64: Implement INDEX_op_rotl{i,v}_vec Date: Fri, 8 May 2020 08:10:51 -0700 Message-Id: <20200508151055.5832-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200508151055.5832-1-richard.henderson@linaro.org> References: <20200508151055.5832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For immediate rotate , we can implement this in two instructions, using SLI. For variable rotate, the oddness of aarch64 right-shift- as-negative-left-shift means a backend-specific expansion works best. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.opc.h | 1 + tcg/aarch64/tcg-target.inc.c | 53 ++++++++++++++++++++++++++++++++++-- 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target.opc.h index 26bfd9c460..bce30accd9 100644 --- a/tcg/aarch64/tcg-target.opc.h +++ b/tcg/aarch64/tcg-target.opc.h @@ -12,3 +12,4 @@ */ =20 DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC) +DEF(aa64_sli_vec, 1, 2, 1, IMPLVEC) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 843fd0ca69..760b0e742d 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -557,6 +557,7 @@ typedef enum { I3614_SSHR =3D 0x0f000400, I3614_SSRA =3D 0x0f001400, I3614_SHL =3D 0x0f005400, + I3614_SLI =3D 0x2f005400, I3614_USHR =3D 0x2f000400, I3614_USRA =3D 0x2f001400, =20 @@ -2411,6 +2412,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_sari_vec: tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2); break; + case INDEX_op_aa64_sli_vec: + tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece)); + break; case INDEX_op_shlv_vec: tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2); break; @@ -2498,8 +2502,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_shlv_vec: case INDEX_op_bitsel_vec: return 1; + case INDEX_op_rotli_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: return -1; case INDEX_op_mul_vec: case INDEX_op_smax_vec: @@ -2517,14 +2524,24 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2, t1; + TCGv_vec v0, v1, v2, t1, t2; + TCGArg a2; =20 va_start(va, a0); v0 =3D temp_tcgv_vec(arg_temp(a0)); v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - v2 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + a2 =3D va_arg(va, TCGArg); + v2 =3D temp_tcgv_vec(arg_temp(a2)); =20 switch (opc) { + case INDEX_op_rotli_vec: + t1 =3D tcg_temp_new_vec(type); + tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); + vec_gen_4(INDEX_op_aa64_sli_vec, type, vece, + tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2= ); + tcg_temp_free_vec(t1); + break; + case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: /* Right shifts are negative left shifts for AArch64. */ @@ -2537,6 +2554,35 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, tcg_temp_free_vec(t1); break; =20 + case INDEX_op_rotlv_vec: + t1 =3D tcg_temp_new_vec(type); + tcg_gen_dupi_vec(vece, t1, 8 << vece); + tcg_gen_sub_vec(vece, t1, v2, t1); + /* Right shifts are negative left shifts for AArch64. */ + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_or_vec(vece, v0, v0, t1); + tcg_temp_free_vec(t1); + break; + + case INDEX_op_rotrv_vec: + t1 =3D tcg_temp_new_vec(type); + t2 =3D tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t1, v2); + tcg_gen_dupi_vec(vece, t2, 8 << vece); + tcg_gen_add_vec(vece, t2, t1, t2); + /* Right shifts are negative left shifts for AArch64. */ + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(t2)); + tcg_gen_or_vec(vece, v0, t1, t2); + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); + break; + default: g_assert_not_reached(); } @@ -2557,6 +2603,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef lZ_l =3D { .args_ct_str =3D { "lZ", "l" } = }; static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; static const TCGTargetOpDef w_w_w =3D { .args_ct_str =3D { "w", "w", "= w" } }; + static const TCGTargetOpDef w_0_w =3D { .args_ct_str =3D { "w", "0", "= w" } }; static const TCGTargetOpDef w_w_wO =3D { .args_ct_str =3D { "w", "w", = "wO" } }; static const TCGTargetOpDef w_w_wN =3D { .args_ct_str =3D { "w", "w", = "wN" } }; static const TCGTargetOpDef w_w_wZ =3D { .args_ct_str =3D { "w", "w", = "wZ" } }; @@ -2751,6 +2798,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &w_w_wZ; case INDEX_op_bitsel_vec: return &w_w_w_w; + case INDEX_op_aa64_sli_vec: + return &w_0_w; =20 default: return NULL; --=20 2.20.1 From nobody Sun May 19 15:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588951006; cv=none; d=zohomail.com; s=zohoarc; b=iZm7x8tA0iVPUlX33Rv8D1LNZ262Ro6mAejxdVg5f2rPSXUgU55ksnfEnYvCJ4BhhnPkhibOELoHc69m5b5hjI4J2PPkaKyfXghvA3YOwV0dUbLjl8AKPdGGSuM0Ik6gziK+6/G3ju2F0JNEhdthCfTXzFhqbfZtU0f12VBfktQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588951006; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id d13sm1557562pga.64.2020.05.08.08.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2020 08:11:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZVy+4Yk59DJUIurfX6sGOQIwnEqBpAUirNM+prnI7JM=; b=rXLeJGQDuu10n7xSRFA8oexKi6TzuV5z73v2KHiVmeVfvx/8vWLlcWspRvFOLIKhYf Brkcfj3cuuvCF6YCkguXaAtN2+YtCzMyrdJ56JAYdKJHMdfuqCYCL/eHkVh3Cs+ZIrpJ XeBUXg2l31h+cig42Moge5jOJWcaKhSnm88LEwIq/Pk4H6x3/vHnFB9TVnB7Ind2Kj4p snH3WuP7a6GAJ5Q+Suy4m6FwWh/zzwM5/7riESkPeeFKX1BOIaRRkwd2eCGAgsogHu12 yJcRkL2fjS4U0QQp2cp1mV1RYEiIPkAh8SaEBq1dFwyUsc1jYmvu2Ue7WkPDBtvORaVO tVmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZVy+4Yk59DJUIurfX6sGOQIwnEqBpAUirNM+prnI7JM=; b=L1Wx0Xkh7aYojs3y3BfYcLhxL2gIGYa6elh4FV9uI+ES1mH8Tw9BrPNAo7Qj7tgtjI alkt7u1gimdB1ifGwLyUjoky7oaJoNcchPeSSd2IVgHmlyk6EfPuTsI0nNPKYhaml0cg B+oWlzooRiJo/H6MJpzm4EVwIl4ZpdnM4yTKV0lMwgGX1ziBY+DSUErHhlNt7QWWyCeJ dPRiaOKydYV/KmVcD+mZrbVW4pzxmFtq/Xz/h9XqfnfJ07/GYWVfX0o1SE9cDYMiTbv6 6yYwNOFDJPqJpfS6P6TsShNiJdyAOVp6w0aUssCLXRjiWvmcRkVCA7vY+DlHZuhGtGOS yyzA== X-Gm-Message-State: AGi0PuaZTfypu65s5AaD+G5PiJCN0kyX2kCPJhf2agjuvGwl1xfGFUGG oowGS83sPK9hPkUSKjdvcjhqO7Ov/cM= X-Google-Smtp-Source: APiQypIw1WEfDm/3ywf6yT1h/NScdNLRW2ZflMy1GajpYGhNjhJj+/yVCkKosbgg5FX8B9EuUDEk6A== X-Received: by 2002:a63:e314:: with SMTP id f20mr2458323pgh.285.1588950665717; Fri, 08 May 2020 08:11:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 07/10] tcg/ppc: Implement INDEX_op_rot[lr]v_vec Date: Fri, 8 May 2020 08:10:52 -0700 Message-Id: <20200508151055.5832-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200508151055.5832-1-richard.henderson@linaro.org> References: <20200508151055.5832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We already had support for rotlv, using a target-specific opcode; convert to use the generic opcode. Handle rotrv via simple negation. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.opc.h | 1 - tcg/ppc/tcg-target.inc.c | 23 +++++++++++++++++++---- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 4a17aebc5a..be5b2901c3 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -163,7 +163,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_rots_vec 0 -#define TCG_TARGET_HAS_rotv_vec 0 +#define TCG_TARGET_HAS_rotv_vec 1 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h index 1373f77e82..db514403c3 100644 --- a/tcg/ppc/tcg-target.opc.h +++ b/tcg/ppc/tcg-target.opc.h @@ -30,4 +30,3 @@ DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC) DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC) DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC) DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC) -DEF(ppc_rotl_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index ee1f9227c1..7da67086c6 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -2995,6 +2995,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: return vece <=3D MO_32 || have_isa_2_07; case INDEX_op_ssadd_vec: case INDEX_op_sssub_vec: @@ -3005,6 +3006,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: + case INDEX_op_rotli_vec: return vece <=3D MO_32 || have_isa_2_07 ? -1 : 0; case INDEX_op_neg_vec: return vece >=3D MO_32 && have_isa_3_00; @@ -3019,6 +3021,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) return 0; case INDEX_op_bitsel_vec: return have_vsx; + case INDEX_op_rotrv_vec: + return -1; default: return 0; } @@ -3301,7 +3305,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_ppc_pkum_vec: insn =3D pkum_op[vece]; break; - case INDEX_op_ppc_rotl_vec: + case INDEX_op_rotlv_vec: insn =3D rotl_op[vece]; break; case INDEX_op_ppc_msum_vec: @@ -3409,7 +3413,7 @@ static void expand_vec_mul(TCGType type, unsigned vec= e, TCGv_vec v0, t3 =3D tcg_temp_new_vec(type); t4 =3D tcg_temp_new_vec(type); tcg_gen_dupi_vec(MO_8, t4, -16); - vec_gen_3(INDEX_op_ppc_rotl_vec, type, MO_32, tcgv_vec_arg(t1), + vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), tcgv_vec_arg(v2), tcgv_vec_arg(t4)); vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v2)); @@ -3434,7 +3438,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, u= nsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2; + TCGv_vec v0, v1, v2, t0; TCGArg a2; =20 va_start(va, a0); @@ -3452,6 +3456,9 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, u= nsigned vece, case INDEX_op_sari_vec: expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); break; + case INDEX_op_rotli_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec); + break; case INDEX_op_cmp_vec: v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); @@ -3460,6 +3467,13 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_mul(type, vece, v0, v1, v2); break; + case INDEX_op_rotlv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + t0 =3D tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t0, v2); + tcg_gen_rotlv_vec(vece, v0, v1, t0); + tcg_temp_free_vec(t0); + break; default: g_assert_not_reached(); } @@ -3664,12 +3678,13 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: case INDEX_op_ppc_mrgh_vec: case INDEX_op_ppc_mrgl_vec: case INDEX_op_ppc_muleu_vec: case INDEX_op_ppc_mulou_vec: case INDEX_op_ppc_pkum_vec: - case INDEX_op_ppc_rotl_vec: case INDEX_op_dup2_vec: return &v_v_v; case INDEX_op_not_vec: --=20 2.20.1 From nobody Sun May 19 15:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588950745; cv=none; d=zohomail.com; s=zohoarc; b=bJRjZnedoi+OmrfQLB+rOg2vtAuIcqG6JMLsV/4Ty2Z/3Mvm7w8pPD/3BRMUTw/l+52YNeTqt+OoJSdDrh/yBYc/1XXJNezg1/ZzZLrvZM64sXZwRjvd2Ayls9Ige40RaaLy8oopR0hS9bEM+W2jYp2f//Dh1C6MpxAIrgLFAnI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588950745; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=usEU+0THdbgtBj9wJbgNK97HinYANEa/S4b+EK/lCNc=; b=TH1JRWqMui9YvqCARHh31s4+FjGRW3M4q1kJ+JYdkC3joc2ZvTUUtpbZILvsJ9CMsTV0ifsDtatLgnCzBZ71YHNrVzpEVLIddyKImU9Xi5maBUGkWEjDkt84ZMLEk9KgpbPvlxXhWNmJSLgDNiWdWObgGkEI9vAi40mYYq+IT9I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15889507453617.17449584056601; Fri, 8 May 2020 08:12:25 -0700 (PDT) Received: from localhost ([::1]:40596 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jX4fo-0004Pm-1n for importer@patchew.org; Fri, 08 May 2020 11:12:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60050) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jX4eb-0002gB-Mp for qemu-devel@nongnu.org; Fri, 08 May 2020 11:11:09 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:38145) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jX4ea-00045Z-Jj for qemu-devel@nongnu.org; Fri, 08 May 2020 11:11:09 -0400 Received: by mail-pf1-x42f.google.com with SMTP id y25so1068536pfn.5 for ; Fri, 08 May 2020 08:11:08 -0700 (PDT) Received: from localhost.localdomain (174-21-149-226.tukw.qwest.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Cc: David Gibson Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/helper.h | 4 ---- target/ppc/int_helper.c | 17 ----------------- target/ppc/translate/vmx-impl.inc.c | 8 ++++---- 3 files changed, 4 insertions(+), 25 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index a95c010391..b0114fc915 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -213,10 +213,6 @@ DEF_HELPER_3(vsubuqm, void, avr, avr, avr) DEF_HELPER_4(vsubecuq, void, avr, avr, avr, avr) DEF_HELPER_4(vsubeuqm, void, avr, avr, avr, avr) DEF_HELPER_3(vsubcuq, void, avr, avr, avr) -DEF_HELPER_3(vrlb, void, avr, avr, avr) -DEF_HELPER_3(vrlh, void, avr, avr, avr) -DEF_HELPER_3(vrlw, void, avr, avr, avr) -DEF_HELPER_3(vrld, void, avr, avr, avr) DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32) DEF_HELPER_3(vextractub, void, avr, avr, i32) DEF_HELPER_3(vextractuh, void, avr, avr, i32) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 6d238b989d..ee308da2ca 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -1347,23 +1347,6 @@ VRFI(p, float_round_up) VRFI(z, float_round_to_zero) #undef VRFI =20 -#define VROTATE(suffix, element, mask) \ - void helper_vrl##suffix(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ - { \ - int i; \ - \ - for (i =3D 0; i < ARRAY_SIZE(r->element); i++) { \ - unsigned int shift =3D b->element[i] & mask; \ - r->element[i] =3D (a->element[i] << shift) | \ - (a->element[i] >> (sizeof(a->element[0]) * 8 - shift)); \ - } \ - } -VROTATE(b, u8, 0x7) -VROTATE(h, u16, 0xF) -VROTATE(w, u32, 0x1F) -VROTATE(d, u64, 0x3F) -#undef VROTATE - void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b) { int i; diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index 403ed3a01c..de2fd136ff 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -900,13 +900,13 @@ GEN_VXFORM3(vsubeuqm, 31, 0); GEN_VXFORM3(vsubecuq, 31, 0); GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ vsubecuq, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM(vrlb, 2, 0); -GEN_VXFORM(vrlh, 2, 1); -GEN_VXFORM(vrlw, 2, 2); +GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0); +GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1); +GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2); GEN_VXFORM(vrlwmi, 2, 2); GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \ vrlwmi, PPC_NONE, PPC2_ISA300) -GEN_VXFORM(vrld, 2, 3); +GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3); GEN_VXFORM(vrldmi, 2, 3); GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \ vrldmi, PPC_NONE, PPC2_ISA300) --=20 2.20.1 From nobody Sun May 19 15:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588951111; cv=none; d=zohomail.com; s=zohoarc; b=OVc1ir0OjexD/wjG/xbzxI0oWtZ9XQvgcWg0aIqkM4MlI0mSITnOLFFaMH8BlNHdmXgi7MW0xz+qakqawEMIK3cffJ5EA/IaQHVD0ED2Q8a3b8T/nQ1OFSugeZUIQTZzHQdH9BbvvOfCagST7KM7h+NoSs0X3fWSZSBcx7XpOKc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588951111; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Merge VERLL and VERLLV into op_vesv and op_ves, alongside all of the other vector shift operations. Cc: David Hildenbrand Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- target/s390x/helper.h | 4 -- target/s390x/translate_vx.inc.c | 66 +++++---------------------------- target/s390x/vec_int_helper.c | 31 ---------------- target/s390x/insn-data.def | 4 +- 4 files changed, 11 insertions(+), 94 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index b5813c2ac2..b7887b552b 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -198,10 +198,6 @@ DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void,= ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i3= 2) DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32) DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32) -DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i= 32) -DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, = i32) -DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) -DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i3= 2) DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i3= 2) DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i= 32) DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.in= c.c index 12347f8a03..eb767f5288 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -1825,63 +1825,6 @@ static DisasJumpType op_vpopct(DisasContext *s, Disa= sOps *o) return DISAS_NEXT; } =20 -static void gen_rll_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_i32 t0 =3D tcg_temp_new_i32(); - - tcg_gen_andi_i32(t0, b, 31); - tcg_gen_rotl_i32(d, a, t0); - tcg_temp_free_i32(t0); -} - -static void gen_rll_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - TCGv_i64 t0 =3D tcg_temp_new_i64(); - - tcg_gen_andi_i64(t0, b, 63); - tcg_gen_rotl_i64(d, a, t0); - tcg_temp_free_i64(t0); -} - -static DisasJumpType op_verllv(DisasContext *s, DisasOps *o) -{ - const uint8_t es =3D get_field(s, m4); - static const GVecGen3 g[4] =3D { - { .fno =3D gen_helper_gvec_verllv8, }, - { .fno =3D gen_helper_gvec_verllv16, }, - { .fni4 =3D gen_rll_i32, }, - { .fni8 =3D gen_rll_i64, }, - }; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - gen_gvec_3(get_field(s, v1), get_field(s, v2), - get_field(s, v3), &g[es]); - return DISAS_NEXT; -} - -static DisasJumpType op_verll(DisasContext *s, DisasOps *o) -{ - const uint8_t es =3D get_field(s, m4); - static const GVecGen2s g[4] =3D { - { .fno =3D gen_helper_gvec_verll8, }, - { .fno =3D gen_helper_gvec_verll16, }, - { .fni4 =3D gen_rll_i32, }, - { .fni8 =3D gen_rll_i64, }, - }; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - gen_gvec_2s(get_field(s, v1), get_field(s, v3), o->addr1, - &g[es]); - return DISAS_NEXT; -} - static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c) { TCGv_i32 t =3D tcg_temp_new_i32(); @@ -1946,6 +1889,9 @@ static DisasJumpType op_vesv(DisasContext *s, DisasOp= s *o) case 0x70: gen_gvec_fn_3(shlv, es, v1, v2, v3); break; + case 0x73: + gen_gvec_fn_3(rotlv, es, v1, v2, v3); + break; case 0x7a: gen_gvec_fn_3(sarv, es, v1, v2, v3); break; @@ -1977,6 +1923,9 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps= *o) case 0x30: gen_gvec_fn_2i(shli, es, v1, v3, d2); break; + case 0x33: + gen_gvec_fn_2i(rotli, es, v1, v3, d2); + break; case 0x3a: gen_gvec_fn_2i(sari, es, v1, v3, d2); break; @@ -1994,6 +1943,9 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps= *o) case 0x30: gen_gvec_fn_2s(shls, es, v1, v3, shift); break; + case 0x33: + gen_gvec_fn_2s(rotls, es, v1, v3, shift); + break; case 0x3a: gen_gvec_fn_2s(sars, es, v1, v3, shift); break; diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c index 0d6bc13dd6..5561b3ed90 100644 --- a/target/s390x/vec_int_helper.c +++ b/target/s390x/vec_int_helper.c @@ -515,37 +515,6 @@ void HELPER(gvec_vpopct##BITS)(void *v1, const void *v= 2, uint32_t desc) \ DEF_VPOPCT(8) DEF_VPOPCT(16) =20 -#define DEF_VERLLV(BITS) = \ -void HELPER(gvec_verllv##BITS)(void *v1, const void *v2, const void *v3, = \ - uint32_t desc) = \ -{ = \ - int i; = \ - = \ - for (i =3D 0; i < (128 / BITS); i++) { = \ - const uint##BITS##_t a =3D s390_vec_read_element##BITS(v2, i); = \ - const uint##BITS##_t b =3D s390_vec_read_element##BITS(v3, i); = \ - = \ - s390_vec_write_element##BITS(v1, i, rol##BITS(a, b)); = \ - } = \ -} -DEF_VERLLV(8) -DEF_VERLLV(16) - -#define DEF_VERLL(BITS) = \ -void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count, = \ - uint32_t desc) = \ -{ = \ - int i; = \ - = \ - for (i =3D 0; i < (128 / BITS); i++) { = \ - const uint##BITS##_t a =3D s390_vec_read_element##BITS(v2, i); = \ - = \ - s390_vec_write_element##BITS(v1, i, rol##BITS(a, count)); = \ - } = \ -} -DEF_VERLL(8) -DEF_VERLL(16) - #define DEF_VERIM(BITS) = \ void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3, = \ uint32_t desc) = \ diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 2bc77f0871..91ddaedd84 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1147,8 +1147,8 @@ /* VECTOR POPULATION COUNT */ F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC) /* VECTOR ELEMENT ROTATE LEFT LOGICAL */ - F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC) - F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC) + F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC) + F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC) /* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */ F(0xe772, VERIM, VRI_d, V, 0, 0, 0, 0, verim, 0, IF_VEC) /* VECTOR ELEMENT SHIFT LEFT */ --=20 2.20.1 From nobody Sun May 19 15:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id d13sm1557562pga.64.2020.05.08.08.11.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2020 08:11:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N87+uoODPiN2PxHSS9BG0v3AbBww5OeyNSCwJsVaeMs=; b=OUWi3kzqWsRbphN5foKSoQBdk58BLmncizVFzR6E4ZSO+NsdqrDlv8iyJ2jeMo0cuV L3ybrT5zWS74B3g0d7rpq75Js4ahJlOgdDzs1BAhZKU43ZyUbjmx6PZ2mI9T9Op5FThL XPohekfig5BGjC12dng8euU1JB9kSYxcEmlp8VUokjlzPc9Oy79IMfe5vfRfq4O32cXm skABQkgV1v4IXQmjLOiFN6Utt8koq4Rvp2ZQ4X4W3vGccqxS30gAkMj5MLJcog/Xriu0 fCk2k0Ip6YvOOotQonItwbMvH0Zv72Wa8UOed2Dyii9zGpg+cHfBk3kERKtLLx9pRHwK SWSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N87+uoODPiN2PxHSS9BG0v3AbBww5OeyNSCwJsVaeMs=; b=nf1LT/dBCRqn57twlnkZXVHMOGyK75Mqb4xg3O/NY+BlolIJrcS/cfphDy5xNhLiT5 ZWsKWtH43gZ4u8cU/gmmMlAlNvjqRR4dh1F+ZvLSeOLEG96Way0w5OrgWXXTdcepezj3 J8NlkfE/W9BoTzrj2g5Wys160tnajHdCSaE/swR2R1wCEbooIc11JUG3nxnHTYq72hzH Z4K1jWsDi91MSxYldIbp+kvR0xvdscBTBkh6fgpF+2n+wZgRweXfzy501xEqLPzDw/WA iUiuVUGJh/QAPJIL9S3xNnlQDFtCdoz7LQXT8F79UH03f9VaVQXpU2AuHpFzP1pW2LIT b7aQ== X-Gm-Message-State: AGi0PuaHc0c9MA/2LdVuMAgX5nqq9BgS1dk33S+vfJWamoaOy27K/A9c mfAuhQqz/AJNL9o0z49mDBkjw1KnxqY= X-Google-Smtp-Source: APiQypJPcot5XcvmP6yDf8BSKrWsJm478BI/I0n/Bdpg7znVPgSn/OTozZKE4MPnKfR/5Fo1XNpMqg== X-Received: by 2002:a17:902:8b88:: with SMTP id ay8mr2862403plb.235.1588950669263; Fri, 08 May 2020 08:11:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 10/10] tcg: Improve move ops in liveness_pass_2 Date: Fri, 8 May 2020 08:10:55 -0700 Message-Id: <20200508151055.5832-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200508151055.5832-1-richard.henderson@linaro.org> References: <20200508151055.5832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" If the output of the move is dead, then the last use is in the store. If we propagate the input to the store, then we can remove the move opcode entirely. Signed-off-by: Richard Henderson --- tcg/tcg.c | 78 +++++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 56 insertions(+), 22 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index aa13158999..216a6963b3 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2982,34 +2982,68 @@ static bool liveness_pass_2(TCGContext *s) } =20 /* Outputs become available. */ - for (i =3D 0; i < nb_oargs; i++) { - arg_ts =3D arg_temp(op->args[i]); + if (opc =3D=3D INDEX_op_mov_i32 || opc =3D=3D INDEX_op_mov_i64) { + arg_ts =3D arg_temp(op->args[0]); dir_ts =3D arg_ts->state_ptr; - if (!dir_ts) { - continue; + if (dir_ts) { + op->args[0] =3D temp_arg(dir_ts); + changes =3D true; + + /* The output is now live and modified. */ + arg_ts->state =3D 0; + + if (NEED_SYNC_ARG(0)) { + TCGOpcode sopc =3D (arg_ts->type =3D=3D TCG_TYPE_I32 + ? INDEX_op_st_i32 + : INDEX_op_st_i64); + TCGOp *sop =3D tcg_op_insert_after(s, op, sopc); + TCGTemp *out_ts =3D dir_ts; + + if (IS_DEAD_ARG(0)) { + out_ts =3D arg_temp(op->args[1]); + arg_ts->state =3D TS_DEAD; + tcg_op_remove(s, op); + } else { + arg_ts->state =3D TS_MEM; + } + + sop->args[0] =3D temp_arg(out_ts); + sop->args[1] =3D temp_arg(arg_ts->mem_base); + sop->args[2] =3D arg_ts->mem_offset; + } else { + tcg_debug_assert(!IS_DEAD_ARG(0)); + } } - op->args[i] =3D temp_arg(dir_ts); - changes =3D true; + } else { + for (i =3D 0; i < nb_oargs; i++) { + arg_ts =3D arg_temp(op->args[i]); + dir_ts =3D arg_ts->state_ptr; + if (!dir_ts) { + continue; + } + op->args[i] =3D temp_arg(dir_ts); + changes =3D true; =20 - /* The output is now live and modified. */ - arg_ts->state =3D 0; + /* The output is now live and modified. */ + arg_ts->state =3D 0; =20 - /* Sync outputs upon their last write. */ - if (NEED_SYNC_ARG(i)) { - TCGOpcode sopc =3D (arg_ts->type =3D=3D TCG_TYPE_I32 - ? INDEX_op_st_i32 - : INDEX_op_st_i64); - TCGOp *sop =3D tcg_op_insert_after(s, op, sopc); + /* Sync outputs upon their last write. */ + if (NEED_SYNC_ARG(i)) { + TCGOpcode sopc =3D (arg_ts->type =3D=3D TCG_TYPE_I32 + ? INDEX_op_st_i32 + : INDEX_op_st_i64); + TCGOp *sop =3D tcg_op_insert_after(s, op, sopc); =20 - sop->args[0] =3D temp_arg(dir_ts); - sop->args[1] =3D temp_arg(arg_ts->mem_base); - sop->args[2] =3D arg_ts->mem_offset; + sop->args[0] =3D temp_arg(dir_ts); + sop->args[1] =3D temp_arg(arg_ts->mem_base); + sop->args[2] =3D arg_ts->mem_offset; =20 - arg_ts->state =3D TS_MEM; - } - /* Drop outputs that are dead. */ - if (IS_DEAD_ARG(i)) { - arg_ts->state =3D TS_DEAD; + arg_ts->state =3D TS_MEM; + } + /* Drop outputs that are dead. */ + if (IS_DEAD_ARG(i)) { + arg_ts->state =3D TS_DEAD; + } } } } --=20 2.20.1