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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Do not explicitly store zero to the NEON high part when we can pass !is_q to clear_vec_high. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 59 +++++++++++++++++++++++--------------- 1 file changed, 36 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b6feb2b9dc..0947eaee05 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -939,11 +939,10 @@ static void do_fp_ld(DisasContext *s, int destidx, TC= Gv_i64 tcg_addr, int size) { /* This always zero-extends and writes to a full 128 bit wide vector */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); - TCGv_i64 tmphi; + TCGv_i64 tmphi =3D NULL; =20 if (size < 4) { MemOp memop =3D s->be_data + size; - tmphi =3D tcg_const_i64(0); tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); } else { bool be =3D s->be_data =3D=3D MO_BE; @@ -961,12 +960,13 @@ static void do_fp_ld(DisasContext *s, int destidx, TC= Gv_i64 tcg_addr, int size) } =20 tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); - tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); - tcg_temp_free_i64(tmplo); - tcg_temp_free_i64(tmphi); =20 - clear_vec_high(s, true, destidx); + if (tmphi) { + tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); + tcg_temp_free_i64(tmphi); + } + clear_vec_high(s, tmphi !=3D NULL, destidx); } =20 /* @@ -6960,8 +6960,8 @@ static void disas_simd_ext(DisasContext *s, uint32_t = insn) return; } =20 - tcg_resh =3D tcg_temp_new_i64(); tcg_resl =3D tcg_temp_new_i64(); + tcg_resh =3D NULL; =20 /* Vd gets bits starting at pos bits into Vm:Vn. This is * either extracting 128 bits from a 128:128 concatenation, or @@ -6973,7 +6973,6 @@ static void disas_simd_ext(DisasContext *s, uint32_t = insn) read_vec_element(s, tcg_resh, rm, 0, MO_64); do_ext64(s, tcg_resh, tcg_resl, pos); } - tcg_gen_movi_i64(tcg_resh, 0); } else { TCGv_i64 tcg_hh; typedef struct { @@ -6988,6 +6987,7 @@ static void disas_simd_ext(DisasContext *s, uint32_t = insn) pos -=3D 64; } =20 + tcg_resh =3D tcg_temp_new_i64(); read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64); elt++; read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); @@ -7003,9 +7003,12 @@ static void disas_simd_ext(DisasContext *s, uint32_t= insn) =20 write_vec_element(s, tcg_resl, rd, 0, MO_64); tcg_temp_free_i64(tcg_resl); - write_vec_element(s, tcg_resh, rd, 1, MO_64); - tcg_temp_free_i64(tcg_resh); - clear_vec_high(s, true, rd); + + if (is_q) { + write_vec_element(s, tcg_resh, rd, 1, MO_64); + tcg_temp_free_i64(tcg_resh); + } + clear_vec_high(s, is_q, rd); } =20 /* TBL/TBX @@ -7042,17 +7045,21 @@ static void disas_simd_tb(DisasContext *s, uint32_t= insn) * the input. */ tcg_resl =3D tcg_temp_new_i64(); - tcg_resh =3D tcg_temp_new_i64(); + tcg_resh =3D NULL; =20 if (is_tblx) { read_vec_element(s, tcg_resl, rd, 0, MO_64); } else { tcg_gen_movi_i64(tcg_resl, 0); } - if (is_tblx && is_q) { - read_vec_element(s, tcg_resh, rd, 1, MO_64); - } else { - tcg_gen_movi_i64(tcg_resh, 0); + + if (is_q) { + tcg_resh =3D tcg_temp_new_i64(); + if (is_tblx) { + read_vec_element(s, tcg_resh, rd, 1, MO_64); + } else { + tcg_gen_movi_i64(tcg_resh, 0); + } } =20 tcg_idx =3D tcg_temp_new_i64(); @@ -7072,9 +7079,12 @@ static void disas_simd_tb(DisasContext *s, uint32_t = insn) =20 write_vec_element(s, tcg_resl, rd, 0, MO_64); tcg_temp_free_i64(tcg_resl); - write_vec_element(s, tcg_resh, rd, 1, MO_64); - tcg_temp_free_i64(tcg_resh); - clear_vec_high(s, true, rd); + + if (is_q) { + write_vec_element(s, tcg_resh, rd, 1, MO_64); + tcg_temp_free_i64(tcg_resh); + } + clear_vec_high(s, is_q, rd); } =20 /* ZIP/UZP/TRN @@ -7111,7 +7121,7 @@ static void disas_simd_zip_trn(DisasContext *s, uint3= 2_t insn) } =20 tcg_resl =3D tcg_const_i64(0); - tcg_resh =3D tcg_const_i64(0); + tcg_resh =3D is_q ? tcg_const_i64(0) : NULL; tcg_res =3D tcg_temp_new_i64(); =20 for (i =3D 0; i < elements; i++) { @@ -7162,9 +7172,12 @@ static void disas_simd_zip_trn(DisasContext *s, uint= 32_t insn) =20 write_vec_element(s, tcg_resl, rd, 0, MO_64); tcg_temp_free_i64(tcg_resl); - write_vec_element(s, tcg_resh, rd, 1, MO_64); - tcg_temp_free_i64(tcg_resh); - clear_vec_high(s, true, rd); + + if (is_q) { + write_vec_element(s, tcg_resh, rd, 1, MO_64); + tcg_temp_free_i64(tcg_resh); + } + clear_vec_high(s, is_q, rd); } =20 /* --=20 2.20.1