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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q74sm961246wme.14.2020.05.07.08.18.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2020 08:18:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rTf9IBDSAsF51iBWcS+fobjD1nzCOzkNrL8OJ1OV40M=; b=i5AQcm++hyCzhLAgoHyYhSW5VN3U/ORNfWsg2zSpo3vBirDxM03uvaBesTfw5L/NOM AHu/BhjjL98extszOh4q9euqMFG51934dyNOn+U4Iqg7KcKlrJoNee2ukpRGyfdmovqV 2ibXtvztYqGMs0XgEBu8RGNAvWi7u2mMnITilnBXlTcSse69UbbSktCksXOs8bCigKht w1OX9s6MD/dCiFIWcKQKtkjAmMTZj1DQnUCb9DYP0fKJKtUpxrtSbyje1c849hAEChjT g2BuxEpGBOLXOk3jFz95RrF49Sih9A4yPxHRhJiLNXkIwOinRY9Pg8EYVDqWzLeC/KQ4 3cSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rTf9IBDSAsF51iBWcS+fobjD1nzCOzkNrL8OJ1OV40M=; b=hc2mul+vzdrMr09l/DCaVehpIub1UJAgH0ax1naix+YgvTOwPGnt4tX6sK5urv3SAz VdE5P3HoWd32/qR8k+jibjmJ+3nL2dk+NpUyl7+O4HHvDUpKKp9BCLc8K0O8A3TDep6X u3YHR5CHAlpyqiGh1C6buvIvZjSZlhkWdHlVqtmBP33F3QfMgqn4d+/kyMtmdCVuHaf7 SD7FP7KGQ3Jk6NtMbPgDWWoJOPBcfTYZCpLRmwRDyGsQDYzEgNruLYF7aqNG4ciJHWoS ST3N6daxdM5miKrGvy3YtUS+V51ckCzgziHSr8i1/hdJJ1LY2b7RjHekoPf+0ZtLPv8x cHyA== X-Gm-Message-State: AGi0PuYrezzcFLKSDAeKtgirG7o86N7mYG5kGtHC3olzoV4Zt1d7f+zZ MlmRQZ3eiULHzW4/YOEo2QedUw== X-Google-Smtp-Source: APiQypJ35Usq63LoiRjN0xCWHXpjkwG8aieOIze9ulmvT4dI4uhcuW7jbfyLqYEs2Dp8sxWgzZIYBA== X-Received: by 2002:adf:e58d:: with SMTP id l13mr17143980wrm.187.1588864708620; Thu, 07 May 2020 08:18:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/5] docs/system: Document Musca boards Date: Thu, 7 May 2020 16:18:19 +0100 Message-Id: <20200507151819.28444-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200507151819.28444-1-peter.maydell@linaro.org> References: <20200507151819.28444-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Provide a minimal documentation of the Musca boards. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Edgar E. Iglesias --- docs/system/arm/musca.rst | 31 +++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + MAINTAINERS | 1 + 3 files changed, 33 insertions(+) create mode 100644 docs/system/arm/musca.rst diff --git a/docs/system/arm/musca.rst b/docs/system/arm/musca.rst new file mode 100644 index 00000000000..8375c5008d5 --- /dev/null +++ b/docs/system/arm/musca.rst @@ -0,0 +1,31 @@ +Arm Musca boards (``musca-a``, ``musca-b1``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The Arm Musca development boards are a reference implementation +of a system using the SSE-200 subsystem for embedded. They are +dual Cortex-M33 systems. + +QEMU provides models of the A and B1 variants of this board. + +Unimplemented devices: + +- SPI +- |I2C| +- |I2S| +- PWM +- QSPI +- Timer +- SCC +- GPIO +- eFlash +- MHU +- PVT +- SDIO +- CryptoCell + +Note that (like the real hardware) the Musca-A machine is +asymmetric: CPU 0 does not have the FPU or DSP extensions, +but CPU 1 does. Also like the real hardware, the memory maps +for the A and B1 variants differ significantly, so guest +software must be built for the right variant. + diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 15bcf9f81f0..1b86b93c346 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -72,6 +72,7 @@ undocumented; you can get a complete list by running =20 arm/integratorcp arm/mps2 + arm/musca arm/realview arm/versatile arm/vexpress diff --git a/MAINTAINERS b/MAINTAINERS index ea7bdd359e0..f8e0fdb4ef2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -706,6 +706,7 @@ M: Peter Maydell L: qemu-arm@nongnu.org S: Maintained F: hw/arm/musca.c +F: docs/system/arm/musca.rst =20 Musicpal M: Jan Kiszka --=20 2.20.1