From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588657836; cv=none; d=zohomail.com; s=zohoarc; b=L4CsCytzSyIgCS2WAuOLiMR642kYdrQU7rirlCil9QnTXkohXowetQUYgkcN57FPtBDp83Z38t1HJQ2ykO1Lss6bWdo49Em2ITdBBczT6yFxUfwFxL9BVubYGwSqlOcaAL1xMtdLlG0jtoqOJx+EQRtPFteZ3qiSDHqFiSS5yPA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588657836; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dCGDM3AbEhnk1L7eBBVSGCUEeRNpyHuneyEcKP/dUgs=; b=ik4qYomf6o6Rpc/A4aSdxxsohBwVWmd2/MVUc5XaCcY4aRSOplNCMzgJyk9nd8Uiz1IxDJ2okR4zN07DHN6z4MlCuZlqWZj93fwjMe2dMjRHRJ8oNuXEgCEyHzhL62pEhPncAkZa6sBuyuB8PtmbBaxOJQjjsHgSna2bH42RVwg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588657836952449.8817258257086; Mon, 4 May 2020 22:50:36 -0700 (PDT) Received: from localhost ([::1]:58040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jVqTS-0000Lf-QN for importer@patchew.org; Tue, 05 May 2020 01:50:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53544) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS5-00072J-FX; Tue, 05 May 2020 01:49:09 -0400 Received: from charlie.dont.surf ([128.199.63.193]:56242) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS1-0005CH-Ue; Tue, 05 May 2020 01:49:07 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 573E2BF7AF; Tue, 5 May 2020 05:49:03 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 01/18] nvme: fix pci doorbell size calculation Date: Tue, 5 May 2020 07:48:23 +0200 Message-Id: <20200505054840.186586-2-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen The size of the BAR is 0x1000 (main registers) + 8 bytes for each queue. Currently, the size of the BAR is calculated like so: n->reg_size =3D pow2ceil(0x1004 + 2 * (n->num_queues + 1) * 4); Since the 'num_queues' parameter already accounts for the admin queue, this should in any case not need to be incremented by one. Also, the size should be initialized to (0x1000). n->reg_size =3D pow2ceil(0x1000 + 2 * n->num_queues * 4); This, with the default value of num_queues (64), we will set aside room for 1 admin queue and 63 I/O queues (4 bytes per doorbell, 2 doorbells per queue). Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 9b453423cf2c..1d7d7fb3c67a 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -54,6 +54,9 @@ #include "trace.h" #include "nvme.h" =20 +#define NVME_REG_SIZE 0x1000 +#define NVME_DB_SIZE 4 + #define NVME_GUEST_ERR(trace, fmt, ...) \ do { \ (trace_##trace)(__VA_ARGS__); \ @@ -1403,7 +1406,9 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) pcie_endpoint_cap_init(pci_dev, 0x80); =20 n->num_namespaces =3D 1; - n->reg_size =3D pow2ceil(0x1004 + 2 * (n->num_queues + 1) * 4); + + /* num_queues is really number of pairs, so each has two doorbells */ + n->reg_size =3D pow2ceil(NVME_REG_SIZE + 2 * n->num_queues * NVME_DB_S= IZE); n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; =20 n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588658038; cv=none; d=zohomail.com; s=zohoarc; b=npSisOnIS4WvUJ+Bx5nHPa3SVjqlESOz7N2bArqMDEHzn/l0+nvb0chUUpoExWcRyM1X3wGO89Y+IHcCzTsBfXp1O7aXfp+jYhjQJY8YrqRCNQDkl1jEcSiPcVpe4KShbcidkBagnWgCzqtjpGDrl5UrgR+GpWeFY4eM/FXBIXQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588658038; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=n6P7b3TUhajMvyqDh8rCSqfhMP8va+ED5enrbw3yGVQ=; b=T1tes/p702xvUHYenvnrIjK1lxcP5RJc/6guSPdVbr3HtBP9qZhnv7BcGBiBpWNlsHT6P+xRK3dFwpVwtPjD4i4sdbwMgmv+yA0Rqn6+6zfauEmsXyViIussDDwUD0T8Ia/ageiMRXsVoKxDbsl+jm5DA3UvMP7uzARFlby5ILo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158865803872736.4857315832769; Mon, 4 May 2020 22:53:58 -0700 (PDT) Received: from localhost ([::1]:49104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jVqWj-0000C5-Ac for importer@patchew.org; Tue, 05 May 2020 01:53:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53582) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS9-00078I-FM; Tue, 05 May 2020 01:49:13 -0400 Received: from charlie.dont.surf ([128.199.63.193]:56252) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS2-0005CM-Pe; Tue, 05 May 2020 01:49:13 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 77842BF9A4; Tue, 5 May 2020 05:49:04 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 02/18] nvme: rename trace events to pci_nvme Date: Tue, 5 May 2020 07:48:24 +0200 Message-Id: <20200505054840.186586-3-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Change the prefix of all nvme device related trace events to 'pci_nvme' to not clash with trace events from the nvme block driver. Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 198 +++++++++++++++++++++--------------------- hw/block/trace-events | 180 +++++++++++++++++++------------------- 2 files changed, 188 insertions(+), 190 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 1d7d7fb3c67a..6702812ecdd1 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -126,16 +126,16 @@ static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *= cq) { if (cq->irq_enabled) { if (msix_enabled(&(n->parent_obj))) { - trace_nvme_irq_msix(cq->vector); + trace_pci_nvme_irq_msix(cq->vector); msix_notify(&(n->parent_obj), cq->vector); } else { - trace_nvme_irq_pin(); + trace_pci_nvme_irq_pin(); assert(cq->cqid < 64); n->irq_status |=3D 1 << cq->cqid; nvme_irq_check(n); } } else { - trace_nvme_irq_masked(); + trace_pci_nvme_irq_masked(); } } =20 @@ -160,7 +160,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, int num_prps =3D (len >> n->page_bits) + 1; =20 if (unlikely(!prp1)) { - trace_nvme_err_invalid_prp(); + trace_pci_nvme_err_invalid_prp(); return NVME_INVALID_FIELD | NVME_DNR; } else if (n->cmbsz && prp1 >=3D n->ctrl_mem.addr && prp1 < n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size)) { @@ -174,7 +174,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, len -=3D trans_len; if (len) { if (unlikely(!prp2)) { - trace_nvme_err_invalid_prp2_missing(); + trace_pci_nvme_err_invalid_prp2_missing(); goto unmap; } if (len > n->page_size) { @@ -190,7 +190,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, =20 if (i =3D=3D n->max_prp_ents - 1 && len > n->page_size) { if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))= ) { - trace_nvme_err_invalid_prplist_ent(prp_ent); + trace_pci_nvme_err_invalid_prplist_ent(prp_ent); goto unmap; } =20 @@ -203,7 +203,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, } =20 if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) { - trace_nvme_err_invalid_prplist_ent(prp_ent); + trace_pci_nvme_err_invalid_prplist_ent(prp_ent); goto unmap; } =20 @@ -218,7 +218,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, } } else { if (unlikely(prp2 & (n->page_size - 1))) { - trace_nvme_err_invalid_prp2_align(prp2); + trace_pci_nvme_err_invalid_prp2_align(prp2); goto unmap; } if (qsg->nsg) { @@ -266,20 +266,20 @@ static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_= t *ptr, uint32_t len, QEMUIOVector iov; uint16_t status =3D NVME_SUCCESS; =20 - trace_nvme_dma_read(prp1, prp2); + trace_pci_nvme_dma_read(prp1, prp2); =20 if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) { return NVME_INVALID_FIELD | NVME_DNR; } if (qsg.nsg > 0) { if (unlikely(dma_buf_read(ptr, len, &qsg))) { - trace_nvme_err_invalid_dma(); + trace_pci_nvme_err_invalid_dma(); status =3D NVME_INVALID_FIELD | NVME_DNR; } qemu_sglist_destroy(&qsg); } else { if (unlikely(qemu_iovec_from_buf(&iov, 0, ptr, len) !=3D len)) { - trace_nvme_err_invalid_dma(); + trace_pci_nvme_err_invalid_dma(); status =3D NVME_INVALID_FIELD | NVME_DNR; } qemu_iovec_destroy(&iov); @@ -368,7 +368,7 @@ static uint16_t nvme_write_zeros(NvmeCtrl *n, NvmeNames= pace *ns, NvmeCmd *cmd, uint32_t count =3D nlb << data_shift; =20 if (unlikely(slba + nlb > ns->id_ns.nsze)) { - trace_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); + trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); return NVME_LBA_RANGE | NVME_DNR; } =20 @@ -396,11 +396,11 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *n= s, NvmeCmd *cmd, int is_write =3D rw->opcode =3D=3D NVME_CMD_WRITE ? 1 : 0; enum BlockAcctType acct =3D is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_R= EAD; =20 - trace_nvme_rw(is_write ? "write" : "read", nlb, data_size, slba); + trace_pci_nvme_rw(is_write ? "write" : "read", nlb, data_size, slba); =20 if (unlikely((slba + nlb) > ns->id_ns.nsze)) { block_acct_invalid(blk_get_stats(n->conf.blk), acct); - trace_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); + trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); return NVME_LBA_RANGE | NVME_DNR; } =20 @@ -435,7 +435,7 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, = NvmeRequest *req) uint32_t nsid =3D le32_to_cpu(cmd->nsid); =20 if (unlikely(nsid =3D=3D 0 || nsid > n->num_namespaces)) { - trace_nvme_err_invalid_ns(nsid, n->num_namespaces); + trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces); return NVME_INVALID_NSID | NVME_DNR; } =20 @@ -449,7 +449,7 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, = NvmeRequest *req) case NVME_CMD_READ: return nvme_rw(n, ns, cmd, req); default: - trace_nvme_err_invalid_opc(cmd->opcode); + trace_pci_nvme_err_invalid_opc(cmd->opcode); return NVME_INVALID_OPCODE | NVME_DNR; } } @@ -474,11 +474,11 @@ static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeCmd *cmd) uint16_t qid =3D le16_to_cpu(c->qid); =20 if (unlikely(!qid || nvme_check_sqid(n, qid))) { - trace_nvme_err_invalid_del_sq(qid); + trace_pci_nvme_err_invalid_del_sq(qid); return NVME_INVALID_QID | NVME_DNR; } =20 - trace_nvme_del_sq(qid); + trace_pci_nvme_del_sq(qid); =20 sq =3D n->sq[qid]; while (!QTAILQ_EMPTY(&sq->out_req_list)) { @@ -542,26 +542,26 @@ static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeCmd *= cmd) uint16_t qflags =3D le16_to_cpu(c->sq_flags); uint64_t prp1 =3D le64_to_cpu(c->prp1); =20 - trace_nvme_create_sq(prp1, sqid, cqid, qsize, qflags); + trace_pci_nvme_create_sq(prp1, sqid, cqid, qsize, qflags); =20 if (unlikely(!cqid || nvme_check_cqid(n, cqid))) { - trace_nvme_err_invalid_create_sq_cqid(cqid); + trace_pci_nvme_err_invalid_create_sq_cqid(cqid); return NVME_INVALID_CQID | NVME_DNR; } if (unlikely(!sqid || !nvme_check_sqid(n, sqid))) { - trace_nvme_err_invalid_create_sq_sqid(sqid); + trace_pci_nvme_err_invalid_create_sq_sqid(sqid); return NVME_INVALID_QID | NVME_DNR; } if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) { - trace_nvme_err_invalid_create_sq_size(qsize); + trace_pci_nvme_err_invalid_create_sq_size(qsize); return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR; } if (unlikely(!prp1 || prp1 & (n->page_size - 1))) { - trace_nvme_err_invalid_create_sq_addr(prp1); + trace_pci_nvme_err_invalid_create_sq_addr(prp1); return NVME_INVALID_FIELD | NVME_DNR; } if (unlikely(!(NVME_SQ_FLAGS_PC(qflags)))) { - trace_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflags)); + trace_pci_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflag= s)); return NVME_INVALID_FIELD | NVME_DNR; } sq =3D g_malloc0(sizeof(*sq)); @@ -587,17 +587,17 @@ static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeCmd *cmd) uint16_t qid =3D le16_to_cpu(c->qid); =20 if (unlikely(!qid || nvme_check_cqid(n, qid))) { - trace_nvme_err_invalid_del_cq_cqid(qid); + trace_pci_nvme_err_invalid_del_cq_cqid(qid); return NVME_INVALID_CQID | NVME_DNR; } =20 cq =3D n->cq[qid]; if (unlikely(!QTAILQ_EMPTY(&cq->sq_list))) { - trace_nvme_err_invalid_del_cq_notempty(qid); + trace_pci_nvme_err_invalid_del_cq_notempty(qid); return NVME_INVALID_QUEUE_DEL; } nvme_irq_deassert(n, cq); - trace_nvme_del_cq(qid); + trace_pci_nvme_del_cq(qid); nvme_free_cq(cq, n); return NVME_SUCCESS; } @@ -630,27 +630,27 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *= cmd) uint16_t qflags =3D le16_to_cpu(c->cq_flags); uint64_t prp1 =3D le64_to_cpu(c->prp1); =20 - trace_nvme_create_cq(prp1, cqid, vector, qsize, qflags, - NVME_CQ_FLAGS_IEN(qflags) !=3D 0); + trace_pci_nvme_create_cq(prp1, cqid, vector, qsize, qflags, + NVME_CQ_FLAGS_IEN(qflags) !=3D 0); =20 if (unlikely(!cqid || !nvme_check_cqid(n, cqid))) { - trace_nvme_err_invalid_create_cq_cqid(cqid); + trace_pci_nvme_err_invalid_create_cq_cqid(cqid); return NVME_INVALID_CQID | NVME_DNR; } if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) { - trace_nvme_err_invalid_create_cq_size(qsize); + trace_pci_nvme_err_invalid_create_cq_size(qsize); return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR; } if (unlikely(!prp1)) { - trace_nvme_err_invalid_create_cq_addr(prp1); + trace_pci_nvme_err_invalid_create_cq_addr(prp1); return NVME_INVALID_FIELD | NVME_DNR; } if (unlikely(vector > n->num_queues)) { - trace_nvme_err_invalid_create_cq_vector(vector); + trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } if (unlikely(!(NVME_CQ_FLAGS_PC(qflags)))) { - trace_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflags)); + trace_pci_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflag= s)); return NVME_INVALID_FIELD | NVME_DNR; } =20 @@ -665,7 +665,7 @@ static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeIde= ntify *c) uint64_t prp1 =3D le64_to_cpu(c->prp1); uint64_t prp2 =3D le64_to_cpu(c->prp2); =20 - trace_nvme_identify_ctrl(); + trace_pci_nvme_identify_ctrl(); =20 return nvme_dma_read_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl), prp1, prp2); @@ -678,10 +678,10 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIde= ntify *c) uint64_t prp1 =3D le64_to_cpu(c->prp1); uint64_t prp2 =3D le64_to_cpu(c->prp2); =20 - trace_nvme_identify_ns(nsid); + trace_pci_nvme_identify_ns(nsid); =20 if (unlikely(nsid =3D=3D 0 || nsid > n->num_namespaces)) { - trace_nvme_err_invalid_ns(nsid, n->num_namespaces); + trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces); return NVME_INVALID_NSID | NVME_DNR; } =20 @@ -701,7 +701,7 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeI= dentify *c) uint16_t ret; int i, j =3D 0; =20 - trace_nvme_identify_nslist(min_nsid); + trace_pci_nvme_identify_nslist(min_nsid); =20 list =3D g_malloc0(data_len); for (i =3D 0; i < n->num_namespaces; i++) { @@ -730,14 +730,14 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *c= md) case 0x02: return nvme_identify_nslist(n, c); default: - trace_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns)); + trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns)); return NVME_INVALID_FIELD | NVME_DNR; } } =20 static inline void nvme_set_timestamp(NvmeCtrl *n, uint64_t ts) { - trace_nvme_setfeat_timestamp(ts); + trace_pci_nvme_setfeat_timestamp(ts); =20 n->host_timestamp =3D le64_to_cpu(ts); n->timestamp_set_qemu_clock_ms =3D qemu_clock_get_ms(QEMU_CLOCK_VIRTUA= L); @@ -770,7 +770,7 @@ static inline uint64_t nvme_get_timestamp(const NvmeCtr= l *n) /* If the host timestamp is non-zero, set the timestamp origin */ ts.origin =3D n->host_timestamp ? 0x01 : 0x00; =20 - trace_nvme_getfeat_timestamp(ts.all); + trace_pci_nvme_getfeat_timestamp(ts.all); =20 return cpu_to_le64(ts.all); } @@ -794,17 +794,17 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd= *cmd, NvmeRequest *req) switch (dw10) { case NVME_VOLATILE_WRITE_CACHE: result =3D blk_enable_write_cache(n->conf.blk); - trace_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); + trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); break; case NVME_NUMBER_OF_QUEUES: result =3D cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) = << 16)); - trace_nvme_getfeat_numq(result); + trace_pci_nvme_getfeat_numq(result); break; case NVME_TIMESTAMP: return nvme_get_feature_timestamp(n, cmd); break; default: - trace_nvme_err_invalid_getfeat(dw10); + trace_pci_nvme_err_invalid_getfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; } =20 @@ -840,9 +840,9 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) blk_set_enable_write_cache(n->conf.blk, dw11 & 1); break; case NVME_NUMBER_OF_QUEUES: - trace_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, - ((dw11 >> 16) & 0xFFFF) + 1, - n->num_queues - 1, n->num_queues - 1); + trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, + ((dw11 >> 16) & 0xFFFF) + 1, + n->num_queues - 1, n->num_queues - 1); req->cqe.result =3D cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16)); break; @@ -852,7 +852,7 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) break; =20 default: - trace_nvme_err_invalid_setfeat(dw10); + trace_pci_nvme_err_invalid_setfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; } return NVME_SUCCESS; @@ -876,7 +876,7 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *cm= d, NvmeRequest *req) case NVME_ADM_CMD_GET_FEATURES: return nvme_get_feature(n, cmd, req); default: - trace_nvme_err_invalid_admin_opc(cmd->opcode); + trace_pci_nvme_err_invalid_admin_opc(cmd->opcode); return NVME_INVALID_OPCODE | NVME_DNR; } } @@ -939,77 +939,77 @@ static int nvme_start_ctrl(NvmeCtrl *n) uint32_t page_size =3D 1 << page_bits; =20 if (unlikely(n->cq[0])) { - trace_nvme_err_startfail_cq(); + trace_pci_nvme_err_startfail_cq(); return -1; } if (unlikely(n->sq[0])) { - trace_nvme_err_startfail_sq(); + trace_pci_nvme_err_startfail_sq(); return -1; } if (unlikely(!n->bar.asq)) { - trace_nvme_err_startfail_nbarasq(); + trace_pci_nvme_err_startfail_nbarasq(); return -1; } if (unlikely(!n->bar.acq)) { - trace_nvme_err_startfail_nbaracq(); + trace_pci_nvme_err_startfail_nbaracq(); return -1; } if (unlikely(n->bar.asq & (page_size - 1))) { - trace_nvme_err_startfail_asq_misaligned(n->bar.asq); + trace_pci_nvme_err_startfail_asq_misaligned(n->bar.asq); return -1; } if (unlikely(n->bar.acq & (page_size - 1))) { - trace_nvme_err_startfail_acq_misaligned(n->bar.acq); + trace_pci_nvme_err_startfail_acq_misaligned(n->bar.acq); return -1; } if (unlikely(NVME_CC_MPS(n->bar.cc) < NVME_CAP_MPSMIN(n->bar.cap))) { - trace_nvme_err_startfail_page_too_small( + trace_pci_nvme_err_startfail_page_too_small( NVME_CC_MPS(n->bar.cc), NVME_CAP_MPSMIN(n->bar.cap)); return -1; } if (unlikely(NVME_CC_MPS(n->bar.cc) > NVME_CAP_MPSMAX(n->bar.cap))) { - trace_nvme_err_startfail_page_too_large( + trace_pci_nvme_err_startfail_page_too_large( NVME_CC_MPS(n->bar.cc), NVME_CAP_MPSMAX(n->bar.cap)); return -1; } if (unlikely(NVME_CC_IOCQES(n->bar.cc) < NVME_CTRL_CQES_MIN(n->id_ctrl.cqes))) { - trace_nvme_err_startfail_cqent_too_small( + trace_pci_nvme_err_startfail_cqent_too_small( NVME_CC_IOCQES(n->bar.cc), NVME_CTRL_CQES_MIN(n->bar.cap)); return -1; } if (unlikely(NVME_CC_IOCQES(n->bar.cc) > NVME_CTRL_CQES_MAX(n->id_ctrl.cqes))) { - trace_nvme_err_startfail_cqent_too_large( + trace_pci_nvme_err_startfail_cqent_too_large( NVME_CC_IOCQES(n->bar.cc), NVME_CTRL_CQES_MAX(n->bar.cap)); return -1; } if (unlikely(NVME_CC_IOSQES(n->bar.cc) < NVME_CTRL_SQES_MIN(n->id_ctrl.sqes))) { - trace_nvme_err_startfail_sqent_too_small( + trace_pci_nvme_err_startfail_sqent_too_small( NVME_CC_IOSQES(n->bar.cc), NVME_CTRL_SQES_MIN(n->bar.cap)); return -1; } if (unlikely(NVME_CC_IOSQES(n->bar.cc) > NVME_CTRL_SQES_MAX(n->id_ctrl.sqes))) { - trace_nvme_err_startfail_sqent_too_large( + trace_pci_nvme_err_startfail_sqent_too_large( NVME_CC_IOSQES(n->bar.cc), NVME_CTRL_SQES_MAX(n->bar.cap)); return -1; } if (unlikely(!NVME_AQA_ASQS(n->bar.aqa))) { - trace_nvme_err_startfail_asqent_sz_zero(); + trace_pci_nvme_err_startfail_asqent_sz_zero(); return -1; } if (unlikely(!NVME_AQA_ACQS(n->bar.aqa))) { - trace_nvme_err_startfail_acqent_sz_zero(); + trace_pci_nvme_err_startfail_acqent_sz_zero(); return -1; } =20 @@ -1032,14 +1032,14 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, unsigned size) { if (unlikely(offset & (sizeof(uint32_t) - 1))) { - NVME_GUEST_ERR(nvme_ub_mmiowr_misaligned32, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_misaligned32, "MMIO write not 32-bit aligned," " offset=3D0x%"PRIx64"", offset); /* should be ignored, fall through for now */ } =20 if (unlikely(size < sizeof(uint32_t))) { - NVME_GUEST_ERR(nvme_ub_mmiowr_toosmall, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_toosmall, "MMIO write smaller than 32-bits," " offset=3D0x%"PRIx64", size=3D%u", offset, size); @@ -1049,32 +1049,30 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, switch (offset) { case 0xc: /* INTMS */ if (unlikely(msix_enabled(&(n->parent_obj)))) { - NVME_GUEST_ERR(nvme_ub_mmiowr_intmask_with_msix, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix, "undefined access to interrupt mask set" " when MSI-X is enabled"); /* should be ignored, fall through for now */ } n->bar.intms |=3D data & 0xffffffff; n->bar.intmc =3D n->bar.intms; - trace_nvme_mmio_intm_set(data & 0xffffffff, - n->bar.intmc); + trace_pci_nvme_mmio_intm_set(data & 0xffffffff, n->bar.intmc); nvme_irq_check(n); break; case 0x10: /* INTMC */ if (unlikely(msix_enabled(&(n->parent_obj)))) { - NVME_GUEST_ERR(nvme_ub_mmiowr_intmask_with_msix, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix, "undefined access to interrupt mask clr" " when MSI-X is enabled"); /* should be ignored, fall through for now */ } n->bar.intms &=3D ~(data & 0xffffffff); n->bar.intmc =3D n->bar.intms; - trace_nvme_mmio_intm_clr(data & 0xffffffff, - n->bar.intmc); + trace_pci_nvme_mmio_intm_clr(data & 0xffffffff, n->bar.intmc); nvme_irq_check(n); break; case 0x14: /* CC */ - trace_nvme_mmio_cfg(data & 0xffffffff); + trace_pci_nvme_mmio_cfg(data & 0xffffffff); /* Windows first sends data, then sends enable bit */ if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) && !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc)) @@ -1085,42 +1083,42 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, if (NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc)) { n->bar.cc =3D data; if (unlikely(nvme_start_ctrl(n))) { - trace_nvme_err_startfail(); + trace_pci_nvme_err_startfail(); n->bar.csts =3D NVME_CSTS_FAILED; } else { - trace_nvme_mmio_start_success(); + trace_pci_nvme_mmio_start_success(); n->bar.csts =3D NVME_CSTS_READY; } } else if (!NVME_CC_EN(data) && NVME_CC_EN(n->bar.cc)) { - trace_nvme_mmio_stopped(); + trace_pci_nvme_mmio_stopped(); nvme_clear_ctrl(n); n->bar.csts &=3D ~NVME_CSTS_READY; } if (NVME_CC_SHN(data) && !(NVME_CC_SHN(n->bar.cc))) { - trace_nvme_mmio_shutdown_set(); + trace_pci_nvme_mmio_shutdown_set(); nvme_clear_ctrl(n); n->bar.cc =3D data; n->bar.csts |=3D NVME_CSTS_SHST_COMPLETE; } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(n->bar.cc)) { - trace_nvme_mmio_shutdown_cleared(); + trace_pci_nvme_mmio_shutdown_cleared(); n->bar.csts &=3D ~NVME_CSTS_SHST_COMPLETE; n->bar.cc =3D data; } break; case 0x1C: /* CSTS */ if (data & (1 << 4)) { - NVME_GUEST_ERR(nvme_ub_mmiowr_ssreset_w1c_unsupported, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported, "attempted to W1C CSTS.NSSRO" " but CAP.NSSRS is zero (not supported)"); } else if (data !=3D 0) { - NVME_GUEST_ERR(nvme_ub_mmiowr_ro_csts, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ro_csts, "attempted to set a read only bit" " of controller status"); } break; case 0x20: /* NSSR */ if (data =3D=3D 0x4E564D65) { - trace_nvme_ub_mmiowr_ssreset_unsupported(); + trace_pci_nvme_ub_mmiowr_ssreset_unsupported(); } else { /* The spec says that writes of other values have no effect */ return; @@ -1128,55 +1126,55 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, break; case 0x24: /* AQA */ n->bar.aqa =3D data & 0xffffffff; - trace_nvme_mmio_aqattr(data & 0xffffffff); + trace_pci_nvme_mmio_aqattr(data & 0xffffffff); break; case 0x28: /* ASQ */ n->bar.asq =3D data; - trace_nvme_mmio_asqaddr(data); + trace_pci_nvme_mmio_asqaddr(data); break; case 0x2c: /* ASQ hi */ n->bar.asq |=3D data << 32; - trace_nvme_mmio_asqaddr_hi(data, n->bar.asq); + trace_pci_nvme_mmio_asqaddr_hi(data, n->bar.asq); break; case 0x30: /* ACQ */ - trace_nvme_mmio_acqaddr(data); + trace_pci_nvme_mmio_acqaddr(data); n->bar.acq =3D data; break; case 0x34: /* ACQ hi */ n->bar.acq |=3D data << 32; - trace_nvme_mmio_acqaddr_hi(data, n->bar.acq); + trace_pci_nvme_mmio_acqaddr_hi(data, n->bar.acq); break; case 0x38: /* CMBLOC */ - NVME_GUEST_ERR(nvme_ub_mmiowr_cmbloc_reserved, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbloc_reserved, "invalid write to reserved CMBLOC" " when CMBSZ is zero, ignored"); return; case 0x3C: /* CMBSZ */ - NVME_GUEST_ERR(nvme_ub_mmiowr_cmbsz_readonly, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly, "invalid write to read only CMBSZ, ignored"); return; case 0xE00: /* PMRCAP */ - NVME_GUEST_ERR(nvme_ub_mmiowr_pmrcap_readonly, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly, "invalid write to PMRCAP register, ignored"); return; case 0xE04: /* TODO PMRCTL */ break; case 0xE08: /* PMRSTS */ - NVME_GUEST_ERR(nvme_ub_mmiowr_pmrsts_readonly, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrsts_readonly, "invalid write to PMRSTS register, ignored"); return; case 0xE0C: /* PMREBS */ - NVME_GUEST_ERR(nvme_ub_mmiowr_pmrebs_readonly, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrebs_readonly, "invalid write to PMREBS register, ignored"); return; case 0xE10: /* PMRSWTP */ - NVME_GUEST_ERR(nvme_ub_mmiowr_pmrswtp_readonly, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly, "invalid write to PMRSWTP register, ignored"); return; case 0xE14: /* TODO PMRMSC */ break; default: - NVME_GUEST_ERR(nvme_ub_mmiowr_invalid, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid, "invalid MMIO write," " offset=3D0x%"PRIx64", data=3D%"PRIx64"", offset, data); @@ -1191,12 +1189,12 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr= addr, unsigned size) uint64_t val =3D 0; =20 if (unlikely(addr & (sizeof(uint32_t) - 1))) { - NVME_GUEST_ERR(nvme_ub_mmiord_misaligned32, + NVME_GUEST_ERR(pci_nvme_ub_mmiord_misaligned32, "MMIO read not 32-bit aligned," " offset=3D0x%"PRIx64"", addr); /* should RAZ, fall through for now */ } else if (unlikely(size < sizeof(uint32_t))) { - NVME_GUEST_ERR(nvme_ub_mmiord_toosmall, + NVME_GUEST_ERR(pci_nvme_ub_mmiord_toosmall, "MMIO read smaller than 32-bits," " offset=3D0x%"PRIx64"", addr); /* should RAZ, fall through for now */ @@ -1215,7 +1213,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr a= ddr, unsigned size) } memcpy(&val, ptr + addr, size); } else { - NVME_GUEST_ERR(nvme_ub_mmiord_invalid_ofs, + NVME_GUEST_ERR(pci_nvme_ub_mmiord_invalid_ofs, "MMIO read beyond last register," " offset=3D0x%"PRIx64", returning 0", addr); } @@ -1228,7 +1226,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) uint32_t qid; =20 if (unlikely(addr & ((1 << 2) - 1))) { - NVME_GUEST_ERR(nvme_ub_db_wr_misaligned, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned, "doorbell write not 32-bit aligned," " offset=3D0x%"PRIx64", ignoring", addr); return; @@ -1243,7 +1241,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 qid =3D (addr - (0x1000 + (1 << 2))) >> 3; if (unlikely(nvme_check_cqid(n, qid))) { - NVME_GUEST_ERR(nvme_ub_db_wr_invalid_cq, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cq, "completion queue doorbell write" " for nonexistent queue," " sqid=3D%"PRIu32", ignoring", qid); @@ -1252,7 +1250,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 cq =3D n->cq[qid]; if (unlikely(new_head >=3D cq->size)) { - NVME_GUEST_ERR(nvme_ub_db_wr_invalid_cqhead, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cqhead, "completion queue doorbell write value" " beyond queue size, sqid=3D%"PRIu32"," " new_head=3D%"PRIu16", ignoring", @@ -1281,7 +1279,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 qid =3D (addr - 0x1000) >> 3; if (unlikely(nvme_check_sqid(n, qid))) { - NVME_GUEST_ERR(nvme_ub_db_wr_invalid_sq, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sq, "submission queue doorbell write" " for nonexistent queue," " sqid=3D%"PRIu32", ignoring", qid); @@ -1290,7 +1288,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 sq =3D n->sq[qid]; if (unlikely(new_tail >=3D sq->size)) { - NVME_GUEST_ERR(nvme_ub_db_wr_invalid_sqtail, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sqtail, "submission queue doorbell write value" " beyond queue size, sqid=3D%"PRIu32"," " new_tail=3D%"PRIu16", ignoring", diff --git a/hw/block/trace-events b/hw/block/trace-events index aca54bda1423..958fcc5508d1 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -29,100 +29,100 @@ hd_geometry_guess(void *blk, uint32_t cyls, uint32_t = heads, uint32_t secs, int t =20 # nvme.c # nvme traces for successful events -nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u" -nvme_irq_pin(void) "pulsing IRQ pin" -nvme_irq_masked(void) "IRQ is masked" -nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=3D0x%"PRIx64" = prp2=3D0x%"PRIx64"" -nvme_rw(const char *verb, uint32_t blk_count, uint64_t byte_count, uint64_= t lba) "%s %"PRIu32" blocks (%"PRIu64" bytes) from LBA %"PRIu64"" -nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t qsize= , uint16_t qflags) "create submission queue, addr=3D0x%"PRIx64", sqid=3D%"P= RIu16", cqid=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRIu16"" -nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t siz= e, uint16_t qflags, int ien) "create completion queue, addr=3D0x%"PRIx64", = cqid=3D%"PRIu16", vector=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRIu16"= , ien=3D%d" -nvme_del_sq(uint16_t qid) "deleting submission queue sqid=3D%"PRIu16"" -nvme_del_cq(uint16_t cqid) "deleted completion queue, cqid=3D%"PRIu16"" -nvme_identify_ctrl(void) "identify controller" -nvme_identify_ns(uint16_t ns) "identify namespace, nsid=3D%"PRIu16"" -nvme_identify_nslist(uint16_t ns) "identify namespace list, nsid=3D%"PRIu1= 6"" -nvme_getfeat_vwcache(const char* result) "get feature volatile write cache= , result=3D%s" -nvme_getfeat_numq(int result) "get feature number of queues, result=3D%d" -nvme_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "requested c= q_count=3D%d sq_count=3D%d, responding with cq_count=3D%d sq_count=3D%d" -nvme_setfeat_timestamp(uint64_t ts) "set feature timestamp =3D 0x%"PRIx64"" -nvme_getfeat_timestamp(uint64_t ts) "get feature timestamp =3D 0x%"PRIx64"" -nvme_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, interrup= t mask set, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" -nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, interrup= t mask clr, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" -nvme_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=3D0x%"P= RIx64"" -nvme_mmio_aqattr(uint64_t data) "wrote MMIO, admin queue attributes=3D0x%"= PRIx64"" -nvme_mmio_asqaddr(uint64_t data) "wrote MMIO, admin submission queue addre= ss=3D0x%"PRIx64"" -nvme_mmio_acqaddr(uint64_t data) "wrote MMIO, admin completion queue addre= ss=3D0x%"PRIx64"" -nvme_mmio_asqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, admin = submission queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" -nvme_mmio_acqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, admin = completion queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" -nvme_mmio_start_success(void) "setting controller enable bit succeeded" -nvme_mmio_stopped(void) "cleared controller enable bit" -nvme_mmio_shutdown_set(void) "shutdown bit set" -nvme_mmio_shutdown_cleared(void) "shutdown bit cleared" +pci_nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u" +pci_nvme_irq_pin(void) "pulsing IRQ pin" +pci_nvme_irq_masked(void) "IRQ is masked" +pci_nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=3D0x%"PRIx= 64" prp2=3D0x%"PRIx64"" +pci_nvme_rw(const char *verb, uint32_t blk_count, uint64_t byte_count, uin= t64_t lba) "%s %"PRIu32" blocks (%"PRIu64" bytes) from LBA %"PRIu64"" +pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t q= size, uint16_t qflags) "create submission queue, addr=3D0x%"PRIx64", sqid= =3D%"PRIu16", cqid=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRIu16"" +pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t= size, uint16_t qflags, int ien) "create completion queue, addr=3D0x%"PRIx6= 4", cqid=3D%"PRIu16", vector=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRI= u16", ien=3D%d" +pci_nvme_del_sq(uint16_t qid) "deleting submission queue sqid=3D%"PRIu16"" +pci_nvme_del_cq(uint16_t cqid) "deleted completion queue, cqid=3D%"PRIu16"" +pci_nvme_identify_ctrl(void) "identify controller" +pci_nvme_identify_ns(uint16_t ns) "identify namespace, nsid=3D%"PRIu16"" +pci_nvme_identify_nslist(uint16_t ns) "identify namespace list, nsid=3D%"P= RIu16"" +pci_nvme_getfeat_vwcache(const char* result) "get feature volatile write c= ache, result=3D%s" +pci_nvme_getfeat_numq(int result) "get feature number of queues, result=3D= %d" +pci_nvme_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "request= ed cq_count=3D%d sq_count=3D%d, responding with cq_count=3D%d sq_count=3D%d" +pci_nvme_setfeat_timestamp(uint64_t ts) "set feature timestamp =3D 0x%"PRI= x64"" +pci_nvme_getfeat_timestamp(uint64_t ts) "get feature timestamp =3D 0x%"PRI= x64"" +pci_nvme_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, inte= rrupt mask set, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" +pci_nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, inte= rrupt mask clr, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" +pci_nvme_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=3D0= x%"PRIx64"" +pci_nvme_mmio_aqattr(uint64_t data) "wrote MMIO, admin queue attributes=3D= 0x%"PRIx64"" +pci_nvme_mmio_asqaddr(uint64_t data) "wrote MMIO, admin submission queue a= ddress=3D0x%"PRIx64"" +pci_nvme_mmio_acqaddr(uint64_t data) "wrote MMIO, admin completion queue a= ddress=3D0x%"PRIx64"" +pci_nvme_mmio_asqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, ad= min submission queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" +pci_nvme_mmio_acqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, ad= min completion queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" +pci_nvme_mmio_start_success(void) "setting controller enable bit succeeded" +pci_nvme_mmio_stopped(void) "cleared controller enable bit" +pci_nvme_mmio_shutdown_set(void) "shutdown bit set" +pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared" =20 # nvme traces for error conditions -nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size" -nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null or = not page aligned: 0x%"PRIx64"" -nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: 0x%"= PRIx64"" -nvme_err_invalid_prp2_missing(void) "PRP2 is null and more data to be tran= sferred" -nvme_err_invalid_prp(void) "invalid PRP" -nvme_err_invalid_ns(uint32_t ns, uint32_t limit) "invalid namespace %u not= within 1-%u" -nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" -nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx8"" -nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limit) "= Invalid LBA start=3D%"PRIu64" len=3D%"PRIu64" limit=3D%"PRIu64"" -nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deletion, = sid=3D%"PRIu16"" -nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submission= queue, invalid cqid=3D%"PRIu16"" -nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating submission= queue, invalid sqid=3D%"PRIu16"" -nvme_err_invalid_create_sq_size(uint16_t qsize) "failed creating submissio= n queue, invalid qsize=3D%"PRIu16"" -nvme_err_invalid_create_sq_addr(uint64_t addr) "failed creating submission= queue, addr=3D0x%"PRIx64"" -nvme_err_invalid_create_sq_qflags(uint16_t qflags) "failed creating submis= sion queue, qflags=3D%"PRIu16"" -nvme_err_invalid_del_cq_cqid(uint16_t cqid) "failed deleting completion qu= eue, cqid=3D%"PRIu16"" -nvme_err_invalid_del_cq_notempty(uint16_t cqid) "failed deleting completio= n queue, it is not empty, cqid=3D%"PRIu16"" -nvme_err_invalid_create_cq_cqid(uint16_t cqid) "failed creating completion= queue, cqid=3D%"PRIu16"" -nvme_err_invalid_create_cq_size(uint16_t size) "failed creating completion= queue, size=3D%"PRIu16"" -nvme_err_invalid_create_cq_addr(uint64_t addr) "failed creating completion= queue, addr=3D0x%"PRIx64"" -nvme_err_invalid_create_cq_vector(uint16_t vector) "failed creating comple= tion queue, vector=3D%"PRIu16"" -nvme_err_invalid_create_cq_qflags(uint16_t qflags) "failed creating comple= tion queue, qflags=3D%"PRIu16"" -nvme_err_invalid_identify_cns(uint16_t cns) "identify, invalid cns=3D0x%"P= RIx16"" -nvme_err_invalid_getfeat(int dw10) "invalid get features, dw10=3D0x%"PRIx3= 2"" -nvme_err_invalid_setfeat(uint32_t dw10) "invalid set features, dw10=3D0x%"= PRIx32"" -nvme_err_startfail_cq(void) "nvme_start_ctrl failed because there are non-= admin completion queues" -nvme_err_startfail_sq(void) "nvme_start_ctrl failed because there are non-= admin submission queues" -nvme_err_startfail_nbarasq(void) "nvme_start_ctrl failed because the admin= submission queue address is null" -nvme_err_startfail_nbaracq(void) "nvme_start_ctrl failed because the admin= completion queue address is null" -nvme_err_startfail_asq_misaligned(uint64_t addr) "nvme_start_ctrl failed b= ecause the admin submission queue address is misaligned: 0x%"PRIx64"" -nvme_err_startfail_acq_misaligned(uint64_t addr) "nvme_start_ctrl failed b= ecause the admin completion queue address is misaligned: 0x%"PRIx64"" -nvme_err_startfail_page_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvme= _start_ctrl failed because the page size is too small: log2size=3D%u, min= =3D%u" -nvme_err_startfail_page_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvme= _start_ctrl failed because the page size is too large: log2size=3D%u, max= =3D%u" -nvme_err_startfail_cqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvm= e_start_ctrl failed because the completion queue entry size is too small: l= og2size=3D%u, min=3D%u" -nvme_err_startfail_cqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvm= e_start_ctrl failed because the completion queue entry size is too large: l= og2size=3D%u, max=3D%u" -nvme_err_startfail_sqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvm= e_start_ctrl failed because the submission queue entry size is too small: l= og2size=3D%u, min=3D%u" -nvme_err_startfail_sqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvm= e_start_ctrl failed because the submission queue entry size is too large: l= og2size=3D%u, max=3D%u" -nvme_err_startfail_asqent_sz_zero(void) "nvme_start_ctrl failed because th= e admin submission queue size is zero" -nvme_err_startfail_acqent_sz_zero(void) "nvme_start_ctrl failed because th= e admin completion queue size is zero" -nvme_err_startfail(void) "setting controller enable bit failed" +pci_nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size" +pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null= or not page aligned: 0x%"PRIx64"" +pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: = 0x%"PRIx64"" +pci_nvme_err_invalid_prp2_missing(void) "PRP2 is null and more data to be = transferred" +pci_nvme_err_invalid_prp(void) "invalid PRP" +pci_nvme_err_invalid_ns(uint32_t ns, uint32_t limit) "invalid namespace %u= not within 1-%u" +pci_nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" +pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx= 8"" +pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limi= t) "Invalid LBA start=3D%"PRIu64" len=3D%"PRIu64" limit=3D%"PRIu64"" +pci_nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deleti= on, sid=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submis= sion queue, invalid cqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating submis= sion queue, invalid sqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_size(uint16_t qsize) "failed creating submi= ssion queue, invalid qsize=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_addr(uint64_t addr) "failed creating submis= sion queue, addr=3D0x%"PRIx64"" +pci_nvme_err_invalid_create_sq_qflags(uint16_t qflags) "failed creating su= bmission queue, qflags=3D%"PRIu16"" +pci_nvme_err_invalid_del_cq_cqid(uint16_t cqid) "failed deleting completio= n queue, cqid=3D%"PRIu16"" +pci_nvme_err_invalid_del_cq_notempty(uint16_t cqid) "failed deleting compl= etion queue, it is not empty, cqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_cqid(uint16_t cqid) "failed creating comple= tion queue, cqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_size(uint16_t size) "failed creating comple= tion queue, size=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_addr(uint64_t addr) "failed creating comple= tion queue, addr=3D0x%"PRIx64"" +pci_nvme_err_invalid_create_cq_vector(uint16_t vector) "failed creating co= mpletion queue, vector=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_qflags(uint16_t qflags) "failed creating co= mpletion queue, qflags=3D%"PRIu16"" +pci_nvme_err_invalid_identify_cns(uint16_t cns) "identify, invalid cns=3D0= x%"PRIx16"" +pci_nvme_err_invalid_getfeat(int dw10) "invalid get features, dw10=3D0x%"P= RIx32"" +pci_nvme_err_invalid_setfeat(uint32_t dw10) "invalid set features, dw10=3D= 0x%"PRIx32"" +pci_nvme_err_startfail_cq(void) "nvme_start_ctrl failed because there are = non-admin completion queues" +pci_nvme_err_startfail_sq(void) "nvme_start_ctrl failed because there are = non-admin submission queues" +pci_nvme_err_startfail_nbarasq(void) "nvme_start_ctrl failed because the a= dmin submission queue address is null" +pci_nvme_err_startfail_nbaracq(void) "nvme_start_ctrl failed because the a= dmin completion queue address is null" +pci_nvme_err_startfail_asq_misaligned(uint64_t addr) "nvme_start_ctrl fail= ed because the admin submission queue address is misaligned: 0x%"PRIx64"" +pci_nvme_err_startfail_acq_misaligned(uint64_t addr) "nvme_start_ctrl fail= ed because the admin completion queue address is misaligned: 0x%"PRIx64"" +pci_nvme_err_startfail_page_too_small(uint8_t log2ps, uint8_t maxlog2ps) "= nvme_start_ctrl failed because the page size is too small: log2size=3D%u, m= in=3D%u" +pci_nvme_err_startfail_page_too_large(uint8_t log2ps, uint8_t maxlog2ps) "= nvme_start_ctrl failed because the page size is too large: log2size=3D%u, m= ax=3D%u" +pci_nvme_err_startfail_cqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the completion queue entry size is too smal= l: log2size=3D%u, min=3D%u" +pci_nvme_err_startfail_cqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the completion queue entry size is too larg= e: log2size=3D%u, max=3D%u" +pci_nvme_err_startfail_sqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the submission queue entry size is too smal= l: log2size=3D%u, min=3D%u" +pci_nvme_err_startfail_sqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the submission queue entry size is too larg= e: log2size=3D%u, max=3D%u" +pci_nvme_err_startfail_asqent_sz_zero(void) "nvme_start_ctrl failed becaus= e the admin submission queue size is zero" +pci_nvme_err_startfail_acqent_sz_zero(void) "nvme_start_ctrl failed becaus= e the admin completion queue size is zero" +pci_nvme_err_startfail(void) "setting controller enable bit failed" =20 # Traces for undefined behavior -nvme_ub_mmiowr_misaligned32(uint64_t offset) "MMIO write not 32-bit aligne= d, offset=3D0x%"PRIx64"" -nvme_ub_mmiowr_toosmall(uint64_t offset, unsigned size) "MMIO write smalle= r than 32 bits, offset=3D0x%"PRIx64", size=3D%u" -nvme_ub_mmiowr_intmask_with_msix(void) "undefined access to interrupt mask= set when MSI-X is enabled" -nvme_ub_mmiowr_ro_csts(void) "attempted to set a read only bit of controll= er status" -nvme_ub_mmiowr_ssreset_w1c_unsupported(void) "attempted to W1C CSTS.NSSRO = but CAP.NSSRS is zero (not supported)" -nvme_ub_mmiowr_ssreset_unsupported(void) "attempted NVM subsystem reset bu= t CAP.NSSRS is zero (not supported)" -nvme_ub_mmiowr_cmbloc_reserved(void) "invalid write to reserved CMBLOC whe= n CMBSZ is zero, ignored" -nvme_ub_mmiowr_cmbsz_readonly(void) "invalid write to read only CMBSZ, ign= ored" -nvme_ub_mmiowr_pmrcap_readonly(void) "invalid write to read only PMRCAP, i= gnored" -nvme_ub_mmiowr_pmrsts_readonly(void) "invalid write to read only PMRSTS, i= gnored" -nvme_ub_mmiowr_pmrebs_readonly(void) "invalid write to read only PMREBS, i= gnored" -nvme_ub_mmiowr_pmrswtp_readonly(void) "invalid write to read only PMRSWTP,= ignored" -nvme_ub_mmiowr_invalid(uint64_t offset, uint64_t data) "invalid MMIO write= , offset=3D0x%"PRIx64", data=3D0x%"PRIx64"" -nvme_ub_mmiord_misaligned32(uint64_t offset) "MMIO read not 32-bit aligned= , offset=3D0x%"PRIx64"" -nvme_ub_mmiord_toosmall(uint64_t offset) "MMIO read smaller than 32-bits, = offset=3D0x%"PRIx64"" -nvme_ub_mmiord_invalid_ofs(uint64_t offset) "MMIO read beyond last registe= r, offset=3D0x%"PRIx64", returning 0" -nvme_ub_db_wr_misaligned(uint64_t offset) "doorbell write not 32-bit align= ed, offset=3D0x%"PRIx64", ignoring" -nvme_ub_db_wr_invalid_cq(uint32_t qid) "completion queue doorbell write fo= r nonexistent queue, cqid=3D%"PRIu32", ignoring" -nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t new_head) "completion = queue doorbell write value beyond queue size, cqid=3D%"PRIu32", new_head=3D= %"PRIu16", ignoring" -nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell write fo= r nonexistent queue, sqid=3D%"PRIu32", ignoring" -nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail) "submission = queue doorbell write value beyond queue size, sqid=3D%"PRIu32", new_head=3D= %"PRIu16", ignoring" +pci_nvme_ub_mmiowr_misaligned32(uint64_t offset) "MMIO write not 32-bit al= igned, offset=3D0x%"PRIx64"" +pci_nvme_ub_mmiowr_toosmall(uint64_t offset, unsigned size) "MMIO write sm= aller than 32 bits, offset=3D0x%"PRIx64", size=3D%u" +pci_nvme_ub_mmiowr_intmask_with_msix(void) "undefined access to interrupt = mask set when MSI-X is enabled" +pci_nvme_ub_mmiowr_ro_csts(void) "attempted to set a read only bit of cont= roller status" +pci_nvme_ub_mmiowr_ssreset_w1c_unsupported(void) "attempted to W1C CSTS.NS= SRO but CAP.NSSRS is zero (not supported)" +pci_nvme_ub_mmiowr_ssreset_unsupported(void) "attempted NVM subsystem rese= t but CAP.NSSRS is zero (not supported)" +pci_nvme_ub_mmiowr_cmbloc_reserved(void) "invalid write to reserved CMBLOC= when CMBSZ is zero, ignored" +pci_nvme_ub_mmiowr_cmbsz_readonly(void) "invalid write to read only CMBSZ,= ignored" +pci_nvme_ub_mmiowr_pmrcap_readonly(void) "invalid write to read only PMRCA= P, ignored" +pci_nvme_ub_mmiowr_pmrsts_readonly(void) "invalid write to read only PMRST= S, ignored" +pci_nvme_ub_mmiowr_pmrebs_readonly(void) "invalid write to read only PMREB= S, ignored" +pci_nvme_ub_mmiowr_pmrswtp_readonly(void) "invalid write to read only PMRS= WTP, ignored" +pci_nvme_ub_mmiowr_invalid(uint64_t offset, uint64_t data) "invalid MMIO w= rite, offset=3D0x%"PRIx64", data=3D0x%"PRIx64"" +pci_nvme_ub_mmiord_misaligned32(uint64_t offset) "MMIO read not 32-bit ali= gned, offset=3D0x%"PRIx64"" +pci_nvme_ub_mmiord_toosmall(uint64_t offset) "MMIO read smaller than 32-bi= ts, offset=3D0x%"PRIx64"" +pci_nvme_ub_mmiord_invalid_ofs(uint64_t offset) "MMIO read beyond last reg= ister, offset=3D0x%"PRIx64", returning 0" +pci_nvme_ub_db_wr_misaligned(uint64_t offset) "doorbell write not 32-bit a= ligned, offset=3D0x%"PRIx64", ignoring" +pci_nvme_ub_db_wr_invalid_cq(uint32_t qid) "completion queue doorbell writ= e for nonexistent queue, cqid=3D%"PRIu32", ignoring" +pci_nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t new_head) "complet= ion queue doorbell write value beyond queue size, cqid=3D%"PRIu32", new_hea= d=3D%"PRIu16", ignoring" +pci_nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell writ= e for nonexistent queue, sqid=3D%"PRIu32", ignoring" +pci_nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail) "submiss= ion queue doorbell write value beyond queue size, sqid=3D%"PRIu32", new_hea= d=3D%"PRIu16", ignoring" =20 # xen-block.c xen_block_realize(const char *type, uint32_t disk, uint32_t partition) "%s= d%up%u" --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588657846; cv=none; d=zohomail.com; s=zohoarc; b=V6lZawtnN0AuDKgIZsntwCnO3EQbmFsRvT33RLLIKf4AHzpAVGj3W3qwbFnqUh8hILhOWgFFwOFXlLhYr7ytHlrFM7rs5RjeDCn0gcPj5Jp4UoQjJ7LfJ+vPRLY3HHUnwP4g/fljo35mPWAPKKVTKXw30ZR0YJoFlVG1ZcoYRRA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588657846; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zHxqzvvMJ7RxZfYkagKk2nOjtJ1N06XByFt3MACfKR4=; b=RO4uexOY3E2v4hlrrvXO1QlDJXfjyi1E1PHsiC6w1EAglBp1e1VLMdwL4yVs+H/1W8einUxf7iwqQZeJDhqKUzUSZHlHwa4dm4vRAXPmBIS6cH6ufIXGmARb0hsP8eo4lsP1zR7o8v+++4HNQim2ybI1HiHivihwk7WFXGm1+No= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588657846727545.8721056702094; Mon, 4 May 2020 22:50:46 -0700 (PDT) Received: from localhost ([::1]:58614 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jVqTd-0000bj-9M for importer@patchew.org; Tue, 05 May 2020 01:50:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS5-00072S-Rr; Tue, 05 May 2020 01:49:09 -0400 Received: from charlie.dont.surf ([128.199.63.193]:56262) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS2-0005CQ-QP; Tue, 05 May 2020 01:49:09 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id E7DBEBFAF0; Tue, 5 May 2020 05:49:04 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 03/18] nvme: remove superfluous breaks Date: Tue, 5 May 2020 07:48:25 +0200 Message-Id: <20200505054840.186586-4-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen These break statements was left over when commit 3036a626e9ef ("nvme: add Get/Set Feature Timestamp support") was merged. Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Keith Busch --- hw/block/nvme.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 6702812ecdd1..f67499d85f3a 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -802,7 +802,6 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) break; case NVME_TIMESTAMP: return nvme_get_feature_timestamp(n, cmd); - break; default: trace_pci_nvme_err_invalid_getfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; @@ -846,11 +845,8 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd = *cmd, NvmeRequest *req) req->cqe.result =3D cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16)); break; - case NVME_TIMESTAMP: return nvme_set_feature_timestamp(n, cmd); - break; - default: trace_pci_nvme_err_invalid_setfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588657878; cv=none; d=zohomail.com; s=zohoarc; b=mRy3JFakhQGeuj2NdF/eHWQxLbBk/5trAikujrSN5XTIlRxXsWWWeZmVkpZNhJ2Gy+8h223jbDQ2Bya7q0U2c99iaqzP6XDA89eVvfBqo0M0U6doUQg8HXjIDE9BBozB3D9WVtV5r6tXM0MF+EVz9K/exY9QlgbjsLzFtByIvfI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588657878; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8Tt9P1sB40S7nVsH8HMKl38hY8RIq+4IacqHTkiR4FM=; b=lVxDb+1qRLb0A2T/uC1fpLI2mAgVqZCcifzDcTLadmtu0xSHdtFuTKz/XYKLCsyzytGUUaGc7Dq5lJP+71hNq6hGdQJkJV+ubuG3xgUChFY7iVi5F2Wt84o60OuemR/bivfS0KHF6mEllWCnZ80DrYRAkFA01W3x7YyY/872Rvg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588657878724480.6366775670632; Mon, 4 May 2020 22:51:18 -0700 (PDT) Received: from localhost ([::1]:33356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jVqU9-00021I-Er for importer@patchew.org; Tue, 05 May 2020 01:51:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53556) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS7-00072n-Ah; Tue, 05 May 2020 01:49:11 -0400 Received: from charlie.dont.surf ([128.199.63.193]:56266) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS3-0005CY-0g; Tue, 05 May 2020 01:49:11 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 56B2FBFAF2; Tue, 5 May 2020 05:49:05 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 04/18] nvme: move device parameters to separate struct Date: Tue, 5 May 2020 07:48:26 +0200 Message-Id: <20200505054840.186586-5-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Move device configuration parameters to separate struct to make it explicit what is configurable and what is set internally. Signed-off-by: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky --- hw/block/nvme.c | 49 ++++++++++++++++++++++++++----------------------- hw/block/nvme.h | 11 ++++++++--- 2 files changed, 34 insertions(+), 26 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index f67499d85f3a..e26db7591574 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -78,12 +78,12 @@ static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, vo= id *buf, int size) =20 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) { - return sqid < n->num_queues && n->sq[sqid] !=3D NULL ? 0 : -1; + return sqid < n->params.num_queues && n->sq[sqid] !=3D NULL ? 0 : -1; } =20 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid) { - return cqid < n->num_queues && n->cq[cqid] !=3D NULL ? 0 : -1; + return cqid < n->params.num_queues && n->cq[cqid] !=3D NULL ? 0 : -1; } =20 static void nvme_inc_cq_tail(NvmeCQueue *cq) @@ -645,7 +645,7 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cm= d) trace_pci_nvme_err_invalid_create_cq_addr(prp1); return NVME_INVALID_FIELD | NVME_DNR; } - if (unlikely(vector > n->num_queues)) { + if (unlikely(vector > n->params.num_queues)) { trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } @@ -797,7 +797,8 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); break; case NVME_NUMBER_OF_QUEUES: - result =3D cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) = << 16)); + result =3D cpu_to_le32((n->params.num_queues - 2) | + ((n->params.num_queues - 2) << 16)); trace_pci_nvme_getfeat_numq(result); break; case NVME_TIMESTAMP: @@ -841,9 +842,10 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd = *cmd, NvmeRequest *req) case NVME_NUMBER_OF_QUEUES: trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, ((dw11 >> 16) & 0xFFFF) + 1, - n->num_queues - 1, n->num_queues - 1); - req->cqe.result =3D - cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16)); + n->params.num_queues - 1, + n->params.num_queues - 1); + req->cqe.result =3D cpu_to_le32((n->params.num_queues - 2) | + ((n->params.num_queues - 2) << 16)); break; case NVME_TIMESTAMP: return nvme_set_feature_timestamp(n, cmd); @@ -914,12 +916,12 @@ static void nvme_clear_ctrl(NvmeCtrl *n) =20 blk_drain(n->conf.blk); =20 - for (i =3D 0; i < n->num_queues; i++) { + for (i =3D 0; i < n->params.num_queues; i++) { if (n->sq[i] !=3D NULL) { nvme_free_sq(n->sq[i], n); } } - for (i =3D 0; i < n->num_queues; i++) { + for (i =3D 0; i < n->params.num_queues; i++) { if (n->cq[i] !=3D NULL) { nvme_free_cq(n->cq[i], n); } @@ -1350,7 +1352,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) int64_t bs_size; uint8_t *pci_conf; =20 - if (!n->num_queues) { + if (!n->params.num_queues) { error_setg(errp, "num_queues can't be zero"); return; } @@ -1366,12 +1368,12 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) return; } =20 - if (!n->serial) { + if (!n->params.serial) { error_setg(errp, "serial property not set"); return; } =20 - if (!n->cmb_size_mb && n->pmrdev) { + if (!n->params.cmb_size_mb && n->pmrdev) { if (host_memory_backend_is_mapped(n->pmrdev)) { char *path =3D object_get_canonical_path_component(OBJECT(n->p= mrdev)); error_setg(errp, "can't use already busy memdev: %s", path); @@ -1402,25 +1404,26 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) n->num_namespaces =3D 1; =20 /* num_queues is really number of pairs, so each has two doorbells */ - n->reg_size =3D pow2ceil(NVME_REG_SIZE + 2 * n->num_queues * NVME_DB_S= IZE); + n->reg_size =3D pow2ceil(NVME_REG_SIZE + + 2 * n->params.num_queues * NVME_DB_SIZE); n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; =20 n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); - n->sq =3D g_new0(NvmeSQueue *, n->num_queues); - n->cq =3D g_new0(NvmeCQueue *, n->num_queues); + n->sq =3D g_new0(NvmeSQueue *, n->params.num_queues); + n->cq =3D g_new0(NvmeCQueue *, n->params.num_queues); =20 memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); - msix_init_exclusive_bar(pci_dev, n->num_queues, 4, NULL); + msix_init_exclusive_bar(pci_dev, n->params.num_queues, 4, NULL); =20 id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' '); - strpadcpy((char *)id->sn, sizeof(id->sn), n->serial, ' '); + strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' '); id->rab =3D 6; id->ieee[0] =3D 0x00; id->ieee[1] =3D 0x02; @@ -1449,7 +1452,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) n->bar.vs =3D 0x00010200; n->bar.intmc =3D n->bar.intms =3D 0; =20 - if (n->cmb_size_mb) { + if (n->params.cmb_size_mb) { =20 NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2); NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); @@ -1460,7 +1463,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1); NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ - NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->cmb_size_mb); + NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); =20 n->cmbloc =3D n->bar.cmbloc; n->cmbsz =3D n->bar.cmbsz; @@ -1544,7 +1547,7 @@ static void nvme_exit(PCIDevice *pci_dev) g_free(n->cq); g_free(n->sq); =20 - if (n->cmb_size_mb) { + if (n->params.cmb_size_mb) { g_free(n->cmbuf); } =20 @@ -1558,9 +1561,9 @@ static Property nvme_props[] =3D { DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf), DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmrdev, TYPE_MEMORY_BACKEND, HostMemoryBackend *), - DEFINE_PROP_STRING("serial", NvmeCtrl, serial), - DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, cmb_size_mb, 0), - DEFINE_PROP_UINT32("num_queues", NvmeCtrl, num_queues, 64), + DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial), + DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, params.cmb_size_mb, 0), + DEFINE_PROP_UINT32("num_queues", NvmeCtrl, params.num_queues, 64), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 6520a9f0bead..9df244c93c02 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -1,7 +1,14 @@ #ifndef HW_NVME_H #define HW_NVME_H + #include "block/nvme.h" =20 +typedef struct NvmeParams { + char *serial; + uint32_t num_queues; + uint32_t cmb_size_mb; +} NvmeParams; + typedef struct NvmeAsyncEvent { QSIMPLEQ_ENTRY(NvmeAsyncEvent) entry; NvmeAerResult result; @@ -63,6 +70,7 @@ typedef struct NvmeCtrl { MemoryRegion ctrl_mem; NvmeBar bar; BlockConf conf; + NvmeParams params; =20 uint32_t page_size; uint16_t page_bits; @@ -71,10 +79,8 @@ typedef struct NvmeCtrl { uint16_t sqe_size; uint32_t reg_size; uint32_t num_namespaces; - uint32_t num_queues; uint32_t max_q_ents; uint64_t ns_size; - uint32_t cmb_size_mb; uint32_t cmbsz; uint32_t cmbloc; uint8_t *cmbuf; @@ -82,7 +88,6 @@ typedef struct NvmeCtrl { uint64_t host_timestamp; /* Timestamp sent by the h= ost */ uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */ =20 - char *serial; HostMemoryBackend *pmrdev; =20 NvmeNamespace *namespaces; --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Mon, 4 May 2020 22:52:31 -0700 (PDT) Received: from localhost ([::1]:40372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jVqVK-0004rG-I8 for importer@patchew.org; Tue, 05 May 2020 01:52:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS8-00075I-Eg; Tue, 05 May 2020 01:49:12 -0400 Received: from charlie.dont.surf ([128.199.63.193]:56332) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS7-0005D7-Ac; Tue, 05 May 2020 01:49:12 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id BD440BFB2B; Tue, 5 May 2020 05:49:05 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 05/18] nvme: use constants in identify Date: Tue, 5 May 2020 07:48:27 +0200 Message-Id: <20200505054840.186586-6-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Keith Busch --- hw/block/nvme.c | 8 ++++---- include/block/nvme.h | 8 ++++++++ 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index e26db7591574..4058f2c79796 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -693,7 +693,7 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdent= ify *c) =20 static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c) { - static const int data_len =3D 4 * KiB; + static const int data_len =3D NVME_IDENTIFY_DATA_SIZE; uint32_t min_nsid =3D le32_to_cpu(c->nsid); uint64_t prp1 =3D le64_to_cpu(c->prp1); uint64_t prp2 =3D le64_to_cpu(c->prp2); @@ -723,11 +723,11 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *c= md) NvmeIdentify *c =3D (NvmeIdentify *)cmd; =20 switch (le32_to_cpu(c->cns)) { - case 0x00: + case NVME_ID_CNS_NS: return nvme_identify_ns(n, c); - case 0x01: + case NVME_ID_CNS_CTRL: return nvme_identify_ctrl(n, c); - case 0x02: + case NVME_ID_CNS_NS_ACTIVE_LIST: return nvme_identify_nslist(n, c); default: trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns)); diff --git a/include/block/nvme.h b/include/block/nvme.h index 5525c8e34308..1720ee1d5158 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -705,6 +705,14 @@ typedef struct NvmePSD { uint8_t resv[16]; } NvmePSD; =20 +#define NVME_IDENTIFY_DATA_SIZE 4096 + +enum { + NVME_ID_CNS_NS =3D 0x0, + NVME_ID_CNS_CTRL =3D 0x1, + NVME_ID_CNS_NS_ACTIVE_LIST =3D 0x2, +}; + typedef struct NvmeIdCtrl { uint16_t vid; uint16_t ssvid; --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588657939; cv=none; d=zohomail.com; s=zohoarc; b=epqNyyMlruZp98glR3rIEoJzQVM9M1mVyHA1fJBjWOQe1cCuC7Wc6j2mAyEFC+IAW3/DLxWCF2CjNjpTJwrFAkueVbiZQOfn23FzZZ6Ks675MDjFQg2zNOQJb29ok3khgJAcljDdE1GhfdiDtVzi8NcKlUscmzoRaTVrxox3Asw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588657939; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uGkxJ7mUobUpNOAT/x26NIa5I+g+5TFGemUPAgmqJk8=; b=nNpLAUp2x4u4oIWMFt1XZgHqfsi+7wY7Wd6CdgkqxSeJPMy5JOL49HbOsQ+EYBgR0/1u41n2W8P5/YFVaR4zMOdibal36VmgaVRogdH+aZWhVfaJCWSsxp4DQNKurW4KuvVA39bnNjhj5eZMM9Q/Lxv5Vk1cNIhuOV2qdCo655w= ARC-Authentication-Results: i=1; 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Tue, 5 May 2020 05:49:06 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 06/18] nvme: refactor nvme_addr_read Date: Tue, 5 May 2020 07:48:28 +0200 Message-Id: <20200505054840.186586-7-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Maxim Levitsky Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Pull the controller memory buffer check to its own function. The check will be used on its own in later patches. Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch Reviewed-by: Maxim Levitsky --- hw/block/nvme.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 4058f2c79796..623a88be93dc 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -66,14 +66,22 @@ =20 static void nvme_process_sq(void *opaque); =20 +static bool nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr) +{ + hwaddr low =3D n->ctrl_mem.addr; + hwaddr hi =3D n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size); + + return addr >=3D low && addr < hi; +} + static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size) { - if (n->cmbsz && addr >=3D n->ctrl_mem.addr && - addr < (n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size))= ) { + if (n->cmbsz && nvme_addr_is_cmb(n, addr)) { memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size); - } else { - pci_dma_read(&n->parent_obj, addr, buf, size); + return; } + + pci_dma_read(&n->parent_obj, addr, buf, size); } =20 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588657939; cv=none; d=zohomail.com; s=zohoarc; b=AhXc9/nQ0HXsSMKQPVTrwiY/9CZXHvcCWKkYO9/WX/5mVuoHbWSpKj1unmKy+HyEJQSVihXnyaIPzq6MS3dt/5mHlzyjvhNpZKEcOxrTbZWPeKQDrtFJfSL3KLpZ0g3pAdqyQZZWM6bXrY1UV6BSYHFWMEqFfJ0GRkZ0lmTlY+s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588657939; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WFhVXYnHroxWvDmAFmA+JCgFrxJwuSE5d5Q+bGRdNeg=; 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Tue, 05 May 2020 01:49:14 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 9C275BFBB9; Tue, 5 May 2020 05:49:06 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 07/18] nvme: add max_ioqpairs device parameter Date: Tue, 5 May 2020 07:48:29 +0200 Message-Id: <20200505054840.186586-8-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen The num_queues device paramater has a slightly confusing meaning because it accounts for the admin queue pair which is not really optional. Secondly, it is really a maximum value of queues allowed. Add a new max_ioqpairs parameter that only accounts for I/O queue pairs, but keep num_queues for compatibility. Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Keith Busch --- hw/block/nvme.c | 51 ++++++++++++++++++++++++++++++------------------- hw/block/nvme.h | 3 ++- 2 files changed, 33 insertions(+), 21 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 623a88be93dc..3875a5f3dcbf 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -20,7 +20,7 @@ * -device nvme,drive=3D,serial=3D,id=3D, \ * cmb_size_mb=3D, \ * [pmrdev=3D,] \ - * num_queues=3D + * max_ioqpairs=3D * * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at * offset 0 in BAR2 and supports only WDS, RDS and SQS for now. @@ -36,6 +36,7 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/error-report.h" #include "hw/block/block.h" #include "hw/pci/msix.h" #include "hw/pci/pci.h" @@ -86,12 +87,12 @@ static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, vo= id *buf, int size) =20 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) { - return sqid < n->params.num_queues && n->sq[sqid] !=3D NULL ? 0 : -1; + return sqid < n->params.max_ioqpairs + 1 && n->sq[sqid] !=3D NULL ? 0 = : -1; } =20 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid) { - return cqid < n->params.num_queues && n->cq[cqid] !=3D NULL ? 0 : -1; + return cqid < n->params.max_ioqpairs + 1 && n->cq[cqid] !=3D NULL ? 0 = : -1; } =20 static void nvme_inc_cq_tail(NvmeCQueue *cq) @@ -653,7 +654,7 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cm= d) trace_pci_nvme_err_invalid_create_cq_addr(prp1); return NVME_INVALID_FIELD | NVME_DNR; } - if (unlikely(vector > n->params.num_queues)) { + if (unlikely(vector > n->params.max_ioqpairs + 1)) { trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } @@ -805,8 +806,8 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); break; case NVME_NUMBER_OF_QUEUES: - result =3D cpu_to_le32((n->params.num_queues - 2) | - ((n->params.num_queues - 2) << 16)); + result =3D cpu_to_le32((n->params.max_ioqpairs - 1) | + ((n->params.max_ioqpairs - 1) << 16)); trace_pci_nvme_getfeat_numq(result); break; case NVME_TIMESTAMP: @@ -850,10 +851,10 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd= *cmd, NvmeRequest *req) case NVME_NUMBER_OF_QUEUES: trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, ((dw11 >> 16) & 0xFFFF) + 1, - n->params.num_queues - 1, - n->params.num_queues - 1); - req->cqe.result =3D cpu_to_le32((n->params.num_queues - 2) | - ((n->params.num_queues - 2) << 16)); + n->params.max_ioqpairs, + n->params.max_ioqpairs); + req->cqe.result =3D cpu_to_le32((n->params.max_ioqpairs - 1) | + ((n->params.max_ioqpairs - 1) << 16)= ); break; case NVME_TIMESTAMP: return nvme_set_feature_timestamp(n, cmd); @@ -924,12 +925,12 @@ static void nvme_clear_ctrl(NvmeCtrl *n) =20 blk_drain(n->conf.blk); =20 - for (i =3D 0; i < n->params.num_queues; i++) { + for (i =3D 0; i < n->params.max_ioqpairs + 1; i++) { if (n->sq[i] !=3D NULL) { nvme_free_sq(n->sq[i], n); } } - for (i =3D 0; i < n->params.num_queues; i++) { + for (i =3D 0; i < n->params.max_ioqpairs + 1; i++) { if (n->cq[i] !=3D NULL) { nvme_free_cq(n->cq[i], n); } @@ -1360,8 +1361,17 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) int64_t bs_size; uint8_t *pci_conf; =20 - if (!n->params.num_queues) { - error_setg(errp, "num_queues can't be zero"); + if (n->params.num_queues) { + warn_report("num_queues is deprecated; please use max_ioqpairs " + "instead"); + + n->params.max_ioqpairs =3D n->params.num_queues - 1; + } + + if (n->params.max_ioqpairs < 1 || + n->params.max_ioqpairs > PCI_MSIX_FLAGS_QSIZE) { + error_setg(errp, "max_ioqpairs must be between 1 and %d", + PCI_MSIX_FLAGS_QSIZE); return; } =20 @@ -1411,21 +1421,21 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) =20 n->num_namespaces =3D 1; =20 - /* num_queues is really number of pairs, so each has two doorbells */ + /* add one to max_ioqpairs to account for the admin queue pair */ n->reg_size =3D pow2ceil(NVME_REG_SIZE + - 2 * n->params.num_queues * NVME_DB_SIZE); + 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; =20 n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); - n->sq =3D g_new0(NvmeSQueue *, n->params.num_queues); - n->cq =3D g_new0(NvmeCQueue *, n->params.num_queues); + n->sq =3D g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); + n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); =20 memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); - msix_init_exclusive_bar(pci_dev, n->params.num_queues, 4, NULL); + msix_init_exclusive_bar(pci_dev, n->params.max_ioqpairs + 1, 4, NULL); =20 id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); @@ -1571,7 +1581,8 @@ static Property nvme_props[] =3D { HostMemoryBackend *), DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial), DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, params.cmb_size_mb, 0), - DEFINE_PROP_UINT32("num_queues", NvmeCtrl, params.num_queues, 64), + DEFINE_PROP_UINT32("num_queues", NvmeCtrl, params.num_queues, 0), + DEFINE_PROP_UINT32("max_ioqpairs", NvmeCtrl, params.max_ioqpairs, 64), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 9df244c93c02..c4e3edfebe0b 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -5,7 +5,8 @@ =20 typedef struct NvmeParams { char *serial; - uint32_t num_queues; + uint32_t num_queues; /* deprecated since 5.1 */ + uint32_t max_ioqpairs; uint32_t cmb_size_mb; } NvmeParams; =20 --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Mon, 4 May 2020 22:50:44 -0700 (PDT) Received: from localhost ([::1]:58634 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jVqTZ-0000c9-GF for importer@patchew.org; Tue, 05 May 2020 01:50:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS8-00075m-Ic; Tue, 05 May 2020 01:49:12 -0400 Received: from charlie.dont.surf ([128.199.63.193]:56352) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS7-0005GJ-Au; Tue, 05 May 2020 01:49:12 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 0C97DBFD78; Tue, 5 May 2020 05:49:07 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 08/18] nvme: remove redundant cmbloc/cmbsz members Date: Tue, 5 May 2020 07:48:30 +0200 Message-Id: <20200505054840.186586-9-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 7 ++----- hw/block/nvme.h | 2 -- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 3875a5f3dcbf..cc6d3059ff7f 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -77,7 +77,7 @@ static bool nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr) =20 static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size) { - if (n->cmbsz && nvme_addr_is_cmb(n, addr)) { + if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr)) { memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size); return; } @@ -171,7 +171,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, if (unlikely(!prp1)) { trace_pci_nvme_err_invalid_prp(); return NVME_INVALID_FIELD | NVME_DNR; - } else if (n->cmbsz && prp1 >=3D n->ctrl_mem.addr && + } else if (n->bar.cmbsz && prp1 >=3D n->ctrl_mem.addr && prp1 < n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size)) { qsg->nsg =3D 0; qemu_iovec_init(iov, num_prps); @@ -1483,9 +1483,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); =20 - n->cmbloc =3D n->bar.cmbloc; - n->cmbsz =3D n->bar.cmbsz; - n->cmbuf =3D g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n, "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz)= ); diff --git a/hw/block/nvme.h b/hw/block/nvme.h index c4e3edfebe0b..6714616e376e 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -82,8 +82,6 @@ typedef struct NvmeCtrl { uint32_t num_namespaces; uint32_t max_q_ents; uint64_t ns_size; - uint32_t cmbsz; - uint32_t cmbloc; uint8_t *cmbuf; uint64_t irq_status; uint64_t host_timestamp; /* Timestamp sent by the h= ost */ --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588658024; cv=none; d=zohomail.com; s=zohoarc; b=Fr3GfrLMpq+9QwXsW/BLCTVvUEdlX4XPHtTUcLh9QFBvpRd6icbFrhZ1o6Xbp7vG+Roy3hw+lIzv0/H+J+trFRsHQub6YAZjspCFu0AM0S+y66Ia1kFOUoPPglWsyZmNtT0tH9KikeYShB18M9ii4btz+5AS+Pajt0Cs6DbirAQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588658024; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Tue, 05 May 2020 01:49:33 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 74967BFD79; Tue, 5 May 2020 05:49:07 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 09/18] nvme: factor out property/constraint checks Date: Tue, 5 May 2020 07:48:31 +0200 Message-Id: <20200505054840.186586-10-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 48 ++++++++++++++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 18 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index cc6d3059ff7f..13fb90c77e90 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1352,24 +1352,19 @@ static const MemoryRegionOps nvme_cmb_ops =3D { }, }; =20 -static void nvme_realize(PCIDevice *pci_dev, Error **errp) +static void nvme_check_constraints(NvmeCtrl *n, Error **errp) { - NvmeCtrl *n =3D NVME(pci_dev); - NvmeIdCtrl *id =3D &n->id_ctrl; + NvmeParams *params =3D &n->params; =20 - int i; - int64_t bs_size; - uint8_t *pci_conf; - - if (n->params.num_queues) { + if (params->num_queues) { warn_report("num_queues is deprecated; please use max_ioqpairs " "instead"); =20 - n->params.max_ioqpairs =3D n->params.num_queues - 1; + params->max_ioqpairs =3D params->num_queues - 1; } =20 - if (n->params.max_ioqpairs < 1 || - n->params.max_ioqpairs > PCI_MSIX_FLAGS_QSIZE) { + if (params->max_ioqpairs < 1 || + params->max_ioqpairs > PCI_MSIX_FLAGS_QSIZE) { error_setg(errp, "max_ioqpairs must be between 1 and %d", PCI_MSIX_FLAGS_QSIZE); return; @@ -1380,13 +1375,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) return; } =20 - bs_size =3D blk_getlength(n->conf.blk); - if (bs_size < 0) { - error_setg(errp, "could not get backing file size"); - return; - } - - if (!n->params.serial) { + if (!params->serial) { error_setg(errp, "serial property not set"); return; } @@ -1406,6 +1395,29 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) =20 host_memory_backend_set_mapped(n->pmrdev, true); } +} + +static void nvme_realize(PCIDevice *pci_dev, Error **errp) +{ + NvmeCtrl *n =3D NVME(pci_dev); + NvmeIdCtrl *id =3D &n->id_ctrl; + Error *local_err =3D NULL; + + int i; + int64_t bs_size; + uint8_t *pci_conf; + + nvme_check_constraints(n, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + bs_size =3D blk_getlength(n->conf.blk); + if (bs_size < 0) { + error_setg(errp, "could not get backing file size"); + return; + } =20 blkconf_blocksizes(&n->conf); if (!blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.= blk), --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Mon, 4 May 2020 22:54:01 -0700 (PDT) Received: from localhost ([::1]:49576 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jVqWm-0000O1-OV for importer@patchew.org; Tue, 05 May 2020 01:54:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53584) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS9-00078N-I1; Tue, 05 May 2020 01:49:13 -0400 Received: from charlie.dont.surf ([128.199.63.193]:56378) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqS8-0005Kr-HB; Tue, 05 May 2020 01:49:13 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id D8B57BFD93; Tue, 5 May 2020 05:49:07 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 10/18] nvme: factor out device state setup Date: Tue, 5 May 2020 07:48:32 +0200 Message-Id: <20200505054840.186586-11-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 13fb90c77e90..72e838a476af 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1397,6 +1397,17 @@ static void nvme_check_constraints(NvmeCtrl *n, Erro= r **errp) } } =20 +static void nvme_init_state(NvmeCtrl *n) +{ + n->num_namespaces =3D 1; + /* add one to max_ioqpairs to account for the admin queue pair */ + n->reg_size =3D pow2ceil(NVME_REG_SIZE + + 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); + n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); + n->sq =3D g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); + n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); +} + static void nvme_realize(PCIDevice *pci_dev, Error **errp) { NvmeCtrl *n =3D NVME(pci_dev); @@ -1413,6 +1424,8 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) return; } =20 + nvme_init_state(n); + bs_size =3D blk_getlength(n->conf.blk); if (bs_size < 0) { error_setg(errp, "could not get backing file size"); @@ -1431,17 +1444,8 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS); pcie_endpoint_cap_init(pci_dev, 0x80); =20 - n->num_namespaces =3D 1; - - /* add one to max_ioqpairs to account for the admin queue pair */ - n->reg_size =3D pow2ceil(NVME_REG_SIZE + - 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; =20 - n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); - n->sq =3D g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); - n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); - memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); pci_register_bar(pci_dev, 0, --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588658132; cv=none; d=zohomail.com; s=zohoarc; b=TgpHQXUt4jQl9lkk6WrqR5btgfVymk/RlA2fxVS4KMJ+nQ/z7j3y2mH17BASIhTr5rnoLuxM5ERh09oMbbqiUCsWgmtJqvFcRwWBM3hJd4aKrUniHcSqHIYTrtpTP2SQV2wipSiuJL1PpnQeI6G1QDqUlHq5DBwvUdazWY4vaKY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588658132; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Tue, 05 May 2020 01:49:34 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 5278CBFDA3; Tue, 5 May 2020 05:49:08 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 11/18] nvme: factor out block backend setup Date: Tue, 5 May 2020 07:48:33 +0200 Message-Id: <20200505054840.186586-12-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 72e838a476af..acdd735e0aca 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1408,6 +1408,13 @@ static void nvme_init_state(NvmeCtrl *n) n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); } =20 +static void nvme_init_blk(NvmeCtrl *n, Error **errp) +{ + blkconf_blocksizes(&n->conf); + blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.blk), + false, errp); +} + static void nvme_realize(PCIDevice *pci_dev, Error **errp) { NvmeCtrl *n =3D NVME(pci_dev); @@ -1432,9 +1439,9 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) return; } =20 - blkconf_blocksizes(&n->conf); - if (!blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.= blk), - false, errp)) { + nvme_init_blk(n, &local_err); + if (local_err) { + error_propagate(errp, local_err); return; } =20 --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588658199; cv=none; d=zohomail.com; s=zohoarc; b=DQ5PgCh8n4fBd2TXEbp2VUaDvZo66rMukcqTDd/o8dkojGWDHnx4M9DL1TKDwmFom+AcTVvBbtPTSvhKj5vq60cJy8/lN/piFLr2pcEuw2hHILlhbnSrV0O1dX1OQGAXeDOvFodXdx2ED3qX9qTsMApU+AP3yVAE6MOGPEpt2p8= ARC-Message-Signature: i=1; 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Tue, 05 May 2020 01:56:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqSV-0007mL-5g; Tue, 05 May 2020 01:49:35 -0400 Received: from charlie.dont.surf ([128.199.63.193]:56400) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqST-0005LL-8i; Tue, 05 May 2020 01:49:34 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id B60A6BFDAB; Tue, 5 May 2020 05:49:08 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 12/18] nvme: add namespace helpers Date: Tue, 5 May 2020 07:48:34 +0200 Message-Id: <20200505054840.186586-13-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Introduce some small helpers to make the next patches easier on the eye. Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 3 +-- hw/block/nvme.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index acdd735e0aca..720cc91bcb6a 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1571,8 +1571,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) id_ns->dps =3D 0; id_ns->lbaf[0].ds =3D BDRV_SECTOR_BITS; id_ns->ncap =3D id_ns->nuse =3D id_ns->nsze =3D - cpu_to_le64(n->ns_size >> - id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas)].ds); + cpu_to_le64(nvme_ns_nlbas(n, ns)); } } =20 diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 6714616e376e..345eb7bf3a51 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -61,6 +61,17 @@ typedef struct NvmeNamespace { NvmeIdNs id_ns; } NvmeNamespace; =20 +static inline NvmeLBAF *nvme_ns_lbaf(NvmeNamespace *ns) +{ + NvmeIdNs *id_ns =3D &ns->id_ns; + return &id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)]; +} + +static inline uint8_t nvme_ns_lbads(NvmeNamespace *ns) +{ + return nvme_ns_lbaf(ns)->ds; +} + #define TYPE_NVME "nvme" #define NVME(obj) \ OBJECT_CHECK(NvmeCtrl, (obj), TYPE_NVME) @@ -97,4 +108,10 @@ typedef struct NvmeCtrl { NvmeIdCtrl id_ctrl; } NvmeCtrl; =20 +/* calculate the number of LBAs that the namespace can accomodate */ +static inline uint64_t nvme_ns_nlbas(NvmeCtrl *n, NvmeNamespace *ns) +{ + return n->ns_size >> nvme_ns_lbads(ns); +} + #endif /* HW_NVME_H */ --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588658149; cv=none; d=zohomail.com; s=zohoarc; b=CQH7T4rd7cVXxvVGWCAFGLu/qV+bpViL6dNnXBGZbdhRLJ5057M/S5jq9TOKERWVkfUZKsMCcRFEW9OY834YZ7WYiYJax/7DsnNhtQSQBHchcHRutfhzWg/nJOXbPrM0g4wrJaI2Bjh2GPP4GIuYmKqU5uMaSZS4uQDnCoApxvk= ARC-Message-Signature: i=1; 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Tue, 05 May 2020 01:55:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqSV-0007mi-Kk; Tue, 05 May 2020 01:49:36 -0400 Received: from charlie.dont.surf ([128.199.63.193]:56402) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqST-0005MI-MT; Tue, 05 May 2020 01:49:35 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 3CE7CBF7AF; Tue, 5 May 2020 05:49:09 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 13/18] nvme: factor out namespace setup Date: Tue, 5 May 2020 07:48:35 +0200 Message-Id: <20200505054840.186586-14-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 46 ++++++++++++++++++++++++++-------------------- 1 file changed, 26 insertions(+), 20 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 720cc91bcb6a..c05124676e5e 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1415,6 +1415,27 @@ static void nvme_init_blk(NvmeCtrl *n, Error **errp) false, errp); } =20 +static void nvme_init_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **er= rp) +{ + int64_t bs_size; + NvmeIdNs *id_ns =3D &ns->id_ns; + + bs_size =3D blk_getlength(n->conf.blk); + if (bs_size < 0) { + error_setg_errno(errp, -bs_size, "could not get backing file size"= ); + return; + } + + n->ns_size =3D bs_size; + + id_ns->lbaf[0].ds =3D BDRV_SECTOR_BITS; + id_ns->nsze =3D cpu_to_le64(nvme_ns_nlbas(n, ns)); + + /* no thin provisioning */ + id_ns->ncap =3D id_ns->nsze; + id_ns->nuse =3D id_ns->ncap; +} + static void nvme_realize(PCIDevice *pci_dev, Error **errp) { NvmeCtrl *n =3D NVME(pci_dev); @@ -1422,7 +1443,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) Error *local_err =3D NULL; =20 int i; - int64_t bs_size; uint8_t *pci_conf; =20 nvme_check_constraints(n, &local_err); @@ -1433,12 +1453,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) =20 nvme_init_state(n); =20 - bs_size =3D blk_getlength(n->conf.blk); - if (bs_size < 0) { - error_setg(errp, "could not get backing file size"); - return; - } - nvme_init_blk(n, &local_err); if (local_err) { error_propagate(errp, local_err); @@ -1451,8 +1465,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS); pcie_endpoint_cap_init(pci_dev, 0x80); =20 - n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; - memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); pci_register_bar(pci_dev, 0, @@ -1561,17 +1573,11 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) } =20 for (i =3D 0; i < n->num_namespaces; i++) { - NvmeNamespace *ns =3D &n->namespaces[i]; - NvmeIdNs *id_ns =3D &ns->id_ns; - id_ns->nsfeat =3D 0; - id_ns->nlbaf =3D 0; - id_ns->flbas =3D 0; - id_ns->mc =3D 0; - id_ns->dpc =3D 0; - id_ns->dps =3D 0; - id_ns->lbaf[0].ds =3D BDRV_SECTOR_BITS; - id_ns->ncap =3D id_ns->nuse =3D id_ns->nsze =3D - cpu_to_le64(nvme_ns_nlbas(n, ns)); + nvme_init_namespace(n, &n->namespaces[i], &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } } } =20 --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588658228; cv=none; d=zohomail.com; s=zohoarc; b=VJDSQUZJW/QoZ+VOIZOUaaaGT8czY4m4tBDHuRGMWxMG7xPCpDBVi5c/sCqkPgHnBEVobBuVH3zyxIlrYpmJXFH0vgrsSj4l0YS5HlJDZvPfZhrW1kHmVP/aLhr8LQvp8BpAmqQ3FLzgUJxycSttk2iO+OsTbvr62R3qr/bElZ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588658228; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hirfnQ+9ExYBE7eprE1UgtFMD71cI3Jvmwv+TWGPBTw=; b=AJDNSUhaNHGuW9tlUBQPhUTXEMIsFt5MqfWwguDs4g1S+SjwhATx4RDWvTXGBDYVd6JwzBOjsa7kTiZvxq7N1IJPaBR9GRUNkvphueC6oj+wfrP5Lz9F3tlRnnrW87Y3W6mi2a2sJ6jIqzRXWvaoXZbmkIs36TXNuF6C2BBLds4= ARC-Authentication-Results: i=1; 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Tue, 5 May 2020 05:49:09 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 14/18] nvme: factor out pci setup Date: Tue, 5 May 2020 07:48:36 +0200 Message-Id: <20200505054840.186586-15-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index c05124676e5e..2e65a780f4f0 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1436,6 +1436,22 @@ static void nvme_init_namespace(NvmeCtrl *n, NvmeNam= espace *ns, Error **errp) id_ns->nuse =3D id_ns->ncap; } =20 +static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev) +{ + uint8_t *pci_conf =3D pci_dev->config; + + pci_conf[PCI_INTERRUPT_PIN] =3D 1; + pci_config_set_prog_interface(pci_conf, 0x2); + pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS); + pcie_endpoint_cap_init(pci_dev, 0x80); + + memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", + n->reg_size); + pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); + msix_init_exclusive_bar(pci_dev, n->params.max_ioqpairs + 1, 4, NULL); +} + static void nvme_realize(PCIDevice *pci_dev, Error **errp) { NvmeCtrl *n =3D NVME(pci_dev); @@ -1459,19 +1475,9 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) return; } =20 + nvme_init_pci(n, pci_dev); + pci_conf =3D pci_dev->config; - pci_conf[PCI_INTERRUPT_PIN] =3D 1; - pci_config_set_prog_interface(pci_dev->config, 0x2); - pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS); - pcie_endpoint_cap_init(pci_dev, 0x80); - - memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, - "nvme", n->reg_size); - pci_register_bar(pci_dev, 0, - PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, - &n->iomem); - msix_init_exclusive_bar(pci_dev, n->params.max_ioqpairs + 1, 4, NULL); - id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588658097; cv=none; d=zohomail.com; s=zohoarc; b=JCU3fqgq6lH2BE6bLV8n7LtP6+1j7JYjAkYtJn1u2pQdfZ7S2U2wcpNyZvyod0xDJW430kTqoFdzbGvFTKa+uvMThUWYoZJT69akbhmEDn/3vd7/pAYAH1VAu4N6x/IQ6ZNNqoAAKSzLX9EzczJF5UdoQWC/hf2N+TUr9HejMBw= ARC-Message-Signature: i=1; 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Tue, 05 May 2020 01:54:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53680) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqSV-0007mS-GF; Tue, 05 May 2020 01:49:36 -0400 Received: from charlie.dont.surf ([128.199.63.193]:56406) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqST-0005MU-No; Tue, 05 May 2020 01:49:35 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 0CC04BFDAD; Tue, 5 May 2020 05:49:10 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 15/18] nvme: factor out cmb setup Date: Tue, 5 May 2020 07:48:37 +0200 Message-Id: <20200505054840.186586-16-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 43 ++++++++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 2e65a780f4f0..bd255a5c711a 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -57,6 +57,7 @@ =20 #define NVME_REG_SIZE 0x1000 #define NVME_DB_SIZE 4 +#define NVME_CMB_BIR 2 =20 #define NVME_GUEST_ERR(trace, fmt, ...) \ do { \ @@ -1436,6 +1437,28 @@ static void nvme_init_namespace(NvmeCtrl *n, NvmeNam= espace *ns, Error **errp) id_ns->nuse =3D id_ns->ncap; } =20 +static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev) +{ + NVME_CMBLOC_SET_BIR(n->bar.cmbloc, NVME_CMB_BIR); + NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); + + NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1); + NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0); + NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 0); + NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); + NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1); + NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ + NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); + + n->cmbuf =3D g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); + memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n, + "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); + pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc), + PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64 | + PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem); +} + static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev) { uint8_t *pci_conf =3D pci_dev->config; @@ -1512,25 +1535,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) n->bar.intmc =3D n->bar.intms =3D 0; =20 if (n->params.cmb_size_mb) { - - NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2); - NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); - - NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0); - NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 0); - NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ - NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); - - n->cmbuf =3D g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); - memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n, - "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz)= ); - pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc), - PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 | - PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem); - + nvme_init_cmb(n, pci_dev); } else if (n->pmrdev) { /* Controller Capabilities register */ NVME_CAP_SET_PMRS(n->bar.cap, 1); --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 4 May 2020 22:57:57 -0700 (PDT) Received: from localhost ([::1]:39292 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jVqaa-0007wS-4X for importer@patchew.org; Tue, 05 May 2020 01:57:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqSW-0007oF-QP; Tue, 05 May 2020 01:49:37 -0400 Received: from charlie.dont.surf ([128.199.63.193]:56408) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jVqST-0005MX-NF; Tue, 05 May 2020 01:49:36 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 76456BFDAE; Tue, 5 May 2020 05:49:10 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 16/18] nvme: factor out pmr setup Date: Tue, 5 May 2020 07:48:38 +0200 Message-Id: <20200505054840.186586-17-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky --- hw/block/nvme.c | 95 ++++++++++++++++++++++++++----------------------- 1 file changed, 51 insertions(+), 44 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index bd255a5c711a..b0b3d3ffb75f 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -58,6 +58,7 @@ #define NVME_REG_SIZE 0x1000 #define NVME_DB_SIZE 4 #define NVME_CMB_BIR 2 +#define NVME_PMR_BIR 2 =20 #define NVME_GUEST_ERR(trace, fmt, ...) \ do { \ @@ -1459,6 +1460,55 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pc= i_dev) PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem); } =20 +static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev) +{ + /* Controller Capabilities register */ + NVME_CAP_SET_PMRS(n->bar.cap, 1); + + /* PMR Capabities register */ + n->bar.pmrcap =3D 0; + NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0); + NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0); + NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR); + NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0); + /* Turn on bit 1 support */ + NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02); + NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0); + NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0); + + /* PMR Control register */ + n->bar.pmrctl =3D 0; + NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0); + + /* PMR Status register */ + n->bar.pmrsts =3D 0; + NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0); + NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0); + NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0); + NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0); + + /* PMR Elasticity Buffer Size register */ + n->bar.pmrebs =3D 0; + NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0); + NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0); + NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0); + + /* PMR Sustained Write Throughput register */ + n->bar.pmrswtp =3D 0; + NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0); + NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0); + + /* PMR Memory Space Control register */ + n->bar.pmrmsc =3D 0; + NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0); + NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0); + + pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap), + PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64 | + PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr); +} + static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev) { uint8_t *pci_conf =3D pci_dev->config; @@ -1537,50 +1587,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) if (n->params.cmb_size_mb) { nvme_init_cmb(n, pci_dev); } else if (n->pmrdev) { - /* Controller Capabilities register */ - NVME_CAP_SET_PMRS(n->bar.cap, 1); - - /* PMR Capabities register */ - n->bar.pmrcap =3D 0; - NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0); - NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0); - NVME_PMRCAP_SET_BIR(n->bar.pmrcap, 2); - NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0); - /* Turn on bit 1 support */ - NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02); - NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0); - NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0); - - /* PMR Control register */ - n->bar.pmrctl =3D 0; - NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0); - - /* PMR Status register */ - n->bar.pmrsts =3D 0; - NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0); - NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0); - NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0); - NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0); - - /* PMR Elasticity Buffer Size register */ - n->bar.pmrebs =3D 0; - NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0); - NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0); - NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0); - - /* PMR Sustained Write Throughput register */ - n->bar.pmrswtp =3D 0; - NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0); - NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0); - - /* PMR Memory Space Control register */ - n->bar.pmrmsc =3D 0; - NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0); - NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0); - - pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap), - PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 | - PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr); + nvme_init_pmr(n, pci_dev); } =20 for (i =3D 0; i < n->num_namespaces; i++) { --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588658299; cv=none; d=zohomail.com; s=zohoarc; b=j+hvjO1jCHGDuEStjTg2eS+s6dKJOeuavpaW9Mg20EYfBn2rRNyjYyQ9XjCNLi3jKPf92HoRbKepk2S09ecr75++riZ7L0XSQrptWKgiMvk4hcOjmAFpju+RctMp/AVE2rj6gd0OFOUK+4PcK4peNiujCjSYXXZ9TIqJzocDvbg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588658299; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky --- hw/block/nvme.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index b0b3d3ffb75f..6454f3810e5b 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1523,6 +1523,12 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pc= i_dev) pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); msix_init_exclusive_bar(pci_dev, n->params.max_ioqpairs + 1, 4, NULL); + + if (n->params.cmb_size_mb) { + nvme_init_cmb(n, pci_dev); + } else if (n->pmrdev) { + nvme_init_pmr(n, pci_dev); + } } =20 static void nvme_realize(PCIDevice *pci_dev, Error **errp) @@ -1584,12 +1590,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) n->bar.vs =3D 0x00010200; n->bar.intmc =3D n->bar.intms =3D 0; =20 - if (n->params.cmb_size_mb) { - nvme_init_cmb(n, pci_dev); - } else if (n->pmrdev) { - nvme_init_pmr(n, pci_dev); - } - for (i =3D 0; i < n->num_namespaces; i++) { nvme_init_namespace(n, &n->namespaces[i], &local_err); if (local_err) { --=20 2.26.2 From nobody Wed May 15 05:27:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588658113; cv=none; d=zohomail.com; s=zohoarc; b=NB/Y3rHsNmdpBMZRlHV1CQWuzGsxo7cXvF4zlxtatw2bhsTjw98r2W2Ng0/01Kk8aieSSeOylulTjbqEidfRN28d8KqkZ5t5kJUXSjdB3LpBmljvwO2TytIkpWOb2utmx8/H21WoPbKHm/ZFyZKN3L4lK8L4smd3dqLR52UWXJY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588658113; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MK/BoXOLMMlr9BoEOmIBafiTWmXjuLWN5V5LbXmdD/8=; b=ckp7hxw2BKz5wa7QaRzFMsH1+yoYkznm1MjQwgqJgnV/dHaWm0TuN5wbHvfJwA566J18NRhNX6/WKfJdvaUreoACK9Sv5XhzmUtqEA1ejYgWY1QYfG0jP05T6jdGkaEd0gMAA3BQkc9fyE3CaATMVALJdb7mOcv8yxts7VZWZJU= ARC-Authentication-Results: i=1; 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Tue, 5 May 2020 05:49:11 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v5 18/18] nvme: factor out controller identify setup Date: Tue, 5 May 2020 07:48:40 +0200 Message-Id: <20200505054840.186586-19-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200505054840.186586-1-its@irrelevant.dk> References: <20200505054840.186586-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 00:31:35 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Maxim Levitsky Reviewed-by: Keith Busch --- hw/block/nvme.c | 49 ++++++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 23 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 6454f3810e5b..73489a1e0eb6 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1531,32 +1531,11 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *p= ci_dev) } } =20 -static void nvme_realize(PCIDevice *pci_dev, Error **errp) +static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev) { - NvmeCtrl *n =3D NVME(pci_dev); NvmeIdCtrl *id =3D &n->id_ctrl; - Error *local_err =3D NULL; + uint8_t *pci_conf =3D pci_dev->config; =20 - int i; - uint8_t *pci_conf; - - nvme_check_constraints(n, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - nvme_init_state(n); - - nvme_init_blk(n, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - nvme_init_pci(n, pci_dev); - - pci_conf =3D pci_dev->config; id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); @@ -1589,6 +1568,30 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) =20 n->bar.vs =3D 0x00010200; n->bar.intmc =3D n->bar.intms =3D 0; +} + +static void nvme_realize(PCIDevice *pci_dev, Error **errp) +{ + NvmeCtrl *n =3D NVME(pci_dev); + Error *local_err =3D NULL; + + int i; + + nvme_check_constraints(n, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + nvme_init_state(n); + nvme_init_blk(n, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + nvme_init_pci(n, pci_dev); + nvme_init_ctrl(n, pci_dev); =20 for (i =3D 0; i < n->num_namespaces; i++) { nvme_init_namespace(n, &n->namespaces[i], &local_err); --=20 2.26.2